-60 V, 14 mOhm, -64 A, Single P-Channel Power MOSFET

NVMFS5113PL
Power MOSFET
−60 V, 14 mW, −64 A, Single P−Channel
Features
•
•
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
High Current Capability
Avalanche Energy Specified
NVMFS5113PLWF − Wettable Flanks Product
NVM Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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RDS(on)
V(BR)DSS
14 mW @ −10 V
−60 V
S (1, 2, 3)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
−60
V
Gate−to−Source Voltage
VGS
"20
V
ID
−64
A
Continuous Drain Current RqJC (Notes 1, 2, 3)
Power Dissipation RqJC
(Notes 1, 2)
Continuous Drain Current RqJA (Notes 1, 2, 3)
Power Dissipation RqJA
(Notes 1, 2)
Pulsed Drain Current
TC = 25°C
Steady
State
TC = 100°C
TC = 25°C
TC = 100°C
TA = 25°C
Steady
State
ID
Operating Junction and Storage Temperature
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL(pk) = 46 A, L = 0.3 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
D (5, 6)
W
150
MARKING
DIAGRAM
A
−10
D
−7
PD
TA = 100°C
TA = 25°C, tp = 10 ms
P−Channel
75
TA = 100°C
TA = 25°C
G (4)
−45
PD
W
3.8
1.9
IDM
−64 A
22 mW @ −4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
ID
−415
A
TJ, Tstg
−55 to
175
°C
IS
−150
A
EAS
315
mJ
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1
DFN5
CASE 488AA
STYLE 1
A
Y
W
ZZ
S
S
S
G
D
XXXXXX
AYWZZ
D
D
= Assembly Location
= Year
= Work Week
= Lot Traceability
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction−to−Case − Steady State (Drain)
(Note 2)
RqJC
1.0
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
39
°C/W
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Continuous DC current rating. Maximum current for pulses as long as
1 second is higher but is dependent on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 3
1
Publication Order Number:
NVMFS5113PL/D
NVMFS5113PL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
V(BR)DSS
VGS = 0 V, ID = −250 mA
−60
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V,
VDS = −60 V
TJ = 25°C
−1.0
TJ = 125°C
−100
IGSS
VDS = 0 V, VGS = "20 V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = −250 mA
Drain−to−Source On Resistance
RDS(on)
VGS = −10 V, ID = −17 A
gFS
Input Capacitance
Ciss
Output Capacitance
Coss
VGS = 0 V, f = 1.0 MHz,
VDS = −25 V
Reverse Transfer Capacitance
Crss
Gate−to−Source Leakage Current
V
mA
"100
nA
−2.5
V
10.5
14
mW
VGS = −4.5 V, ID = −5 A
16
22
VDS = −15 V, ID = −15 A
43
S
4400
pF
ON CHARACTERISTICS (Note 4)
Froward Transconductance
−1.5
CHARGES AND CAPACITANCES
Total Gate Charge
QG(TOT)
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Plateau Voltage
VGP
505
319
VDS = −48 V,
ID = −17 A
VGS = −4.5 V
45
VGS = −10 V
83
nC
4
VGS = −10 V, VDS = −48 V,
ID = −17 A
13
27
3.5
V
15
ns
SWITCHING CHARACTERISTICS (Notes 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
td(off)
VGS = −10 V, VDS = −48 V,
ID = −17 A, RG = 2.5 W
tf
37
54
77
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
−0.79
TJ = 125°C
−0.65
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = −17 A
41
VGS = 0 V, dls/dt = 100 A/ms,
Is = −17 A
QRR
−1.0
V
ns
22
19
50
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
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2
NVMFS5113PL
TYPICAL CHARACTERISTICS
60.0
120.0
50.0
−6 V to −10 V
40.0
−4.0 V
30.0
20.0
−3.6 V
10.0
−3.2 V
VGS = −2.8 V
1.0
2.0
3.0
4.0
90.0
80.0
70.0
60.0
50.0
TJ = 25°C
40.0
30.0
20.0
10.0
TJ = −55°C
TJ = 125°C
0.0
1
5.0
2
3
4
5
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.020
6
0.050
ID = −17 A
TJ = 25°C
0.018
TJ = 25°C
0.045
0.040
0.035
0.016
0.030
0.014
VGS = −4.5 V
0.025
0.020
0.012
0.015
0.010
4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
−VGS, GATE−TO−SOURCE VOLTAGE (V)
0
10
20
30
40
50
60
70
80
90 100
−ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
2.10
VGS = −10 V
2.00
ID = −17 A
1.90
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
−50 −25
0
VGS = −10 V
0.010
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100000
VGS = 0 V
−IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
100.0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0.0
0.0
VDS = −10 V
110.0
−ID, DRAIN CURRENT (A)
−ID, DRAIN CURRENT (A)
TJ = 25°C
TJ = 150°C
10000
TJ = 125°C
1000
100
25
50
75
100
125
150
175
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
60
NVMFS5113PL
TYPICAL CHARACTERISTICS
C, CAPACITANCE (pF)
VGS = 0 V
TJ = 25°C
f = 1 MHz
Ciss
5000
VGS, GATE−TO−SOURCE VOLTAGE (V)
6000
4000
3000
2000
Coss
1000
0
Crss
0
10
20
30
40
50
10.0
Qgd
4.0
3.0
2.0
VDS = −48 A
ID = −17 A
TJ = 25°C
1.0
0.0
0
10
20
30
40
50
60
70
80
Qg, TOTAL GATE CHARGE (nC)
90
120
−IS, SOURCE CURRENT (A)
100
td(on)
10.0
VDD = −48 V
VGS = −10 V
ID = −17 A
1
10
90
80
70
60
50
40
30
20
10
0
100
0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00
RG, GATE RESISTANCE (W)
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
100 ms 10 ms
VGS ≤ −10 V
Single Pulse
TC = 25°C
10 ms
1 ms
10
dc
1
RDS(on) Limit
Thermal Limit
Package Limit
0.1
VGS = 0 V
TJ = 25°C
110
IPEAK, DRAIN CURRENT (A)
t, TIME (ns)
Qgs
5.0
Figure 8. Gate−to−Source Voltage vs. Total
Charge
1.0
−ID, DRAIN CURRENT (A)
6.0
Figure 7. Capacitance Variation
100.0
0.01
7.0
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
td(off)
tf
tr
0.1
8.0
60
1000.0
100
QT
9.0
1
10
100
TJ(initial) = 25°C
10
1
1.00E−05
TJ(initial) = 125°C
1.00E−04
1.00E−03
1.00E−02
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TAV, TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Avalanche Characteristics
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4
NVMFS5113PL
TYPICAL CHARACTERISTICS
RqJA(t) (°C/W) EFFECTIVE TRANSIENT
THERMAL RESISTANCE
100
Duty Cycle = 0.5
10
0.2
0.1
0.05
1 0.02
0.01
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Marking
Package
Shipping†
NVMFS5113PLT1G
V5113L
DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFS5113PLWFT1G
5113LW
DFN5
(Pb−Free)
1500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NVMFS5113PL
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE M
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
A
2
B
D1
2X
0.20 C
4X
E1
q
E
2
c
1
2
3
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
A1
4
TOP VIEW
C
SEATING
PLANE
DETAIL A
0.10 C
A
0.10 C
SIDE VIEW
0.10
0.05
c
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
2X
0.495
b
C A B
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.00
5.15
5.30
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.30
6.15
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
4.560
2X
8X
1.530
e/2
e
L
1
4
3.200
K
4.530
E2
PIN 5
(EXPOSED PAD)
L1
M
1.330
2X
0.905
1
G
D2
BOTTOM VIEW
0.965
4X
1.000
4X 0.750
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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For additional information, please contact your local
Sales Representative
NVMFS5113PL/D
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