HT66F317_318v100.pdf

Enhanced A/D Type 8-Bit MCU with LCD Driver
HT66F317/HT66F318
Revision: V1.00
Date: �������������
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Table of Contents
Features................................................................................................................. 7
CPU Features...............................................................................................................................7
Peripheral Features.......................................................................................................................7
General Description.............................................................................................. 8
Selection Table...................................................................................................... 8
Block Diagram....................................................................................................... 9
Pin Assignment..................................................................................................... 9
Pin Description................................................................................................... 12
Absolute Maximum Ratings............................................................................... 16
D.C. Characteristics............................................................................................ 16
A.C. Characteristics............................................................................................ 18
A/D Converter Electrical Characteristics.......................................................... 19
LVD & LVR Electrical Characteristics............................................................... 20
Comparator Electrical Characteristics – HT66F318........................................ 21
Power-on Reset Characteristics........................................................................ 21
System Architecture........................................................................................... 22
Clocking and Pipelining...............................................................................................................22
Program Counter.........................................................................................................................23
Stack...........................................................................................................................................23
Arithmetic and Logic Unit – ALU.................................................................................................24
Flash Program Memory...................................................................................... 25
Structure......................................................................................................................................25
Special Vectors...........................................................................................................................25
Look-up Table..............................................................................................................................26
Table Program Example..............................................................................................................26
In Circuit Programming – ICP.....................................................................................................27
On-Chip Debug Support – OCDS...............................................................................................28
RAM Data Memory.............................................................................................. 29
Structure......................................................................................................................................29
Special Function Register Description............................................................. 32
Indirect Addressing Register – IAR0, IAR1.................................................................................32
Memory Pointers – MP0, MP1 ...................................................................................................32
Bank Pointer – BP ......................................................................................................................33
Accumulator – ACC.....................................................................................................................33
Program Counter Low Register – PCL .......................................................................................33
Look-up Table Registers – TBLP, TBHP, TBLH ..........................................................................33
Status Register – STATUS .........................................................................................................34
Rev. 1.00
2
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
EEPROM Data memory...................................................................................... 36
EEPROM Data Memory Structure..............................................................................................36
EEPROM Registers....................................................................................................................36
Reading Data from the EEPROM...............................................................................................38
Writing Data to the EEPROM......................................................................................................38
Write Protection...........................................................................................................................38
EEPROM Interrupt......................................................................................................................38
Programming Considerations......................................................................................................39
Oscillator............................................................................................................. 40
Oscillator Overview ....................................................................................................................40
System Clock Configurations .....................................................................................................40
External Crystal/Ceramic Oscillator – HXT ................................................................................41
Internal RC Oscillator – HIRC ....................................................................................................42
External 32.768kHz Crystal Oscillator – LXT..............................................................................42
Internal 32kHz Oscillator – LIRC ................................................................................................43
Supplementary Oscillators .........................................................................................................43
Operating Modes and System Clocks ............................................................. 44
System Clocks ...........................................................................................................................44
System Operation Modes ...........................................................................................................45
Control Register..........................................................................................................................46
Fast Wake-up .............................................................................................................................47
Operating Mode Switching .........................................................................................................48
Standby Current Considerations ................................................................................................53
Wake-up .....................................................................................................................................53
Programming Considerations .....................................................................................................54
Watchdog Timer.................................................................................................. 55
Watchdog Timer Clock Source....................................................................................................55
Watchdog Timer Control Register...............................................................................................55
Watchdog Timer Operation.........................................................................................................56
Reset and Initialisation....................................................................................... 57
Reset Functions .........................................................................................................................57
Reset Initial Conditions ..............................................................................................................60
Input/Output Ports ............................................................................................. 64
Pull-high Resistors......................................................................................................................64
Port A Wake-up...........................................................................................................................66
I/O Port Control Registers...........................................................................................................66
I/O Pin Structures........................................................................................................................67
Source Current Selection............................................................................................................68
Programming Considerations .....................................................................................................70
Rev. 1.00
3
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Timer Modules – TM........................................................................................... 71
Introduction.................................................................................................................................71
TM Operation..............................................................................................................................71
TM Clock Source.........................................................................................................................72
TM Interrupts...............................................................................................................................72
TM External Pins ........................................................................................................................72
TM Input/Output Pin Control Registers.......................................................................................72
Programming Considerations......................................................................................................75
Compact Type TM – CTM (only for HT66F318)................................................. 76
Compact TM Operation...............................................................................................................76
Compact Type TM Register Description.....................................................................................77
Compact Type TM Operating Modes..........................................................................................81
Standard Type TM – STM (only for HT66F318)................................................. 87
Standard TM Operation ..............................................................................................................87
Standard Type TM Register Description ....................................................................................88
Standard Type TM Operating Modes .........................................................................................92
Periodic Type TM – PTM................................................................................... 102
Periodic TM Operation..............................................................................................................102
Periodic Type TM Register Description.....................................................................................103
Periodic Type TM Operating Modes..........................................................................................107
Analog to Digital Converter – ADC.................................................................. 116
A/D Overview............................................................................................................................ 116
A/D Converter Register Description.......................................................................................... 117
A/D Converter Data Registers – SADOL, SADOH.................................................................... 117
A/D Converter Control Registers – SADC0, SADC1, SADC2, ACERL..................................... 117
A/D Operation...........................................................................................................................122
A/D Reference Voltage..............................................................................................................123
A/D Converter Input Pins..........................................................................................................124
Conversion Rate and Timing Diagram......................................................................................124
Summary of A/D Conversion Steps...........................................................................................125
Programming Considerations....................................................................................................126
A/D Transfer Function...............................................................................................................126
A/D Programming Examples.....................................................................................................127
Comparator (only for HT66F318)..................................................................... 129
Comparator Operation..............................................................................................................129
Comparator Interrupt.................................................................................................................130
Programming Considerations....................................................................................................130
Rev. 1.00
4
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
I2C Interface (only for HT66F318).................................................................... 131
I2C Interface Operation .............................................................................................................131
I2C Registers.............................................................................................................................132
I2C Bus Communication ...........................................................................................................135
I2C Bus Start Signal ..................................................................................................................136
Slave Address ..........................................................................................................................136
I2C Bus Read/Write Signal .......................................................................................................137
I2C Bus Slave Address Acknowledge Signal ............................................................................137
I2C Bus Data and Acknowledge Signal ....................................................................................137
I2C Time-out Control..................................................................................................................140
UART Interface (only for HT66F318)............................................................... 141
UART External Pin Interfacing..................................................................................................141
UART Data Transfer Scheme...................................................................................................142
UART Status and Control Registers.........................................................................................142
Baud Rate Generator................................................................................................................148
UART Setup and Control..........................................................................................................149
UART Transmitter.....................................................................................................................151
UART Receiver.........................................................................................................................152
Managing Receiver Errors........................................................................................................153
UART Module Interrupt Structure..............................................................................................154
Address Detect Mode................................................................................................................155
UART Power Down and Wake-up.............................................................................................156
Interrupts........................................................................................................... 156
Interrupt Registers.....................................................................................................................156
Interrupt Operation....................................................................................................................163
External Interrupt.......................................................................................................................165
Comparator Interrupt.................................................................................................................166
Multi-function Interrupt..............................................................................................................166
A/D Converter Interrupt.............................................................................................................166
Time Base Interrupt...................................................................................................................167
I2C Interrupt...............................................................................................................................168
UART Interrupt..........................................................................................................................168
EEPROM Interrupt....................................................................................................................168
LVD Interrupt ............................................................................................................................169
TM Interrupts ............................................................................................................................169
Interrupt Wake-up Function.......................................................................................................169
Programming Considerations....................................................................................................170
Low Voltage Detector – LVD............................................................................ 171
LVD Register.............................................................................................................................171
LVD Operation...........................................................................................................................172
Rev. 1.00
5
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
SCOM function for LCD.................................................................................... 173
LCD operation...........................................................................................................................173
LCD Bias Current Control.........................................................................................................173
Configuration Option........................................................................................ 176
Application Circuit............................................................................................ 176
Instruction Set................................................................................................... 177
Introduction...............................................................................................................................177
Instruction Timing......................................................................................................................177
Moving and Transferring Data...................................................................................................177
Arithmetic Operations................................................................................................................177
Logical and Rotate Operation...................................................................................................178
Branches and Control Transfer.................................................................................................178
Bit Operations...........................................................................................................................178
Table Read Operations.............................................................................................................178
Other Operations.......................................................................................................................178
Instruction Set Summary................................................................................. 179
Table Conventions.....................................................................................................................179
Instruction Definition........................................................................................ 181
Package Information........................................................................................ 190
16-pin NSOP (150mil) Outline Dimensions...............................................................................191
20-pin SOP (300mil) Outline Dimensions.................................................................................192
24-pin SOP (300mil) Outline Dimensions.................................................................................193
28-pin SOP (300mil) Outline Dimensions.................................................................................194
20-pin SSOP (150mil) Outline Dimensions...............................................................................195
24-pin SSOP (150mil) Outline Dimensions...............................................................................196
28-pin SSOP (150mil) Outline Dimensions...............................................................................197
Rev. 1.00
6
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Features
CPU Features
• Operating Voltage
♦♦
fSYS = 4MHz: 1.8V~5.5V
♦♦
fSYS = 8MHz: 2.0V~5.5V
♦♦
fSYS = 12MHz: 2.7V~5.5V
♦♦
fSYS = 16MHz: 3.3V~5.5V
• Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V
• Power down and wake-up functions to reduce power consumption
• Oscillators
♦♦
External Crystal – HXT
♦♦
External 32.768kHz Crystal – LXT
♦♦
Internal RC – HIRC
♦♦
Internal 32kHz RC – LIRC
• Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP
• Fully integrated internal 4/8/12MHz oscillator requires no external components
• All instructions executed in one or two instruction cycles
• Table read instructions
• 63 powerful instructions
• 8-level subroutine nesting
• Bit manipulation instruction
Peripheral Features
• Flash Program Memory: 2K×16 ~ 4K×16
• RAM Data Memory: 128×8 ~ 192×8
• EEPROM Memory: 64×8
• Watchdog Timer function
• Up to 26 bidirectional I/O lines
• Software controlled 4-SCOM lines LCD driver with 1/2 bias
• Source current selectable
• Two pin-shared external interrupts
• Multiple Timer Module for time measure, input capture, compare match output, PWM output or
single pulse output functions
• One Comparator function – only for the HT66F318
• UART and I2C Interfaces – only for the HT66F318
• Dual Time-Base functions for generation of fixed time interrupt signals
• 8-channel 12-bit resolution A/D converter
• Low voltage reset function
• Low voltage detect function
• Wide range of available package types
Rev. 1.00
7
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
General Description
The devices are Flash Memory type 8-bit high performance RISC architecture microcontrollers.
Offering users the convenience of Flash Memory multi-programming features, the devices also
include a wide range of functions and features. Other memory includes an area of RAM Data
Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial
numbers, calibration data etc.
Analog features include a multi-channel 12-bit A/D converter and a comparator functions. Multiple
and extremely flexible Timer Modules provide timing, pulse generation and PWM generation
functions. Communication with the outside world is catered for by including fully integrated I2C
and UART interface functions, two popular interfaces which provide designers with a means of easy
communication with external peripheral hardware. Protective features such as an internal Watchdog
Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and
ESD protection ensure that reliable operation is maintained in hostile electrical environments.
A full choice of HXT, LXT, HIRC and LIRC oscillator functions are provided including a fully
integrated system oscillator which requires no external components for its implementation. The
ability to operate and switch dynamically between a range of operating modes using different
clock sources gives users the ability to optimise microcontroller operation and minimize power
consumption.
The inclusion of flexible I/O programming features, Time-Base functions along with many other
features ensure that the devices will find excellent use in applications such as electronic metering,
environmental monitoring, handheld instruments, household appliances, electronically controlled
tools, motor driving in addition to many others.
Selection Table
Most features are common to these devices, the main features distinguishing them are Memory
capacity, I/O count, Timer types, comparator function, I2C function, UART function and the package
types. The following table summarises the main features of each device.
VDD
Program
Memory
Data
Memory
Data
EEPROM
HT66F317
1.8V~5.5V
2K×16
128×8
HT66F318
1.8V~5.5V
4K×16
192×8
Part No.
Part No.
Rev. 1.00
Timer Module Comparator UART
I/O
Ext.
Int.
A/D
LCD Driver
64×8
18
2
12-bit×8
4-SCOM
64×8
26
2
12-bit×8
4-SCOM
I2C
Time Base Stack
Package
HT66F317
10-bit PTM×2
—
—
—
2
8
16NSOP
20/24SOP/SSOP
HT66F318
16-bit CTM×1
10-bit PTM×1
16-bit STM×1
1
1
1
2
8
20/24/28SOP/SSOP
8
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Block Diagram
Watchdog
Timer
Low
Voltage
Detect
Flash/EEPROM
Programming Circ�itry
(ICP/OCDS)
EEPROM
Data
Memory
8-bit
RISC
MCU
Core
Low
Voltage
Reset
Flash
Program
Memory
Interr�pt
Controller
HXT/LXT
Oscillators
RAM
Data
Memory
HIRC/LIRC
Oscillators
1�-bit A/D
Converter
I/O
TMs
I�C
UART
Comparator
Time
Bases
SCOM
Only for HT66F318
Only for HT66F318
Pin Assignment
VSS/AVSS
1
16
VDD/AVDD
PC0/OSC1
�
1�
PB0/INT0/AN0/XT1
PC1/OSC�
3
14
PB1/INT1/AN1/XT�
PC�
4
13
PB�/TCK0/AN�
PA0/TP0/ICPDA/OCDSDA
�
1�
PA4/TCK1/AN3
PA1/SCOM0
6
11
PA�/AN4/VREF
PA�/ICPCK/OCDSCK
7
10
PA6/VREFO/AN�
PB�/SCOM3
8
9
PB3/[TP1]/AN7
HT66F317/HT66V317
16 NSOP-A
VSS/AVSS
1
�0
VDD/AVDD
PC0/OSC1
�
19
PB0/INT0/AN0/XT1
PC1/OSC�
3
18
PB1/INT1/AN1/XT�
PC�
4
17
PB�/TCK0/AN�
PA0/TP0/ICPDA/OCDSDA
�
16
PA4/TCK1/AN3
PA1/SCOM0
6
1�
PA�/AN4/VREF
PA�/ICPCK/OCDSCK
7
14
PA6/VREFO/AN�
PA3/SCOM1
8
13
PA7/TP1/AN6
PB6/SCOM�
9
1�
PB3/[TP1]/AN7
PB�/SCOM3
10
11
PB4/CLO
HT66F317/HT66V317
20 SOP-A/SSOP-A
Rev. 1.00
9
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
VSS/AVSS
1
�4
VDD/AVDD
PC0/OSC1
�
�3
PB0/INT0/AN0/XT1
PC1/OSC�
3
��
PB1/INT1/AN1/XT�
PC�
4
�1
PB�/TCK0/AN�
PC3
�
�0
PC6
PC4
6
19
PC�
PA0/TP0/ICPDA/OCDSDA
7
18
PA4/TCK1/AN3
PA1/SCOM0
8
17
PA�/AN4/VREF
PA�/ICPCK/OCDSCK
9
16
PA3/SCOM1
10
1�
PA7/TP1/AN6
PB6/SCOM�
11
14
PB3/[TP1]/AN7
PB�/SCOM3
1�
13
PB4/CLO
PA6/VREFO/AN�
HT66F317/HT66V317
24 SOP-A/SSOP-A
VSS/AVSS
1
�0
VDD/AVDD
PC0/OSC1
�
19
PB0/INT0/AN0/XT1
PC1/OSC�
3
18
PB1/INT1/AN1/XT�
PC�
4
17
PB�/TCK0/AN�
PA0/TP0/ICPDA/OCDSDA
�
16
PA4/TCK1/AN3
PA1/SCOM0
6
1�
PA�/AN4/VREF
PA�/ICPCK/OCDSCK
7
14
PA6/TCK�/VREFO/AN�
PA3/SCOM1/CX
8
13
PA7/TP1/AN6
PB6/SCOM�/C+
9
1�
PB3/TP�/AN7
PB�/SCOM3/C-
10
11
PB4/CLO
HT66F318/HT66V318
20 SOP-A/SSOP-A
VSS/AVSS
1
�4
VDD/AVDD
PC0/OSC1
�
�3
PB0/INT0/AN0/XT1
PC1/OSC�
3
��
PB1/INT1/AN1/XT�
PC�
4
�1
PB�/TCK0/AN�
PC3/TX
�
�0
PC6/SCL
PC4/RX
6
19
PC�/SDA
PA0/TP0/ICPDA/OCDSDA
7
18
PA4/TCK1/AN3
PA1/SCOM0
8
17
PA�/AN4/VREF
PA�/ICPCK/OCDSCK
9
16
PA6/TCK�/VREFO/AN�
PA3/SCOM1/CX
10
1�
PA7/TP1/AN6
PB6/SCOM�/C+
11
14
PB3/TP�/AN7
PB�/SCOM3/C-
1�
13
PB4/CLO
HT66F318/HT66V318
24 SOP-A/SSOP-A
Rev. 1.00
10
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
VSS/AVSS
1
�8
VDD/AVDD
PD0
�
�7
PB0/INT0/AN0/XT1
PD1
3
�6
PB1/INT1/AN1/XT�
PC0/OSC1
4
��
PB�/TCK0/AN�
PC1/OSC�
�
�4
PC6/SCL
PC�
6
�3
PC�/SDA
PC3/TX
7
��
PA4/TCK1/AN3
PC4/RX
8
�1
PA�/AN4/VREF
PA0/TP0/ICPDA/OCDSDA
9
�0
PA6/TCK�/VREFO/AN�
PA1/SCOM0
10
19
PA7/TP1/AN6
PA�/ICPCK/OCDSCK
11
18
PD3
PA3/SCOM1/CX
1�
17
PD�
PB6/SCOM�/C+
13
16
PB3/TP�/AN7
PB�/SCOM3/C-
14
1�
PB4/CLO
HT66F318/HT66V318
28 SOP-A/SSOP-A
Note: 1. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the
right side of the “/” sign can be used for higher priority.
2. VDD/AVDD means the VDD and AVDD are the double bonding.
3. VSS/AVSS means the VSS and AVSS are the double bonding.
4. The OCDSCK and OCDSDA pins are only for the EV chips.
Rev. 1.00
11
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Pin Description
With the exception of the power pins, all pins on the device can be referenced by its Port name,
e.g. PA0, PA1 etc, which refer to the digital I/O function of the pins. However these Port pins are
also shared with other function such as the Analog to Digital Converter, Timer Module pins etc.
The function of each pin is listed in the following table, however the details behind how each pin is
configured is contained in other sections of the datasheet.
As the Pin Description table shows the situation for the package with the most pins, not all pins in
the table will be available on smaller package sizes.
HT66F317
Pin Name
PA0/TP0/ICPDA/
OCDSDA
PA1/SCOM0
PA2/ICPCK/OCDSCK
PA3/SCOM1
PA4/TCK1/AN3
PA5/AN4/VREF
PA6/VREFO/AN5
PA7/TP1/AN6
PB0/INT0/AN0/XT1
Rev. 1.00
Function
OP
PA0
PAPU
PAWU
I/T
O/T
ST
General purpose I/O. Register enabled pull-high and
CMOS
wake-up.
Description
CMOS TM0 output
TP0
TMPC
ST
ICPDA
—
ST
CMOS ICP Address/Data
OCDSDA
—
ST
CMOS OCDS Address/Data, for EV chip only
PA1
PAPU
PAWU
ST
CMOS
SCOM0
SCOMC
—
SCOM LCD driver output for LCD panel common
PA2
PAPU
PAWU
ST
CMOS
General purpose I/O. Register enabled pull-high and
wake-up.
General purpose I/O. Register enabled pull-high and
wake-up.
ICPCK
—
ST
—
ICP Clock pin
OCDSCK
—
ST
—
OCDS Clock pin, for EV chip only
PA3
PAPU
PAWU
ST
CMOS
SCOM1
SCOMC
—
SCOM LCD driver output for LCD panel common
PA4
PAPU
PAWU
ST
CMOS
General purpose I/O. Register enabled pull-high and
wake-up.
General purpose I/O. Register enabled pull-high and
wake-up.
TCK1
TM1C0
ST
—
TM1 clock input
AN3
ACERL
AN
—
A/D channel 3
PA5
PAPU
PAWU
ST
General purpose I/O. Register enabled pull-high and
CMOS
wake-up.
AN4
ACERL
AN
—
A/D channel 4
VREF
SADC2
AN
—
A/D Converter reference voltage input pin
PA6
PAPU
PAWU
ST
CMOS
VREFO
SADC2
—
AN
A/D Converter reference output pin
AN5
ACERL
AN
—
A/D channel 5
PA7
PAPU
PAWU
ST
CMOS
CMOS TM1 output
General purpose I/O. Register enabled pull-high and
wake-up.
General purpose I/O. Register enabled pull-high and
wake-up.
TP1
TMPC
ST
AN6
ACERL
AN
PB0
PBPU
ST
INT0
INTC0
INTEG
ST
—
AN0
ACERL
AN
—
A/D channel 0
XT1
CO
LXT
—
Low frequency crystal pin
—
A/D channel 6
CMOS General purpose I/O. Register enabled pull-high.
12
External Interrupt 0
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Pin Name
PB1/INT1/AN1/XT2
PB2/TCK0/AN2
PB3/[TP1]/AN7
PB4/CLO
PB5/SCOM3
PB6/SCOM2
PC0/OSC1
PC1/OSC2
PC2~PC6
VDD/AVDD
VSS/AVSS
Function
OP
I/T
PB1
PBPU
ST
O/T
INT1
INTC2
INTEG
ST
AN1
ACERL
AN
—
XT2
CO
—
LXT
Description
CMOS General purpose I/O. Register enabled pull-high.
—
External Interrupt 1
A/D channel 1
Low frequency crystal pin
PB2
PBPU
ST
TCK0
TM0C0
ST
—
TM0 clock input
AN2
ACERL
AN
—
A/D channel 2
PB3
PBPU
ST
CMOS General purpose I/O. Register enabled pull-high.
TP1
TMPC
ST
CMOS TM1 output
AN7
ACERL
AN
PB4
PBPU
ST
CMOS General purpose I/O. Register enabled pull-high.
CLO
TMPC
ST
CMOS System clock output
PB5
PBPU
ST
CMOS General purpose I/O. Register enabled pull-high.
SCOM3
SCOMC
—
SCOM LCD driver output for LCD panel common
PB6
PBPU
ST
CMOS General purpose I/O. Register enabled pull-high.
SCOM2
SCOMC
—
SCOM LCD driver output for LCD panel common
PC0
PCPU
ST
CMOS General purpose I/O. Register enabled pull-high.
OSC1
CO
HXT
PC1
PCPU
ST
OSC2
CO
—
PC2~PC6
PCPU
ST
VDD
—
PWR
CMOS General purpose I/O. Register enabled pull-high.
—
—
A/D channel 7
HXT pin
CMOS General purpose I/O. Register enabled pull-high.
HXT
HXT pin
CMOS General purpose I/O. Register enabled pull-high.
—
Power Supply
AVDD
—
PWR
—
ADC Power Supply
VSS
—
PWR
—
Ground
AVSS
—
PWR
—
ADC Ground
Note: I/T: Input type; O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; CMOS: CMOS output; AN: Analog signal;
HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator
Rev. 1.00
13
ST: Schmitt Trigger input
SCOM: SCOM output
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
HT66F318
Pin Name
PA0/TP0/ICPDA/OCDSDA
PA1/SCOM0
PA2/ICPCK/OCDSCK
PA3/SCOM1/CX
PA4/TCK1/AN3
PA5/AN4/VREF
PA6/TCK2/VREFO/AN5
PA7/TP1/AN6
PB0/INT0/AN0/XT1
PB1/INT1/AN1/XT2
PB2/TCK0/AN2
PB3/TP2/AN7
Rev. 1.00
Function
OP
PA0
PAPU
PAWU
I/T
O/T
ST
General purpose I/O. Register enabled pull-high
CMOS
and wake-up.
Description
TP0
TMPC
ST
CMOS TM0 output
ICPDA
—
ST
CMOS ICP Address/Data
OCDSDA
—
ST
CMOS OCDS Address/Data, for EV chip only
PA1
PAPU
PAWU
ST
CMOS
SCOM0
SCOMC
—
SCOM LCD driver output for LCD panel common
PA2
PAPU
PAWU
ST
CMOS
General purpose I/O. Register enabled pull-high
and wake-up.
General purpose I/O. Register enabled pull-high
and wake-up.
ICPCK
—
ST
—
ICP Clock pin
OCDSCK
—
ST
—
OCDS Clock pin, for EV chip only
PA3
PAPU
PAWU
ST
CMOS
SCOM1
SCOMC
—
SCOM LCD driver output for LCD panel common
CX
CPC
—
CMOS Comparator output
PA4
PAPU
PAWU
ST
CMOS
General purpose I/O. Register enabled pull-high
and wake-up.
General purpose I/O. Register enabled pull-high
and wake-up.
TCK1
TM1C0
ST
—
TM1 clock input
AN3
ACERL
AN
—
A/D channel 3
PA5
PAPU
PAWU
ST
General purpose I/O. Register enabled pull-high
CMOS
and wake-up.
AN4
ACERL
AN
—
A/D channel 4
VREF
SADC2
AN
—
ADC reference voltage input pin
PA6
PAPU
PAWU
ST
CMOS
TCK2
TM2C0
ST
—
TM2 clock input
VREFO
SADC2
—
AN
A/D Converter reference output
AN5
ACERL
AN
—
A/D channel 5
PA7
PAPU
PAWU
ST
CMOS
CMOS TM1 output
General purpose I/O. Register enabled pull-high
and wake-up.
General purpose I/O. Register enabled pull-high
and wake-up.
TP1
TMPC
ST
AN6
ACERL
AN
PB0
PBPU
ST
INT0
INTC0
INTEG
ST
—
AN0
ACERL
AN
—
A/D channel 0
XT1
CO
LXT
—
Low frequency crystal pin
PB1
PBPU
ST
INT1
INTC2
INTEG
ST
AN1
ACERL
AN
—
XT2
CO
—
LXT
PB2
PBPU
ST
—
A/D channel 6
CMOS General purpose I/O. Register enabled pull-high.
External Interrupt 0
CMOS General purpose I/O. Register enabled pull-high.
—
External Interrupt 1
A/D channel 1
Low frequency crystal pin
CMOS General purpose I/O. Register enabled pull-high.
TCK0
TM0C0
ST
—
TM0 clock input
AN2
ACERL
AN
—
A/D channel 2
PB3
PBPU
ST
CMOS General purpose I/O. Register enabled pull-high.
CMOS TM2 output
TP2
TMPC
ST
AN7
ACERL
AN
—
14
A/D channel 7
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Pin Name
PB4/CLO
PB5/SCOM3/C-
PB6/SCOM2/C+
PC0/OSC1
PC1/OSC2
PC2
PC3/TX
PC4/RX
PC5/SDA
PC6/SCL
PD0~PD3
VDD/AVDD
VSS/AVSS
Function
OP
I/T
PB4
PBPU
ST
CMOS General purpose I/O. Register enabled pull-high.
O/T
CLO
TMPC
ST
CMOS System clock output
PB5
PBPU
ST
CMOS General purpose I/O. Register enabled pull-high.
SCOM3
SCOMC
—
SCOM LCD driver output for LCD panel common
C-
CPC
AN
PB6
PBPU
ST
CMOS General purpose I/O. Register enabled pull-high.
SCOM2
SCOMC
—
SCOM LCD driver output for LCD panel common
C+
CPC
AN
PC0
PCPU
ST
OSC1
CO
HXT
—
—
Description
Comparator input
Comparator input
CMOS General purpose I/O. Register enabled pull-high.
—
HXT pin
PC1
PCPU
ST
OSC2
CO
—
CMOS General purpose I/O. Register enabled pull-high.
PC2
PCPU
ST
CMOS General purpose I/O. Register enabled pull-high.
PC3
PCPU
ST
CMOS General purpose I/O. Register enabled pull-high.
TX
UCR1
UCR2
—
CMOS UART transmit line
PC4
PCPU
ST
CMOS General purpose I/O. Register enabled pull-high.
RX
UCR1
UCR2
ST
HXT
—
HXT pin
UART receive line
PC5
PCPU
ST
CMOS General purpose I/O. Register enabled pull-high.
SDA
IICC0
ST
NMOS I2C data line
PC6
PCPU
ST
CMOS General purpose I/O. Register enabled pull-high.
SCL
IICC0
ST
NMOS I2C clock line
PD0~PD3
PDPU
ST
CMOS General purpose I/O. Register enabled pull-high.
VDD
—
PWR
—
Power Supply
AVDD
—
PWR
—
ADC Power Supply
VSS
—
PWR
—
Ground
AVSS
—
PWR
—
ADC Ground
Note: I/T: Input type; O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; CMOS: CMOS output; NMOS: NCOM output;
AN: Analog signal;
HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator
Rev. 1.00
15
ST: Schmitt Trigger input
SCOM: SCOM output
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Absolute Maximum Ratings
Supply Voltage....................................................................................................VSS-0.3V to VSS+6.0V
Input Voltage...................................................................................................... VSS-0.3V to VDD+0.3V
Storage Temperature.......................................................................................................-50°C to 125°C
Operating Temperature..................................................................................................... -40°C to 85°C
IOL Total........................................................................................................................................ 80mA
IOH Total........................................................................................................................................ -80mA
Total Power Dissipation.............................................................................................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute
Maximum Ratings” may cause substantial damage to the device. Functional operation of this
device at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Symbol
VDD1
VDD2
Parameter
Operating Voltage
(HXT)
Operating Voltage
(HIRC)
Test Conditions
IDD1
─
5.5
V
─
5.5
V
fSYS=12MHz
2.7
─
5.5
V
fSYS=16MHz
3.3
─
5.5
V
fSYS=4MHz
1.8
─
5.5
V
─
fSYS=8MHz
2.0
─
5.5
V
fSYS=12MHz
2.7
─
5.5
V
3V
No load, fH=4MHz, ADC off,
WDT enable
─
0.7
1.1
mA
─
1.8
2.7
mA
─
1.2
1.2
mA
─
2.3
4.3
mA
─
1.7
2.7
mA
─
3.8
5.8
mA
─
4.8
7.3
mA
mA
─
3V
5V
3V
5V
3V
5V
3V
5V
3V
IDD3
5V
3V
5V
IDD4
Rev. 1.00
Operating Current, Slow Mode,
fSYS=fL=LIRC, fSUB=LIRC
Unit
1.8
3V
Operating Current, Slow Mode,
fSYS=fL=LXT, fSUB=LXT
Max.
2.0
5V
IDD2
Typ.
fSYS=8MHz
5V
Operating Current,
Normal Mode, fSYS=fH
(HIRC)
Min.
fSYS=4MHz
5V
Operating Current,
Normal Mode, fSYS=fH
(HXT)
Conditions
VDD
3V
5V
No load, fH=8MHz, ADC off,
WDT enable
No load, fH=12MHz, ADC off,
WDT enable
No load, fH=16MHz, ADC off,
WDT enable
─
1.0
2.3
─
1.5
4.3
mA
No load, fH=8MHz, ADC off,
WDT enable
─
2.0
2.8
mA
─
3.0
4.5
mA
No load, fH=12MHz, ADC off,
WDT enable
─
3.0
4.2
mA
─
4.5
6.7
mA
No load, fSYS=LXT, ADC off,
WDT enable, LXTLP=1
─
10
20
μA
─
30
50
μA
No load, fSYS=LXT, ADC off,
WDT enable, LXTLP=0
─
10
20
μA
─
40
60
μA
─
10
20
μA
─
30
50
μA
No load, fH=4MHz, ADC off,
WDT enable
No load, fSYS=LIRC, ADC off,
WDT enable
16
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Symbol
IDD5
IDD6
Parameter
Test Conditions
3V
Operating Current,
Normal Mode, fH=8MHz
(HIRC)
5V
Operating Current,
Normal Mode, fH=12MHz
(HXT)
5V
3V
5V
3V
3V
5V
3V
IIDLE01
IDLE0 Mode Standby Current
(LXT on)
5V
3V
5V
3V
IIDLE02
IDLE0 Mode Standby Current
(LIRC on)
5V
IIDLE11
IDLE1 Mode Standby Current
(HXT)
5V
IIDLE12
IDLE1 Mode Standby Current
(HXT)
3V
3V
5V
3V
5V
IIDLE12B
IDLE1 Mode Standby Current
(HIRC)
3V
5V
3V
5V
IIDLE13
IDLE1 Mode Standby Current
(HXT)
IIDLE14
IDLE1 Mode Standby Current
(HXT)
ISLEEP0
SLEEP0 Mode Standby Current
(LIRC off)
Min.
Typ.
Max.
Unit
No load, fSYS=fH/2,
ADC off, WDT enable
─
1.7
2.4
mA
─
2.6
4.4
mA
No load, fSYS=fH/64,
ADC off, WDT enable
─
1.2
1.6
mA
─
1.6
2.4
mA
No load, fSYS=fH/2,
ADC off, WDT enable
─
1.1
1.7
mA
─
2.8
4.1
mA
No load, fSYS=fH/64,
ADC off, WDT enable
─
0.67
0.91
mA
─
1.7
2.4
mA
No load, ADC off,
WDT enable, LXTLP=0
─
5
10
μA
─
16
32
μA
No load, ADC off,
WDT enable, LXTLP=1
─
5
10
μA
─
16
32
μA
No load, ADC off,
WDT enable, LVR disable
─
1.3
3.0
μA
─
2.2
5.0
μA
No load, ADC off,
WDT enable, fSYS=4MHz on
─
0.4
0.8
mA
─
0.8
1.6
mA
No load, ADC off,
WDT enable, fSYS=8MHz on
─
0.7
1.2
mA
─
1.3
2.3
mA
No load, ADC off,
WDT enable, fSYS=4MHz on
─
0.4
0.8
mA
─
0.5
1.0
mA
No load, ADC off,
WDT enable, fSYS=8MHz on
─
0.8
1.6
mA
─
1.0
2.0
mA
No load, ADC off,
WDT enable, fSYS=12MHz on
─
1.2
2.4
mA
─
1.5
3.0
mA
─
0.8
1.4
mA
─
1.5
2.7
mA
─
2.3
4.3
mA
No load, ADC off,
WDT disable, LVR disable
─
0.1
1.0
μA
─
0.3
2.0
μA
No load, ADC off,
WDT enable, LXTLP=1,
LVR disable
─
5
10
μA
─
16
32
μA
─
5
10
μA
─
15
30
μA
─
1.3
5.0
μA
─
2.2
10
μA
Conditions
VDD
3V
5V
5V
3V
5V
3V
No load, ADC off,
WDT enable, fSYS=12MHz on
No load, ADC off,
WDT enable, fSYS=16MHz on
ISLEEP11
SLEEP1 Mode Standby Current
(LXT on)
ISLEEP12
SLEEP1 Mode Standby Current
(LXT on)
5V
ISLEEP13
SLEEP1 Mode Standby Current
(LIRC on)
5V
VIL1
Input Low Voltage for I/O Ports or
Input Pins
5V
─
0
─
1.5
V
─
─
0
─
0.2VDD
V
Input High Voltage for I/O Ports
or Input Pins
5V
─
3.5
─
5.0
V
─
VIH1
5V
3V
3V
I/O Port Sink Current
Rev. 1.00
No load, ADC off,
WDT enable, LVR disable
0.8VDD
─
VDD
V
VOL=0.1VDD
7
14
─
mA
3V
VOL=0.1VDD
16
32
─
mA
5V
VOL=0.1VDD
32
64
─
mA
─
1.8V
IOL
No load, ADC off,
WDT enable, LXTLP=0,
LVR disable
17
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Symbol
IOH
RPH
IBIAS
VSCOM
Parameter
I/O Port Source Current
Pull-high Resistance for I/O Ports
1/2 bias current for LCD COM port
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
3V
VOH=0.9VDD, PxPS=00
-1.0
-2.0
─
mA
5V
VOH=0.9VDD, PxPS=00
-2.0
-4.0
─
mA
3V
VOH=0.9VDD, PxPS=01
-1.75
-3.5
─
mA
5V
VOH=0.9VDD, PxPS=01
-3.5
-7.0
─
mA
3V
VOH=0.9VDD, PxPS=10
-2.5
-5.0
─
mA
5V
VOH=0.9VDD, PxPS=10
-5.0
-10
─
mA
3V
VOH=0.9VDD, PxPS=11
-5.5
-11
─
mA
5V
VOH=0.9VDD, PxPS=11
-11
-22
─
mA
3V
LVPU=0
20
60
100
kΩ
5V
LVPU=0
10
30
50
kΩ
3V
LVPU=1
6.67
15
23
kΩ
5V
LVPU=1
3.5
7.5
12
kΩ
ISEL[1:0]=00
17.5
25.0
32.5
μA
ISEL[1:0]=01
35
50
65
μA
μA
5V
ISEL[1:0]=10
70
100
130
ISEL[1:0]=11
140
200
260
μA
0.475
0.5
0.525
VDD
1/2 bias voltage for LCD COM port 2.2V~5.5V No load
A.C. Characteristics
Ta=25°C
Symbol
fCPU
fSYS
Parameter
Operating Clock
System Clock (HXT)
Test Conditions
Min.
Typ.
Max.
Unit
1.8V~5.5V
DC
─
4
MHz
2.0V~5.5V
DC
─
8
MHz
MHz
Conditions
VDD
─
2.7V~5.5V
DC
─
12
3.3V~5.5V
DC
─
16
MHz
1.8V~5.5V
0.4
─
4
MHz
0.4
─
8
MHz
0.4
─
12
MHz
0.4
─
16
MHz
2.0V~5.5V
─
2.7V~5.5V
3.3V~5.5V
fHIRC
System Clock (HIRC)
fLIRC
System Clock (LIRC)
tTIMER
TCKn and Timer Capture Input
Pin Minimum Pulse Width
Rev. 1.00
3V/5V
Ta=25°C
-2%
4
+2%
MHz
3V/5V
Ta=25°C
-2%
8
+2%
MHz
5V
Ta=25°C
-2%
12
+2%
MHz
2.2V~3.6V
Ta=-40°C~85°C,
trim @3V, 4MHz
-5%
4
+5%
MHz
3.0V~5.5V
Ta=-40°C~85°C,
trim @5V, 4MHz
-5%
4
+5%
MHz
2.7V~3.6V
Ta=-40°C~85°C,
trim @3V, 8MHz
-10%
8
+10%
MHz
3.0V~5.5V
Ta=-40°C~85°C,
trim @5V, 8MHz
-5%
8
+5%
MHz
4.5V~5.5V
Ta=-40°C~85°C,
trim @5V, 12MHz
-3%
12
+3%
MHz
Ta = 25°C
-10%
32
+10%
kHz
Ta = -40°C to 85°C
-50%
32
+60%
kHz
0.3
─
─
μs
5V
2.2V~5.5V
─
─
18
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Symbol
Parameter
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
tINT
Interrupt Minimum Pulse Width
─
─
10
─
─
μs
tEERD
EEPROM Read Time
─
─
1
2
4
tSYS
tEEWR
EEPROM Write Time
─
tSST
tRSTD
1
2
4
ms
fSYS=fHXT ~ fHXT/64
─
512
─
─
tHXT
fSYS=fLXT
128
─
─
tLXT
fSYS=fHIRC ~ fHIRC/64
16
─
─
tHIRC
fSYS=fLIRC
2
─
─
tLRIC
System Start-up Timer Period
(Wake-up from HALT, fSYS off at
HALT state)
─
System Start-up Timer Period
(Wake-up from HALT, fSYS on at
HALT state)
─
─
─
2
─
tSYS
System Reset Delay Time
(Power On Reset, LVR Reset,
LVR S/W reset (LVRC),
WDT S/W reset (WDTC))
─
─
25
50
100
ms
System Reset Delay Time
(WDT normal reset)
─
─
8.3
16.7
33.3
ms
Note: 1. tSYS=1/fSYS
2.To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
A/D Converter Electrical Characteristics
Ta=25°C
Symbol
AVDD
VADI
VREF
VBG
Parameter
A/D Converter Operating Voltage
A/D Converter Input Voltage
A/D Converter Reference Voltage
Reference Voltage with Buffer Voltage
Test Conditions
VDD
Conditions
─
─
Min.
Typ.
Max.
Unit
1.8
─
5.5
V
V
─
─
0
─
AVDD/
VREF
1.8V
─
1.8
─
AVDD
V
3V
─
1.8
─
AVDD
V
5V
─
1.8
─
AVDD
V
3V
─
-5%
1.0
+5%
V
-3
─
+3
LSB
-4
─
+4
LSB
1.8V VREF=AVDD=VDD, tADCK=2.0μs
DNL
Differential Non-linearity
3V
5V
VREF=AVDD=VDD, tADCK=0.5μs
1.8V VREF=AVDD=VDD, tADCK=2.0μs
INL
Differential Non-linearity
3V
5V
VREF=AVDD=VDD, tADCK=0.5μs
IADC
Additional Power Consumption if A/D
Converter is used
3V
tADCK
A/D Converter Clock Period
─
tADC
A/D Conversion Time
(Include Sample and Hold Time)
─
tADS
A/D Converter Sampling Time
─
─
─
tON2ST
A/D Converter On-to-Start Time
─
─
2
tBGS
VBG Turn on Stable Time
─
─
200
─
5V
No load (tADCK=0.5μs)
─
1.0
2.0
mA
─
1.5
3.0
mA
1.8V ≤ VDD ≤ 2.0V
2.0
─
10
μs
2.0V ≤ VDD ≤ 5.5V
0.5
─
10
μs
12-bit A/D Converter
16
─
20
tADCK
4
─
tADCK
─
─
μs
─
μs
Note: ADC conversion time (tADC) = n (bits ADC) + 4 (sampling time), the conversion for each bit needs one ADC
clock (tADCK).
Rev. 1.00
19
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
LVD & LVR Electrical Characteristics
Ta=25˚C
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
VLVR1
LVR Enable, 1.7V option
1.7
VLVR2
LVR Enable, 1.9V option
1.9
VLVR3
Low Voltage Reset Voltage
—
LVR Enable, 2.55V option
-5%
2.55
Max.
Unit
V
V
+5%
V
VLVR4
LVR Enable, 3.15V option
3.15
VLVR5
LVR Enable, 3.8V option
3.8
V
VLVD1
LVDEN=1, VLVD=1.8V
1.8
V
VLVD2
LVDEN=1, VLVD=2.0V
2.0
V
VLVD3
LVDEN=1, VLVD=2.4V
2.4
V
VLVD4
LVDEN=1, VLVD=2.7V
2.7
VLVD5
Low Voltage Detector Voltage
—
LVDEN=1, VLVD=3.0V
-5%
3.0
V
+5%
V
V
VLVD6
LVDEN=1, VLVD=3.3V
3.3
V
VLVD7
LVDEN=1, VLVD=3.6V
3.6
V
VLVD8
LVDEN=1, VLVD=4.0V
4.0
ILVR
Additional Power Consumption
if LVR is Used
3V
5V
3V
ILVD
Additional Power Consumption
if LVD is Used
5V
3V
5V
LVR disable → LVR enable
V
—
6
8
μA
—
10
15
μA
LVD disable → LVD enable
(LVR disable)
—
6
8
μA
—
10
15
μA
LVD disable → LVD enable
(LVR enable)
—
6
8
μA
—
10
15
μA
tLVR
Low Voltage Width to Reset
—
—
120
240
480
μs
tLVD
Low Voltage Width to Interrupt
—
—
60
120
240
μs
—
—
15
μs
—
—
150
μs
45
90
120
μs
tLVDS
LVDO Stable Time
tSRESET
Software Reset Width to Reset
Rev. 1.00
—
LVR enable, LVD off → on
—
LVR disable, LVD off → on
—
—
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HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Comparator Electrical Characteristics – HT66F318
Ta=25°C
Symbol
VCMP
Test Conditions
Parameter
Comparator Operating Voltage
VDD
Conditions
─
─
3V
─
Min.
Typ.
Max.
Unit
1.8
─
5.5
V
─
37
56
μA
ICMP
Comparator Operating Current
5V
─
─
130
200
μA
VCMPOS
Comparator Input Offset Voltage
─
─
-10
─
+10
mV
VHYS
Hysteresis Width
─
20
40
60
mV
VCM
Comparator Common Mode
Voltage Range
─
VDD>2.0V
VSS+0.2
─
VDD-1.4
V
─
VDD=1.8V~2.0V
VSS+0.2
─
VDD-1.0
V
AOL
Comparator Open Loop Gain
─
60
80
─
dB
tPD
Comparator Response Time
─
─
370
560
ns
─
─
With 100mV overdrive(Note)
Note: Measured with comparator one input pin at VCM=(VDD-1.4)/2 while the other pin input transition from VSS to
(VCM+100mV) or from VDD to (VCM-100mV).
Power-on Reset Characteristics
Ta=25°C
Symbol
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to Ensure Power-on Reset
—
—
—
—
100
mV
RRVDD
VDD Raising Rate to Ensure Power-on Reset
—
—
0.035
—
—
V/ms
tPOR
Minimum Time for VDD Stays at VPOR to
Ensure Power-on Reset
—
—
1
—
—
ms
tPOR
RRVDD
VDD
VPOR
Rev. 1.00
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System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to
their internal system architecture. The range of the device take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance.
The pipelining scheme is implemented in such a way that instruction fetching and instruction
execution are overlapped, hence instructions are effectively executed in one cycle, with the
exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set
operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement,
branch decisions, etc. The internal data path is simplified by moving data through the Accumulator
and the ALU. Certain internal registers are implemented in the Data Memory and can be directly
or indirectly addressed. The simple addressing methods of these registers along with additional
architectural features ensure that a minimum of external components is required to provide a
functional I/O and A/D control system with maximum reliability and flexibility. This makes the
devices suitable for low-cost, high-volume production for controller applications.
Clocking and Pipelining
The main system clock, derived from either a HXT, LXT, HIRC or LIRC oscillator is subdivided
into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented
at the beginning of the T1 clock during which time a new instruction is fetched. The remaining
T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock
cycle forms one instruction cycle. Although the fetching and execution of instructions takes place
in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that
instructions are effectively executed in one instruction cycle. The exception to this are instructions
where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which
case the instruction will take one more instruction cycle to execute.
fSYS
(System Clock)
Phase Clock T1
Phase Clock T�
Phase Clock T3
Phase Clock T4
Program Co�nter
Pipelining
PC
PC+1
PC+�
Fetch Inst. (PC)
Exec�te Inst. (PC-1)
Fetch Inst. (PC+1)
Exec�te Inst. (PC)
Fetch Inst. (PC+�)
Exec�te Inst. (PC+1)
System Clocking and Pipelining
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
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Enhanced A/D Type 8-Bit MCU with LCD Driver
1
MOV A�[1�H]
�
CALL DELAY
3
CPL [1�H]
4
:
�
:
6 DELAY: NOP
Fetch Inst. 1
Exec�te Inst. 1
Fetch Inst. �
Exec�te Inst. �
Fetch Inst. 3
Fl�sh Pipeline
Fetch Inst. 6
Exec�te Inst. 6
Fetch Inst. 7
Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the next
instruction to be executed. It is automatically incremented by one each time an instruction is ex­
ecuted except for instructions, such as “JMP” or “CALL” that demands a jump to a non-consecutive
Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are
directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is
obtained.
Device
Program Counter
Program Counter High Byte
HT66F317
PC10~PC8
HT66F318
PC11~PC8
PCL Register
PCL7~PCL0
Program Counter
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly. However, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory, that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is
needed to pre-fetch.
Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack is organized into 8 levels and neither part of the data nor part of the program space,
and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is
neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of
the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value
from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still
be executed which will result in a stack overflow. Precautions should be taken to avoid such cases
which might cause unpredictable program branching.
If the stack is overflow, the first Program Counter save in the stack will be lost.
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Enhanced A/D Type 8-Bit MCU with LCD Driver
Program Co�nter
Top of Stack
Stack Level 1
Stack Level �
Stack
Pointer
Stack Level 3
Bottom of Stack
Stack Level 8
:
:
:
Program Memory
Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
• Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
• Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
• Increment and Decrement: INCA, INC, DECA, DEC
• Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
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Enhanced A/D Type 8-Bit MCU with LCD Driver
Flash Program Memory
The Program Memory is the location where the user code or program is stored. For this device series
the Program Memory is Flash type, which means it can be programmed and re-programmed a large
number of times, allowing the user the convenience of code modification on the same device. By
using the appropriate programming tools, the Flash device offer users the flexibility to conveniently
debug and develop their applications while also offering a means of field programming and
updating.
Structure
The Program Memory has a capacity of 2K×16 ~ 4K×16 bits. The Program Memory is addressed
by the Program Counter and also contains data, table information and interrupt entries. Table data,
which can be setup in any location within the Program Memory, is addressed by a separate table
pointer register.
Device
Capacity
HT66F317
2K×16
HT66F318
4K×16
000H
004H
HT66F317
HT66F318
Reset
Reset
Interr�pt Vector
Interr�pt Vector
0�4H
0�CH
7FFH
16 bits
FFFH
16 bits
Program Memory Structure
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location
000H is reserved for use by the device reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
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Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the address
of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers
define the total address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory using
the “TABRD [m]” or “TABRDL [m]” instructions, respectively. When the instruction is executed,
the lower order table byte from the Program Memory will be transferred to the user defined
Data Memory register [m] as specified in the instruction. The higher order table data byte from
the Program Memory will be transferred to the TBLH special register. Any unused bits in this
transferred higher order byte will be read as “0”.
The accompanying diagram illustrates the addressing data flow of the look-up table.
Program Memory
Address
Last Page or
TBHP Register
TBLP Register
Data
16 bits
Register TBLH
User Selected
Register
High Byte
Low Byte
Table Program Example
The following example shows how the table pointer and table data is defined and retrieved from the
microcontroller. This example uses raw table data located in the Program Memory which is stored
there using the ORG statement. The value at this ORG statement is “700H” which refers to the start
address of the last page within the 2K Program Memory of the HT66F317. The table pointer low
byte register is setup here to have an initial value of “06H”. This will ensure that the first data read
from the data table will be at the Program Memory address “706H” or 6 locations after the start of
the last page. Note that the value for the table pointer is referenced to the address specified by the
TBHP and TBLP registers if the “TABRD [m]” instruction is being used. The high byte of the table
data which in this case is equal to zero will be transferred to the TBLH register automatically when
the “TABRD [m]” instruction is executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
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Enhanced A/D Type 8-Bit MCU with LCD Driver
Table Read Program Example
tempreg1 db? ; temporary register #1
tempreg2 db? ; temporary register #2
:
mov a, 06h ; initialise low table pointer - note that this address is referenced
mov tblp, a ; to the last page or specific page
mov a, 07h ; initialise high table pointer
mov tbhp, a
:
tabrd tempreg1 ; transfers value in table referenced by table pointer to tempreg1
; data at program memory address 706H transferred to tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
tabrd tempreg2 ; transfers value in table referenced by table pointer
; data at program memory address 705H transferred to tempreg2 and TBLH
; in this example the data 1AH is transferred to tempreg1 and data 0FH
; to register tempreg2 the value 00H will be transferred to the high
; byte register TBLH
:
org 700h; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
In Circuit Programming – ICP
The provision of Flash type Program Memory provides the user with a means of convenient and easy
upgrades and modifications to their programs on the same device. As an additional convenience,
Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface.
This provides manufacturers with the possibility of manufacturing their circuit boards complete with
a programmed or un-programmed microcontroller, and then programming or upgrading the program
at a later stage. This enables product manufacturers to easily keep their manufactured products
supplied with the latest program releases without removal and re-insertion of the device.
The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows:
Holtek Writer Pins
MCU Programming Pins
ICPDA
PA0
Programming Serial Data/Address
Pin Description
ICPCK
PA2
Programming Clock
VDD
VDD
Power Supply
VSS
VSS
Ground
The Program Memory and EEPROM data Memory can both be programmed serially in-circuit using
this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional
line for the clock. Two additional lines are required for the power supply. The technical details
regarding the in-circuit programming of the device are beyond the scope of this document and will
be supplied in supplementary literature.
During the programming process, taking control of the ICPDA and ICPCK pins for data and clock
programming purposes. The user must there take care to ensure that no other outputs are connected
to these two pins.
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Enhanced A/D Type 8-Bit MCU with LCD Driver
W r ite r C o n n e c to r
S ig n a ls
M C U
W r ite r _ V D D
V D D
IC P D A
P A 0
IC P C K
P A 2
W r ite r _ V S S
V S S
*
P r o g r a m m in g
P in s
*
T o o th e r C ir c u it
Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance
of * must be less than 1nF.
On-Chip Debug Support – OCDS
There are two EV chips named HT66V317 and HT66V318 which are used to emulate the HT66F317
and HT66F318 repectively. Each EV chip device also provides an “On-Chip Debug” function to
debug the corresponding MCU device during the development process. The EV chip and the actual
MCU device are almost functionally compatible except for the “On-Chip Debug” function. Users
can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA
and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/
Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the
EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in
the actual MCU device will have no effect in the EV chip. However, the two OCDS pins which are
pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for
ICP. For a more detailed OCDS description, refer to the corresponding document named “Holtek
e-Link for 8-bit MCU OCDS User’s Guide”.
Rev. 1.00
Holtek e-Link Pins
EV Chip Pins
OCDSDA
OCDSDA
On-chip Debug Support Data/Address input/output
Pin Description
OCDSCK
OCDSCK
On-chip Debug Support Clock input
VDD
VDD
Power Supply
VSS
VSS
Ground
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Enhanced A/D Type 8-Bit MCU with LCD Driver
RAM Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored.
Structure
Divided into two areas, the first of these is an area of RAM, known as the Special Function Data
Memory. Here are located registers which are necessary for correct operation of the devices. Many
of these registers can be read from and written to directly under program control, however, some
remain protected from user manipulation. The second area of Data Memory is known as the General
Purpose Data Memory, which is reserved for general purpose use. All locations within this area are
read and write accessible under program control.
The overall Data Memory is subdivided into two banks, the structure of which depends upon
the device chosen. The Special Purpose Data Memory registers are accessible in all banks, with
the exception of the EEC register at address 40H, which is only accessible in Bank 1. Switching
between the different Data Memory banks is achieved by setting the Bank Pointer to the correct
value. The start address of the Data Memory for the devices is the address 00H.
Device
Capacity
Banks
HT66F317
128×8
0: 80H~FFH
HT66F318
192×8
0: A0H~FFH
1: A0H~FFH
General Purpose Data Memory
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Enhanced A/D Type 8-Bit MCU with LCD Driver
   
   
   
   
        
   
HT66F317 Special Purpose Data Memory
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   
      
HT66F318 Special Purpose Data Memory
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Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional sections,
however several registers require a separate description in this section.
Indirect Addressing Register – IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM
register space, do not actually physically exist as normal registers. The method of indirect addressing
for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in
contrast to direct memory addressing, where the actual memory address is specified. Actions on the
IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather
to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can
access data from any bank. As the Indirect Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the
registers indirectly will result in no operation.
Memory Pointers – MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be manipulated in the same way as normal
registers providing a convenient way with which to address and track data. When any operation to
the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller
is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to
access data from all banks according to BP register. Direct Addressing can only be used with Bank 0,
all other Banks must be addressed indirectly using MP1 and IAR1.
The following example shows how to clear a section of four Data Memory locations already defined
as locations adres1 to adres4.
Indirect Addressing Program Example
data.section ‘data’
adres1 db?
adres2 db?
adres3 db?
adres4 db?
block db?
code.section at 0 code
org 00h
start:
mov a, 04h; setup size of block
mov block, a
mov a, offset adres1 ; Accumulator loaded with first RAM address
mov mp0, a ; setup memory pointer with first RAM address
loop:
clr IAR0 ; clear the data at address defined by MP0
inc mp0; increment memory pointer
sdz block ; check if last memory location has been cleared
jmp loop
continue:
The important point to note here is that in the example shown above, no reference is made to specific
Data Memory addresses.
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Bank Pointer – BP
For these devices, the Data Memory is divided into two banks, Bank0 and Bank1. Selecting the
required Data Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer is used to
select Data Memory Banks 0~1.
The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the
SLEEP or IDLE Modes, in which case, the Data Memory bank remains unaffected. It should be
noted that the Special Function Data Memory is not affected by the bank selection, which means that
the Special Function Registers can be accessed from within any bank. Directly addressing the Data
Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer.
Accessing data from Bank1 must be implemented using Indirect Addressing.
BP Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
DMBP0
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
Bit 7~1
Unimplemented, read as “0”
Bit 0DMBP0: Select Data Memory Banks
0: Bank 0
1: Bank 1
Accumulator – ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator, for example, when transferring data between
one user defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register – PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Look-up Table Registers – TBLP, TBHP, TBLH
These three special function registers are used to control operation of the look-up table which is
stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location
where the table data is located. Their value must be setup before any table read commands are
executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing
for easy table data pointing and reading. TBLH is the location where the high order byte of the table
data is stored after a table read data instruction has been executed. Note that the lower order table
data byte is transferred to a user defined location.
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Status Register – STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation
and system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing
the “HALT” or “CLR WDT” instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
• C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
• PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by
executing the “HALT” instruction.
• TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is
set by a WDT time-out.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the subroutine can corrupt the status register, precautions must be taken to correctly save it.
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STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
TO
PDF
OV
Z
AC
C
R/W
—
—
R
R
R/W
R/W
R/W
R/W
POR
—
—
0
0
x
x
x
x
“x” unknown
Bit 7~6
Unimplemented, read as “0”
Bit 5TO: Watchdog Time-Out flag
0: After power up or executing the “CLR WDT” or “HALT” instruction
1: A watchdog time-out occurred.
Bit 4PDF: Power down flag
0: After power up or executing the “CLR WDT” instruction
1: By executing the “HALT” instruction
Bit 3OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Bit 2Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1AC: Auxiliary flag
0: No auxiliary carry
1: An operation results in a carry out of the low nibbles in addition, or no borrow
from the high nibble into the low nibble in subtraction
Bit 0C: Carry flag
0: No carry-out
1: An operation results in a carry during an addition operation or if a borrow does
not take place during a subtraction operation
C is also affected by a rotate through carry instruction.
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EEPROM Data memory
These devices contain an area of internal EEPROM Data Memory. EEPROM, which stands for
Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form
of re-programmable memory, with data retention even when its power supply is removed. By
incorporating this kind of data memory, a whole new host of application possibilities are made
available to the designer. The availability of EEPROM storage allows information such as product
identification numbers, calibration values, specific user data, system setup data or other product
information to be stored directly within the product microcontroller. The process of reading and
writing data to the EEPROM memory has been reduced to a very trivial affair.
EEPROM Data Memory Structure
The EEPROM Data Memory capacity is 64×8 bits for these devices. Unlike the Program Memory
and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space
and is therefore not directly addressable in the same way as the other types of memory. Read and
Write operations to the EEPROM are carried out in single byte operations using an address and data
register in Bank 0 and a single control register in Bank 1.
Device
Capacity
Address
HT66F317/HT66F318
64×8
00H~3FH
EEPROM Registers
Three registers control the overall operation of the internal EEPROM Data Memory. These are the
address register, EEA, the data register, EED and a single control register, EEC. As both the EEA
and EED registers are located in Bank 0, they can be directly accessed in the same was as any other
Special Function Register. The EEC register however, being located in Bank1, cannot be directly
addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer
and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H
in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register,
BP, set to the value, 01H, before any operations on the EEC register are executed.
Bit
Register
Name
7
6
5
4
3
2
1
0
EEA
—
—
D5
D4
D3
D2
D1
D0
EED
D7
D6
D5
D4
D3
D2
D1
D0
EEC
—
—
—
—
WREN
WR
RDEN
RD
2
1
0
EEPROM Register List
EEA Register
Bit
7
6
Name
—
—
D5
D4
D3
D2
D1
D0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
5
4
3
Unimplemented, read as “0”
Bit 5~0D5~D0: Data EEPROM address
Data EEPROM address bit 5 ~ bit 0
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EED Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: Data EEPROM data
Data EEPROM data bit 7 ~ bit 0
EEC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
WREN
WR
RDEN
RD
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as “0”
Bit 3WREN: Data EEPROM Write Enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data
EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM write operations.
Bit 2WR: EEPROM Write Control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application
program will activate a write cycle. This bit will be automatically reset to zero by the
hardware after the write cycle has finished. Setting this bit high will have no effect if
the WREN has not first been set high.
Bit 1RDEN: Data EEPROM Read Enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM read operations.
Bit 0RD: EEPROM Read Control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application
program will activate a read cycle. This bit will be automatically reset to zero by the
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: The WREN, WR, RDEN and RD can not be set to “1” at the same time in one instruction. The
WR and RD can not be set to “1” at the same time.
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Reading Data from the EEPROM
To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set
high to enable the read function. The EEPROM address of the data to be read must then be placed
in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated.
Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When
the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can
be read from the EED register. The data will remain in the EED register until another read or write
operation is executed. The application program can poll the RD bit to determine when the data is
valid for reading.
Writing Data to the EEPROM
The EEPROM address of the data to be written must first be placed in the EEA register and the data
placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC
register must first be set high to enable the write function. After this, the WR bit in the EEC register
must be immediately set high to initiate a write cycle. These two instructions must be executed
consecutively. The global interrupt bit EMI should also first be cleared before implementing any
write operations, and then set again after the write cycle has started. Setting the WR bit high will not
initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled
using an internal timer whose operation is asynchronous to microcontroller system clock, a certain
time will elapse before the data will have been written into the EEPROM. Detecting when the write
cycle has finished can be implemented either by polling the WR bit in the EEC register or by using
the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared
to zero by the microcontroller, informing the user that the data has been written to the EEPROM.
The application program can therefore poll the WR bit to determine when the write cycle has ended.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered-on the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data
Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a
further measure of protection against spurious write operations. During normal program operation,
ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect
write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However as
the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt
enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its
associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function
Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag
will be automatically reset, the EEPROM interrupt flag must be manually reset by the application
program. More details can be obtained in the Interrupt section.
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Programming Considerations
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be
enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also
the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where
the EEPROM control register exist. Although certainly not necessary, consideration might be given
in the application program to the checking of the validity of new write data by a simple read back
process. When writing data the WR bit must be set high immediately after the WREN bit has been
set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be
cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that
the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is
totally complete. Otherwise, the EEPROM read or write operation will fail.
Programming Examples
Reading data from the EEPROM – polling method
MOV A, EEPROM_ADRES MOV EEA, A
MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A
SET IAR1.1 SET IAR1.0
BACK:
SZ IAR1.0 JMP BACK
CLR IAR1 CLR BP
MOV A, EED
MOV READ_DATA, A
; user defined address
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
; set RDEN bit, enable read operations
; start Read Cycle - set RD bit
; check for read cycle end
; disable EEPROM read/write
; move read data to register
Writing Data to the EEPROM – polling method
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, EEPROM_DATA MOV EED, A
MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A
CLR EMI
SET IAR1.3
SET IAR1.2
SET EMI
BACK:
SZ IAR1.2 JMP BACK
CLR IAR1 CLR BP
Rev. 1.00
; user defined address
; user defined data
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
; set WREN bit, enable write operations
; start Write Cycle - set WR bit
; check for write cycle end
; disable EEPROM read/write
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Oscillator
Various oscillator options offer the user a wide range of functions according to their various
application requirements. The flexible features of the oscillator functions ensure that the best
optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation
are selected through a combination of configuration options and registers.
Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external
components as well as fully integrated internal oscillators, requiring no external components,
are provided to form a wide range of both fast and slow system oscillators. All oscillator options
are selected through the configuration options. The higher frequency oscillators provide higher
performance but carry with it the disadvantage of higher power requirements, while the opposite
is of course true for the lower frequency oscillators. With the capability of dynamically switching
between fast and slow system clock, the devices have the flexibility to optimise the performance/
power ratio, a feature especially important in power sensitive portable applications.
Name
Freq.
Pins
External Crystal
Type
HXT
400kHz~16MHz
OSC1/OSC2
Internal High Speed RC
HIRC
4, 8, 12MHz
—
External Low Speed Crystal
LXT
32.768kHz
XT1/XT2
Internal Low Speed RC
LIRC
32kHz
—
Oscillator Types
System Clock Configurations
There are four methods of generating the system clock, two high speed oscillators and two low
speed oscillators. The high speed oscillators are the external crystal/ceramic oscillator - HXT and the
internal 4MHz, 8MHz, 12MHz RC oscillator - HIRC. The two low speed oscillators are the internal
32kHz RC oscillator - LIRC and the external 32.768kHz crystal oscillator - LXT. Selecting whether
the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit
and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected.
The actual source clock used for each of the high speed and low speed oscillators is chosen
via configuration options. The frequency of the slow speed or high speed system clock is also
determined using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. Note that two
oscillator selections must be made namely one high speed and one low speed system oscillators. It is
not possible to choose a no-oscillator selection for either the high or low speed oscillator. The OSC1/
OSC2 and XT1/XT2 pins are used to connect the external components for the external crystal.
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High Speed Oscillator
HXT
fH
6-stage Prescaler
HIRC
fH/�
fH/4
fH/8
fH/16
fH/3�
fH/64
High Speed Oscillator
Config�ration Option
fSYS
fL
Low Speed Oscillator
LXT
Fast Wake-�p from SLEEP
Mode or IDLE Mode Control
(for HXT only)
HLCLK�
CKS�~CKS0 bits
fSUB
LIRC
Low speed Oscillator
Config�ration Option
System Clock Configurations
External Crystal/Ceramic Oscillator – HXT
The External Crystal/Ceramic System Oscillator is one of the high frequency oscillator choices,
which is selected via configuration option. For most crystal oscillator configurations, the simple
connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for
oscillation, without requiring external capacitors. However, for some crystal types and frequencies,
to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a
ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as
shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the
crystal or resonator manufacturer’s specification.
For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure
that the crystal and any associated resistors and capacitors along with interconnecting lines are all
located as close to the MCU as possible.
     Crystal/Resonator Oscillator – HXT
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Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
12MHz
0pF
0pF
8MHz
0pF
0pF
4MHz
0pF
0pF
1MHz
100pF
100pF
Note: C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
Internal RC Oscillator – HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has three fixed frequencies of 4MHz, 8MHz, 12MHz. Device trimming
during the manufacturing process and the inclusion of internal frequency compensation circuits are
used to ensure that the influence of the power supply voltage, temperature and process variations on
the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a
temperature of 25°C degrees, the fixed oscillation frequency of 4MHz, 8MHz or 12MHz will have
a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no
external pins for its operation, PC0 and PC1 are free for use as normal I/O pins.
External 32.768kHz Crystal Oscillator – LXT
The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices,
which is selected via configuration option. This clock source has a fixed frequency of 32.768kHz
and requires a 32.768kHz crystal to be connected between pins XT1 and XT2. The external resistor
and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation.
For applications where precise frequencies are essential, these components may be required to
provide frequency compensation due to different crystal manufacturing tolerances. During power-up
there is a time delay associated with the LXT oscillator waiting for it to start-up.
When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop
microcontroller activity and to conserve power. However, in many microcontroller applications
it may be necessary to keep the internal timers operational even when the microcontroller is in
the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be
provided.
However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary
to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should
be selected in consultation with the crystal or resonator manufacturer specification. The external
parallel feedback resistor, RP, is required.
Some configuration options determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O
pins or other pin-shared functional pins.
• If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/
O or other pin-shared functional pins.
• If the LXT oscillator is used for any clock source, the 32.768kHz crystal should be connected to
the XT1/XT2 pins.
For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure
that the crystal and any associated resistors and capacitors along with interconnecting lines are all
located as close to the MCU as possible.
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‚   
­ €
  ‚  External LXT Oscillator
LXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
32.768kHz
10pF
10pF
Note: 1. C1 and C2 values are for guidance only.
2. RP=5M~10MΩ is recommended.
32.768kHz Crystal Recommended Capacitor Values
LXT Oscillator Low Power Function
The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power
Mode. The mode selection is executed using the LXTLP bit in the TBC register.
LXTLP Bit
LXT Mode
0
Quick Start
1
Low-power
After power on, the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator
is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up
and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed
into the Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but
with reduced current consumption, as the higher current consumption is only required during the
LXT oscillator start-up. In power sensitive applications, such as battery applications, where power
consumption must be kept to a minimum, it is therefore recommended that the application program
sets the LXTLP bit high about 2 seconds after power-on.
It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will
always function normally, the only difference is that it will take more time to start up if in the Lowpower mode.
Internal 32kHz Oscillator – LIRC
The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is
selected via configuration option. It is a fully integrated RC oscillator with a typical frequency of
32kHz at 5V, requiring no external components for its implementation. Device trimming during
the manufacturing process and the inclusion of internal frequency compensation circuits are used
to ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of
25°C degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%.
Supplementary Oscillators
The low speed oscillators, in addition to providing a system clock source are also used to provide
a clock source to other device functions. These are the Watchdog Timer, Time Base Interrupts and
Timer Modules.
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Operating Modes and System Clocks
Present day applications require that their microcontrollers have high performance but often still
demand that they consume as little power as possible, conflicting requirements that are especially
true in battery powered portable applications. The fast clocks required for high performance will
by their nature increase current consumption and of course vice-versa, lower speed clocks reduce
current consumption. As Holtek has provided the devices with both high and low speed clock
sources and the means to switch between them dynamically, the user can optimise the operation of
their microcontroller to achieve the best performance/power ratio.
System Clocks
The devices have many different clock sources for both the CPU and peripheral function operation.
By providing the user with a wide range of clock options using configuration options and register
programming, a clock system can be configured to obtain maximum application performance.
The main system clock, can come from either a high frequency fH or low frequency fSUB source, and
is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system
clock can be sourced from either an HXT or HIRC oscillator, selected via a configuration option.
The low speed system clock source can be sourced from internal clock fSUB. If fSUB is selected then it
can be sourced by either the LXT or LIRC oscillator, selected via a configuration option. The other
choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64.
There are two additional internal clocks for the peripheral circuits, the substitute clock, fSUB, and
the Time Base clock, fTBC. Each of these internal clocks is sourced by either the LXT or LIRC
oscillators, selected via configuration options. The fSUB clock is used to provide a substitute clock for
the microcontroller just after a wake-up has occurred to enable faster wake-up times.
High Speed
Oscillator
HXT
fH
6-stage Prescaler
HIRC
fH/�
fH/4
fH/8
fH/16
fH/3�
fH/64
High Speed Oscillator
Config�ration Option
Low Speed
Oscillator
LXT
fSYS
fSUB
LIRC
HLCLK�
CKS�~CKS0 bits
Low Speed Oscillator
Config�ration Option
fSUB
fSYS/4
fTB
fTBC
Fast Wake-�p from
SLEEP or IDLE Mode
Control (for HXT only)
Time Base
TBCK
fS
Watchdog Timer
Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation will
stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use.
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System Operation Modes
There are six different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance and
power requirements of the application. There are two modes allowing normal operation of the
microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0,
SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to
conserve power.
Operating Mode
Description
CPU
fSYS
fSUB
fS
NORMAL Mode
on
fH~fH/64
on
on
fTBC
on
SLOW Mode
on
fSUB
on
on
on
IDLE0 Mode
off
off
on
on
on
IDLE1 Mode
off
on
on
on
on
SLEEP0 Mode
off
off
off
off
off
SLEEP1 Mode
off
off
on
on
off
NORMAL Mode
As the name suggests this is one of the main operating modes where the microcontroller has all of
its functions operational and where the system clock is provided by one of the high speed oscillators.
This mode operates allowing the microcontroller to operate normally with a clock source will come
from one of the high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator
will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the
CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used,
running the microcontroller at a divided clock ratio reduces the operating current.
SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower speed
clock source. The clock source used will be from one of the low speed oscillators, either the LXT
or the LIRC. Running the microcontroller in this mode allows it to run with much lower operating
currents. In the SLOW Mode, the fH is off.
SLEEP0 Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the
SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fSUB and fS clocks will
be stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN must be set
to “0”. If the LVDEN is set to “1”, it will not enter the SLEEP0 Mode.
SLEEP1 Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in
the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fSUB and fS
clocks will continue to operate if the LVDEN is “1” or the Watchdog Timer function is enabled with
its clock source coming from the fSUB.
IDLE0 Mode
The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the
system oscillator will be inhibited from driving the CPU but some peripheral functions will remain
operational such as the Watchdog Timer and TMs. In the IDLE0 Mode, the system oscillator will be
stopped.
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IDLE1 Mode
The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the
system oscillator will be inhibited from driving the CPU but may continue to provide a clock source
to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1
Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low
speed system oscillator.
Control Register
A single register, SMOD, is used for overall control of the internal clocks within the devices.
SMOD Register
Bit
7
6
5
4
3
2
1
0
Name
CKS2
CKS1
CKS0
FSTEN
LTO
HTO
IDLEN
HLCLK
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
POR
0
0
0
0
0
0
1
1
Bit 7~5CKS2~CKS0: The system clock selection when HLCLK is “0”
000: fSUB (fLXT or fLIRC)
001: fSUB (fLXT or fLIRC)
010: fH/64
011: fH/32
100: fH/16
101: fH/8
110: fH/4
111: fH/2
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source, which can be either the LXT or LIRC, a divided
version of the high speed system oscillator can also be chosen as the system clock
source.
Bit 4FSTEN: Fast Wake-up Control (only for HXT)
0: Disable
1: Enable
This is the Fast Wake-up Control bit which determines if the fSUB clock source is
initially used after the device wakes up. When the bit is high, the fSUB clock source can
be used as a temporary system clock to provide a faster wake up time as the fSUB clock
is available.
Bit 3LTO: Low speed system oscillator ready flag
0: Not ready
1: Ready
This is the low speed system oscillator ready flag which indicates when the low speed
system oscillator is stable after power on reset or a wake-up has occurred. The flag
will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will
change to a high level after 1024 clock cycles if the LXT oscillator is used and 1~2
clock cycles if the LIRC oscillator is used.
Bit 2HTO: High speed system oscillator ready flag
0: Not ready
1: Ready
This is the high speed system oscillator ready flag which indicates when the high speed
system oscillator is stable. This flag is cleared to “0” by hardware when the device is
powered on and then changes to a high level after the high speed system oscillator is
stable.
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Therefore this flag will always be read as “1” by the application program after device
power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wakeup has occurred, the flag will change to a high level after 128 clock cycles if the HXT
oscillator is used and after 15~16 clock cycles if the HIRC oscillator is used.
Bit 1IDLEN: IDLE Mode control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running
but the system clock will continue to keep the peripheral functions operational, if
FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop
in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT
instruction is executed.
Bit 0HLCLK: system clock selection
0: fH/2 ~ fH/64 or fSUB
1: fH
This bit is used to select if the fH clock or the fH/2~fH/64 or fSUB clock is used as
the system clock. When the bit is high the fH clock will be selected and if low the
fH/2~fH/64 or fSUB clock will be selected. When system clock switches from the fH
clock to the fSUB clock and the fH clock will be automatically switched off to conserve
power.
Fast Wake-up
To minimise power consumption the devices can enter the SLEEP or IDLE0 Mode, where the
system clock source to the devices will be stopped. However when the device is woken up again,
it can take a considerable time for the original system oscillator to restart, stabilise and allow
normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wakeup function is provided, which allows fSUB, namely either the LXT or LIRC oscillator, to act as a
temporary clock to first drive the system until the original system oscillator has stabilised. As the
clock source for the Fast Wake-up function is fSUB, the Fast Wake-up function is only available in
the SLEEP1 and IDLE0 modes. When the device is woken up from the SLEEP0 mode, the Fast
Wake-up function has no effect because the fSUB clock is stopped. The Fast Wake-up enable/disable
function is controlled using the FSTEN bit in the SMOD register.
If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up
function is enabled, then it will take one to two tSUB clock cycles of the LIRC or LXT oscillator for
the system to wake-up. The system will then initially run under the fSUB clock source until 128 HXT
clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch
over to operating from the HXT oscillator.
If the HIRC oscillator or LIRC oscillator is used as the system oscillator then it will take 15~16
clock cycles of the HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or
IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases.
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System FSTEN
Oscillator
Bit
Wake-up Time
(SLEEP0 Mode)
Wake-up Time
(SLEEP1 Mode)
Wake-up Time
(IDLE0 Mode)
Wake-up Time
(IDLE1 Mode)
128 HXT cycles
128 HXT cycles
1
128 HXT cycles
1~2 fSUB cycles
(System runs with fSUB first for 128 HXT
1~2 HXT cycles
cycles and then switches over to run with
the HXT clock)
HIRC
x
15~16 HIRC cycles 15~16 HIRC cycles
1~2 HIRC cycles
LIRC
x
1~2 LIRC cycles
1~2 LIRC cycles
1~2 LIRC cycles
LXT
x
1024 LXT cycles
1024 LXT cycles
1~2 LXT cycles
0
HXT
1~2 HXT cycles
“x”: don’t care
Wake-Up Times
Note that if the Watchdog Timer is disabled, which means that the LXT and LIRC are all both off,
then there will be no Fast Wake-up function available when the device wake-up from the SLEEP0
Mode.
Operating Mode Switching
The devices can switch between operating modes dynamically allowing the user to select the best
performance/power ratio for the present task in hand. In this way microcontroller operations that
do not require high performance can be executed using slower clocks thus requiring less operating
current and prolonging battery life in portable applications.
In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed
using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the
NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When
a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is
determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL
register.
When the HLCLK bit switches to a low level, which implies that clock source is switched from the
high speed clock source, fH, to the clock source, fH/2~fH/64 or fSUB. If the clock is from the fSUB, the
high speed clock source will stop running to conserve power. When this happens it must be noted
that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation
of other internal functions such as the TMs. The accompanying flowchart shows what happens when
the devices move between the various operating modes.
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NORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore
consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit
to “0” and set the CKS2~CKS0 bits to “000” or “001” in the SMOD register. This will then use the
low speed system oscillator which will consume less power. Users may decide to do this for certain
operations which do not require high performance and can subsequently reduce power consumption.
The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these
oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the
SMOD register.
NORMAL Mode
CKS�~CKS0 = 00xB &
HLCLK = 0
SLOW Mode
WDT and LVD are all off
IDLEN=0
HALT instr�ction is exec�ted
SLEEP0 Mode
WDT or LVD is on
IDLEN=0
HALT instr�ction is exec�ted
SLEEP1 Mode
IDLEN=1� FSYSON=0
HALT instr�ction is exec�ted
IDLE0 Mode
IDLEN=1� FSYSON=1
HALT instr�ction is exec�ted
IDLE1 Mode
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SLOW Mode to NORMAL Mode Switching
In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator. To switch
back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should
be set to “1” or HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “011”, “100”, “101”, “110”
or “111”. As a certain amount of time will be required for the high frequency clock to stabilise,
the status of the HTO bit is checked. The amount of time required for high speed system oscillator
stabilisation depends upon which high speed system oscillator type is used.
SLOW Mode
CKS2~CKS0 ≠ 000B or 001B
as HLCLK = 0 or HLCLK = 1
NORMAL Mode
WDT and LVD are all off
IDLEN=0
HALT instruction is executed
SLEEP0 Mode
WDT or LVD is on
IDLEN=0
HALT instruction is executed
SLEEP1 Mode
IDLEN=1, FSYSON=0
HALT instruction is executed
IDLE0 Mode
IDLEN=1, FSYSON=1
HALT instruction is executed
IDLE1 Mode
Entering the SLEEP0 Mode
There is only one way for the devices to enter the SLEEP0 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the
WDT and LVD both off. When this instruction is executed under the conditions described above, the
following will occur:
• The system clock, WDT clock and Time Base clock will be stopped and the application program
will stop at the “HALT” instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and stopped.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
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Entering the SLEEP1 Mode
There is only one way for the devices to enter the SLEEP1 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the
WDT or LVD on. When this instruction is executed under the conditions described above, the
following will occur:
• The system clock and Time Base clock will be stopped and the application program will stop at
the “HALT” instruction, but the WDT or LVD will remain with the clock source coming from the
fSUB clock.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE0 Mode
There is only one way for the devices to enter the IDLE0 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the
FSYSON bit in CTRL register equal to “0”. When this instruction is executed under the conditions
described above, the following will occur:
• The system clock will be stopped and the application program will stop at the “HALT”
instruction, but the Time Base clock and fSUB clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the
FSYSON bit in CTRL register equal to “1”. When this instruction is executed under the conditions
described above, the following will occur:
• The system clock and Time Base clock and fSUB clock will be on and the application program will
stop at the “HALT” instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
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Standby Current Considerations
As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of
the devices to as low a value as possible, perhaps only in the order of several micro-amps except
in the IDLE1 Mode, there are other considerations which must also be taken into account by the
circuit designer if the power consumption is to be minimised. Special attention must be made to the
I/O pins on the devices. All high-impedance input pins must be connected to either a fixed high or
low level as any floating input pins could create internal oscillations and result in increased current
consumption. This also applies to the devices which has different package types, as there may be
unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high
resistors connected.
Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs.
These should be placed in a condition in which minimum current is drawn or connected only to
external circuits that do not draw current, such as other CMOS inputs. Also note that additional
standby current will also be required if the configuration options have enabled the LXT or LIRC
oscillator.
In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system
oscillator, the additional standby current will also be perhaps in the order of several hundred microamps.
Wake-up
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources
listed as follows:
• An external falling edge on Port A
• A system interrupt
• A WDT overflow
If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. The actual
source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is
cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when
executing the “HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wakeup that only resets the Program Counter and Stack Pointer, the other flags remain in their original
status.
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at
the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then
two possible situations may occur. The first is where the related interrupt is disabled or the interrupt
is enabled but the stack is full, in which case the program will resume execution at the instruction
following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not
be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled
or when a stack level becomes free. The other situation is where the related interrupt is enabled and
the stack is not full, in which case the regular interrupt response takes place. If an interrupt request
flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related
interrupt will be disabled.
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Programming Considerations
The high speed and low speed oscillators both use the same SST counter. For example, if the system
is woken up from the SLEEP0 Mode and both the HIRC and LXT oscillators need to start-up from
an off state. The LXT oscillator uses the SST counter after HIRC oscillator has finished its SST
period.
• If the device is woken up from the SLEEP0 Mode to the NORMAL Mode, the high speed system
oscillator needs an SST period. The device will execute first instruction after HTO is “1”. At this
time, the LXT oscillator may not be stability if fSUB is from LXT oscillator. The same situation
occurs in the power-on state. The LXT oscillator is not ready yet when the first instruction is executed.
• If the device is woken up from the SLEEP1 Mode to NORMAL Mode, and the system clock
source is from HXT oscillator and FSTEN is “1”, the system clock can be switched to the LIRC
oscillator after wake up.
• There are peripheral functions, such as Time Bases and TMs, for which the fSYS is used. If the
system clock source is switched from fH to fSUB, the clock source to the peripheral functions mentioned above will change accordingly.
• The on/off condition of fSUB and fS depends upon whether the WDT is enabled or disabled as the
WDT clock source is selected from fSUB.
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Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by
the LIRC or LXT oscillator. The LXT oscillator is supplied by an external 32.768kHz crystal. The
LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it
should be noted that this specified internal clock period can vary with VDD, temperature and process
variations. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer
timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register.
Watchdog Timer Control Register
A single register, WDTC, controls the required timeout period as well as the enable/disable
operation. This register controls the overall operation of the Watchdog Timer.
WDTC Register
Bit
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
WS2
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
1
1
Bit 7~3WE4~WE0: WDT function software control
10101: Disable
01010: Enable
Other: Reset MCU
When these bits are changed by the environmental noise or software setting to reset
the microcontroller, the reset operation will be activated after 2~3 LIRC clock cycles
and the WRF bit in the CTRL register will be set to “1”.
Bit 2~0WS2~WS0: WDT time-out period selection
000: 28/fS
001: 210/fS
010: 212/fS
011: 214/fS
100: 215/fS
101: 216/fS
110: 217/fS
111: 218/fS
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CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
x
0
0
“x” unknown
Bit 7FSYSON: fSYS Control in IDLE Mode
Described elsewhere
Bit 6~3
Unimplemented, read as “0”
Bit 2LVRF: LVR function reset flag
Described elsewhere
Bit 1LRF: LVR Control register software reset flag
Described elsewhere
Bit 0WRF: WDT Control register software reset flag
0: Not occur
1: Occurred
This bit is set to “1” by the WDT Control register software reset and cleared by the
application program. Note that this bit can only be cleared to “0” by the application
program.
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, these clear instructions will not be executed in the
correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to
the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC register
to offer additional enable/disable and reset control of the Watchdog Timer. The WDT function
will be disabled when the WE4~WE0 bits are set to a value of 10101B. The WDT function will be
enabled if the WE4~WE0 bits value is equal to 01010B. If the WE4~WE0 bits are set to any other
values by the environmental noise or software setting, except 01010B and 10101B, it will reset the
device after 2~3 LIRC clock cycles. After power on these bits will have the value of 01010B.
WE4 ~ WE0 Bits
WDT Function
10101B
Disable
01010B
Enable
Any other value
Reset MCU
Watchdog Timer Enable/Disable Control
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDT reset, which means a certain value except 01010B and 10101B written into the
WE4~WE0 bit filed, the second is using the Watchdog Timer software clear instruction and the third
is via a HALT instruction.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the single “CLR WDT” instruction to clear the WDT.
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The maximum time out period is when the 218 division ratio is selected. As an example, with a
32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8
seconds for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration.
WDTC Register WE4~WE0 bits
Reset MCU
CLR
“HALT”Instr�ction
“CLR WDT”Instr�ction
LXT
LIRC
M
U
X
fSUB
fS
Low Speed Oscillator
Config�ration option
8-stage Divider
fS/�8
WS�~WS0
WDT Prescaler
8-to-1 MUX
WDT Time-o�t
(�8/fS ~ �18/fS)
Watchdog Timer
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
Another type of reset is when the Watchdog Timer overflows and resets. All types of reset operations
result in different register conditions being setup. Another reset exists in the form of a Low Voltage
Reset, LVR, where a full reset, is implemented in situations where the power supply voltage falls
below a certain threshold.
Reset Functions
There are several ways in which a reset can occur, each of which will be described as follows.
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that
all I/O ports will be first set to inputs.
VDD
Power-on Reset
tRSTD
SST Time-o�t
Power-On Reset Timing Chart
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Low Voltage Reset — LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the
device. The LVR function is always enabled with a specific LVR voltage VLVR. If the supply voltage
of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery,
the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will
also be set to “1”. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between
0.9V~VLVR must exist for a time greater than that specified by tLVR in the LVD&LVR Electrical
Characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the
low supply voltage and will not perform a reset function. The actual VLVR value can be selected by
the LVS bits in the LVRC register. If the LVS7~LVS0 bits are changed to some certain values by the
environmental noise or software setting, the LVR will reset the device after 2~3 LIRC clock cycles.
When this happens, the LRF bit in the CTRL register will be set to “1”. After power on the register
will have the value of 01010101B. Note that the LVR function will be automatically disabled when
the device enters the SLEEP or IDLE mode.
LVR
tRSTD + tSST
Internal Reset
Low Voltage Reset Timing Chart
LVRC Register
Bit
7
6
5
4
3
2
1
0
Name
LVS7
LVS6
LVS5
LVS4
LVS3
LVS2
LVS1
LVS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
1
0
0
1
1
0
Bit 7~0LVS7~LVS0: LVR voltage select
01100110: 1.7V (default)
01010101: 1.9V
00110011: 2.55V
10011001: 3.15V
10101010: 3.8V
11110000: LVR disable
Any other value: Generates MCU reset -- register is reset to POR value
When an actual low voltage condition occurs, as specified by one of the five defined
LVR voltage values above, an MCU reset will be generated. In this situation the
register contents will remain the same after such a reset occurs.
Any register value, other than the five defined LVR values above, will also result in
the generation of an MCU reset. The reset operation will be activated after 2~3 LIRC
clock cycles. However in this situation the register contents will be reset to the POR
value.
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CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
x
0
0
“x” unknown
Bit 7FSYSON: fSYS Control in IDLE Mode
Described elsewhere.
Bit 6~3
Unimplemented, read as “0”
Bit 2LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to “1” when a specific Low Voltage Reset situation condition occurs.
This bit can only be cleared to “0” by the application program.
Bit 1LRF: LVR Control register software reset flag
0: Not occur
1: Occurred
This bit is set to “1” if the LVRC register contains any non defined LVR voltage
register values. This in effect acts like a software reset function. This bit can only be
cleared to “0” by the application program.
Bit 0WRF: WDT Control register software reset flag
Described elsewhere.
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware LVR reset except
that the Watchdog time-out flag TO will be set to “1”.
WDT Time-o�t
tRSTD + tSST
Internal Reset
WDT Time-out Reset during Normal Operation Timing Chart
Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for
tSST details.
WDT Time-o�t
tSST
Internal Reset
WDT Time-out Reset during Sleep or Idle Mode Timing Chart
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June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO
PDF
0
0
Power-on reset
Reset Conditions
u
u
LVR reset during Normal or SLOW Mode operation
1
u
WDT time-out reset during Normal or SLOW Mode operation
1
1
WDT time-out reset during IDLE or SLEEP Mode operation
Note: “u” stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Condition after Reset
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins counting
Timer/Event Counter
Timer Counter will be turned off
Input/Output Ports
I/O ports will be setup as inputs, AN0~AN7 as A/D input pin
Stack Pointer
Stack Pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers. Note that
where more than one package type exists the table will reflect the situation for the larger package
type.
HT66F317
Power On Reset
LVR Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
MP0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
MP1
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BP
---- ---0
---- ---0
---- ---0
---- ---u
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBHP
---- -xxx
- - - - - uuu
- - - - - uuu
- - - - - uuu
STATUS
--00 xxxx
- - uu uuuu
- - 1 u uuuu
- - 1 1 uuuu
SMOD
0 0 0 0 0 0 11
0 0 0 0 0 0 11
0 0 0 0 0 0 11
uuuu uuuu
LVDC
--00 0000
--00 0000
--00 0000
- - uu uuuu
INTEG
---- 0000
---- 0000
---- 0000
- - - - uuuu
INTC0
-0-0 0-00
-0-0 0-00
-0-0 0-00
- u - u u - uu
INTC1
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC2
--00 --00
--00 --00
--00 --00
- - uu - - uu
MFI0
--00 --00
--00 --00
--00 --00
- - uu - - uu
MFI1
--00 --00
--00 --00
--00 --00
- - uu - - uu
MFI2
--00 --00
--00 --00
--00 --00
- - uu - - uu
Register
Rev. 1.00
60
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Power On Reset
LVR Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAPU
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAWU
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMPC
0--- -000
0--- -000
0--- -000
u - - - - uuu
WDTC
0 1 0 1 0 0 11
0 1 0 1 0 0 11
0 1 0 1 0 0 11
uuuu uuuu
TBC
0 0 11 0 111
0 0 11 0 111
0 0 11 0 111
uuuu uuuu
SCOMC
-000 0000
-000 0000
-000 0000
- uuu uuuu
EEA
--00 0000
--00 0000
--00 0000
- - uu uuuu
EED
0000 0000
0000 0000
0000 0000
uuuu uuuu
SADOL (ADRFS=0)
xxxx ----
xxxx ----
xxxx ----
uuuu - - - -
SADOL (ADRFS=1)
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
SADOH (ADRFS=0)
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
SADOH (ADRFS=1)
---- xxxx
---- xxxx
---- xxxx
- - - - uuuu
SADC0
0000 -000
0000 -000
0000 -000
uuuu - uuu
SADC1
000- -000
000- -000
000- -000
uuu - - uuu
SADC2
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACERL
1111 1111
1111 1111
1111 1111
uuuu uuuu
CTRL
0--- -x00
0--- -000
0--- -000
u - - - - uuu
LVRC
0 11 0 0 11 0
0 11 0 0 11 0
0 11 0 0 11 0
uuuu uuuu
TM0C0
0000 0---
0000 0---
0000 0---
uuuu u - - -
TM0C1
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0DL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0DH
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0AL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0AH
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0RPL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0RPH
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1C0
0000 0---
0000 0---
0000 0---
uuuu u - - -
TM1C1
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1DL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1DH
---- --00
---- --00
---- --00
- - - - - - uu
TM1AL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1AH
---- --00
---- --00
---- --00
- - - - - - uu
TM1RPL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1RPH
---- --00
---- --00
---- --00
- - - - - - uu
PC
- 111 1111
- 111 1111
- 111 1111
- uuu uuuu
PCC
- 111 1111
- 111 1111
- 111 1111
- uuu uuuu
PCPU
-000 0000
-000 0000
-000 0000
- uuu uuuu
PB
- 111 1111
- 111 1111
- 111 1111
- uuu uuuu
PBC
- 111 1111
- 111 1111
- 111 1111
- uuu uuuu
PBPU
-000 0000
-000 0000
-000 0000
- uuu uuuu
SLEDC0
0101 0101
0101 0101
0101 0101
uuuu uuuu
SLEDC1
---- 0101
---- 0101
---- 0101
- - - - uuuu
EEC
---- 0000
---- 0000
---- 0000
- - - - uuuu
Register
Rev. 1.00
61
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
HT66F318
Power On Reset
LVR Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
MP0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
MP1
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BP
- - - -
- - - -
- - - -
- - 0
---- ---u
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
Register
- - 0
- - 0
PCL
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBHP
---- xxxx
- - - - uuuu
- - - - uuuu
- - - - uuuu
STATUS
--00 xxxx
- - uu uuuu
- - 1 u uuuu
- - 1 1 uuuu
SMOD
0 0 0 0 0 0 11
0 0 0 0 0 0 11
0 0 0 0 0 0 11
uuuu uuuu
LVDC
--00 0000
--00 0000
--00 0000
- - uu uuuu
INTEG
---- 0000
---- 0000
---- 0000
- - - - uuuu
INTC0
-000 0000
-000 0000
-000 0000
- uuu uuuu
INTC1
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC2
0000 0000
0000 0000
0000 0000
uuuu uuuu
MFI0
--00 --00
--00 --00
--00 --00
- - uu - - uu
MFI1
0000 0000
0000 0000
0000 0000
uuuu uuuu
MFI2
--00 --00
--00 --00
--00 --00
- - uu - - uu
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAPU
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAWU
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMPC
0--- -000
0--- -000
0--- -000
u - - - - uuu
WDTC
0 1 0 1 0 0 11
0 1 0 1 0 0 11
0 1 0 1 0 0 11
uuuu uuuu
TBC
0 0 11 0 111
0 0 11 0 111
0 0 11 0 111
uuuu uuuu
CTRL
0--- -x00
0--- -000
0--- -000
u - - - - uuu
LVRC
0 11 0 0 11 0
0 11 0 0 11 0
0 11 0 0 11 0
uuuu uuuu
EEA
--00 0000
--00 0000
--00 0000
- - uu uuuu
EED
0000 0000
0000 0000
0000 0000
uuuu uuuu
SADOL (ADRFS=0)
xxxx ----
xxxx ----
xxxx ----
uuuu - - - -
SADOL (ADRFS=1)
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
SADOH (ADRFS=0)
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
SADOH (ADRFS=1)
---- xxxx
---- xxxx
---- xxxx
- - - - uuuu
SADC0
0000 -000
0000 -000
0000 -000
uuuu - uuu
SADC1
000- -000
000- -000
000- -000
uuu - - uuu
SADC2
0000 0000
0000 0000
0000 0000
uuuu uuuu
PB
- 111 1111
- 111 1111
- 111 1111
- uuu uuuu
PBC
- 111 1111
- 111 1111
- 111 1111
- uuu uuuu
PBPU
-000 0000
-000 0000
-000 0000
- uuu uuuu
TM2C0
0000 0---
0000 0---
0000 0---
uuuu u - - -
TM2C1
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM2DL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM2DH
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM2AL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM2AH
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM2RP
0000 0000
0000 0000
0000 0000
uuuu uuuu
Rev. 1.00
62
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Power On Reset
LVR Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
TM0C0
0000 0---
0000 0---
0000 0---
uuuu u - - -
TM0C1
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0DL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0DH
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0AL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0AH
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0RP
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1C0
0000 0---
0000 0---
0000 0---
uuuu u - - -
TM1C1
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1DL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1DH
---- --00
---- --00
---- --00
- - - - - - uu
TM1AL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1AH
---- --00
---- --00
---- --00
- - - - - - uu
TM1RPL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1RPH
---- --00
---- --00
---- --00
- - - - - - uu
CPC
1000 0001
1000 0001
1000 0001
uuuu uuuu
SCOMC
-000 0000
-000 0000
-000 0000
- uuu uuuu
PC
- 111 1111
- 111 1111
- 111 1111
- uuu uuuu
PCC
- 111 1111
- 111 1111
- 111 1111
- uuu uuuu
PCPU
-000 0000
-000 0000
-000 0000
- uuu uuuu
ACERL
1111 1111
1111 1111
1111 1111
uuuu uuuu
USR
0 0 0 0 1 0 11
0 0 0 0 1 0 11
0 0 0 0 1 0 11
uuuu uuuu
UCR1
0000 00x0
0000 00x0
0000 00x0
uuuu uuuu
UCR2
0000 0000
0000 0000
0000 0000
uuuu uuuu
BRG
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TXR_RXR
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
IICC0
---- 000-
---- 000-
---- 000-
- - - - uuu -
IICC1
1000 0001
1000 0001
1000 0001
uuuu uuuu
IICD
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
IICA
0000 000-
0000 000-
0000 000-
uuuu uuu -
I2CTOC
0000 0000
0000 0000
0000 0000
uuuu uuuu
PD
- - - - 1111
- - - - 1111
- - - - 1111
- - - - 1111
PDC
- - - - 1111
- - - - 1111
- - - - 1111
- - - - 1111
Register
PDPU
---- 0000
---- 0000
---- 0000
---- 0000
SLEDC0
0101 0101
0101 0101
0101 0101
uuuu uuuu
SLEDC1
--01 0101
--01 0101
--01 0101
- - uu uuuu
EEC
---- 0000
---- 0000
---- 0000
- - - - uuuu
Note: “u” stands for unchanged
“x” stands for unknown
“-” stands for unimplemented
Rev. 1.00
63
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
The devices provide bidirectional input/output lines labeled with port names PA~PD. These I/O
ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used for input and output operations. For input
operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge
of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is
latched and remains unchanged until the output latch is rewritten.
Device
Bit
Register
Name
7
6
5
4
3
2
1
0
PA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PAC
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
PAPU7
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PAWU
PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0
HT66F317
HT66F318
HT66F318
PB
—
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PBC
—
PBC6
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
PBPU
—
PC
—
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PCC
—
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0
PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0
PCPU
—
PD
—
—
—
—
PD3
PD2
PD1
PD0
PDC
—
—
—
—
PDC3
PDC2
PDC1
PDC0
PDPU
—
—
—
—
PDPU3 PDPU2 PDPU1 PDPU0
I/O Register List
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as an input have the capability of being connected to an internal pull-high resistor. These
pull-high resistors are selected using registers PAPU~PDPU and LVPU bit in the LVDC register, and
are implemented using weak PMOS transistors.
PAPU Register
Bit
7
6
5
4
3
2
1
0
Name
PAPU7
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0PAPU7~PAPU0: Port A bit 7 ~ bit 0 Pull-high Control
0: Disable
1: Enable
Rev. 1.00
64
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
PBPU Register
Bit
7
6
5
4
3
2
1
0
Name
—
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as “0”
Bit 6~0PBPU6~PBPU0: Port B bit 6 ~ bit 0 Pull-high Control
0: Disable
1: Enable
PCPU Register
Bit
7
6
5
4
3
2
1
0
Name
—
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as “0”
Bit 6~0PCPU6~PCPU0: Port C bit 6 ~ bit 0 Pull-high Control
0: Disable
1: Enable
PDPU Register — HT66F318
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
PDPU3
PDPU2
PDPU1
PDPU0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as “0”
Bit 3~0PDPU3~PDPU0: Port D bit 3 ~ bit 0 Pull-high Control
0: Disable
1: Enable
LVDC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
LVDO
LVDEN
LVPU
VLVD2
VLVD1
VLVD0
R/W
—
—
R
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5LVDO: LVD Output Flag
Described elsewhere.
Bit 4LVDEN: Low Voltage Detector Control
Described elsewhere.
Bit 3LVPU: All pin pull high resistor selection
0: All pin pull high resistor is 30kΩ@5V or 60kΩ@3V (normal mode)
1: All pin pull high resistor is 7.5 kΩ@5V or 15kΩ@3V (Low Voltage mode)
For more details about RPH, refer to the D.C characteristics table.
Bit 2~0VLVD2~VLVD0: Select LVD Voltage
Described elsewhere.
Rev. 1.00
65
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port
A pins from high to low. This function is especially suitable for applications that can be woken up
via external switches. Each pin on Port A can be selected individually to have this wake-up feature
using the PAWU register.
PAWU Register
Bit
7
6
5
4
3
2
1
0
Name
PAWU7
PAWU6
PAWU5
PAWU4
PAWU3
PAWU2
PAWU1
PAWU0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0PAWU7~PAWU0: Port A bit 7 ~ bit 0 Wake-up Control
0: Disable
1: Enable
I/O Port Control Registers
Each I/O port has its own control register known as PAC~PDC, to control the input/output
configuration. With this control register, each CMOS output or input can be reconfigured
dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its
associated port control register. For the I/O pin to function as an input, the corresponding bit of the
control register must be written as a “1”. This will then allow the logic state of the input pin to be
directly read by instructions. When the corresponding bit of the control register is written as a “0”,
the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions
can still be used to read the output register. However, it should be noted that the program will in fact
only read the status of the output data latch and not the actual logic status of the output pin.
PAC Register
Bit
7
6
5
4
3
2
1
0
Name
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit 7~0PAC7~PAC0: Port A bit 7 ~ bit 0 Input/Output Control
0: Output
1: Input
PBC Register
Bit
7
6
5
4
3
2
1
0
Name
—
PBC6
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
1
1
1
1
1
1
1
Bit 7
Unimplemented, read as “0”
Bit 6~0PBC6~PBC0: Port B bit 6 ~ bit 0 Input/Output Control
0: Output
1: Input
Rev. 1.00
66
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
PCC Register
Bit
7
6
5
4
3
2
1
0
Name
—
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
1
1
1
1
1
1
1
Bit 7
Unimplemented, read as “0”
Bit 6~0PCC6~PCC0: Port C bit 6 ~ bit 0 Input/Output Control
0: Output
1: Input
PDC Register — HT66F318
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
PDC3
PDC2
PDC1
PDC0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
1
1
1
1
Bit 7~4
Unimplemented, read as “0”
Bit 3~0PDC3~PDC0: Port D bit 3 ~ bit 0 Input/Output Control
0: Output
1: Input
I/O Pin Structures
The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As
the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a
guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared
structures does not permit all types to be shown.
    
  Generic Input/Output Structure
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 €  
 ­
­
   
A/D Input/Output Structure
Source Current Selection
The source current of each pin in these devices can be configured with different source current
which is selected by the corresponding pin source current select bits. These source current bits are
available when the corresponding pin is configured as a CMOS output. Otherwise, these select bits
have no effect. Users should refer to the D.C. Characteristics section to obtain the exact value for
different applications.
SLEDC0 Register
Bit
7
6
5
4
3
2
1
0
Name
PBPS3
PBPS2
PBPS1
PBPS0
PAPS3
PAPS2
PAPS1
PAPS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7 ~ 6PBPS3~PBPS2: PB6~PB4 source current select
00: source = Level 0 (min.)
01: source = Level 1
10: source = Level 2
11: source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
Bit 5 ~ 4PBPS1~PBPS0: PB3~PB0 source current select
00: source = Level 0 (min.)
01: source = Level 1
10: source = Level 2
11: source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
Bit 3 ~ 2PAPS3~PAPS2: PA7~PA4 source current select
00: source = Level 0 (min.)
01: source = Level 1
10: source = Level 2
11: source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
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Bit 1 ~ 0PAPS1~PAPS0: PA3~PA0 source current select
00: source = Level 0 (min.)
01: source = Level 1
10: source = Level 2
11: source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
SLEDC1 Register — HT66F317
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
PCPS3
PCPS2
PCPS1
PCPS0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
1
0
1
Bit 7 ~ 4
Unimplemented, read as “0”
Bit 3 ~ 2PCPS3~PCPS2: PC6~PC4 source current select
00: source = Level 0 (min.)
01: source = Level 1
10: source = Level 2
11: source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
Bit 1 ~ 0PCPS1~PCPS0: PC3~PC0 source current select
00: source = Level 0 (min.)
01: source = Level 1
10: source = Level 2
11: source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
SLEDC1 Register — HT66F318
Bit
7
6
5
4
3
2
1
0
Name
—
—
PDPS1
PDPS0
PCPS3
PCPS2
PCPS1
PCPS0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
1
0
1
0
1
Bit 7 ~ 6
Unimplemented, read as “0”
Bit 5 ~ 4PDPS1~PDPS0: PD3~PD0 source current select
00: source = Level 0 (min.)
01: source = Level 1
10: source = Level 2
11: source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
Bit 3 ~ 2PCPS3~PCPS2: PC6~PC4 source current select
00: source = Level 0 (min.)
01: source = Level 1
10: source = Level 2
11: source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
Bit 1 ~ 0PCPS1~PCPS0: PC3~PC0 source current select
00: source = Level 0 (min.)
01: source = Level 1
10: source = Level 2
11: source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
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Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, all of
the I/O data and port control registers will be set high. This means that all I/O pins will default to
an input state, the level of which depends on the other connected circuitry and whether pull-high
selections have been chosen. If the port control registers, PAC~PDC, are then programmed to setup
some pins as outputs, these output pins will have an initial high output value unless the associated
port data registers, PA~PD, are first programmed. Selecting which pins are inputs and which are
outputs can be achieved byte-wide by loading the correct values into the appropriate port control
register or by programming individual bits in the port control register using the “SET [m].i” and
“CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write
operation takes place. The microcontroller must first read in the data on the entire port, modify it to
the required new bit values and then rewrite this data back to the output ports.
The power-on reset condition of the A/D converter control registers ensures that any A/D input
pins which are always shared with other I/O functions, will be setup as analog inputs after a reset.
Although these pins will be configured as A/D inputs after a reset, the A/D converter will not be
switched on. It is therefore important to note that if it is required to use these pins as I/O digital
input pins or as other functions, the A/D converter control registers must be correctly programmed
to remove the A/D function. Note also that as the A/D channel is enabled, any internal pull-high
resistor connections will be removed.
Port A has the additional capability of providing wake-up functions. When the device is in the
SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high
to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this
function.
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Timer Modules – TM
One of the most fundamental functions in any microcontroller device is the ability to control and
measure time. To implement time related functions each device includes several Timer Modules,
abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide
operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output
as well as being the functional unit for the generation of PWM signals. Each of the TMs has two
individual interrupts. The addition of input and output pins for each TM ensures that users are
provided with timing units with a wide and flexible range of features.
The common features of the different TM types are described here with more detailed information
provided in the individual Compact, Standard and Periodic TM sections.
Introduction
The devices contain from two to three TMs depending upon which device is selected with each
TM having a reference name of TM0, TM1 and TM2. Each individual TM can be categorised as a
certain type, namely Compact Type TM, Standard Type TM or Periodic Type TM. Although similar
in nature, the different TM types vary in their feature complexity. The common features to all of the
Compact, Standard and Periodic TMs will be described in this section and the detailed operation
regarding each of the TM types will be described in separate sections. The main features and
differences between the three types of TMs are summarised in the accompanying table.
CTM
STM
PTM
Timer/Counter
Function
√
√
√
I/P Capture
—
√
√
Compare Match Output
√
√
√
PWM Channels
1
1
1
Single Pulse Output
—
1
1
Edge
Edge
Edge
Duty or Period
Duty or Period
Duty or Period
PWM Alignment
PWM Adjustment Period & Duty
TM Function Summary
Each chip contains a specific number of either Compact Type, Standard Type or Periodic Type TM
units which are shown in the table together with their individual reference names, TM0~TM2.
Device
TM0
TM1
HT66F317
10-bit PTM
10-bit PTM
TM2
—
HT66F318
16-bit STM
10-bit PTM
16-bit CTM
TM Name/Type Reference
TM Operation
The three different types of TM offer a diverse range of functions, from simple timing operations
to PWM signal generation. The key to understanding how the TM operates is to see it in terms of
a free running counter whose value is then compared with the value of pre-programmed internal
comparators. When the free running counter has the same value as the pre-programmed comparator,
known as a compare match situation, a TM interrupt signal will be generated which can clear the
counter and perhaps also change the condition of the TM output pin. The internal TM counter is
driven by a user selectable clock source, which can be an internal clock or an external pin.
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TM Clock Source
The clock source which drives the main counter in each TM can originate from various sources.
The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM
control registers. The clock source can be a ratio of either the system clock fSYS, the internal high
clock fH, the fTBC clock source or the external TCKn pin. The TCKn pin clock source is used to allow
an external signal to drive the TM as an external clock source or for event counting.
TM Interrupts
The Compact Type, Standard Type and Periodic Type TMs each have two internal interrupts, one for
each of the internal comparator A or comparator P, which generate a TM interrupt when a compare
match condition occurs. When a TM interrupt is generated it can be used to clear the counter and
also to change the state of the TM output pin.
TM External Pins
Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM
input pin is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in
the TMnC0 register. This external TM input pin allows an external clock source to drive the internal
TM. This external TM input pin is shared with other functions but will be connected to the internal
TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a
rising or falling active edge.
The TMs each have one output pin with the label TPn. When the TM is in the Compare Match
Output Mode, this pin can be controlled by the TM to switch to a high or low level or to toggle
when a compare match situation occurs. The external TPn output pin is also the pin where the
TM generates the PWM output waveform. The TPn pin acts as an input when the TM is setup to
operate in the Capture Input Mode. As the TPn pins are pin-shared with other functions, the TPn
pin function must first be setup using a register. A single bit in the TMPC register determines if its
associated pin is to be used as an TM pin or if it is to have another function. When the corresponding
TM configuration selects the TPn pin to be used as an output pin, the associated pin will be setup as
an external TM output pin. If the TM configuration selects the TPn pin to be setup as an input pin,
the input signal supplied on the associated pin can be derived from an external signal and other pinshared output function. If the TM configuration determines that the TPn pin function is not used, the
associated pin will be controlled by other pin-shared functions. The details of the TPn pin for each
TM type and device are provided in the accompanying table.
Device
STM
PTM
CTM
Register
HT66F317
—
TP0, TP1
—
TMPC
HT66F318
TP0
TP1
TP2
TMPC
TM Output Pins
TM Input/Output Pin Control Registers
Selecting to have a TM input/output or whether to retain its other shared functions is implemented
using one register with a single bit in each register corresponding to a TM input/output pin. Setting
the bit high will setup the corresponding pin as a TM input/output if reset to zero the pin will retain
its original other functions.
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TM0 Function Pin Control Block Diagram - HT66F318
TM0 Function Pin Control Block Diagram – HT66F317
TM1 Function Pin Control Block Diagram – HT66F317/HT66F318
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TM2 Function Pin Control Block Diagram – HT66F318
TMPC Register — HT66F317
Bit
7
6
5
4
3
2
1
0
Name
CLOP
—
—
—
—
T1CP1
T1CP0
T0CP
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
0
0
0
Bit 7CLOP: CLO pin control
0: Disable
1: Enable
Bit 6~3
Unimplemented, read as “0”
Bit 2T1CP1: TP1 pin control
0: Disable, PB3 or other pin functions
1: Enable, TP1
Bit 1T1CP0: TP1 pin control
0: Disable, PA7 or other pin functions
1: Enable, TP1
Note that the T1CP1 and T1CP0 bits can not be “1” at same time, only one control bit
can be used to select the TP1 function.
Bit 0T0CP: TP0 pin control
0: Disable
1: Enable
TMPC Register — HT66F318
Bit
7
6
5
4
3
2
1
0
Name
CLOP
—
—
—
—
T2CP
T1CP
T0CP
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
0
0
0
Bit 7CLOP: CLO pin control
0: Disable
1: Enable
Bit 6~3
Unimplemented, read as “0”
Bit 2T2CP: TP2 pin control
0: Disable
1: Enable
Bit 1T1CP: TP1 pin control
0: Disable
1: Enable
Bit 0T0CP: TP0 pin control
0: Disable
1: Enable
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Programming Considerations
The TM Counter Registers and the Capture/Compare CCRA registers, being either 10-bit or 16bit, and CCRP register pair for Periodic Timer Module, being 10-bit, all have a low and high byte
structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an
internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way.
The important point to note is that data transfer to and from the 8-bit buffer and its related low byte
only takes place when a write or read operation to its corresponding high byte is executed.
As the CCRA register and PTM CCRP registers are implemented in the way shown in the
following diagram and accessing the register is carried out in a specific way described above, it is
recommended to use the “MOV” instruction to access the CCRA or PTM CCRP low byte register,
named TMxAL or TMxRPL, using the following access procedures. Accessing the CCRA or PTM
CCRP low byte register without following these access procedures will result in unpredictable
values.
TM Co�nter Register (Read only)
TMnDL
TMnDH
8-bit
B�ffer
TMnAL
TMnAH
TM CCRA Register (Read/Write)
TMnRPL
TMnRPH
PTM CCRP Register (Read/Write)
Data B�s
The following steps show the read and write procedures:
• Writing Data to CCRA or PTM CCRP
♦♦
Step 1. Write data to Low Byte TMxAL or TMxRPL
––Note that here data is only written to the 8-bit buffer.
♦♦
Step 2. Write data to High Byte TMxAH or TMxRPH
––Here data is written directly to the high byte registers and simultaneously data is latched
from the 8-bit buffer to the Low Byte registers.
• Reading Data from the Counter Registers and CCRA or PTM CCRP
Rev. 1.00
♦♦
Step 1. Read data from the High Byte TMxDH, TMxAH or TMxRPH
––Here data is read directly from the High Byte registers and simultaneously data is latched
from the Low Byte register into the 8-bit buffer.
♦♦
Step 2. Read data from the Low Byte TMxDL, TMxAL or TMxRPL
––This step reads data from the 8-bit buffer.
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Compact Type TM – CTM (only for HT66F318)
Although the simplest form of the three TM types, the Compact TM type still contains three
operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes.
The Compact TM can be controlled with an external input pin and can drive one external output pin.
Device
Name
TM No.
TM Input Pin
TM Output Pin
HT66F318
16-bit CTM
2
TCK2
TP2
Compact TM Operation
At its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock
source. There are also two internal comparators with the names, Comparator A and Comparator
P. These comparators will compare the value in the counter with CCRP and CCRA registers. The
CCRP is 8-bit wide whose value is compared with the highest eight bits in the counter while the
CCRA is 16-bit wide and therefore compares with all counter bits.
The only way of changing the value of the 16-bit counter using the application program, is to
clear the counter by changing the TnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Compact
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control an output pin. All operating setup conditions are
selected using relevant internal registers.
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 
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    Compact Type TM Block Diagram (n=2)
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Compact Type TM Register Description
Overall operation of the Compact TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store
the internal 16-bit CCRA value. There is also a read/write register used to store the internal 8-bit
CCRP value. The remaining two registers are control registers which setup the different operating
and control modes.
Bit
Register
Name
7
6
5
4
3
2
1
0
TMnC0
TnPAU
TnCK2
TnCK1
TnCK0
TnON
—
—
—
TMnC1
TnM1
TnM0
TnIO1
TnIO0
TnOC
TnPOL
TnDPX
TnCCLR
TMnDL
D7
D6
D5
D4
D3
D2
D1
D0
TMnDH
D15
D14
D13
D12
D11
D10
D9
D8
TMnAL
D7
D6
D5
D4
D3
D2
D1
D0
TMnAH
D15
D14
D13
D12
D11
D10
D9
D8
TMnRP
TnRP7
TnRP6
TnRP5
TnRP4
TnRP3
TnRP2
TnRP1
TnRP0
16-bit Compact TM Register List (n=2)
TMnC0 Register (n=2)
Bit
7
6
5
4
3
2
1
0
Name
TnPAU
TnCK2
TnCK1
TnCK0
TnON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7TnPAU: TMn Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6~4TnCK2~TnCK0: Select TMn Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: fH/8
110: TCKn rising edge clock
111: TCKn falling edge clock
These three bits are used to select the clock source for the TM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fH and fTBC are other internal clocks, the details of which can
be found in the oscillator section.
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Bit 3TnON: TMn Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the
counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the
counter from counting and turn off the TM which will reduce its power consumption.
When the bit changes state from low to high the internal counter value will be reset
to zero, however when the bit changes from high to low, the internal counter will
retain its residual value. If the TM is in the Compare Match Output Mode then the TM
output pin will be reset to its initial condition, as specified by the TnOC bit, when the
TnON bit changes from low to high.
Bit 2~0
Unimplemented, read as “0”
TMnC1 Register (n=2)
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
TnM1
TnM0
TnIO1
TnIO0
TnOC
TnPOL
TnDPX
TnCCLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
TnM1, TnM0: Select TMn Operating Mode
00: Compare Match Output Mode
01: Undefined
10: PWM Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation
the TM should be switched off before any changes are made to the TnM1 and TnM0
bits. In the Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4
TnIO1, TnIO0: Select TPn output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode
00: PWM Output inactive state
01: PWM Output active state
10: PWM output
11: Undefined
Timer/Counter Mode
Unused
These two bits are used to determine how the TM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the TM is running.
In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the
TM output pin changes state when a compare match occurs from the Comparator A.
The TM output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the TM output
pin should be setup using the TnOC bit in the TMnC1 register. Note that the output
level requested by the TnIO1 and TnIO0 bits must be different from the initial value
setup using the TnOC bit otherwise no change will occur on the TM output pin when
a compare match occurs. After the TM output pin changes state, it can be reset to its
initial level by changing the level of the TnON bit from low to high.
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In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin
changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to only change the
values of the TnIO1 and TnIO0 bits only after the TMn has been switched off.
Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when
the TM is running.
Bit 3TnOC: TPn Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon
whether TM is being used in the Compare Match Output Mode or in the PWM Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output
Mode it determines the logic level of the TM output pin before a compare match
occurs. In the PWM Mode it determines if the PWM signal is active high or active
low.
Bit 2TnPOL: TPn Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TPn output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
Bit 1TnDPX: TMn PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0TnCCLR: Select TMn Counter clear condition
0: TMn Comparatror P match
1: TMn Comparatror A match
This bit is used to select the method which clears the counter. Remember that the
Compact TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the TnCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not
used in the PWM Mode.
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TMnDL Register (n=2)
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: TMn Counter Low Byte Register bit 7 ~ bit 0
TMn 16-bit Counter bit 7 ~ bit 0
TMnDH Register (n=2)
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0D15~D8: TMn Counter High Byte Register bit 7 ~ bit 0
TMn 16-bit Counter bit 15 ~ bit 8
TMnAL Register (n=2)
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: TMn CCRA Low Byte Register bit 7 ~ bit 0
TMn 16-bit CCRA bit 7 ~ bit 0
TMnAH Register (n=2)
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0D15~D8: TMn CCRA High Byte Register bit 7 ~ bit 0
TMn 16-bit CCRA bit 15 ~ bit 8
TMnRP Register (n=2)
Bit
7
6
5
4
3
2
1
0
Name
TnRP7
TnRP6
TnRP5
TnRP4
TnRP3
TnRP2
TnRP1
TnRP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0TnRP7~TnRP0: TMn CCRP Register bit 7 ~ bit 0, compared with the TMn Counter
bit 15 ~ bit 8. Comparator P Match Period
0: 65536 TMn clocks
1~255: 256×(1~255) TMn clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which
are then compared with the internal counter’s highest eight bits. The result of this
comparison can be selected to clear the internal counter if the TnCCLR bit is set to
zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest eight counter bits, the compare values exist in 256 clock cycle multiples.
Clearing all eight bits to zero is in effect allowing the counter to overflow at its
maximum value.
Rev. 1.00
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Enhanced A/D Type 8-Bit MCU with LCD Driver
Compact Type TM Operating Modes
The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,
PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0
bits in the TMnC1 register.
Compare Match Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00B respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which
allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator
A and Comparator P respectively, will both be generated.
If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the TnAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero,
the counter will overflow when it reaches its maximum 16-bit, FFFF Hex, value, however here the
TnAF interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the TM output pin will change
state. The TM output pin condition however only changes state when a TnAF interrupt request flag
is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag,
generated from a compare match occurs from Comparator P, will have no effect on the TM output
pin. The way in which the TM output pin changes state are determined by the condition of the
TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1
and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match
occurs from Comparator A. The initial condition of the TM output pin, which is setup after the
TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0
bits are zero then no pin change will take place.
Rev. 1.00
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Enhanced A/D Type 8-Bit MCU with LCD Driver
Co�nter Val�e
CCRP = 0
TnCCLR = 0; TnM [1:0] = 00
Co�nter
overflow
CCRP > 0
Co�nter cleared by CCRP val�e
CCRP > 0
0xFFFF
CCRP
Pa�se Res�me
CCRA
Stop
Co�nter
Reset
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
O�tp�t Pin set
to Initial Level
Low if TnOC = 0
O�tp�t Toggle
with TnAF flag
Now TnIO [1:0] = 10
Active High O�tp�t Select
O�tp�t not affected by
TnAF flag. Remains High
�ntil reset by TnON bit
O�tp�t inverts
when TnPOL is high
O�tp�t Pin
Reset to initial val�e
O�tp�t controlled
by other pin-shared f�nction
Here TnIO [1:0] = 11
Toggle O�tp�t Select
Compare Match Output Mode – TnCCLR = 0 (n=2)
Note: 1. With TnCCLR=0, a Comparator P match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
Rev. 1.00
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Enhanced A/D Type 8-Bit MCU with LCD Driver
TnCCLR = 1; TnM[1:0] = 00
Co�nter Val�e
CCRA = 0
Co�nter overflows
CCRA > 0 Co�nter cleared by CCRA val�e
0xFFFF
CCRA = 0
CCRA
Pa�se Res�me
Co�nter
Reset
Stop
CCRP
Time
TnON bit
TnPAU bit
TnPOL bit
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
O�tp�t does
not change
TnPF not
generated
O�tp�t Pin set
to Initial Level
Low if TnOC = 0
O�tp�t not affected by
TnAF flag remains High
�ntil reset by TnON bit
O�tp�t Toggle
with TnAF flag
Now TnIO[1:0] = 10
Active High O�tp�t
Select
O�tp�t controlled by
other pin-shared f�nction
O�tp�t inverts
when TnPOL is high
O�tp�t Pin
Reset to initial val�e
Here TnIO[1:0] = 11
Toggle O�tp�t Select
Compare Match Output Mode – TnCCLR = 1 (n=2)
Note: 1. With TnCCLR=1, a Comparator A match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
4. The TnPF flag is not generated when TnCCLR=1
Rev. 1.00
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Enhanced A/D Type 8-Bit MCU with LCD Driver
Timer/Counter Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output
pin is not used. Therefore the above description and Timing Diagrams for the Compare Match
Output Mode can be used to understand its function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively.
The PWM function within the TM is useful for applications which require functions such as motor
control, heating control, illumination control etc. By providing a signal of fixed frequency but
of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with
varying equivalent DC RMS values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM
operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one
register is used to clear the internal counter and thus control the PWM waveform frequency, while
the other one is used to control the duty cycle. Which register is used to control either frequency
or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform
frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to
select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to
enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is
used to reverse the polarity of the PWM output waveform.
• 16-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
1~255
0
Period
CCRP×256
65536
Duty
CCRA
If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 2 and CCRA = 128,
The TM PWM output frequency = (fSYS/4)/(2×256)=fSYS/2048=7.8125kHz, duty=128/(2×256)=25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 16-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
1~255
Period
0
CCRA
Duty
CCRP×256
65536
The PWM output period is determined by the CCRA register value together with the TM clock
while the PWM duty cycle is defined by the (CCRP×256) except when the CCRP value is equal to
000b.
Rev. 1.00
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Enhanced A/D Type 8-Bit MCU with LCD Driver
Co�nter Val�e
TnDPX = 0; TnM [1:0] = 10
Co�nter cleared
by CCRP
Co�nter Reset when
TnON ret�rns high
CCRP
Pa�se Res�me
CCRA
Co�nter Stop if
TnON bit low
Time
TnON
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM D�ty Cycle
set by CCRA
PWM Period
set by CCRP
PWM res�mes
operation
O�tp�t controlled by
O�tp�t Inverts
other pin-shared f�nction
when TnPOL = 1
PWM Mode – TnDPX = 0 (n=2)
Note: 1. Here TnDPX=0 – Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
Rev. 1.00
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Enhanced A/D Type 8-Bit MCU with LCD Driver
Co�nter Val�e
TnDPX = 1; TnM [1:0] = 10
Co�nter cleared
by CCRA
Co�nter Reset when
TnON ret�rns high
CCRA
Pa�se Res�me
CCRP
Co�nter Stop if
TnON bit low
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM D�ty Cycle
set by CCRP
PWM Period
set by CCRA
PWM res�mes
operation
O�tp�t controlled by
O�tp�t Inverts
other pin-shared f�nction
when TnPOL = 1
PWM Mode – TnDPX = 1 (n=2)
Note: 1. Here TnDPX = 1 – Counter cleared by CCRA
2. A counter clear sets the PWM Period
3. The internal PWM function continues even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
Rev. 1.00
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HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Standard Type TM – STM (only for HT66F318)
The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can
also be controlled with an external input pin and can drive one external output pin.
Device
Name
TM No.
TM Input Pin
TM Output Pin
HT66F318
16-bit STM
0
TCK0
TP0
Standard TM Operation
There is a 16-bit wide STM. At the core is a 16-bit count-up counter which is driven by a user
selectable internal or external clock source. There are also two internal comparators with the names,
Comparator A and Comparator P. These comparators will compare the value in the counter with
CCRP and CCRA registers. The CCRP comparator is 8-bit wide whose value is compared with the
highest 8 bits in the counter while the CCRA is the 16 bits and therefore compares all counter bits.
The only way of changing the value of the 16-bit counter using the application program, is to
clear the counter by changing the TnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Standard
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control an output pin. All operating setup conditions are
selected using relevant internal registers.
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Rev. 1.00
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HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Standard Type TM Register Description
Overall operation of the Standard TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store
the internal 16-bit CCRA value. There is also a read/write register used to store the internal 8-bit
CCRP value. The remaining two registers are control registers which setup the different operating
and control modes.
Bit
Register
Name
7
6
5
4
3
2
1
0
TMnC0
TnPAU
TnCK2
TnCK1
TnCK0
TnON
—
—
—
TMnC1
TnM1
TnM0
TnIO1
TnIO0
TnOC
TnPOL
TnDPX
TnCCLR
TMnDL
D7
D6
D5
D4
D3
D2
D1
D0
TMnDH
D15
D14
D13
D12
D11
D10
D9
D8
TMnAL
D7
D6
D5
D4
D3
D2
D1
D0
TMnAH
D15
D14
D13
D12
D11
D10
D9
D8
TMnRP
TnRP7
TnRP6
TnRP5
TnRP4
TnRP3
TnRP2
TnRP1
TnRP0
16-bit Standard TM Register List (n=0)
TMnC0 Register (n=0)
Bit
7
6
5
4
3
2
1
0
Name
TnPAU
TnCK2
TnCK1
TnCK0
TnON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7TnPAU: TMn Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6~4TnCK2~TnCK0: Select TMn Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: fH/8
110: TCKn rising edge clock
111: TCKn falling edge clock
These three bits are used to select the clock source for the TM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fH and fTBC are other internal clocks, the details of which can
be found in the oscillator section.
Rev. 1.00
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Enhanced A/D Type 8-Bit MCU with LCD Driver
Bit 3TnON: TMn Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the
counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the
counter from counting and turn off the TM which will reduce its power consumption.
When the bit changes state from low to high the internal counter value will be reset
to zero, however when the bit changes from high to low, the internal counter will
retain its residual value. If the TM is in the Compare Match Output Mode then the TM
output pin will be reset to its initial condition, as specified by the TnOC bit, when the
TnON bit changes from low to high.
Bit 2~0
Unimplemented, read as “0”
TMnC1 Register (n=0)
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
TnM1
TnM0
TnIO1
TnIO0
TnOC
TnPOL
TnDPX
TnCCLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
TnM1, TnM0: Select TMn Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation
the TM should be switched off before any changes are made to the TnM1 and TnM0
bits. In the Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4
TnIO1, TnIO0: Select TPn output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/Single Pulse Output Mode
00: PWM Output inactive state
01: PWM Output active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of TPn
01: Input capture at falling edge of TPn
10: Input capture at falling/rising edge of TPn
11: Input capture disabled
Timer/Counter Mode
Unused
These two bits are used to determine how the TM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the TM is running.
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Enhanced A/D Type 8-Bit MCU with LCD Driver
In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the
TM output pin changes state when a compare match occurs from the Comparator A.
The TM output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the TM output
pin should be setup using the TnOC bit in the TMnC1 register. Note that the output
level requested by the TnIO1 and TnIO0 bits must be different from the initial value
setup using the TnOC bit otherwise no change will occur on the TM output pin when
a compare match occurs. After the TM output pin changes state, it can be reset to its
initial level by changing the level of the TnON bit from low to high.
In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin
changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to only change
the values of the TnIO1 and TnIO0 bits only after the TM has been switched off.
Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when
the TM is running.
Bit 3TnOC: TPn Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon
whether TM is being used in the Compare Match Output Mode or in the PWM Mode/
Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In
the Compare Match Output Mode it determines the logic level of the TM output pin
before a compare match occurs. In the PWM Mode it determines if the PWM signal is
active high or active low.
Bit 2TnPOL: TPn Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TPn output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
Bit 1TnDPX: TMn PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0TnCCLR: Select TMn Counter clear condition
0: TMn Comparatror P match
1: TMn Comparatror A match
This bit is used to select the method which clears the counter. Remember that the
Compact TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the TnCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not
used in the PWM Mode, Single Pulse or Input Capture Mode.
Rev. 1.00
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Enhanced A/D Type 8-Bit MCU with LCD Driver
TMnDL Register (n=0)
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: TMn Counter Low Byte Register bit 7 ~ bit 0
TMn 16-bit Counter bit 7 ~ bit 0
TMnDH Register (n=0)
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0D15~D8: TMn Counter High Byte Register bit 7 ~ bit 0
TMn 16-bit Counter bit 15 ~ bit 8
TMnAL Register (n=0)
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
2
D10
R/W
0
1
D9
R/W
0
0
D8
R/W
0
Bit 7~0D7~D0: TMn CCRA Low Byte Register bit 7 ~ bit 0
TMn 16-bit CCRA bit 7 ~ bit 0
TMnAH Register (n=0)
Bit
Name
R/W
POR
7
D15
R/W
0
6
D14
R/W
0
5
D13
R/W
0
4
D12
R/W
0
3
D11
R/W
0
Bit 7~0D15~D8: TMn CCRA High Byte Register bit 7 ~ bit 0
TMn 16-bit CCRA bit 15 ~ bit 8
TMnRP Register (n=0)
Bit
7
6
5
4
3
2
1
0
Name
TnRP7
TnRP6
TnRP5
TnRP4
TnRP3
TnRP2
TnRP1
TnRP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0TnRP7~TnRP0: TMn CCRP Register bit 7 ~ bit 0, compared with the TMn Counter
bit 15 ~ bit 8. Comparator P Match Period
0: 65536 TMn clocks
1~255: 256×(1~255) TMn clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which
are then compared with the internal counter’s highest eight bits. The result of this
comparison can be selected to clear the internal counter if the TnCCLR bit is set to
zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest eight counter bits, the compare values exist in 256 clock cycle multiples.
Clearing all eight bits to zero is in effect allowing the counter to overflow at its
maximum value.
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Standard Type TM Operating Modes
The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register.
Compare Match Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match from Comparator P, the other is when the CCRP bits are all zero which allows
the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and
Comparator P respectively, will both be generated.
If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the TnAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output
Mode, the CCRA can not be set to “0”.
As the name of the mode suggests, after a comparison is made, the TM output pin, will change
state. The TM output pin condition however only changes state when a TnAF interrupt request flag
is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag,
generated from a compare match occurs from Comparator P, will have no effect on the TM output
pin. The way in which the TM output pin changes state are determined by the condition of the
TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1
and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match
occurs from Comparator A. The initial condition of the TM output pin, which is setup after the
TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0
bits are zero then no pin change will take place.
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Co�nter Val�e
CCRP = 0
TnCCLR = 0; TnM [1:0] = 00
Co�nter
overflow
CCRP > 0
Co�nter cleared by CCRP val�e
CCRP > 0
0xFFFF
CCRP
Pa�se Res�me
CCRA
Stop
Co�nter
Reset
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
O�tp�t Pin set
to Initial Level
Low if TnOC = 0
O�tp�t Toggle
with TnAF flag
Now TnIO [1:0] = 10
Active High O�tp�t Select
O�tp�t not affected by
TnAF flag. Remains High
�ntil reset by TnON bit
O�tp�t inverts
when TnPOL is high
O�tp�t Pin
Reset to initial val�e
O�tp�t controlled
by other pin-shared f�nction
Here TnIO [1:0] = 11
Toggle O�tp�t Select
Compare Match Output Mode – TnCCLR = 0 (n=0)
Note: 1. With TnCCLR=0 a Comparator P match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to itsinitial state by a TnON bit rising edge
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TnCCLR = 1; TnM[1:0] = 00
Co�nter Val�e
CCRA = 0
Co�nter overflows
CCRA > 0 Co�nter cleared by CCRA val�e
0xFFFF
CCRA = 0
CCRA
Pa�se Res�me
Co�nter
Reset
Stop
CCRP
Time
TnON bit
TnPAU bit
TnPOL bit
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
O�tp�t does
not change
TnPF not
generated
O�tp�t Pin set
to Initial Level
Low if TnOC = 0
O�tp�t not affected by
TnAF flag remains High
�ntil reset by TnON bit
O�tp�t Toggle
with TnAF flag
Now TnIO[1:0] = 10
Active High O�tp�t
Select
O�tp�t controlled by
other pin-shared f�nction
O�tp�t inverts
when TnPOL is high
O�tp�t Pin
Reset to initial val�e
Here TnIO[1:0] = 11
Toggle O�tp�t Select
Compare Match Output Mode – TnCCLR = 1 (n=0)
Note: 1. With TnCCLR=1 a Comparator A match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
4. A TnPF flag is not generated when TnCCLR=1
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Timer/Counter Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output
pin is not used. Therefore the above description and Timing Diagrams for the Compare Match
Output Mode can be used to understand its function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively
and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within
the TM is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM
period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. Which register is used to control either frequency or duty cycle
is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty
cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to
select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to
enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is
used to reverse the polarity of the PWM output waveform.
• 16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
1~255
0
Period
CCRP×256
65536
Duty
CCRA
If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 2 and CCRA = 128,
The TM PWM output frequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz, duty=128/(2×256)=25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
1~255
Period
0
CCRA
Duty
CCRP×256
65536
The PWM output period is determined by the CCRA register value together with the TM clock
while the PWM duty cycle is defined by the (CCRP×256) except when the CCRP value is equal to
000b.
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Co�nter Val�e
TnDPX = 0; TnM [1:0] = 10
Co�nter cleared
by CCRP
Co�nter Reset when
TnON ret�rns high
CCRP
Pa�se Res�me
CCRA
Co�nter Stop if
TnON bit low
Time
TnON
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM D�ty Cycle
set by CCRA
PWM Period
set by CCRP
PWM res�mes
operation
O�tp�t controlled by
O�tp�t Inverts
other pin-shared f�nction
when TnPOL = 1
PWM Mode – TnDPX = 0 (n=0)
Note: 1. Here TnDPX=0 – Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
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Co�nter Val�e
TnDPX = 1; TnM [1:0] = 10
Co�nter cleared
by CCRA
Co�nter Reset when
TnON ret�rns high
CCRA
Pa�se Res�me
CCRP
Co�nter Stop if
TnON bit low
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM D�ty Cycle
set by CCRP
PWM Period
set by CCRA
PWM res�mes
operation
O�tp�t controlled by
O�tp�t Inverts
other pin-shared f�nction
when TnPOL = 1
PWM Mode – TnDPX = 1 (n=0)
Note: 1. Here TnDPX=1 – Counter cleared by CCRA
2. A counter clear sets the PWM Period
3. The internal PWM function continues even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
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Single Pulse Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively
and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode,
as the name suggests, will generate a single shot pulse on the TM output pin.
The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can
be implemented using the application program. However in the Single Pulse Mode, the TnON bit
can also be made to automatically change from low to high using the external TCKn pin, which will
in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter
will start running and the pulse leading edge will be generated. The TnON bit should remain high
when the pulse is in its active state. The generated pulse trailing edge will be generated when the
TnON bit is cleared to zero, which can be implemented using the application program or when a
compare match occurs from Comparator A.
            Single Pulse Generation (n=0)
However a compare match from Comparator A will also automatically clear the TnON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control
the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter
can only be reset back to zero when the TnON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in
this Mode.
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Co�nter Val�e
TnM [1:0] = 10 ; TnIO [1:0] = 11
Co�nter stopped
by CCRA
Co�nter Reset when
TnON ret�rns high
CCRA
Pa�se
Co�nter Stops
by software
Res�me
CCRP
Time
TnON
Software
Trigger
A�to. set by
TCKn pin
Cleared by
CCRA match
TCKn pin
Software
Trigger
Software
Trigger
Software
Software Trigger
Clear
TCKn pin
Trigger
TnPAU
TnPOL
CCRP Int.
Flag TnPF
No CCRP Interr�pts
generated
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
O�tp�t Inverts
when TnPOL = 1
P�lse Width
set by CCRA
Single Pulse Mode (n=0)
Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse is triggered by the TCKn pin or by setting the TnON bit high
4. A TCKn pin active edge will automatically set the TnON bit hight
5. In the Single Pulse Mode, TnIO [1:0] must be set to “11” and can not be changed.
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Capture Input Mode
To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal
is supplied on the TPn pin, whose active edge can be either a rising edge, a falling edge or both
rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits
in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is
initiated using the application program.
When the required edge transition appears on the TPn pin the present value in the counter will be
latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on
the TPn pin the counter will continue to free run until the TnON bit changes from high to low. When
a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value
can be used to control the maximum counter value. When a CCRP compare match occurs from
Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt
signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and
TnIO0 bits can select the active trigger edge on the TPn pin to be a rising edge, falling edge or both
edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place
irrespective of what happens on the TPn pin, however it must be noted that the counter will continue
to run.
As the TPn pin is pin shared with other functions, care must be taken if the TM is in the Capture
Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may
cause an input capture operation to be executed. The TnCCLR and TnDPX bits are not used in this
Mode.
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Counter Value
TnM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
YY
Pause
Resume
XX
Time
TnON
TnPAU
TM capture
pin TPn
Active
edge
Active
edge
Active edge
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
CCRA
Value
TnIO [1:0]
Value
XX
00 – Rising edge
YY
01 – Falling edge
XX
10 – Both edges
YY
11 – Disable Capture
Capture Input Mode (n=0)
Note: 1. TnM [1:0] = 01 and active edge set by the TnIO [1:0] bits
2. A TM Capture input pin active edge transfers the counter value to CCRA
3. TnCCLR bit not used
4. No output function – TnOC and TnPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to
zero.
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Periodic Type TM – PTM
The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can
be controlled with an external input pin and can drive one external output pin.
Device
Name
TM No.
TM Input Pin
TM Output Pin
HT66F317
10-bit PTM
0, 1
TCK0, TCK1
TP0, TP1
HT66F318
10-bit PTM
1
TCK1
TP1
Periodic TM Operation
At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock
source. There are two internal comparators with the names, Comparator A and Comparator P. These
comparators will compare the value in the counter with the CCRA and CCRP registers.
The only way of changing the value of the 10-bit counter using the application program, is to
clear the counter by changing the TnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Periodic
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control the output pin. All operating setup conditions are
selected using relevant internal registers.
CCRP
fSYS/4
fSYS
fH/16
fH/64
fTBC
fH
10-bit Comparator P
001
b0~b9
011
10-bit Co�nt-�p Co�nter
100
101
TnON
TnPAU
111
TnCK�~TnCK0
b0~b9
10-bit Comparator A
TnMPF Interr�pt
TnOC
010
110
TCKn
Comparator P Match
000
Co�nter Clear
0
1
TnCCLR
Comparator A Match
O�tp�t
Control
Polarity
Control
TnM1� TnM0
TnIO1� TnIO0
TnPOL
TPn Pin
Inp�t/O�tp�t
TPn
TnAF Interr�pt
TnIO1� TnIO0
CCRA
Edge
Detector
0
1
TnCAPTS
Periodic Type TM Block Diagram (n=0 or 1)
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Enhanced A/D Type 8-Bit MCU with LCD Driver
Periodic Type TM Register Description
Overall operation of the Periodic TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store
the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which
setup the different operating and control modes.
Bit
Register
Name
7
6
5
4
3
2
1
0
TMnC0
TnPAU
TnCK2
TnCK1
TnCK0
TnON
—
—
—
TMnC1
TnM1
TnM0
TnIO1
TnIO0
TnOC
TnPOL
TnCAPTS
TnCCLR
TMnDL
D7
D6
D5
D4
D3
D2
D1
D0
TMnDH
—
—
—
—
—
—
D9
D8
TMnAL
D7
D6
D5
D4
D3
D2
D1
D0
TMnAH
—
—
—
—
—
—
D9
D8
TMnRPL
D7
D6
D5
D4
D3
D2
D1
D0
TMnRPH
—
—
—
—
—
—
D9
D8
10-bit Periodic TM Register List (n=0 or 1)
TMnC0 Register (n=0 or 1)
Bit
7
6
5
4
3
2
1
0
Name
TnPAU
TnCK2
TnCK1
TnCK0
TnON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7TnPAU: TMn Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6~4TnCK2~TnCK0: Select TMn Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: fH
110: TCKn rising edge clock
111: TCKn falling edge clock
These three bits are used to select the clock source for the TM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fH and fTBC are other internal clocks, the details of which can
be found in the oscillator section.
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Bit 3TnON: TMn Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the
counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the
counter from counting and turn off the TM which will reduce its power consumption.
When the bit changes state from low to high the internal counter value will be reset to
zero, however when the bit changes from high to low, the internal counter will retain
its residual value until the bit returns high again.
If the TM is in the Compare Match Output Mode then the TM output pin will be reset
to its initial condition, as specified by the TnOC bit, when the TnON bit changes from
low to high.
Bit 2~0
Unimplemented, read as “0”
TMnC1 Register (n=0 or 1)
Bit
7
6
5
4
3
2
1
0
Name
TnM1
TnM0
TnIO1
TnIO0
TnOC
TnPOL
TnCAPTS
TnCCLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6TnM1~TnM0: Select TMn Operation Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation
the TM should be switched off before any changes are made to the TnM1 and TnM0
bits. In the Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4TnIO1~TnIO0: Select TPn output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/Single Pulse Output Mode
00: PWM Output inactive state
01: PWM Output active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of TPn or TCKn
01: Input capture at falling edge of TPn or TCKn
10: Input capture at falling/rising edge of TPn or TCKn
11: Input capture disabled
Timer/counter Mode
Unused
These two bits are used to determine how the TM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the TM is running.
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In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the
TM output pin changes state when a compare match occurs from the Comparator A.
The TM output pin can be setup to switch high, switch low or to toggle its present state
when a compare match occurs from the Comparator A. When these bits are both zero,
then no change will take place on the output. The initial value of the TM output pin
should be setup using the TnOC bit. Note that the output level requested by the TnIO1
and TnIO0 bits must be different from the initial value setup using the TnOC bit
otherwise no change will occur on the TM output pin when a compare match occurs.
After the TM output pin changes state, it can be reset to its initial level by changing
the level of the TnON bit from low to high.
In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin
changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to change the values
of the TnIO1 and TnIO0 bits only after the TM has been switched off. Unpredictable
PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is
running.
Bit 3TnOC: TPn Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/ Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon
whether TM is being used in the Compare Match Output Mode or in the PWM Mode/
Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In
the Compare Match Output Mode it determines the logic level of the TM output pin
before a compare match occurs. In the PWM Mode it determines if the PWM signal is
active high or active low.
Bit 2TnPOL: TPn Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TPn output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
Bit 1TnCAPTS: TMn capture trigger source select
0: From TPn pin
1: From TCKn pin
Bit 0TnCCLR: Select TMn Counter clear condition
0: TMn Comparatror P match
1: TMn Comparatror A match
This bit is used to select the method which clears the counter. Remember that the
Periodic TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the TnCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not
used in the PWM, Single Pulse or Input Capture Mode.
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TMnDL Register (n=0 or 1)
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: TMn Counter Low Byte Register bit 7 ~ bit 0
TMn 10-bit Counter bit 7 ~ bit 0
TMnDH Register (n=0 or 1)
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R
R
POR
—
—
—
—
—
—
0
0
2
1
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0D9~D8: TMn Counter High Byte Register bit 1 ~ bit 0
TMn 10-bit Counter bit 9 ~ bit 8
TMnAL Register (n=0 or 1)
Bit
7
6
5
4
3
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: TMn CCRA Low Byte Register bit 7 ~ bit 0
TMn 10-bit CCRA bit 7 ~ bit 0
TMnAH Register (n=0 or 1)
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
2
1
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0D9~D8: TMn CCRA High Byte Register bit 1 ~ bit 0
TMn 10-bit CCRA bit 9 ~ bit 8
TMnRPL Register (n=0 or 1)
Bit
7
6
5
4
3
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: TMn CCRP Low Byte Register bit 7 ~ bit 0
TMn 10-bit CCRP bit 7 ~ bit 0
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TMnRPH Register (n=0 or 1)
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0D9~D8: TMn CCRP High Byte Register bit 1 ~ bit 0
TMn 10-bit CCRP bit 9 ~ bit 8
Periodic Type TM Operating Modes
The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register.
Compare Match Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be all cleared to 00
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be
cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits
are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt request
flags for Comparator Aand Comparator P respectively, will both be generated.
If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the TnAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output
Mode, the CCRA can not be set to “0”.
As the name of the mode suggests, after a comparison is made, the TM output pin, will change
state. The TM output pin condition however only changes state when a TnAF interrupt request flag
is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag,
generated from a compare match from Comparator P, will have no effect on the TM output pin. The
way in which the TM output pin changes state are determined by the condition of the TnIO1 and
TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0
bits to go high, to go low or to toggle from its present condition when a compare match occurs from
Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes
from low to high, is setup using the TnOC bit. Note that if the TnIO1, TnIO0 bits are zero then no
pin change will take place.
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Counter Value
Counter overflow
CCRP=0
0x3FF
TnCCLR = 0; TnM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Counter
Restart
Resume
CCRP
Pause
CCRA
Stop
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
Output pin set to
initial Level Low
if TnOC=0
Output not affected by TnAF
flag. Remains High until reset
by TnON bit
Output Toggle with
TnAF flag
Here TnIO [1:0] = 11
Toggle Output select
Note TnIO [1:0] = 10
Active High Output select
Output Inverts
when TnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – TnCCLR = 0 (n=0 or 1)
Note: 1. With TnCCLR = 0 – a Comparator P match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to initial state by a TnON bit rising edge
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Counter Value
TnCCLR = 1; TnM [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0x3FF
CCRA=0
Resume
CCRA
Pause
Stop
Counter Restart
CCRP
Time
TnON
TnPAU
TnPOL
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TnPF not
generated
Output does
not change
TM O/P Pin
Output pin set to
initial Level Low
if TnOC=0
Output not affected by
TnAF flag. Remains High
until reset by TnON bit
Output Toggle with
TnAF flag
Here TnIO [1:0] = 11
Toggle Output select
Note TnIO [1:0] = 10
Active High Output select
Output Inverts
when TnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – TnCCLR = 1 (n=0 or 1)
Note: 1. With TnCCLR = 1 – a Comparator A match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to initial state by a TnON rising edge
4. The TnPF flag is not generated when TnCCLR = 1
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Timer/Counter Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should all be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output
pin is not used. Therefore the above description and Timing Diagrams for the Compare Match
Output Mode can be used to understand its function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other pin-shared functions.
PWM Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively
and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within
the TM is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM
period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, the CCRP
register is used to clear the internal counter and thus control the PWM waveform frequency, while
the CCRA register is used to control the duty cycle. The PWM waveform frequency and duty cycle
can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to
select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to
enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is
used to reverse the polarity of the PWM output waveform.
• 10-bit PTM, PWM Mode
CCRP
1~1023
0
Period
1~1023
1024
Duty
CCRA
If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 512 and CCRA = 128,
The TM PWM output frequency = (fSYS/4) /512= fSYS/2048 = 7.8125kHz, duty = 128/512 = 25%,
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
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Counter Value
TnM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
TnON returns high
CCRP
Pause Resume
CCRA
Counter Stop if
TnON bit low
Time
TnON
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRA
PWM resumes
operation
PWM Period
set by CCRP
Output controlled by
other pin-shared function
Output Inverts
when TnPOL = 1
PWM Mode (n=0 or 1)
Note: 1. Here Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when TnIO[1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
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Single Pulse Output Mode
To select this mode, the required bit pairs, TnM1 and TnM0 should be set to 10 respectively and also
the corresponding TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output
Mode, as the name suggests, will generate a single shot pulse on the TM output pin.
The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can
be implemented using the application program. However in the Single Pulse Mode, the TnON bit
can also be made to automatically change from low to high using the external TCKn pin, which will
in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter
will start running and the pulse leading edge will be generated. The TnON bit should remain high
when the pulse is in its active state. The generated pulse trailing edge will be generated when the
TnON bit is cleared to zero, which can be implemented using the application program or when a
compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the TnON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the
pulse width. A compare match from Comparator A will also generate TM interrupts. The counter can
only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In
the Single Pulse Mode CCRP is not used. The TnCCLR bit is also not used.
            Single Pulse Generation (n=0 or 1)
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Co�nter Val�e
TnM [1:0] = 10 ; TnIO [1:0] = 11
Co�nter stopped
by CCRA
Co�nter Reset when
TnON ret�rns high
CCRA
Pa�se
Co�nter Stops
by software
Res�me
CCRP
Time
TnON
Software
Trigger
A�to. set by
TCKn pin
Cleared by
CCRA match
TCKn pin
Software
Trigger
Software
Trigger
Software
Clear
Software
Trigger
TCKn pin
Trigger
TnPAU
TnPOL
CCRP Int.
Flag TnPF
No CCRP Interr�pts
generated
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
O�tp�t Inverts
when TnPOL = 1
P�lse Width
set by CCRA
Single Pulse Mode (n=0 or 1)
Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse is triggered by the TCKn pin or by setting the TnON bit high
4. A TCKn pin active edge will automatically set the TnON bit high
5. In the Single Pulse Mode, TnIO [1:0] must be set to “11” and can not be changed.
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Capture Input Mode
To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal is
supplied on the TPn or TCKn pin, selected by the TnCAPTS bit in the TMnC1 register. The input
pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active
edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter
is started when the TnON bit changes from low to high which is initiated using the application
program.
When the required edge transition appears on the TPn or TCKn pin the present value in the counter
will be latched into the CCRA register and a TM interrupt generated. Irrespective of what events
occur on the TPn or TCKn pin the counter will continue to free run until the TnON bit changes from
high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way
the CCRP value can be used to control the maximum counter value. When a CCRP compare match
occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow
interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1
and TnIO0 bits can select the active trigger edge on the TPn or TCKn pin to be a rising edge, falling
edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation
will take place irrespective of what happens on the TPn or TCKn pin, however it must be noted that
the counter will continue to run.
As the TPn or TCKn pin is pin shared with other functions, care must be taken if the TMn is in the
Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin
may cause an input capture operation to be executed. The TnCCLR, TnOC and TnPOL bits are not
used in this Mode.
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Counter Value
TnM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
YY
Pause
Resume
XX
Time
TnON
TnPAU
TM capture
pin TPn or
TCKn
Active
edge
Active
edge
Active edge
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
CCRA
Value
TnIO [1:0]
Value
XX
00 – Rising edge
YY
01 – Falling edge
XX
10 – Both edges
YY
11 – Disable Capture
Capture Input Mode (n=0 or 1)
Note: 1. TnM[1:0] = 01 and active edge set by the TnIO[1:0] bits
2. A TM Capture input pin active edge transfers counter value to CCRA
3. The TnCCLR bit is not used
4. No output function – TnOC and TnPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to
zero
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Analog to Digital Converter – ADC
The need to interface to real world analog signals is a common requirement for many electronic
systems. However, to properly process these signals by a microcontroller, they must first be
converted into digital signals by A/D converters. By integrating the A/D conversion electronic
circuitry into the microcontroller, the need for external components is reduced significantly with the
corresponding follow-on benefits of lower costs and reduced component space requirements.
A/D Overview
The devices contain a multi-channel analog to digital converter which can directly interface
to external analog signals, such as that from sensors or other control signals and convert these
signals directly into a 12-bit digital value. The external or internal analog signal to be converted
is determined by the SAINS and SACS bit fields. Note that when the internal analog signal is
to be converted, the selected external input channel will be automatically disconnected to avoid
malfunction. More detailed information about the A/D input signal is described in the “A/D
Converter Control Registers” and “A/D Converter Input Signal” sections respectively.
Device
Input Channels
A/D Channel Select Bits
Input Pins
8
SAINS2~SAINS0,
SACS2~SACS0
AN0~AN7
HT66F317/HT66F318
The accompanying block diagram shows the overall internal structure of the A/D converter, together
with its associated registers.
AVDD
fSYS
ACE7~ACE0
SACS�~SACS0
AN0
SACKS�~
SACKS0
÷ �N
(N=0~7)
ENADC
AVSS
A/D Clock
AN1
ADRFS
SADOL
A/D Converter
A/D Data
Registers
SADOH
AN7
A/D Reference Voltage
START
ADBZ
ENADC
SAINS�~SAINS0
VREFO
SAVRS3~SAVRS0
AVDD
VREFO
AVDD/�
AVDD/4
VBG (1.0V)
VRI OPA
VREF
(Gain=1~4)
VREFI
ENOPA
AVDD
VR
A/D Converter Structure
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Enhanced A/D Type 8-Bit MCU with LCD Driver
A/D Converter Register Description
Overall operation of the A/D converter is controlled using six registers. A read only register pair
exists to store the ADC data 12-bit value. The remaining four registers are control registers which
setup the operating and control function of the A/D converter.
Bit
Register Name
7
6
5
4
3
2
1
0
SADOL(ADRFS=0)
D3
D2
D1
D0
—
—
—
—
SADOL(ADRFS=1)
D7
D6
D5
D4
D3
D2
D1
D0
SADOH(ADRFS=0)
D11
D10
D9
D8
D7
D6
D5
D4
SADOH(ADRFS=1)
—
—
—
—
D11
D10
D9
D8
SADC0
START
ADBZ
ENADC
ADRFS
—
SACS2
SACS1
SACS0
SADC1
SAINS2
SAINS1
SAINS0
—
—
SACKS2
SACKS1
SACKS0
SADC2
ENOPA
VBGEN
VREFI
VREFO
SAVRS3
SAVRS2
SAVRS1
SAVRS0
ACERL
ACE7
ACE6
ACE5
ACE4
ACE3
ACE2
ACE1
ACE0
A/D Converter Register List
A/D Converter Data Registers – SADOL, SADOH
As the devices contain an internal 12-bit A/D converter, it requires two data registers to store the
converted value. These are a high byte register, known as SADOH, and a low byte register, known
as SADOL. After the conversion process takes place, these registers can be directly read by the
microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space
is utilised, the format in which the data is stored is controlled by the ADRFS bit in the SADC0
register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any
unused bits will be read as zero. Note that the A/D converter data register contents will be cleared to
zero if the A/D converter is disabled.
ADRFS
0
1
SADOH
7
6
D11 D10
0
0
SADOL
5
4
3
2
1
0
7
6
5
4
3
2
1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A/D Data Registers
A/D Converter Control Registers – SADC0, SADC1, SADC2, ACERL
To control the function and operation of the A/D converter, several control registers known as
SADC0, SADC1 and SADC2 are provided. These 8-bit registers define functions such as the
selection of which analog channel is connected to the internal A/D converter, the digitised data
format, the A/D clock source as well as controlling the start function and monitoring the A/D
converter busy status. As the device contains only one actual analog to digital converter hardware
circuit, each of the external and internal analog signals must be routed to the converter. The
SACS2~SACS0 bits in the SADC0 register are used to determine which external channel input is
selected to be converted. The SAINS2~SAINS0 bits in the SADC1 register are used to determine
that the analog signal to be converted comes from the internal analog signal or external analog
channel input. If the SAINS2~SAINS0 bits are set to “000” or “100”, the external analog channel
input is selected to be converted and the SACS2~SACS0 bits can determine which external channel
is selected to be converted. If the SAINS2~SAINS0 bits are set to any other values except “000” and
“100”, one of the internal analog signals is selected to be converted. The internal analog signals can
be derived from the A/D converter supply power, AVDD, with a specific ratio of 1, 1/2 or 1/4. If the
internal analog signal is selected to be converted, the external channel signal input will automatically
be switched off to avoid the signal contention.
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Enhanced A/D Type 8-Bit MCU with LCD Driver
SAINS [2:0]
SACS [2:0]
Input Signals
000, 100
000~111
AN0~AN7
Description
001
xxx
VDD
010
xxx
VDD/2
A/D converter power supply voltage/2
011
xxx
VDD/4
A/D converter power supply voltage/4
External channel analog input
A/D converter power supply voltage
A/D Converter Input Signal Selection
The ACERL control registers contains the ACE7~ACE0 bits which determine which pins on
Port A and Port B are used as analog inputs for the A/D converter input and which pins are not to
be used as the A/D converter input. Setting the corresponding bit high will select the A/D input
function, clearing the bit to zero will select either the I/O or other pin-shared function. When the
pin is selected to be an A/D input, its original function whether it is an I/O or other pin-shared
function will be removed. In addition, any internal pull-high resistors connected to these pins will be
automatically removed if the pin is selected to be an A/D input.
SADC0 Register
Bit
7
6
5
4
3
2
1
0
Name
START
ADBZ
ENADC
ADRFS
—
SACS2
SACS1
SACS0
R/W
R/W
R
R/W
R/W
—
R/W
R/W
R/W
POR
0
0
0
0
—
0
0
0
Bit 7START: Start the A/D conversion
0→1→0: Start A/D conversion
0→1: Reset the A/D converter and set ADBZ to 0
1→0: Start A/D conversion and set ADBZ to 1
This bit is used to initiate an A/D conversion process. The bit is normally low but if set
high and then cleared low again, the A/D converter will initiate a conversion process.
Bit 6ADBZ: A/D Converter busy flag
0: No A/D conversion is in progress
1: A/D conversion is in progress
This read only flag is used to indicate whether the A/D conversion is in progress or
not. When the START bit is set from low to high and then to low again, the ADBZ flag
will be set high to indicate that the A/D conversion is initiated. The ADBZ flag will be
cleared to zero after the A/D conversion is complete.
Bit 5ENADC: A/D Converter function enable control
0: Disable
1: Enable
This bit controls the A/D internal function. This bit should be set high to enable the A/D
converter. If the bit is set low, then the A/D converter will be switched off reducing the
device power consumption. When the A/D converter function is disabled, the contents
of the A/D data register pair, SADOH and SADOL, will be cleared to zero.
Bit 4ADRFS: A/D Converter data format control
0: ADC output data format → SADOH=D[11:4]; SADOL=D[3:0]
1: ADC output data format → SADOH=D[11:8]; SADOL=D[7:0]
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers. Details are provided in the A/D converter data register section.
Bit 3
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Bit 2~0SACS2~SACS0: A/D converter external analog input channel selection
000: AN0
001: AN1
010: AN2
011: AN3
100: AN4
101: AN5
110: AN6
111: AN7
SADC1 Register
Bit
7
6
5
4
3
2
1
0
Name
SAINS2
SAINS1
SAINS0
—
—
SACKS2
SACKS1
SACKS0
R/W
R/W
R/W
R/W
—
—
R/W
R/W
R/W
POR
0
0
0
—
—
0
0
0
Bit 7~5SAINS2~SAINS0: A/D converter input signal selection
000,100: External signal – External analog channel input
001: Internal signal – Internal A/D converter power supply voltage AVDD
010: Internal signal – Internal A/D converter power supply voltage AVDD/2
011: Internal signal – Internal A/D converter power supply voltage AVDD/4
101, 110, 111: Reserved
When the internal analog signal is selected to be converted, the external channel input
signal will automatically be switched off regardless of the SACS2~SACS0 bit field
value.
Bit 4~3
Unimplemented, read as “0”
Bit 2~0SACKS2~SACKS0: A/D conversion clock source selection
000: fSYS
001: fSYS /2
010: fSYS /4
011: fSYS /8
100: fSYS /16
101: fSYS /32
110: fSYS /64
111: fSYS /128
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SADC2 Register
Bit
7
6
5
4
3
2
1
0
Name
ENOPA
VBGEN
VREFI
VREFO
SAVRS3
SAVRS2
SAVRS1
SAVRS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7ENOPA: A/D converter OPA enable/disable control
0: Disable
1: Enable
This bit controls the internal OPA function to provide various reference voltage for
the A/D converter. When the bit is set high, the internal reference voltage, VR, can be
used as the internal converter signal or reference voltage by the A/D converter. If the
internal reference voltage is not used by the A/D converter, then the OPA function
should be properly configured to conserve power.
Bit 6VBGEN: Internal Bandgap reference voltage enable control
0: Disable
1: Enable
This is controls the internal Bandgap circuit on/off function to the A/D converter.
When the bit is set high, the Bandgap reference voltage can be used by the A/D
converter. If the Bandgap reference voltage is not used by the A/D converter and
the LVD or LVR function is disabled, then the bandgap reference circuit will be
automatically switched off to conserve power. When the Bandgap reference voltage
is switched on for use by the A/D converter, a certain time should be allowed for the
Bandgap circuit to stabilise before implementing an A/D conversion.
Bit 5VREFI: VREF input control
0: Disable
1: Enable
Bit 4VREFO: VREFO output control
0: Disable
1: Enable
Bit 3~0SAVRS3~SAVRS0: A/D converter reference voltage selection
0000: AVDD
0001: VREF
0010: VREF × 2
0011: VREF × 3
0100: VREF × 4
1001: Inhibit to use
1010: VBG × 2
1011: VBG × 3
1100: VBG × 4
Others: AVDD
When the A/D converter reference voltage source is selected to derive from the
internal VBG voltage, the reference voltage which comes from the AVDD or VREF pin
will be automatically switched off.
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ACERL Register
Bit
7
6
5
4
3
2
1
0
Name
ACE7
ACE6
ACE5
ACE4
ACE3
ACE2
ACE1
ACE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit 7ACE7: Define PB3 is A/D input or not
0: Not A/D input
1: A/D input, AN7
Bit 6ACE6: Define PA7 is A/D input or not
0: Not A/D input
1: A/D input, AN6
Bit 5ACE5: Define PA6 is A/D input or not
0: Not A/D input
1: A/D input, AN5
Bit 4ACE4: Define PA5 is A/D input or not
0: Not A/D input
1: A/D input, AN4
Bit 3ACE3: Define PA4 is A/D input or not
0: Not A/D input
1: A/D input, AN3
Bit 2ACE2: Define PB2 is A/D input or not
0: Not A/D input
1: A/D input, AN2
Bit 1ACE1: Define PB1 is A/D input or not
0: Not A/D input
1: A/D input, AN1
Bit 0ACE0: Define PB0 is A/D input or not
0: Not A/D input
1: A/D input, AN0
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A/D Operation
The START bit is used to start and reset the A/D converter. When the microcontroller sets this bit
from low to high and then low again, an analog to digital conversion cycle will be initiated. When
the START bit is brought from low to high but not low again, the ADBZ bit in the SADC0 register
will be cleared to zero and the analog to digital converter will be reset. It is the START bit that is
used to control the overall start operation of the internal analog to digital converter.
The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion
process is in process or not. When the A/D converter is reset by setting the START bit from low
to high, the ADBZ flag will be cleared to “0”. This bit will be automatically set to “1” by the
microcontroller after an A/D conversion is successfully initiated. When the A/D conversion is
complete, the ADBZ will be cleared to “0”. In addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal
interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to
the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled,
the microcontroller can be used to poll the ADBZ bit in the SADC0 register to check whether it has
been cleared as an alternative method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen
to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the
SACKS2~SACKS0 bits in the SADC1 register. Although the A/D clock source is determined by
the system clock fSYS, and by bits SACKS2~SACKS0, there are some limitations on the maximum
A/D clock source speed that can be selected. As the recommended value of permissible A/D clock
period, tADCK, is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example,
if the system clock operates at a frequency of 4MHz, the SACKS2~SACKS0 bits should not be set
to “000”, “110” or “111”. Doing so will give A/D clock periods that are less than the minimum A/D
clock period or greater than the maximum A/D clock period which may result in inaccurate A/D
conversion values. Refer to the following table for examples, where values marked with an asterisk
* show where, depending upon the device, special care must be taken, as the values may be less than
the specified minimum A/D Clock Period.
A/D Clock Period (tADCK)
SACKS2,
SACKS1,
SACKS0
=000
(fSYS)
SACKS2,
SACKS1,
SACKS0
=001
(fSYS/2)
SACKS2,
SACKS1,
SACKS0
=010
(fSYS/4)
SACKS2,
SACKS1,
SACKS0
=011
(fSYS/8)
SACKS2,
SACKS1,
SACKS0
=100
(fSYS/16)
SACKS2,
SACKS1,
SACKS0
=101
(fSYS/32)
SACKS2,
SACKS1,
SACKS0
=110
(fSYS/64)
SACKS2,
SACKS1,
SACKS0
=111
(fSYS/128)
1MHz
1μs
2μs
4μs
8μs
16μs*
32μs*
64μs*
128μs*
2MHz
500ns
1μs
2μs
4μs
8μs
16μs*
32μs*
64μs*
4MHz
250ns*
500ns
1μs
2μs
4μs
8μs
16μs*
32μs*
8MHz
125ns*
250ns*
500ns
1μs
2μs
4μs
8μs
16μs*
10.67μs*
fSYS
12MHz
83ns*
167ns*
333ns*
667ns
1.33μs
2.67μs
5.33μs
16MHz
62.5ns*
125ns*
250ns*
500ns
1μs
2μs
4μs
8μs
20MHz
50ns*
100ns*
200ns*
400ns*
800ns
1.6μs
3.2μs
6.4μs
A/D Clock Period Examples
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Controlling the power on/off function of the A/D converter circuitry is implemented using the
ENADC bit in the SADC0 register. This bit must be set high to power on the A/D converter. When
the ENADC bit is set high to power on the A/D converter internal circuitry a certain delay, as
indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if
no pins are selected for use as A/D inputs by configuring the corresponding pin control bits, if the
ENADC bit is high then some power will still be consumed. In power conscious applications it is
therefore recommended that the ENADC is set low to reduce power consumption when the A/D
converter function is not being used.
A/D Reference Voltage
The reference voltage supply to the A/D Converter can be supplied from the positive power supply
pin, AVDD, an external reference source supplied on pin VREF or an internal reference source
derived from the Bandgap circuit. Then the selected reference voltage source can be amplified
through an operational amplifier except the one sourced from AVDD. The OPA gain can be equal to
1, 2, 3 or 4. The desired selection is made using the SAVRS3~SAVRS0 bits in the SADC2 register
and relevant pin function control bits. Note that the desired selected reference voltage will be output
on the VREFO pin which is pin-shared with other functions. As the VREF and VREFO pins both
are pin-shared with other functions, when the VREF or VREFO pin is selected as the reference
voltage supply pin, the pin function control bit VREFI or VREFO should be set high to disable other
pin-shared functions. When VREF or VBG is selected by ADC reference voltage, the OPA needs to
be enabled by setting the ENOPA bit to “1”. In addition, if the programs select external reference
voltage VREF and the internal reference voltage VBG as ADC reference voltage, then the hardware
will only choose the internal reference voltage VBG as an ADC reference voltage input.
SAVRS[3:0]
Reference
Description
0000/others
AVDD
ADC Reference Voltage comes from AVDD
0001
VREF
ADC Reference Voltage comes from External VREF
0010
VREF×2
ADC Reference Voltage comes from External VREF×2
0011
VREF×3
ADC Reference Voltage comes from External VREF×3
0100
VREF×4
ADC Reference Voltage comes from External VREF×4
1010
VBG×2
ADC Reference Voltage comes from VBG×2
1011
VBG×3
ADC Reference Voltage comes from VBG×3
1100
VBG×4
ADC Reference Voltage comes from VBG×4
A/D Converter Reference Voltage Selection
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A/D Converter Input Pins
All of the A/D analog input pins are pin-shared with the I/O pins on Port A and Port B as well as
other functions. The corresponding selection bit in the ACERL register, determines whether the
input pin is setup as A/D converter analog input or whether it has other functions. If the control bit
configures its corresponding pin as an A/D analog channel input, the pin will be setup to be an A/D
converter external channel input and the original pin functions disabled. In this way, pins can be
changed under program control to change their function between A/D inputs and other functions.
All pull-high resistors, which are setup through register programming, will be automatically
disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D
pin as an input in the PAC and PBC port control register to enable the A/D input as when the control
bits enable an A/D input, the status of the port control register will be overridden.
The A/D converter has its own reference voltage pin, VREF. However the reference voltage can
also be supplied from the power supply pin or an internal Bandgap circuit, a choice which is made
through the SAVRS3~ SAVRS0 bits in the SADC2 register. The selected A/D reference voltage can
be output on the VREFO pin. The analog input values must not be allowed to exceed the value of
VREF.
Conversion Rate and Timing Diagram
A complete A/D conversion contains two parts, data sampling and data conversion. The data
sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/D
clock cycles. Therefore a total of 16 A/D clock cycles for an A/D conversion which is defined as tADC
are necessary.
Maximum single A/D conversion rate = A/D clock period /16
The accompanying diagram shows graphically the various stages involved in an analog to digital
conversion process and its associated timing. After an A/D conversion process has been initiated
by the application program, the microcontroller internal hardware will begin to carry out the
conversion, during which time the program can continue with other functions. The time taken for the
A/D conversion is 16tADCK clock cycles where tADCK is equal to the A/D clock period.
tON�ST
ENADC
off
on
off
A/D sampling time
tADS
A/D sampling time
tADS
Start of A/D conversion
Start of A/D conversion
on
START
ADBZ
SACS[�:0]
End of A/D
conversion
011B
A/D channel switch
End of A/D
conversion
010B
tADC
A/D conversion time
Start of A/D conversion
000B
tADC
A/D conversion time
001B
tADC
A/D conversion time
A/D Conversion Timing
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Summary of A/D Conversion Steps
The following summarises the individual steps that should be executed in order to implement an A/D
conversion process.
• Step 1
Select the required A/D conversion clock by properly programming the SACKS2 ~ SACKS0 bits
in the SADC1 register.
• Step 2
Enable the A/D converter by setting the ENADC bit in the SADC0 register to “1”.
• Step 3
Select which signal is to be connected to the internal A/D converter by correctly configuring the
SAINS2 ~ SAINS0 bits.
Select the external channel input to be converted, go to Step 4.
Select the internal analog signal to be converted, go to Step 5.
• Step 4
If the A/D input signal comes from the external channel input selecting by configuring the SAINS
bit field, the corresponding pin should first be configured as A/D input function by configuring
the relevant pin control bit in the ACERL register. The desired analog channel then should be
selected by configuring the SACS bit field. After this step, go to Step 6.
• Step 5
If the A/D input signal is selected to come from the internal analog signal, the SAINS bit
field should be properly configured and then the external channel input will automatically be
disconnected regardless of the SACS bit field value. After this step, go to Step 6.
• Step 6
Select the reference voltage source by configuring the SAVRS3~SAVRS0 bits.
Note: If select VREF as reference voltage, the VREFI bit must be set high.
• Step 7
Select A/D converter output data format by configuring the ADRFS bit.
• Step 8
If A/D conversion interrupt is used, the interrupt control registers must be correctly configured
to ensure the A/D interrupt function is active. The master interrupt control bit, EMI, and the A/D
converter interrupt bits, ADE, must both set high in advance.
• Step 9
The A/D conversion procedure can now be initialised by setting the START bit from low to high
and then low again.
• Step 10
If A/D conversion is in progress, the ADBZ flag will be set high. After the A/D conversion
process is completed, the ADBZ flag will go low and then output data can be read from the
SADOH and SADOL registers. If the ADC interrupt is enabled and the stack is not full, data can
be acquired by interrupt service program.
Note: When checking for the end of the conversion process, if the method of polling the ADBZ bit
in the SADC0 register is used, the interrupt enable step above can be omitted.
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Programming Considerations
During microcontroller operations where the A/D converter is not being used, the A/D internal
circuitry can be switched off to reduce power consumption, by clearing the ENADC bit in the
SADC0 register. When this happens, the internal A/D converter circuits will not consume power
irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are
used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then
this may lead to some increase in power consumption.
A/D Transfer Function
As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to
FFFH. Since the full-scale analog input value is equal to the VREFO voltage, this gives a single bit
analog input value of VREFO divided by 4096.
1 LSB = VREFO / 4096
The A/D Converter input voltage value can be calculated using the following equation:
A/D input voltage = A/D output digital value ×VREFO / 4096
The diagram shows the ideal transfer function between the analog input value and the digitised
output value for the A/D converter. Except for the digitised zero value, the subsequent digitised
values will change at a point 0.5 LSB below where they would change without the offset, and the
last full scale digitised value will change at a point 1.5 LSB below the VREFO level.
    
­  
      Ideal A/D Transfer Function
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A/D Programming Examples
The following two programming examples illustrate how to setup and implement an A/D conversion.
In the first example, the method of polling the ADBZ bit in the SADC0 register is used to detect
when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to
determine when the conversion is complete.
Example: using an ADBZ polling method to detect the end of conversion
clr
ADE; disable ADC interrupt
mova,03H
mov SADC1,a ; select fSYS/8 as A/D clock
set ENADC
mov a,01h ; setup ACERL to configure pin AN0
mov ACERL,a
mova,20h
mov SADC0,a ; enable and connect AN0 channel to A/D converter
:
start_conversion:
clr START ; high pulse on start bit to initiate conversion
set START ; reset A/D
clr START ; start A/D
polling_EOC:
sz ADBZ ; poll the SADC0 register ADBZ bit to detect end of A/D conversion
jmp polling_EOC ; continue polling
mov a,SADOL ; read low byte conversion result value
mov SADOL_buffer,a ; save result to user defined register
mov a,SADOH ; read high byte conversion result value
mov SADOH_buffer,a ; save result to user defined register
:
:
jmp start_conversion ; start next A/D conversion
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Example: using the interrupt method to detect the end of conversion
clr
ADE ; disable ADC interrupt
mova,03H
mov SADC1,a ; select fSYS/8 as A/D clock
set ENADC
mov a,01h ; setup ACERL to configure pin AN0
mov ACERL,a
mova,20h
mov SADC0,a ; enable and connect AN0 channel to A/D converter
Start_conversion:
clr START ; high pulse on START bit to initiate conversion
set START ; reset A/D
clr START ; start A/D
clr ADF ; clear ADC interrupt request flag
set
ADE ; enable ADC interrupt
set EMI ; enable global interrupt
:
:
; ADC interrupt service routine
ADC_ISR:
mov acc_stack,a ; save ACC to user defined memory
mov a,STATUS
mov status_stack,a ; save STATUS to user defined memory
:
:
mov a,SADOL ; read low byte conversion result value
mov SADOL_buffer,a ; save result to user defined register
mov a,SADOH ; read high byte conversion result value
mov SADOH_buffer,a ; save result to user defined register
:
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a ; restore STATUS from user defined memory
mov a,acc_stack ; restore ACC from user defined memory
reti
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Comparator (only for HT66F318)
An analog comparator is contained within this device. The comparator function offers flexibility
via their register controlled features such as power-down, polarity select, hysteresis etc. In sharing
their pins with normal I/O pins the comparators do not waste precious I/O pins if there functions are
otherwise unused.
Comparator
Comparator Operation
The device contains a comparator function which is used to compare two analog voltages and
provide an output based on their difference. Full control over the internal comparator is provided
via the control register CPC assigned to the comparator. The comparator output is recorded via a bit
in the control register, but can also be transferred out onto a shared I/O pin. Additional comparator
functions include, output polarity, hysteresis functions and power down control.
Any pull-high resistors connected to the shared comparator input pins will be automatically
disconnected when the comparator is enabled. As the comparator inputs approach their switching
level, some spurious output signals may be generated on the comparator output due to the slow
rising or falling nature of the input signals. This can be minimised by selecting the hysteresis
function will apply a small amount of positive feedback to the comparator. Ideally the comparator
should switch at the point where the positive and negative inputs signals are at the same voltage
level, however, unavoidable input offsets introduce some uncertainties here. The hysteresis function,
if enabled, also increases the switching offset value.
CPC Register
Bit
7
6
5
4
3
2
1
0
Name
CSEL
CEN
CPOL
COUT
COS
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
POR
1
0
0
0
0
0
0
1
CMPEG1 CMPEG0
CHYEN
Bit 7CSEL: Select Comparator pins or other pin functions
0: Other pin functions
1: Comparator input pin C+ and C- selected
This is the Comparator input pin or other pin functions select bit. If the bit is high
the comparator input pins will be enabled. As a result, these two pins will lose their
original pin functions. Any pull-high options associated with the comparator shared
pins will also be automatically disconnected.
Bit 6CEN: Comparator On/Off control
0: Off
1: On
This is the Comparator on/off control bit. If the bit is zero the comparator will be
switched off and no power consumed even if analog voltages are applied to its inputs.
For power sensitive applications this bit should be cleared to zero if the comparator is
not used or before the device enters the SLEEP or IDLE mode.
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Bit 5CPOL: Comparator output polarity
0: Output not inverted
1: Output inverted
This is the comparator polarity bit. If the bit is zero then the COUT bit will reflect
the non-inverted output condition of the comparator. If the bit is high the comparator
COUT bit will be inverted.
Bit 4COUT: Comparator output bit
CPOL=0
0: C+ < C1: C+ > CCPOL=1
0: C+ > C1: C+ < CThis bit stores the comparator output bit. The polarity of the bit is determined by the
voltages on the comparator inputs and by the condition of the CPOL bit.
Bit 3COS: Output path select
0: CX pin (compare output can output to CX pin)
1: I/O pin or other pin functions (compare output only internal use)
Bit 2~1CMPEG1~CMPEG0: Comparator interrupt edge Control
00: Rising edge
01: Falling edge
1x: Rising edge and falling edge
Bit 0CHYEN: Hysteresis Control
0: Off
1: On
This is the hysteresis control bit and if set high will apply a limited amount of
hysteresis to the comparator, as specified in the Comparator Electrical Characteristics
table. The positive feedback induced by hysteresis reduces the effect of spurious
switching near the comparator threshold.
Comparator Interrupt
The comparator possesses its own interrupt function. When the comparator output bit changes state,
its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump
to its relevant interrupt vector will be executed. Note that it is the changing state of the COUT bit
and not the output pin which generates an interrupt. If the microcontroller is in the SLEEP or IDLE
Mode and the Comparator is enabled, then if the external input lines cause the Comparator output bit
to change state, the resulting generated interrupt flag will also generate a wake-up. If it is required to
disable a wake-up from occurring, then the interrupt flag should be first set high before entering the
SLEEP or IDLE Mode.
Programming Considerations
If the comparator is enabled, it will remain active when the microcontroller enters the SLEEP or
IDLE Mode, however as it will consume a certain amount of power, the user may wish to consider
disabling it before the SLEEP or IDLE Mode is entered. As comparator pins are shared with normal
I/O pins the I/O registers for these pins will be read as zero (port control register is “1”) or read as
port data register value (port control register is “0”) if the comparator function is enabled.
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I2C Interface (only for HT66F318)
The I 2C interface is used to communicate with external peripheral devices such as sensors,
EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface
for synchronous serial data transfer. The advantage of only two lines for communication, relatively
simple communication protocol and the ability to accommodate multiple devices on the same bus
has made it an extremely popular interface type for many applications.
I2C Master/Slave Bus Connection
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­ …
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„ I2C Block Diagram
I2C Interface Operation
The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As
many devices may be connected together on the same bus, their outputs are both open drain types.
For this reason it is necessary that external pull-high resistors are connected to these outputs. Note
that no chip select line exists, as each device on the I2C bus is identified by a unique address which
will be transmitted and received on the I2C bus.
When two devices communicate with each other on the bidirectional I2C bus, one is known as the
master device and one as the slave device. Both master and slave can transmit and receive data,
however, it is the master device that has overall control of the bus. For these devices, which only
operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit
mode and the slave receive mode.
It is suggested that the user shall not enter the micro processor to HALT status by application
program during processing I2C communication.
If the pin is configured to SDA or SCL function of I2C interface, the pin is configured to open-collect
Input/Output port and its Pull-high function can be enabled by programming the related Generic
Pull-high Control Register.
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Enhanced A/D Type 8-Bit MCU with LCD Driver
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I2C Registers
There are four control registers associated with the I2C bus, IICC0, IICC1, IICA and I2CTOC and
one data register, IICD.
Bit
Register
Name
7
6
5
4
3
2
I2CDBNC1 I2CDBNC0
1
0
IICEN
—
IICC0
—
—
—
—
IICC1
IICHCF
IICHAAS
IICHBB
IICHTX
IICTXAK
IICSRW
IICD
IICD7
IICD6
IICD5
IICD4
IICD3
IICD2
IICD1
IICD0
IICA
IICA6
IICA5
IICA4
IICA3
IICA2
IICA1
IICA0
—
I2CTOS3
I2CTOS2
I2CTOC I2CTOEN I2CTOF I2CTOS5 I2CTOS4
IICAMWU IICRXAK
I2CTOS1 I2CTOS0
I2C Registers List
IICC0 Register
Bit
7
6
5
4
Name
—
—
—
—
R/W
—
—
—
—
R/W
POR
—
—
—
—
0
Bit 7~4
3
2
1
0
IICEN
—
R/W
R/W
—
0
0
—
I2CDBNC1 I2CDBNC0
Unimplemented, read as “0”
Bit 3~2I2CDBNC1~I2CDBNC0: I2C Debounce Time Selection
00: No debounce
01: 2 system clock debounce
10: 4 system clock debounce
11: 4 system clock debounce
If fSYS comes from fH and is ready, or IICAMWU=0, the debounce circuit is effect.
Otherwise, SCL and SDA will bypass the debounce circuit.
Rev. 1.00
Bit 1
IICEN: I2C Control
0: Disable
1: Enable
Bit 0
Unimplemented, read as “0”
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The I2C function could be turned off or turned on by controlling the bit IICEN. When the pinshared I/O ports are chosen to be the functions other than SDA and SCL by clearing the IICEN bit to
zero, the I2C function is turned off and its operating current will be reduced to a minimum value. In
contrary, the I2C function is turned on when the pin-shared I/O ports are chosen to be the SDA and
SCL pins by setting the IICEN bit high.
IICC1 Register
Bit
7
6
5
4
3
2
Name
IICHCF
IICHAAS
IICHBB
IICHTX
IICTXAK
IICSRW
1
0
R/W
R
R
R
R/W
R/W
R
R/W
R
POR
1
0
0
0
0
0
0
1
IICAMWU IICRXAK
Bit 7IICHCF: I C Bus data transfer completion flag
0: Data is being transferred
1: Completion of an 8-bit data transfer
The IICHCF flag is the data transfer flag. This flag will be zero when data is being
transferred. Upon completion of an 8-bit data transfer the flag will go high and an
interrupt will be generated. Below is an example of the flow of a two-byte I2C data
transfer.
First, the I2C slave device receives a start signal from the I2C master and then the
IICHCF bit is automatically cleared to zero. Second, the I2C slave device finishes
receiving the 1st data byte and then the IICHCF bit is automatically set to one. Third,
users read the 1st data byte from the IICD register by the application program and then
the IICHCF bit is automatically cleared to zero. Fourth, the I2C slave device finishes
receiving the 2nd data byte and then the IICHCF bit is automatically set high and so
on. Finally, the I2C slave device receives a stop signal from the I2C master and then the
IICHCF bit is automatically set high.
2
Bit 6IICHAAS: I2C Bus address match flag
0: Not address match
1: Address match
The IICHAAS flag is the address match flag. This flag is used to determine if the slave
device address is same as the master transmit address. If the addresses match then this
bit will be high, if there is no match then the flag will be low.
Bit 5IICHBB: I2C Bus busy flag
0: I2C Bus is not busy
1: I2C Bus is busy
The IICHBB flag is the I2C busy flag. This flag will be “1” when the I2C bus is busy
which will occur when a START signal is detected. The flag will be set to “0” when
the bus is free which will occur when a STOP signal is detected.
Bit 4IICHTX: Select I2C slave device is transmitter or receiver
0: Slave device is the receiver
1: Slave device is the transmitter
Bit 3
Rev. 1.00
IICTXAK: I2C Bus transmit acknowledge flag
0: Slave send acknowledge flag
1: Slave do not send acknowledge flag
The IICTXAK bit is the transmit acknowledge flag. After the slave device receipt of
8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave
device. The slave device must always clear the IICTXAK bit to zero before further
data is received.
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Bit 2
IICSRW: I2C Slave Read/Write flag
0: Slave device should be in receive mode
1: Slave device should be in transmit mode
The IICSRW flag is the I2C Slave Read/Write flag. This flag determines whether
the master device wishes to transmit or receive data from the I2C bus. When the
transmitted address and slave address is match, that is when the IICHAAS flag is set
high, the slave device will check the IICSRW flag to determine whether it should be
in transmit mode or receive mode. If the IICSRW flag is high, the master is requesting
to read data from the bus, so the slave device should be in transmit mode. When the
IICSRW flag is zero, the master will write data to the bus, therefore the slave device
should be in receive mode to read this data.
Bit 1IICAMWU: I2C Address Match Control
0: Disable
1: Enable
If fSYS comes from fH and is ready, then this control bit has no effect, I2C address match
can always generate an interrupt as its interrupt enable bit is set.
Otherwise, setting IICAMWU=1 also can generate an interrupt when I2C address
match and its interrupt enable bit is set, but setting IICAMWU=0 maybe cannot
generate an interrupt when I2C address match even if its interrupt enable bit is set.
Bit 0
IICRXAK: I2C Bus Receive acknowledge flag
0: Slave receive acknowledge flag
1: Slave do not receive acknowledge flag
The IICRXAK flag is the receiver acknowledge flag. When the IICRXAK flag is “0”,
it means that a acknowledge signal has been received at the 9th clock, after 8 bits of
data have been transmitted. When the slave device in the transmit mode, the slave
device checks the IICRXAK flag to determine if the master receiver wishes to receive
the next byte. The slave transmitter will therefore continue sending out data until the
IICRXAK flag is “1”. When this occurs, the slave transmitter will release the SDA line
to allow the master to send a STOP signal to release the I2C Bus.
I2CTOC Register
Bit
7
6
Name
I2CTOEN
I2CTOF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
5
4
3
2
1
0
I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0
I2CTOEN: I C Time-out Countrol
0: Disable
1: Enable
2
Bit 6IICTOF: I2C Time-out flag
0: No time-out occurred
1: Time-out occurred
This bit is set high when time-out occurs and can only be cleared by application
program.
Bit 5~0I2CTOS5~I2CTOS0: I2C Time-out period selection
I2C time-out clock source is fSUB/32.
I2C time-out period is equal to (I2CTOS[5:0]+1) × (32/fSUB)
The IICD register is used to store the data being transmitted and received. Before the device writes
data to the I2C bus, the actual data to be transmitted must be placed in the IICD register. After the
data is received from the I2C bus, the device can read it from the IICD register. Any transmission or
reception of data from the I2C bus must be made via the IICD register.
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IICD Register
Bit
7
6
5
4
3
2
1
0
Name
IICD7
IICD6
IICD5
IICD4
IICD3
IICD2
IICD1
IICD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x” unknown
IICA Register
Bit
7
6
5
4
3
2
1
0
Name
IICA6
IICA5
IICA4
IICA3
IICA2
IICA1
IICA0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
POR
0
0
0
0
0
0
0
—
Bit 7~1
IICA6~IICA0: I2C slave address
IICA6~ IICA0 is the I2C slave address bit 6 ~ bit 0.
The IICA register is the location where the 7-bit slave address of the slave device
is stored. Bits 7 ~ 1 of the IICA register define the device slave address. Bit 0 is not
defined.
When a master device, which is connected to the I2C bus, sends out an address, which
matches the slave address in the IICA register, the slave device will be selected.
Bit 0
Unimplemented, read as “0”
I2C Bus Communication
Communication on the I2C bus requires four separate steps, a START signal, a slave device address
transmission, a data transmission and finally a STOP signal. When a START signal is placed on
the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of
data on the bus. The first seven bits of the data will be the slave address with the first bit being the
MSB. If the address of the slave device matches that of the transmitted address, the IICHAAS bit
in the IICC1 register will be set and an I2C interrupt will be generated. After entering the interrupt
service routine, the slave device must first check the condition of the IICHAAS and I2CTOF
bits to determine whether the interrupt source originates from an address match or from an I2C
communication time-out or from the completion of an 8-bit data transfer. During a data transfer, note
that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the
read/write bit whose value will be placed in the IICSRW bit. This bit will be checked by the slave
device to determine whether to go into transmit or receive mode. Before any transfer of data to or
from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this:
• Step 1
Set the IICEN bit in the IICC0 register high to enable the I2C bus.
• Step 2
Write the slave address of the device to the I2C bus address register IICA.
• Step 3
Set the IICE interrupt enable bit of the interrupt control register to enable the I2C interrupt.
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I2C Bus Initialisation Flow Chart
I2C Bus Start Signal
The START signal can only be generated by the master device connected to the I2C bus and not by
the slave device. This START signal will be detected by all devices connected to the I2C bus. When
detected, this indicates that the I2C bus is busy and therefore the IICHBB bit will be set. A START
condition occurs when a high to low transition on the SDA line takes place when the SCL line
remains high.
Slave Address
The transmission of a START signal by the master will be detected by all devices on the I2C bus.
To determine which slave device the master wishes to communicate with, the address of the slave
device will be sent out immediately following the START signal. All slave devices, after receiving
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by
the master matches the internal address of the microcontroller slave device, then an internal I2C bus
interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines
the read/write status and will be saved to the IICSRW bit of the IICC1 register. The slave device will
then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set
the status flag IICHAAS when the addresses match.
As an I2C bus interrupt can come from three sources, when the program enters the interrupt
subroutine, the IICHAAS and I2CTOF bits should be examined to see whether the interrupt source
has come from a matching slave address or from an I2C communication time-out or from the
completion of a data byte transfer. When a slave address is matched, the device must be placed in
either the transmit mode and then write data to the IICD register, or in the receive mode where it
must implement a dummy read from the IICD register to release the SCL line.
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I2C Bus Read/Write Signal
The IICSRW bit in the IICC1 register defines whether the slave device wishes to read data from the
I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is
to be a transmitter or a receiver. If the IICSRW flag is “1” then this indicates that the master device
wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C
bus as a transmitter. If the IICSRW flag is “0” then this indicates that the master wishes to send data
to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver.
I2C Bus Slave Address Acknowledge Signal
After the master has transmitted a calling address, any slave device on the I2C bus, whose own
internal address matches the calling address, must generate an acknowledge signal. The acknowledge
signal will inform the master that a slave device has accepted its calling address. If no acknowledge
signal is received by the master then a STOP signal must be transmitted by the master to end the
communication. When the IICHAAS flag is high, the addresses have matched and the slave device
must check the IICSRW flag to determine if it is to be a transmitter or a receiver. If the IICSRW flag
is high, the slave device should be setup to be a transmitter so the IICHTX bit in the IICC1 register
should be set high. If the IICSRW flag is low, then the microcontroller slave device should be setup
as a receiver and the IICHTX bit in the IICC1 register should be cleared to zero.
I2C Bus Data and Acknowledge Signal
The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged
receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last.
After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level “0”, before
it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal
from the master receiver, then the slave transmitter will release the SDA line to allow the master
to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the IICD
register. If setup as a transmitter, the slave device must first write the data to be transmitted into the
IICD register. If setup as a receiver, the slave device must read the transmitted data from the IICD
register.
When the slave receiver receives the data byte, it must generate an acknowledge bit, known as
IICTXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the
IICRXAK bit in the IICC1 register to determine if it is to send another data byte, if not then it will
release the SDA line and await the receipt of a STOP signal from the master.
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Note: *When a slave address is matched, the device must be placed in either the transmit mode and
then write data to the IICD register, or in the receive mode where it must implement a dummy
read from the IICD register to release the SCL line.
I2C Communication Timing Diagram
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    I2C Bus ISR Flow Chart
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I2C Time-out Control
In order to reduce the problem of I2C lockup due to reception of erroneous clock sources, a time-out
function is provided. If the clock source to the I2C is not received for a while, then the I2C circuitry
and registers will be reset after a certain time-out period. The time-out counter starts counting on an
I2C bus “START” & “address match” condition, and is cleared by an SCL falling edge. Before the
next SCL falling edge arrives, if the time elapsed is greater than the time-out setup by the I2CTOC
register, then a time-out condition will occur. The time-out function will stop when an I2C “STOP”
condition occurs.
S C L
S ta rt
IIC S R W
S la v e A d d r e s s
0
1
S D A
1
1
0
1
0
A C K
1
0
I2 C t i m e - o u t
c o u n te r s ta rt
S to p
S C L
1
0
0
1
0
1
0
0
S D A
I2 C t im e - o u t c o u n t e r r e s e t
o n S C L n e g a tiv e tr a n s itio n
I2C Time-out
When an I2C time-out counter overflow occurs, the counter will stop and the I2CTOEN bit will be
cleared to zero and the I2CTOF bit will be set high to indicate that a time-out condition as occurred.
The time-out condition will also generate an interrupt which uses the I2C interrrupt vector. When
an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the
following condition:
Register
After I2C Time-out
IICD, IICA, IICC0
No change
IICC1
Reset to POR condition
I C Registers After Time-out
2
The I2CTOF flag can be cleared by the application program. There are 64 time-out periods which
can be selected using I2CTOS bits in the I2CTOC register. The time-out time is given by the
formula:
((1~64) × 32) / fSUB
This gives a range of about 1ms to 64ms.
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UART Interface (only for HT66F318)
The device contains an integrated full-duplex asynchronous serial communications UART interface
that enables communication with external devices that contain a serial interface. The UART function
has many features and can transmit and receive data serially by transferring a frame of data with
eight or nine data bits per transmission as well as being able to detect errors when the data is
overwritten or incorrectly framed. The UART function possesses its own internal interrupt which
can be used to indicate when a reception occurs or when a transmission terminates.
The integrated UART function contains the following features:
• Full-duplex, Universal Asynchronous Receiver and Transmitter (UART) communication
• 8 or 9 bits character length
• Even, odd or no parity options
• One or two stop bits
• Baud rate generator with 8-bit prescaler
• Parity, framing, noise and overrun error detection
• Support for interrupt on address detect (last character bit=1)
• Transmitter and receiver enabled independently
• 2-byte Deep FIFO Receive Data Buffer
• Transmit and Receive Multiple Interrupt Generation Sources:
♦♦
Transmitter Empty
♦♦
Transmitter Idle
♦♦
Receiver Full
♦♦
Receiver Overrun
♦♦
Address Mode Detect
♦♦
RX pin wake-up interrupt (RX enable, RX falling edge)
UART External Pin Interfacing
To communicate with an external serial interface, the internal UART has two external pins known
as TX and RX. The TX and RX pins are the UART transmitter and receiver pins respectively. Along
with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O or other
pin-shared functional pins to their respective TX output and RX input conditions and disable any
pull-high resistor option which may exist on the TX or RX pins. When the TX or RX pin function
is disabled by clearing the UARTEN and TXEN or RXEN bit, the TX or RX pin can be used as a
general purpose I/O or other pin-shared functional pin.
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UART Data Transfer Scheme
The block diagram shows the overall data transfer structure arrangement for the UART interface.
The actual data to be transmitted from the MCU is first transferred to the TXR_RXR register by the
application program. The data will then be transferred to the Transmit Shift Register from where it
will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only
the TXR_RXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not
mapped and is therefore inaccessible to the application program.
Data to be received by the UART is accepted on the external RX pin, from where it is shifted in,
LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the
shift register is full, the data will then be transferred from the shift register to the internal TXR_RXR
register, where it is buffered and can be manipulated by the application program. Only the TXR_
RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and
is therefore inaccessible to the application program.
It should be noted that the actual register for data transmission and reception, although referred
to the following figure, as separate TXR and RXR registers, only exists as a single shared register
in the Data Memory. This shared register known as the TXR_RXR register is used for both data
transmission and data reception.
Transmitter Shift Register
MSB
…………………………
Receiver Shift Register
LSB
TX Pin
CLK
RX Pin
MSB
LSB
CLK
Ba�d Rate
Generator
TXR Register
…………………………
RXR Register
B�ffer
MCU Data B�s
UART Data Transfer Scheme
UART Status and Control Registers
There are five control registers associated with the UART function. The USR, UCR1 and UCR2
registers control the overall function of the UART, while the BRG register controls the Baud rate.
The actual data to be transmitted and received on the serial interface is managed through the TXR_
RXR data register.
Bit
Register
Name
7
6
5
4
3
2
1
0
USR
PERR
NF
FERR
OERR
RIDLE
RXIF
TIDLE
TXIF
UCR1
UARTEN
BNO
PREN
PRT
STOPS
TXBRK
RX8
TX8
UCR2
TXEN
RXEN
BRGH
ADDEN
WAKE
RIE
TIIE
TEIE
TXR_
RXR
TXRX7
TXRX6
TXRX5
TXRX4
TXRX3
TXRX2
TXRX1
TXRX0
BRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
UART Register List
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USR register
The USR register is the status register for the UART, which can be read by the program to determine
the present status of the UART. All flags within the USR register are read only. Further explanation
on each of the flags is given below.
Bit
7
6
5
4
3
2
1
0
Name
PERR
NF
FERR
OERR
RIDLE
RXIF
TIDLE
TXIF
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
1
0
1
1
Bit 7PERR: Parity error flag
0: No parity error is detected
1: Parity error is detected
The PERR flag is the parity error flag. When this read only flag is “0”, it indicates a
parity error has not been detected. When the flag is “1”, it indicates that the parity of
the received word is incorrect. This error flag is applicable only if Parity mode (odd or
even) is selected. The flag can also be cleared by a software sequence which involves
a read to the status register USR followed by an access to the TXR_RXR data register.
Bit 6NF: Noise flag
0: No noise is detected
1: Noise is detected
The NF flag is the noise flag. When this read only flag is “0”, it indicates no noise
condition. When the flag is “1”, it indicates that the UART has detected noise on the
receiver input. The NF flag is set during the same cycle as the RXIF flag but will not
be set in the case of as overrun. The NF flag can be cleared by a software sequence
which will involve a read to the status register USR followed by an access to the
TXR_RXR data register.
Bit 5FERR: Framing error flag
0: No framing error is detected
1: Framing error is detected
The FERR flag is the framing error flag. When this read only flag is “0”, it indicates
that there is no framing error. When the flag is “1”, it indicates that a framing error
has been detected for the current character. The flag can also be cleared by a software
sequence which will involve a read to the status register USR followed by an access to
the TXR_RXR data register.
Bit 4OERR: Overrun error flag
0: No overrun error is detected
1: Overrun error is detected
The OERR flag is the overrun error flag which indicates when the receiver buffer has
overflowed. When this read only flag is “0”, it indicates that there is no overrun error.
When the flag is “1”, it indicates that an overrun error occurs which will inhibit further
transfers to the TXR_RXR receive data register. The flag is cleared by a software
sequence, which is a read to the status register USR followed by an access to the
TXR_RXR data register.
Bit 3RIDLE: Receiver status
0: Data reception is in progress (data being received)
1: No data reception is in progress (receiver is idle)
The RIDLE flag is the receiver status flag. When this read only flag is “0”, it indicates
that the receiver is between the initial detection of the start bit and the completion of
the stop bit. When the flag is “1”, it indicates that the receiver is idle. Between the
completion of the stop bit and the detection of the next start bit, the RIDLE bit is “1”
indicating that the UART receiver is idle and the RX pin stays in logic high condition.
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Bit 2RXIF: Receive TXR_RXR data register status
0: TXR_RXR data register is empty
1: TXR_RXR data register has available data
The RXIF flag is the receive data register status flag. When this read only flag is “0”,
it indicates that the TXR_RXR read data register is empty. When the flag is “1”, it
indicates that the TXR_RXR read data register contains new data. When the contents
of the shift register are transferred to the TXR_RXR register, an interrupt is generated
if RIE=1 in the UCR2 register. If one or more errors are detected in the received word,
the appropriate receive-related flags NF, FERR, and/or PERR are set within the same
clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set,
followed by a read from the TXR_RXR register, and if the TXR_RXR register has no
data available.
Bit 1TIDLE: Transmission idle
0: Data transmission is in progress (data being transmitted)
1: No data transmission is in progress (transmitter is idle)
The TIDLE flag is known as the transmission complete flag. When this read only
flag is “0”, it indicates that a transmission is in progress. This flag will be set to “1”
when the TXIF flag is “1” and when there is no transmit data or break character being
transmitted. When TIDLE is equal to “1”, the TX pin becomes idle with the pin state
in logic high condition. The TIDLE flag is cleared by reading the USR register with
TIDLE set and then writing to the TXR_RXR register. The flag is not generated when
a data character or a break is queued and ready to be sent.
Bit 0TXIF: Transmit TXR_RXR data register status
0: Character is not transferred to the transmit shift register
1: Character has transferred to the transmit shift register (TXR_RXR data register is
empty)
The TXIF flag is the transmit data register empty flag. When this read only flag is “0”,
it indicates that the character is not transferred to the transmitter shift register. When
the flag is “1”, it indicates that the transmitter shift register has received a character
from the TXR_RXR data register. The TXIF flag is cleared by reading the UART
status register (USR) with TXIF set and then writing to the TXR_RXR data register.
Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit
data register is not yet full.
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UCR1 register
The UCR1 register together with the UCR2 register are the two UART control registers that are used
to set the various options for the UART function, such as overall on/off control, parity control, data
transfer bit length etc. Further explanation on each of the bits is given below.
Bit
7
6
5
4
3
2
1
0
Name
UARTEN
BNO
PREN
PRT
STOPS
TXBRK
RX8
TX8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
W
POR
0
0
0
0
0
0
x
0
“x” unknown
Bit 7UARTEN: UART function enable control
0: Disable UART. TX and RX pins are as I/O or other pin-shared functional pins
1: Enable UART. TX and RX pins function as UART pins
The UARTEN bit is the UART enable bit. When this bit is equal to “0”, the UART
will be disabled and the RX pin as well as the TX pin will be as General Purpose I/O
or other pin-shared functional pins. When the bit is equal to “1”, the UART will be
enabled and the TX and RX pins will function as defined by the TXEN and RXEN
enable control bits.
When the UART is disabled, it will empty the buffer so any character remaining in
the buffer will be discarded. In addition, the value of the baud rate counter will be
reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN,
RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the
TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and
BRG registers will remain unaffected. If the UART is active and the UARTEN bit is
cleared, all pending transmissions and receptions will be terminated and the module
will be reset as defined above. When the UART is re-enabled, it will restart in the
same configuration.
Bit 6BNO: Number of data transfer bits selection
0: 8-bit data transfer
1: 9-bit data transfer
This bit is used to select the data length format, which can have a choice of either
8-bit or 9-bit format. When this bit is equal to “1”, a 9-bit data length format will be
selected. If the bit is equal to “0”, then an 8-bit data length format will be selected. If
9-bit data length format is selected, then bits RX8 and TX8 will be used to store the
9th bit of the received and transmitted data respectively.
Note: 1. If BNO=1 (9-bit data transfer), the parity function is enabled, the 9th bit of
data is the parity bit which will not be transferred to RX8.
2. If BNO=0 (8-bit data transfer), the parity function is enabled, the 8th bit of
data is the parity bit which will not be transferred to RX7.
Bit 5PREN: Parity function enable control
0: Parity function is disabled
1: Parity function is enabled
This is the parity enable bit. When this bit is equal to “1”, the parity function will be
enabled. If the bit is equal to “0”, then the parity function will be disabled.
Bit 4PRT: Parity type selection bit
0: Even parity for parity generator
1: Odd parity for parity generator
This bit is the parity type selection bit. When this bit is equal to “1”, odd parity type
will be selected. If the bit is equal to “0”, then even parity type will be selected.
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Bit 3STOPS: Number of stop bits selection
0: One stop bit format is used
1: Two stop bits format is used
This bit determines if one or two stop bits are to be used for the TX pin. When this bit
is equal to “1”, two stop bits are used. If this bit is equal to “0”, then only one stop bit
is used.
Bit 2TXBRK: Transmit break character
0: No break character is transmitted
1: Break characters transmit
The TXBRK bit is the Transmit Break Character bit. When this bit is “0”, there are
no break characters and the TX pin operates normally. When the bit is “1”, there are
transmit break characters and the transmitter will send logic zeros. When this bit is
equal to “1”, after the buffered data has been transmitted, the transmitter output is held
low for a minimum of a 13-bit length and until the TXBRK bit is reset.
Bit 1RX8: Receive data bit 8 for 9-bit data transfer format (read only)
This bit is only used if 9-bit data transfers are used, in which case this bit location will
store the 9th bit of the received data known as RX8. The BNO bit is used to determine
whether data transfers are in 8-bit or 9-bit format.
Bit 0TX8: Transmit data bit 8 for 9-bit data transfer format (write only)
This bit is only used if 9-bit data transfers are used, in which case this bit location
will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to
determine whether data transfers are in 8-bit or 9-bit format.
UCR2 register
The UCR2 register is the second of the two UART control registers and serves several purposes. One
of its main functions is to control the basic enable/disable operation of the UART Transmitter and
Receiver as well as enabling the various UART interrupt sources. The register also serves to control
the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on
each of the bits is given below.
Bit
7
6
5
4
3
2
1
0
Name
TXEN
RXEN
BRGH
ADDEN
WAKE
R/W
R/W
R/W
R/W
R/W
R/W
RIE
TIIE
TEIE
R/W
R/W
POR
0
0
0
0
0
0
R/W
0
0
Bit 7TXEN: UART Transmitter enabled control
0: UART transmitter is disabled
1: UART transmitter is enabled
The bit named TXEN is the Transmitter Enable Bit. When this bit is equal to “0”, the
transmitter will be disabled with any pending data transmissions being aborted. In
addition the buffers will be reset. In this situation the TX pin will be used as an I/O or
other pin-shared functional pin.
If the TXEN bit is equal to “1” and the UARTEN bit is also equal to “1”, the
transmitter will be enabled and the TX pin will be controlled by the UART. Clearing
the TXEN bit during a transmission will cause the data transmission to be aborted and
will reset the transmitter.
Bit 6RXEN: UART Receiver enabled control
0: UART receiver is disabled
1: UART receiver is enabled
The bit named RXEN is the Receiver Enable Bit. When this bit is equal to “0”, the
receiver will be disabled with any pending data receptions being aborted. In addition
the receive buffers will be reset. In this situation the RX pin will be used as an I/O or
other pin-shared functional pin. If the RXEN bit is equal to “1” and the UARTEN bit
is also equal to “1”, the receiver will be enabled and the RX pin will be controlled by
the UART. Clearing the RXEN bit during a reception will cause the data reception to
be aborted and will reset the receiver.
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Bit 5BRGH: Baud Rate speed selection
0: Low speed baud rate
1: High speed baud rate
The bit named BRGH selects the high or low speed mode of the Baud Rate Generator.
This bit, together with the value placed in the baud rate register BRG, controls the
Baud Rate of the UART. If this bit is equal to “1”, the high speed mode is selected. If
the bit is equal to “0”, the low speed mode is selected.
Bit 4ADDEN: Address detect function enable control
0: Address detection function is disabled
1: Address detection function is enabled
The bit named ADDEN is the address detect function enable control bit. When this
bit is equal to “1”, the address detect function is enabled. When it occurs, if the 8th
bit, which corresponds to RX7 if BNO=0 or the 9th bit, which corresponds to RX8 if
BNO=1, has a value of “1”, then the received word will be identified as an address,
rather than data. If the corresponding interrupt is enabled, an interrupt request will be
generated each time the received word has the address bit set, which is the 8th or 9th
bit depending on the value of BNO. If the address bit known as the 8th or 9th bit of the
received word is “0” with the address detect function being enabled, an interrupt will
not be generated and the received data will be discarded.
Bit 3WAKE: RX pin falling edge wake-up function enable control
0: RX pin wake-up function is disabled
1: RX pin wake-up function is enabled
This bit enables or disables the receiver wake-up function. If this bit is equal to “1”
and the device is in the IDLE0 or SLEEP mode, a falling edge on the RX input pin
will wake-up the device. If this bit is equal to “0” and the device is in the IDLE or
SLEEP mode, any edge transitions on the RX pin will not wake-up the device.
Bit 2RIE: Receiver interrupt enable control
0: Receiver related interrupt is disabled
1: Receiver related interrupt is enabled
This bit enables or disables the receiver interrupt. If this bit is equal to “1” and when
the receiver overrun flag OERR or receive data available flag RXIF is set, the UART
interrupt request flag will be set. If this bit is equal to “0”, the UART interrupt request
flag will not be influenced by the condition of the OERR or RXIF flags.
Bit 1TIIE: Transmitter Idle interrupt enable control
0: Transmitter idle interrupt is disabled
1: Transmitter idle interrupt is enabled
This bit enables or disables the transmitter idle interrupt. If this bit is equal to “1” and
when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the
UART interrupt request flag will be set. If this bit is equal to “0”, the UART interrupt
request flag will not be influenced by the condition of the TIDLE flag.
Bit 0TEIE: Transmitter Empty interrupt enable control
0: Transmitter empty interrupt is disabled
1: Transmitter empty interrupt is enabled
This bit enables or disables the transmitter empty interrupt. If this bit is equal to “1”
and when the transmitter empty flag TXIF is set, due to a transmitter empty condition,
the UART interrupt request flag will be set. If this bit is equal to “0”, the UART
interrupt request flag will not be influenced by the condition of the TXIF flag.
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TXR_RXR register
The TXR_RXR register is the data register which is used to store the data to be transmitted on the
TX pin or being received from the RX pin.
Bit
7
6
5
4
3
2
1
0
Name
TXRX7
TXRX6
TXRX5
TXRX4
TXRX3
TXRX2
TXRX1
TXRX0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x” unknown
Bit 7~0TXRX7~TXRX0: UART Transmit/Receive Data bit 7 ~ bit 0
Baud Rate Generator
To setup the speed of the serial data communication, the UART function contains its own dedicated
baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the
period of which is determined by two factors. The first of these is the value placed in the baud rate
register BRG and the second is the value of the BRGH bit with the control register UCR2. The
BRGH bit decides if the baud rate generator is to be used in a high speed mode or low speed mode,
which in turn determines the formula that is used to calculate the baud rate. The value in the BRG
register, N, which is used in the following baud rate calculation formula determines the division
factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and
255.
UCR2 BRGH Bit
0
1
Baud Rate (BR)
fSYS / [64 (N+1)]
fSYS / [16 (N+1)]
By programming the BRGH bit which allows selection of the related formula and programming the
required value in the BRG register, the required baud rate can be setup. Note that because the actual
baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error
associated between the actual and requested value. The following example shows how the BRG
register value N and the error value can be calculated.
BRG Register
Bit
7
6
5
4
3
2
1
0
Name
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x” unknown
Bit 7~0BRG7~BRG0: Baud Rate values
By programming the BRGH bit in UCR2 Register which allows selection of the
related formula described above and programming the required value in the BRG
register, the required baud rate can be setup.
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Calculating the Baud Rate and error values
For a clock frequency of 4MHz, and with BRGH set to “0” determine the BRG register value N, the
actual baud rate and the error value for a desired baud rate of 4800.
From the above table the desired baud rate BR = fSYS / [64 (N+1)]
Re-arranging this equation gives N = [fSYS / (BR×64)] - 1
Giving a value for N = [4000000 / (4800×64)] - 1 = 12.0208
To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives
an actual or calculated baud rate value of BR = 4000000 / [64× (12 + 1)] = 4808
Therefore the error is equal to (4808 - 4800) / 4800 = 0.16%
The following table shows actual values of baud rate and error values for the two values of BRGH.
Baud Rate
K/BPS
fSYS=8MHz
Baud Rates for BRGH=0
BRG
Kbaud
Baud Rates for BRGH=1
Error (%)
BRG
Kbaud
Error (%)
—
0.3
—
—
—
—
—
1.2
103
1.202
0.16
—
—
—
2.4
51
2.404
0.16
207
2.404
0.16
4.8
25
4.808
0.16
103
4.808
0.16
9.6
12
9.615
0.16
51
9.615
0.16
19.2
6
17.8857
-6.99
25
19.231
0.16
38.4
2
41.667
8.51
12
38.462
0.16
57.6
1
62.500
8.51
8
55.556
-3.55
115.2
0
125
8.51
3
125
8.51
250
—
—
—
1
250
0
Baud Rates and Error Values
UART Setup and Control
For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ,
format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity
is supported by the UART hardware, and can be setup to be even, odd or no parity. For the most
common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used
as the default setting, which is the setting at power-on. The number of data bits and stop bits, along
with the parity, are setup by programming the corresponding BNO, PRT, PREN, and STOPS bits
in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal
8-bit baud rate generator, while the data is transmitted and received LSB first. Although the UART
transmitter and receiver are functionally independent, they both use the same data format and baud
rate. In all cases stop bits will be used for data transmission.
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Enabling/disabling the UART interface
The basic on/off function of the internal UART function is controlled using the UARTEN bit in the
UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act
as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX
pin, then it will default to a logic high value.
Clearing the UARTEN bit will disable the TX and RX pins and allow these two pins to be used as
normal I/O or other pin-shared functional pins. When the UART function is disabled the buffer will
be reset to an empty condition, at the same time discarding any remaining residual data. Disabling
the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR,
FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining
control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in
the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions
will be immediately suspended and the UART will be reset to a condition as defined above. If the
UART is then subsequently re-enabled, it will restart again in the same configuration.
Data, parity and stop bit selection
The format of the data to be transferred is composed of various factors such as data bit length,
parity on/off, parity type, address bits and the number of stop bits. These factors are determined by
the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits
which can be set to either 8 or 9, the PRT bit controls the choice of odd or even parity, the PREN
bit controls the parity on/off function and the STOPS bit decides whether one or two stop bits are to
be used. The following table shows various formats for data transmission. The address bit identifies
the frame as an address character. The number of stop bits, which can be either one or two, is
independent of the data length and are only to be used for Transmitter. There is only one stop bit for
Receiver.
Start Bit
Data Bits
Address Bits
Parity Bits
Stop Bit
Example of 8-bit Data Formats
1
8
0
0
1
1
7
0
1
1
1
7
1
0
1
Example of 9-bit Data Formats
1
9
0
0
1
1
8
0
1
1
1
8
1
0
1
Transmitter Receiver Data Format
The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data
formats.
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UART Transmitter
Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1
register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which
is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies
the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from
the transmit data register, which is known as the TXR_RXR register. The data to be transmitted
is loaded into this TXR_RXR register by the application program. The TSR register is not written
to with new data until the stop bit from the previous transmission has been sent out. As soon as
this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR_RXR
register, if it is available. It should be noted that the TSR register, unlike many other registers, is not
directly mapped into the Data Memory area and as such is not available to the application program
for direct read/write operations. An actual transmission of data will normally be enabled when the
TXEN bit is set, but the data will not be transmitted until the TXR_RXR register has been loaded
with data and the baud rate generator has defined a shift clock source. However, the transmission
can also be initiated by first loading data into the TXR_RXR register, after which the TXEN bit can
be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to
the TXR_RXR register will result in an immediate transfer to the TSR. If during a transmission the
TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The
TX output pin will then return to the I/O or other pin-shared function.
Transmitting Data
When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with
the least significant bit first. In the transmit mode, the TXR_RXR register forms a buffer between
the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been
selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a
data transfer can be summarized as follows:
• Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word
length, parity type and number of stop bits.
• Setup the BRG register to select the desired baud rate.
• Set the TXEN bit to ensure that the UART transmitter is enabled and the TX pin is used as a
UART transmitter pin.
• Access the USR register and write the data that is to be transmitted into the TXR_RXR register.
Note that this step will clear the TXIF bit.
This sequence of events can now be repeated to send additional data. It should be noted that when
TXIF is “0”, data will be inhibited from being written to the TXR_RXR register. Clearing the TXIF
flag is always achieved using the following software sequence:
• A USR register access
• A TXR_RXR register write execution
The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR_RXR
register is empty and that other data can now be written into the TXR_RXR register without
overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt.
During a data transmission, a write instruction to the TXR_RXR register will place the data into the
TXR_RXR register, which will be copied to the shift register at the end of the present transmission.
When there is no data transmission in progress, a write instruction to the TXR_RXR register will
place the data directly into the shift register, resulting in the commencement of data transmission,
and the TXIF bit being immediately set. When a frame transmission is complete, which happens
after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the
following software sequence is used:
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• A USR register access
• A TXR_RXR register write execution
Note that both the TXIF and TIDLE bits are cleared by the same software sequence.
Transmitting Break
If the TXBRK bit is set then break characters will be sent on the next transmission. Break character
transmission consists of a start bit, followed by 13×N ‘0’ bits and stop bits, where N=1, 2, etc. If a
break character is to be transmitted then the TXBRK bit must be first set by the application program
and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit
interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually
kept at a logic high level then the transmitter circuitry will transmit continuous break characters.
After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the
last break character and subsequently send out one or two stop bits. The automatic logic highs at the
end of the last break character will ensure that the start bit of the next frame is recognized.
UART Receiver
The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming
the BNO bit in the UCR register. If the BNO bit is set, the word length will be set to 9 bits with the
MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies the Receive Serial
Shift Register, commonly known as the RSR. The data which is received on the RX external input
pin is sent to the data recovery block. The data recovery block operating speed is 16 times that of the
baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled
for the stop bit, the received data in RSR is transferred to the receive data register, if the register is
empty. The data which is received on the external RX input pin is sampled three times by a majority
detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted
that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area
and as such is not available to the application program for direct read/write operations.
Receiving Data
When the UART receiver is receiving data, the data is serially shifted in on the external RX input
pin to the shift register, with the least significant bit LSB first. The TXR_RXR register is a two byte
deep FIFO data buffer, where two bytes can be held in the FIFO while a third byte can continue to
be received. Note that the application program must ensure that the data is read from TXR_RXR
before the third byte has been completely shifted in, otherwise this third byte will be discarded and
an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be
summarized as follows:
• Make the correct selection of BNO, PRT and PREN bits to define the word length and parity
type.
• Setup the BRG register to select the desired baud rate.
• Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART
receiver pin.
At this point the receiver will be enabled which will begin to look for a start bit.
When a character is received, the following sequence of events will occur:
• The RXIF bit in the USR register will be set when TXR_RXR register has data available, at least
one character can be read.
• When the contents of the shift register have been transferred to the TXR_RXR register and if the
RIE bit is set, then an interrupt will be generated.
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• If during reception, a frame error, noise error, parity error, or an overrun error has been detected,
then the error flags can be set.
The RXIF bit can be cleared using the following software sequence:
• A USR register access
• An TXR_RXR register read execution
Receive Break
Any break character received by the UART will be managed as a framing error. The receiver will
count and expect a certain number of bit times as specified by the values programmed into the BNO
and one STOPS bit. If the break is much longer than 13 bit times, the reception will be considered
as complete after the number of bit times specified by BNO and one STOP bit. The RXIF bit is set,
FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate
and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a
start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a
valid stop bit before looking for the next start bit. The receiver will not make the assumption that the
break condition on the line is the next start bit. A break is regarded as a character that contains only
zeros with the FERR flag set. The break character will be loaded into the buffer and no further data
will be received until stop bits are received. It should be noted that the RIDLE read only flag will go
high when the stop bits have not yet been received. The reception of a break character on the UART
registers will result in the following:
• The framing error flag, FERR, will be set.
• The receive data register, TXR_RXR, will be cleared.
• The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set.
Idle Status
When the receiver is reading data, which means it will be in between the detection of a start bit and
the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE
flag, will have a zero value. In between the reception of a stop bit and the detection of the next start
bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition.
Receiver Interrupt
The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the
receiver. An interrupt is generated if RIE bit is “1”, when a word is transferred from the Receive
Shift Register, RSR, to the Receive Data Register, TXR_RXR. An overrun error can also generate
an interrupt if RIE is “1”.
Managing Receiver Errors
Several types of reception errors can occur within the UART module, the following section describes
the various types and how they are managed by the UART.
Overrun Error – OERR flag
The TXR_RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be
held in the FIFO register, while a third byte can continue to be received. Before this third byte has
been entirely shifted in, the data should be read from the TXR_RXR register. If this is not done, the
overrun error flag OERR will be consequently indicated.
In the event of an overrun error occurring, the following will happen:
• The OERR flag in the USR register will be set.
• The RXR contents will not be lost.
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• The shift register will be overwritten.
• An interrupt will be generated if the RIE bit is set.
The OERR flag can be cleared by an access to the USR register followed by a read to the TXR_
RXR register.
Noise Error – NF Flag
Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is
detected within a frame the following will occur:
• The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit.
• Data will be transferred from the Shift register to the TXR_RXR register.
• No interrupt will be generated. However this bit rises at the same time as the RXIF bit which
itself generates an interrupt.
Note that the NF flag is reset by a USR register read operation followed by a TXR_RXR register
read operation.
Framing Error – FERR Flag
The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of
stop bits. If two stop bits are selected, only the first stop bit is detected, it must be high. If the first
stop bit is low, the FERR flag will be set. The FERR flag is buffered along with the received data
and is cleared on any reset.
Parity Error – PERR Flag
The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is
incorrect. This error flag is only applicable if the parity is enabled, PREN bit is “1”, and if the parity
type, odd or even is selected. The read only PERR flag is buffered along with the received data
bytes. It is cleared on any reset. It should be noted that the FERR and PERR flags are buffered along
with the corresponding word and should be read before reading the data word.
UART Module Interrupt Structure
Several individual UART conditions can generate a UART interrupt. When these conditions exist,
a low pulse will be generated to get the attention of the microcontroller. These conditions are a
transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address
detect and an RX pin wake-up. When any of these conditions are created, if its corresponding
interrupt control is enabled and the stack is not full, the program will jump to its corresponding
interrupt vector where it can be serviced before returning to the main program. Four of these
conditions have the corresponding USR register flags which will generate a UART interrupt if its
associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt
conditions have their own corresponding enable control bits, while the two receiver interrupt
conditions have a shared enable control bit. These enable bits can be used to mask out individual
UART interrupt sources.
The address detect condition, which is also a UART interrupt source, does not have an associated
flag, but will generate a UART interrupt when an address detect condition occurs if its function
is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a
UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the
microcontroller is woken up from IDLE0 or SLEEP mode by a falling edge on the RX pin, if the
WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt
occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for
the oscillator to restart and stabilize before the system resumes normal operation.
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Note that the USR register flags are read only and cannot be cleared or set by the application
program, neither will they be cleared when the program jumps to the corresponding interrupt
servicing routine, as is the case for some of the other interrupts. The flags will be cleared
automatically when certain actions are taken by the UART, the details of which are given in the
UART register section. The overall UART interrupt can be disabled or enabled by the related
interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether
the interrupt requested by the UART module is masked out or allowed.
USR Register
UCR� Register
Transmitter Empty
Flag TXIF
TEIE
Transmitter Idle
Flag TIDLE
TIIE
0
1
RIE
0
1
Receiver Overr�n
Flag OERR
OR
Receiver Data
Available RXIF
RX Pin
Wake-�p
WAKE
ADDEN
0
1
UART Interr�pt
Req�est Flag
UARTF
INTC�
Register
UARTE
INTC0
Register
EMI
0
1
0
1
0
1
RX7 if BNO=0
RX8 if BNO=1
UCR� Register
UART Interrupt Scheme
Address Detect Mode
Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode.
If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver
Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is “1”, then when
data is available, an interrupt will only be generated, if the highest received bit has a high value.
Note that the related interrupt enable control bit and the EMI bit must also be enabled for correct
interrupt generation. This highest address bit is the 9th bit if BNO bit is “1” or the 8th bit if BNO
bit is “0”. If this bit is high, then the received word will be defined as an address rather than data. A
Data Available interrupt will be generated every time the last bit of the received word is set. If the
ADDEN bit is “0”, then a Receiver Data Available interrupt will be generated each time the RXIF
flag is set, irrespective of the data last bit status. The address detect mode and parity enable are
mutually exclusive functions. Therefore if the address detect mode is enabled, then to ensure correct
operation, the parity function should be disabled by resetting the parity enable bit PREN to zero.
ADDEN
0
1
Bit 9 if BNO=1,
Bit 8 if BNO=0
UART Interrupt Generated
0
√
1
√
0
×
1
√
ADDEN Bit Function
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UART Power Down and Wake-up
When the device system clock is switched off, the UART will cease to function. If the device
executes the “HALT” instruction and switches off the system clock while a transmission is still
in progress, then the transmission will be paused until the UART clock source derived from the
microcontroller is activated. In a similar way, if the device executes the “HALT” instruction and
switches off the system clock while receiving data, then the reception of data will likewise be
paused. When the device enters the IDLE or SLEEP Mode, note that the USR, UCR1, UCR2,
transmit and receive registers, as well as the BRG register will not be affected. It is recommended
to make sure first that the UART data transmission or reception has been finished before the
microcontroller enters the IDLE or SLEEP mode.
The UART function contains a receiver RX pin wake-up function, which is enabled or disabled
by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the
receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the device enters the
IDLE0 or SLEEP Mode, then a falling edge on the RX pin will wake up the device from the IDLE0
or SLEEP Mode. Note that as it takes certain system clock cycles after a wake-up, before normal
microcontroller operation resumes, any data received during this time on the RX pin will be ignored.
For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global
interrupt enable bit, EMI, and the UART interrupt enable bit, UARTE, must also be set. If these two
bits are not set then only a wake up event will occur and no interrupt will be generated. Note also
that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes,
the UART interrupt will not be generated until after this time has elapsed.
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an
internal function such as a Timer Module or an A/D converter requires microcontroller attention,
their corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs. The devices contain several external
interrupt and internal interrupts functions. The external interrupt is generated by the action of the
external INTn pin, while the internal interrupts are generated by various internal functions such as
TMs, Comparator, I2C, UART, Time Base, LVD, EEPROM and the A/D converter.
Interrupt Registers
Overall interrupt control, which basically means the setting of request flags when certain
microcontroller conditions occur and the setting of interrupt enable bits by the application program,
is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the
accompanying table. The first is the INTC0~INTC2 registers which setup the primary interrupts,
the second is the MFI0~MFI2 registers which setup the Multi-function interrupts. Finally there is an
INTEG register to setup the external interrupt trigger edge type.
Each register contains a number of enable bits to enable or disable individual registers as well as
interrupt flags to indicate the presence of an interrupt request. The naming convention of these
follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of
that interrupt followed by either an “E” for enable/ disable bit or “F” for request flag.
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Function
Enable Bit
Request Flag
EMI
—
—
INTnE
INTnF
n=0 or 1
CPE
CPF
Only for HT66F318
Multi-function
MFnE
MFnF
n=0~2
A/D Converter
ADE
ADF
—
Time Base
TBnE
TBnF
n=0 or 1
—
Global
INTn Pin
Comparator
Notes
LVD
LVE
LVF
EEPROM
DEE
DEF
—
I2C
IICE
IICF
Only for HT66F318
UARTE
UARTF
Only for HT66F318
TnPE
TnPF
TnAE
TnAF
n=0~1 for HT66F317
n=0~2 for HT66F318
UART
TM
Interrupt Register Bit Naming Conventions
Interrupt Register Contents
• HT66F317
Bit
Register
Name
7
6
5
4
3
2
1
0
INTEG
—
—
—
—
INT1S1
INT1S0
INT0S1
INT0S0
INTC0
—
MF0F
—
INT0F
MF0E
—
INT0E
EMI
INTC1
TB0F
ADF
MF2F
MF1F
TB0E
ADE
MF2E
MF1E
INTC2
—
—
INT1F
TB1F
—
—
INT1E
TB1E
MFI0
—
—
T0AF
T0PF
—
—
T0AE
T0PE
MFI1
—
—
T1AF
T1PF
—
—
T1AE
T1PE
MFI2
—
—
DEF
LVF
—
—
DEE
LVE
• HT66F318
Rev. 1.00
Bit
Register
Name
7
6
5
4
3
2
1
0
INTEG
—
—
—
—
INT1S1
INT1S0
INT0S1
INT0S0
INTC0
—
MF0F
CPF
INT0F
MF0E
CPE
INT0E
EMI
INTC1
TB0F
ADF
MF2F
MF1F
TB0E
ADE
MF2E
MF1E
INTC2
UARTF
IICF
INT1F
TB1F
UARTE
IICE
INT1E
TB1E
MFI0
—
—
T0AF
T0PF
—
—
T0AE
T0PE
MFI1
T2AF
T2PF
T1AF
T1PF
T2AE
T2PE
T1AE
T1PE
MFI2
—
—
DEF
LVF
—
—
DEE
LVE
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INTEG Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
INT1S1
INT1S0
INT0S1
INT0S0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
0
Bit 7~4
Unimplemented, read as “0”
Bit 3~2INT1S1~INT1S0: interrupt edge control for INT1 pin
00: Disable
01: Rising edge
10: Falling edge
11: Both rising and falling edges
Bit 1~0INT0S1~INT0S0: interrupt edge control for INT0 pin
00: Disable
01: Rising edge
10: Falling edge
11: Both rising and falling edges
INTC0 Register — HT66F317
Bit
7
6
5
4
3
2
1
Name
—
MF0F
—
INT0F
MF0E
—
INT0E
EMI
R/W
—
R/W
—
R/W
R/W
—
R/W
R/W
POR
—
0
—
0
0
—
0
0
Bit 7
Unimplemented, read as “0”
Bit 6MF0F: Multi-function Interrupt 0 Request Flag
0: No request
1: Interrupt request
Bit 5
Unimplemented, read as “0”
Bit 4INT0F: INT0 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 3MF0E: Multi-function 0 Interrupt Control
0: Disable
1: Enable
Bit 2
Unimplemented, read as “0”
Bit 1INT0E: INT0 Interrupt Control
0: Disable
1: Enable
Bit 0EMI: Global Interrupt Control
0: Disable
1: Enable
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INTC0 Register — HT66F318
Bit
7
6
5
4
3
2
1
0
Name
—
MF0F
CPF
INT0F
MF0E
CPE
INT0E
EMI
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as “0”
Bit 6MF0F: Multi-function Interrupt 0 Request Flag
0: No request
1: Interrupt request
Bit 5CPF: Comparator interrupt request flag
0: No request
1: Interrupt request
Bit 4INT0F: INT0 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 3MF0E: Multi-function 0 Interrupt Control
0: Disable
1: Enable
Bit 2CPE: Comparator interrupt control
0: Disable
1: Enable
Bit 1INT0E: INT0 Interrupt Control
0: Disable
1: Enable
Bit 0EMI: Global Interrupt Control
0: Disable
1: Enable
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INTC1 Register
Bit
7
6
5
4
3
2
1
0
Name
TB0F
ADF
MF2F
MF1F
TB0E
ADE
MF2E
MF1E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7TB0F: Time Base 0 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 6ADF: A/D Converter Interrupt Request Flag
0: No request
1: Interrupt request
Bit 5MF2F: Multi-function Interrupt 2 Request Flag
0: No request
1: Interrupt request
Bit 4MF1F: Multi-function Interrupt 1 Request Flag
0: No request
1: Interrupt request
Bit 3TB0E: Time Base 0 Interrupt Control
0: Disable
1: Enable
Bit 2ADE: A/D Converter Interrupt Control
0: Disable
1: Enable
Bit 1MF2E: Multi-function 2 Interrupt Control
0: Disable
1: Enable
Bit 0MF1E: Multi-function 1 Interrupt Control
0: Disable
1: Enable
INTC2 Register — HT66F317
Bit
7
6
5
4
3
2
1
0
Name
—
—
INT1F
TB1F
—
—
INT1E
TB1E
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5INT1F: INT1 pin interrupt request flag
0: No request
1: Interrupt request
Bit 4TB1F: Time Base 1 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 3~2
Unimplemented, read as “0”
Bit 1INT1E: INT1 pin interrupt control
0: Disable
1: Enable
Bit 0TB1E: Time Base 1 Interrupt Control
0: Disable
1: Enable
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INTC2 Register — HT66F318
Bit
7
6
5
4
3
2
1
0
Name
UARTF
IICF
INT1F
TB1F
UARTE
IICE
INT1E
TB1E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7UARTF: UART interrupt request flag
0: No request
1: Interrupt request
Bit 6
IICF: I2C interrupt request flag
0: No request
1: Interrupt request
Bit 5INT1F: INT1 pin interrupt request flag
0: No request
1: Interrupt request
Bit 4TB1F: Time Base 1 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 3UARTE: UART interrupt control
0: Disable
1: Enable
Bit 2
IICE: I2C interrupt control
0: Disable
1: Enable
Bit 1INT1E: INT1 pin interrupt control
0: Disable
1: Enable
Bit 0TB1E: Time Base 1 Interrupt Control
0: Disable
1: Enable
MFI0 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
T0AF
T0PF
—
—
T0AE
T0PE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5T0AF: TM0 Comparator A match interrupt request flag
0: No request
1: Interrupt request
Bit 4T0PF: TM0 Comparator P match interrupt request flag
0: No request
1: Interrupt request
Bit 3~2
Unimplemented, read as “0”
Bit 1T0AE: TM0 Comparator A match interrupt control
0: Disable
1: Enable
Bit 0T0PE: TM0 Comparator P match interrupt control
0: Disable
1: Enable
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MFI1 Register — HT66F317
Bit
7
6
5
4
3
2
1
0
Name
—
—
T1AF
T1PF
—
—
T1AE
T1PE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5T1AF: TM1 Comparator A match interrupt request flag
0: No request
1: Interrupt request
Bit 4T1PF: TM1 Comparator P match interrupt request flag
0: No request
1: Interrupt request
Bit 3~2
Unimplemented, read as “0”
Bit 1T1AE: TM1 Comparator A match interrupt control
0: Disable
1: Enable
Bit 0T1PE: TM1 Comparator P match interrupt control
0: Disable
1: Enable
MFI1 Register — HT66F318
Bit
7
6
5
4
3
2
1
0
Name
T2AF
T2PF
T1AF
T1PF
T2AE
T2PE
T1AE
T1PE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7T2AF: TM2 Comparator A match interrupt request flag
0: No request
1: Interrupt request
Bit 6T2PF: TM2 Comparator P match interrupt request flag
0: No request
1: Interrupt request
Bit 5T1AF: TM1 Comparator A match interrupt request flag
0: No request
1: Interrupt request
Bit 4T1PF: TM1 Comparator P match interrupt request flag
0: No request
1: Interrupt request
Bit 3T2AE: TM2 Comparator A match interrupt control
0: Disable
1: Enable
Bit 2T2PE: TM2 Comparator P match interrupt control
0: Disable
1: Enable
Bit 1T1AE: TM1 Comparator A match interrupt control
0: Disable
1: Enable
Bit 0T1PE: TM1 Comparator P match interrupt control
0: Disable
1: Enable
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MFI2 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
DEF
LVF
—
—
DEE
LVE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5DEF: Data EEPROM interrupt request flag
0: No request
1: Interrupt request
Bit 4LVF: LVD interrupt request flag
0: No request
1: Interrupt request
Bit 3~2
Unimplemented, read as “0”
Bit 1DEE: Data EEPROM Interrupt Control
0: Disable
1: Enable
Bit 0LVE: LVD Interrupt Control
0: Disable
1: Enable
Interrupt Operation
When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A match
or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether the request
flag actually generates a program jump to the relevant interrupt vector is determined by the condition
of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant
vector, if the enable bit is zero then although the interrupt request flag is set an actual interrupt will
not be generated and the program will not jump to the relevant interrupt vector. The global interrupt
enable bit, if cleared to zero, will disable all interrupts.
When an interrupt is generated, the Program Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will
then fetch its next instruction from this interrupt vector. The instruction at this vector will usually
be a “JMP” which will jump to another section of program which is known as the interrupt service
routine. Here is located the code to control the appropriate interrupt. The interrupt service routine
must be terminated with a “RETI”, which retrieves the original Program Counter address from
the stack and allows the microcontroller to continue with normal execution at the point where the
interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
Accompanying diagrams with their order of priority. Some interrupt sources have their own
individual vector while others share the same multi-function interrupt vector. Once an interrupt
subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit,
EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring.
However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded.
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If an interrupt requires immediate servicing while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until
the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from
becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that
is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or
IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set
before the device is in SLEEP or IDLE Mode.
Legend
xxF
Req�est Flag� no a�to reset in ISR
xxF
Req�est Flag� a�to reset in ISR
xxE
Enable Bits
TM0P
T0PF
T0PE
TM0A
T0AF
T0AE
TM1P
T1PF
T1PE
TM1A
T1AF
T1AE
LVD
LVF
LVE
EEPROM
DEF
DEE
Interr�pts contained within M�ltiF�nction Interr�pts
EMI a�to disabled in ISR
Interr�pt Name
Req�est
Flags
Enable Bits
Master
Enable
Vector
INT0 Pin
INT0F
INT0E
EMI
04H
M. F�nct. 0
MF0F
MF0E
EMI
0CH
M. F�nct. 1
MF1F
MF1E
EMI
10H
M. F�nct. �
MF�F
MF�E
EMI
14H
A/D
ADF
ADE
EMI
18H
Time Base 0
TB0F
TB0E
EMI
1CH
Time Base 1
TB1F
TB1E
EMI
�0H
INT1 Pin
INT1F
INT1E
EMI
�4H
Priority
High
Low
HT66F317 Interrupt Structure
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Enhanced A/D Type 8-Bit MCU with LCD Driver
Legend
xxF
Req�est Flag� no a�to reset in ISR
xxF
Req�est Flag� a�to reset in ISR
xxE
Enable Bits
EMI a�to disabled in ISR
Interr�pt Name Req�est
Flags
Enable Bits
Master
Enable
Vector
INT0 Pin
INT0F
INT0E
EMI
04H
Comparator
CPF
CPE
EMI
08H
M. F�nct. 0
MF0F
MF0E
EMI
0CH
M. F�nct. 1
MF1F
MF1E
EMI
10H
T�AE
M. F�nct. �
MF�F
MF�E
EMI
14H
LVF
LVE
A/D
ADF
ADE
EMI
18H
DEF
DEE
Time Base 0
TB0F
TB0E
EMI
1CH
Time Base 1
TB1F
TB1E
EMI
�0H
INT1 Pin
INT1F
INT1E
EMI
�4H
I�C
IICF
IICE
EMI
�8H
UART
UARTF
UARTE
EMI
�CH
TM0P
T0PF
T0PE
TM0A
T0AF
T0AE
TM1P
T1PF
T1PE
TM1A
T1AF
T1AE
TM�P
T�PF
T�PE
TM�A
T�AF
LVD
EEPROM
Interr�pts contained within M�ltiF�nction Interr�pts
Priority
High
Low
HT66F318 Interrupt Structure
External Interrupt
The external interrupt is controlled by signal transitions on the INTn pins. An external interrupt
request will take place when the external interrupt request flag, INTnF, is set, which will occur
when a transition, whose type is chosen by the edge select bits, appears on the external interrupt
pin. To allow the program to branch to its respective interrupt vector address, the global interrupt
enable bit, EMI, and respective external interrupt enable bit, INTnE, must first be set. Additionally
the correct interrupt edge type must be selected using the related register to enable the external
interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared
with I/O pin, it can only be configured as external interrupt pin if the external interrupt enable bit in
the corresponding interrupt register has been set. The pin must also be setup as an input by setting
the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full
and the correct transition type appears on the external interrupt pin, a subroutine call to the external
interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag,
INTnF, will be automatically reset and the EMI bit will be automatically cleared to disable other
interrupts. Note that any pull-high resistor selections on the external interrupt pin will remain valid
even if the pin is used as an external interrupt input.
The INTEG register is used to select the type of active edge that will trigger the external interrupt.
A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt.
Note that the INTEG register can also be used to disable the external interrupt function.
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Comparator Interrupt
Only the HT66F318 has the comparator interrupt function. The comparator interrupt is controlled
by the internal comparator. A comparator interrupt request will take place when the comparator
interrupt request flag, CPF, is set, a situation that will occur when the comparator output bit changes
state. To allow the program to branch to its respective interrupt vector address, the global interrupt
enable bit, EMI, and comparator interrupt enable bit, CPE, must first be set. When the interrupt is
enabled, the stack is not full and the comparator inputs generate a comparator output transition, a
subroutine call to the comparator interrupt vector, will take place. When the interrupt is serviced, the
comparator interrupt request flag, will be automatically reset and the EMI bit will be automatically
cleared to disable other interrupts.
The CMPEG1~CMPEG0 bits in the CPC register are used to select the type of active edge that will
trigger the comparator interrupt. A choice of either rising or falling or both edge types can be chosen
to trigger an external interrupt.
Multi-function Interrupt
Within these devices there are up to three Multi-function interrupts. Unlike the other independent
interrupts, these interrupts have no independent source, but rather are formed from other existing
interrupt sources, namely the TM Interrupts, LVD interrupt and EEPROM interrupt.
A Multi-function interrupt request will take place the Multi-function interrupt request flag, MFnF
is set. The Multi-function interrupt flag will be set when any of its included functions generate an
interrupt request flag. To allow the program to branch to its respective interrupt vector address,
when the Multi-function interrupt is enabled and the stack is not full and either one of the interrupts
contained within each of Multi-function interrupt occurs, a subroutine call to the Multi-function
interrupt vector will take place. When the interrupt is serviced, the related Multi-Function request
flag will be automatically reset and the EMI bit will be automatically cleared to disable other
interrupts.
However, it must be noted that, although the Multi-function Interrupt flags will be automatically
reset when the interrupt is serviced, the request flags from the original source of the Multifunction interrupts, namely the TM Interrupts, LVD interrupt and EEPROM interrupt, will not be
automatically reset and must be manually reset by the application program.
A/D Converter Interrupt
The devices contain an A/D converter which has its own independent interrupt. The A/D Converter
Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt
request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs
when the A/D conversion process finishes. To allow the program to branch to its respective interrupt
vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be
set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a
subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced,
the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be
automatically cleared to disable other interrupts.
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Time Base Interrupt
The function of the Time Base Interrupts is to provide regular time signal in the form of an internal
interrupt. They are controlled by the overflow signals from their respective timer functions. When
these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the
program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI
and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack
is not full and the Time Base overflows, a subroutine call to their respective vector locations will
take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will
be automatically reset and the EMI bit will be cleared to disable other interrupts.
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their
clock sources originate from the internal clock source fTB. This fTB input clock passes through a
divider, the division ratio of which is selected by programming the appropriate bits in the TBC
register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB,
which in turn controls the Time Base interrupt period, can originate from several different sources,
as shown in the System Operating Mode section.
TBC Register
Bit
7
6
5
4
3
2
1
0
Name
TBON
TBCK
TB11
TB10
LXTLP
TB02
TB01
TB00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
1
1
0
1
1
1
Bit 7TBON: TB0 and TB1 Control
0: Disable
1: Enable
Bit 6TBCK: Select fTB Clock
0: fTBC
1: fSYS/4
Bit 5~4
TB11, TB10: Select Time Base 1 Time-out Period
00: 4096/fTB
01: 8192/fTB
10: 16384/fTB
11: 32768/fTB
Bit 3LXTLP: LXT Low Power Control
0: Disable (LXT quick start-up)
1: Enable (LXT slow start-up)
Bit 2~0TB02~TB00: Select Time Base 0 Time-out Period
000: 256/fTB
001: 512/fTB
010: 1024/fTB
011: 2048/fTB
100: 4096/fTB
101: 8192/fTB
110: 16384/fTB
111: 32768/fTB
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      Time Base Interrupt
I2C Interrupt
Only the HT66F318 has the I2C interrupt function. An I2C Interrupt request will take place when
the I2C Interrupt request flag, IICF, is set, which occurs when an address match occurs, or an I2C
communication time-out occurs, or a byte of data has been received or transmitted by the I2C
interface. To allow the program to branch to its respective interrupt vector address, the global
interrupt enable bit, EMI, and the I2C Interface Interrupt enable bit, IICE, must first be set. When
the interrupt is enabled, the stack is not full and any these conditions are created, a subroutine call
to the respective interrupt vector, will take place. When the I2C Interface Interrupt is serviced, the
I2C interrupt request flag, IICF, will be automatically cleared and the EMI bit will be automatically
cleared to disable other interrupts.
UART Interrupt
Only the HT66F318 has the UART interrupt function. Several individual UART conditions can
generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the
attention of the microcontroller. These conditions are a transmitter data register empty, transmitter
idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. To allow the
program to branch to the respective interrupt vector addresses, the global interrupt enable bit, EMI,
and UART interrupt enable bit, UARTE, must first be set. When the interrupt is enabled, the stack is
not full and any of these conditions are created, a subroutine call to the UART Interrupt vector will
take place. When the interrupt is serviced, the UART Interrupt flag, UARTF, will be automatically
cleared. The EMI bit will also be automatically cleared to disable other interrupts. However, the
USR register flags will be cleared automatically when certain actions are taken by the UART, the
details of which are given in the UART section.
EEPROM Interrupt
The EEPROM interrupt is contained within the Multi-function Interrupt. An EEPROM Interrupt
request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs
when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt
vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, and
associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the
stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM
Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be
automatically cleared to disable other interrupts, however only the Multi-function interrupt request
flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it has to be
cleared by the application program.
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LVD Interrupt
The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. A LVD
Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs
when the Low Voltage Detector function detects a low power supply voltage. To allow the program
to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage
Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When
the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to
the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the
EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function
interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically
cleared, it has to be cleared by the application program.
TM Interrupts
The Compact, Standard and Periodic Type TMs have two interrupts each. All of the TM interrupts
are contained within the Multi-function Interrupts. For each of the Compact, Standard and Periodic
Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and
TnAE. A TM interrupt request will take place when any of the TM request flags are set, a situation
which occurs when a TM comparator P or A match situation happens.
To allow the program to branch to its respective interrupt vector address, the global interrupt enable
bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE,
must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match
situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take
place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other
interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt
request flags will not be automatically cleared, they have to be cleared by the application program.
Note that the TM interrupt request flags and interrupt enable bits with the same serial number from
different devices may not represent the same TM type, for more related details refer to the TM
sections.
Interrupt Wake-up Function
Each of the interrupt functions has the capability of waking up the microcontroller when in the
SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to
high and is independent of whether the interrupt is enabled or not. Therefore, even though the device
is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge
transitions on the external interrupt pins, a low power supply voltage or comparator input change
may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care
must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up
function is to be disabled then the corresponding interrupt request flag should be set high before the
device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt
wake-up function.
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Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will remain in this condition in the
interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt
service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be
automatically cleared, the individual request flag for the function needs to be cleared by the
application program.
It is recommended that programs do not use the “CALL” instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will be
damaged once a CALL subroutine is executed in the interrupt subroutine.
Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is
required to prevent a certain interrupt from waking up the microcontroller then its respective request
flag should be first set high before enter SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the
contents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service
routine.
To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI
instruction in addition to executing a return to the main program also automatically sets the EMI
bit high to allow further interrupts. The RET instruction however only executes a return to the main
program leaving the EMI bit in its present zero state and therefore disabling the execution of further
interrupts.
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Low Voltage Detector – LVD
Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to
monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain
level. This function may be especially useful in battery applications where the supply voltage will
gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated.
The Low Voltage Detector also has the capability of generating an interrupt signal.
LVD Register
The Low Voltage Detector function is controlled using a single register with the name LVDC. Three
bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a
low voltage conditionwill be determined. A low voltage condition is indicatedwhen the LVDO bit is
set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value.
The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the
bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low
voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may
be desirable to switch off the circuit when not in use, an important consideration in power sensitive
battery powered applications.
LVDC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
LVDO
LVDEN
LVPU
VLVD2
VLVD1
VLVD0
R/W
—
—
R
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5LVDO: LVD Output Flag
0: No Low Voltage Detect
1: Low Voltage Detect
Bit 4LVDEN: Low Voltage Detector Control
0: Disable
1: Enable
Bit 3LVPU: All pin pull high resistor selection
Described elsewhere.
Bit 2~0VLVD2~VLVD0: Select LVD Voltage
000: 1.8V
001: 2.0V
010: 2.4V
011: 2.7V
100: 3.0V
101: 3.3V
110: 3.6V
111: 4.0V
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LVD Operation
The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a
pre-specified voltage level stored in the LVDC register. This has a range of between 1.8V and 4.0V.
When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will
be set high indicating a low power supply voltage condition. The Low Voltage Detector function
is supplied by a reference voltagewhich will be automatically enabled. When the device is in
the SLEEP mode, the low voltage detector will be disabled even if the LVDEN bit is high. After
enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise
before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the
voltage nears that of VLVD, there may be multiple bit LVDO transitions.
LVD Operation
The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling
the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been
set high by a low voltage condition. In this case, the LVF interrupt request flag will be set, causing
an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to
wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is
not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE
Mode.
When LVD function is enabled, it is recommenced to clear LVD flag first, and then enables interrupt
function to avoid mistake action.
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SCOM function for LCD
The devices have the capability of driving external LCD panels. The common pins for LCD driving,
SCOM0~SCOM3, are pin shared with certain pin on the I/O ports. The LCD signals are generated
using the application program.
LCD operation
An external LCD panel can be driven using these devices by configuring the I/O pins as common
pins. The LCD driver function is controlled using the SCOMC register which in addition to
controlling the overall on/off function also controls the bias voltage setup function. This enables the
LCD COM driver to generate the necessary VDD/2 voltage levels for LCD 1/2 bias operation.
The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver. The LCD
SCOMn pin is selected to be used for LCD driving by the corresponding pin function control bit.
Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD
driver operation.
LCD COM Bias
The SCOMEN bit in the SCOMC register is used in conjunction with the COMnEN bits to select
which I/O pins are used for LCD driving.
SCOMEN
COMnEN
Pin Function
O/P Level
0
x
I/O
0 or 1
1
0
I/O
0 or 1
1
1
SCOMn
VDD/2
Output Control
LCD Bias Current Control
The LCD COM driver enables a range of selections to be provided to suit the requirement of the
LCD panel which are being used. The bias resistor choice is implemented using the ISEL1 and
ISEL0 bits in the SCOMC register.
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SCOMC Register — HT66F317
Bit
7
6
5
Name
—
ISEL1
ISEL0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
4
3
2
1
0
SCOMEN COM3EN COM2EN COM1EN COM0EN
Unimplemented, read as “0”
Bit 6~5ISEL1~ISEL0: Select resistor for R type LCD bias current (VDD=5V)
00: 2×100kΩ (1/2 Bias), IBIAS = 25μA
01: 2×50kΩ (1/2 Bias), IBIAS = 50μA
10: 2×25kΩ (1/2 Bias), IBIAS = 100μA
11: 2×12.5kΩ (1/2 Bias), IBIAS = 200μA
Bit 4SCOMEN: LCD control bit
0: Disable
1: Enable
When SCOMEN is set, it will turn on the DC path of the selected resistor to generate
1/2 VDD bias voltage.
Bit 3COM3EN: PB5 or SCOM3 selection
0: PB5
1: SCOM3
Bit 2COM2EN: PB6 or SCOM2 selection
0: PB6
1: SCOM2
Bit 1COM1EN: PA3 or SCOM1 selection
0: PA3
1: SCOM1
Bit 0COM0EN: PA1 or SCOM0 selection
0: PA1
1: SCOM0
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SCOMC Register — HT66F318
Bit
7
6
5
Name
—
ISEL1
ISEL0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
4
3
2
1
0
SCOMEN COM3EN COM2EN COM1EN COM0EN
Unimplemented, read as “0”
Bit 6~5ISEL1~ISEL0: Select resistor for R type LCD bias current (VDD=5V)
00: 2×100kΩ (1/2 Bias), IBIAS = 25μA
01: 2×50 kΩ (1/2 Bias), IBIAS = 50μA
10: 2×25 kΩ (1/2 Bias), IBIAS = 100μA
11: 2×12.5 kΩ (1/2 Bias), IBIAS = 200μA
Bit 4SCOMEN: LCD control bit
0: Disable
1: Enable
When SCOMEN is set, it will turn on the DC path of resistor to generate 1/2 VDD bias
voltage.
Bit 3COM3EN: PB5/C- or SCOM3 selection
0: PB5/C1: SCOM3
When selecting the SCOM3 function, in addition to setting the COM3EN bit to “1”,
the CSEL bit must also be cleared to “0”.
Bit 2COM2EN: PB6/C+ or SCOM2 selection
0: PB6/C+
1: SCOM2
When selecting the SCOM2 function, in addition to setting the COM2EN bit to “1”,
the CSEL bit must also be cleared to “0”.
Bit 1COM1EN: PA3/CX or SCOM1 selection
0: PA3/CX
1: SCOM1
When selecting the SCOM1 function, in addition to setting the COM1EN bit to “1”,
the COS bit must also be set to “1”.
Bit 0COM0EN: PA1 or SCOM0 selection
0: PA1
1: SCOM0
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Configuration Option
Configuration options refer to certain options within the MCU that are programmed into the device
during the programming process. During the development process, these options are selected using
the HT-IDE software development tools. As these options are programmed into the device using
the hardware programming tools, once they are selected they cannot be changed later using the
application program. All options must be defined for proper system function, the details of which are
shown in the table.
No.
Options
Oscillator Options
1
High Speed System Oscillator Selection – fH:
1. HXT
2. HIRC
2
Low Speed System Oscillator Selection – fSUB:
1. LXT
2. LIRC
3
HIRC Frequency Selection:
1. 4MHz
2. 8MHz
3. 12MHz
4
HXT mode selection (for Low Voltage mode):
1. HXT ≤ 10MHz or ≤ 4MHz @ 1.8V (HXT mode selection = 0)
2. HXT > 10MHz or ≤ 8MHz @ 2.0V (HXT mode selection = 1)
Application Circuit
 Note: The PD0~PD3 pins, comparator pins, I2C pins and UART pins are only for the HT66F318 device.
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Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of several kinds of MOV instructions, data can be transferred from registers
to the Accumulator and vice-versa as well as being able to move specific immediate data directly
into the Accumulator. One of the most important data transfer applications is to receive data from
the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions such as INC,
INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the
values in the destination specified.
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Logical and Rotate Operation
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
which rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction
or to a subroutine using the CALL instruction. They differ in the sense that in the case of a
subroutine call, the program must return to the instruction immediately when the subroutine has
been carried out. This is done by placing a return instruction “RET” in the subroutine which will
cause the program to jump back to the address right after the CALL instruction. In the case of a JMP
instruction, the program simply jumps to the desired location. There is no requirement to jump back
to the original jumping off point as in the case of the CALL instruction. One special and extremely
useful set of branch instructions are the conditional branches. Here a decision is first made regarding
the condition of a certain data memory or individual bits. Depending upon the conditions, the
program will continue with the next instruction or skip over it and jump to the following instruction.
These instructions are the key to decision making and branching within the program perhaps
determined by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i”
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port with
the correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be setup as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the “HALT” instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
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Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and
can be consulted as a basic instruction reference using the following listed conventions.
Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
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Mnemonic
Description
Cycles
Flag Affected
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (specific page) to TBLH and Data Memory
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
2Note
None
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch Operation
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read Operation
TABRD [m]
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no
skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the
execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2”
instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C
ADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C
Add Data Memory to ACC
ADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C
ADD A,x
Description
Operation
Affected flag(s)
Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C
ADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C
AND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
AND A,x
Description
Operation
Affected flag(s)
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
ANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
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CALL addr
Description
Operation
Affected flag(s)
Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None
CLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
CLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
CLR WDT
Description
Operation
Affected flag(s)
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT1
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in
conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have
effect. Repetitively executing this instruction without alternately executing CLR WDT2 will
have no effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT2
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction
with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect.
Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
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CPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
DAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
DEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
DECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
HALT
Description
Operation
Affected flag(s)
Enter power down mode
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDF
INC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
INCA [m]
Description
Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
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JMP addr
Description
Operation
Affected flag(s)
Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None
MOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
MOV A,x
Description
Operation
Affected flag(s)
Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← x
None
MOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
NOP
Description
Operation
Affected flag(s)
No operation
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
OR A,x
Description
Operation
Affected flag(s)
Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
ORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
RET
Description
Operation
Affected flag(s)
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
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RET A,x
Description
Operation
Affected flag(s)
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
RETI
Description
Operation
Affected flag(s)
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Program Counter ← Stack
EMI ← 1
None
RL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
RLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
RLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
RLCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
RR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
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RRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
RRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
RRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
SBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C
SBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C
SDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
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SDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
SET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
SET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
SIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
SIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
SNZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is not 0
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
SUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C
Rev. 1.00
187
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
SUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C
SUB A,x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C
SWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
SWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
SZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
SZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
SZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
Rev. 1.00
188
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
TABRD [m]
Description
Operation
Affected flag(s)
Read table (specific page) to TBLH and Data Memory
The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDC [m]
Description
Operation
Affected flag(s)
Read table (current page) to TBLH and Data Memory
The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
XOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
XORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
XOR A,x
Description
Operation
Affected flag(s)
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z
Rev. 1.00
189
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the package information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.00
190
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
16-pin NSOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
—
A
—
0.236 BSC
B
—
0.154 BSC
—
C
0.012
—
0.020
C’
—
0.390 BSC
—
D
—
—
0.069
E
—
0.050 BSC
—
F
0.004
—
0.010
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
—
8°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
—
A
—
6.0 BSC
B
—
3.9 BSC
—
C
0.31
—
0.51
C’
—
9.9 BSC
—
D
—
—
1.75
E
—
1.27 BSC
—
F
0.10
—
0.25
G
0.40
—
1.27
H
0.10
—
0.25
α
0°
—
8°
191
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
20-pin SOP (300mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.406 BSC
—
B
—
0.295 BSC
—
C
0.012
—
0.020
C’
—
0.504 BSC
—
0.104
D
—
—
E
—
0.050 BSC
—
F
0.004
—
0.012
G
0.016
—
0.050
H
0.008
—
0.013
α
0°
—
8°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
A
—
10.30 BSC
Max.
—
B
—
7.5 BSC
—
0.51
C
0.31
—
C’
—
12.8 BSC
—
D
—
—
2.65
E
—
1.27 BSC
—
F
0.10
—
0.30
G
0.40
—
1.27
H
0.20
—
0.33
α
0°
—
8°
192
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
24-pin SOP (300mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
A
—
0.406 BSC
—
B
—
0.295 BSC
—
C
0.012
—
0.020
C’
—
0.606 BSC
—
D
—
—
0.104
E
—
0.050 BSC
—
F
0.004
—
0.012
Max.
G
0.016
—
0.050
H
0.008
—
0.013
α
0°
—
8°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
—
10.30 BSC
—
B
—
7.5 BSC
—
C
0.31
—
0.51
C’
—
15.4 BSC
—
D
—
—
2.65
E
—
1.27 BSC
—
F
0.10
—
0.30
G
0.40
—
1.27
H
0.20
—
0.33
α
0°
—
8°
193
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
28-pin SOP (300mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
—
A
—
0.406 BSC
B
—
0.295 BSC
—
C
0.012
—
0.020
C’
—
0.705 BSC
—
D
—
—
0.104
E
—
0.050 BSC
—
0.012
F
0.004
—
G
0.016
—
0.050
H
0.008
—
0.013
α
0°
—
8°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
—
10.30 BSC
—
B
—
7.50 BSC
—
0.51
C
0.31
—
C’
—
17.90 BSC
—
D
—
—
2.65
E
—
1.27 BSC
—
F
0.10
—
0.30
G
0.40
—
1.27
H
0.20
—
0.33
α
0°
—
8°
194
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
20-pin SSOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.236 BSC
—
B
—
0.154 BSC
—
C
0.008
—
0.012
C’
—
0.341 BSC
—
D
—
—
0.069
E
—
0.025 BSC
—
F
0.004
—
0.010
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
—
8°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
—
A
—
6.0 BSC
B
—
3.9 BSC
—
C
0.20
—
0.30
C’
—
8.66 BSC
—
D
—
—
1.75
E
—
0.635 BSC
—
F
0.10
—
0.25
G
0.41
—
1.27
H
0.10
—
0.25
α
0°
—
8°
195
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
24-pin SSOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.236 BSC
—
B
—
0.154 BSC
—
C
0.008
—
0.012
C’
—
0.341 BSC
—
D
—
—
0.069
E
—
0.025 BSC
—
F
0.004
—
0.010
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
—
8°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
—
6.0 BSC
—
B
—
3.9 BSC
—
C
0.20
—
0.30
C’
—
8.66 BSC
—
D
—
—
1.75
E
—
0.635 BSC
—
F
0.10
—
0.25
G
0.41
—
1.27
H
0.10
—
0.25
α
0°
—
8°
196
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
28-pin SSOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.236 BSC
—
B
—
0.154 BSC
—
C
0.008
—
0.012
C’
—
0.390 BSC
—
D
—
—
0.069
E
—
0.025 BSC
—
F
0.004
—
0.010
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
—
8°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
—
6.0 BSC
—
B
—
3.9 BSC
—
C
0.20
—
0.30
C’
—
9.9 BSC
—
D
—
—
1.75
E
—
0.635 BSC
—
F
0.10
—
0.25
G
0.41
—
1.27
H
0.10
—
0.25
α
0°
—
8°
197
June 12, 2015
HT66F317/HT66F318
Enhanced A/D Type 8-Bit MCU with LCD Driver
Copyright© 2015 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.00
198
June 12, 2015