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600 W Ha lf B ridg e L L C E v alu ati on B o ar d wi th
600 V C o ol MOS™ C7
Authors:
Steiner Alois
Di Domenico Francesco
Catly Johnald
Stückler Franz
Application Note
About this document
Scope and purpose
The present 600 W Evaluation Board is a great example of a full Infineon solution, including high voltage and
low voltage power devices, controllers and drivers in order to demonstrate the most flexible and effective
way to design the High Voltage DC/DC stage of a Server PSU fulfilling the 80Plus® Titanium Standard.
Furthermore the reader will get additional information how the 600 V CoolMOS™ C7 behaves in this LLC
board and what benefits will be achieved.
Intended audience
This document is intended for design engineers who want to improve their high voltage power conversion
applications.
Table of Contents
1
Introduction ................................................................................................................................... 3
2
2.1
2.2
2.3
2.4
2.5
2.6
2.6.1
2.6.2
2.7
2.8
2.9
HB LLC Converter Design Considerations ...................................................................................... 4
Principle of operation ......................................................................................................................... 4
Input design data ................................................................................................................................ 5
Selection of the inductance factor m ................................................................................................. 6
Gain curve ............................................................................................................................................ 6
Resonant components calculation..................................................................................................... 6
The ZVS behavior: energy and time considerations .......................................................................... 7
Energy related equations.............................................................................................................. 7
Time related equations ................................................................................................................. 7
The main transformer design ............................................................................................................. 8
The resonant choke design ............................................................................................................... 10
The Synchronous Rectification Stage .............................................................................................. 11
3
3.1
3.2
3.2.1
Board description ........................................................................................................................ 12
General overview............................................................................................................................... 12
Infineon BOM ..................................................................................................................................... 13
Primary HV MOSFETs CoolMOSTM IPP60R180C7......................................................................... 13
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Introduction
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.3
3.3.1
3.3.2
3.3.3
LLC analog controller ICE2HS01G .............................................................................................. 13
Half Bridge Gate Drive 2EDL05N06PF ......................................................................................... 13
Advanced dual-channel Gate Drive 2EDN7524F ........................................................................ 14
Bias QR Flyback controller ICE2QR2280Z................................................................................... 15
Synchronous Rectification MOSFETs OptiMOSTM BSC010N04LS............................................... 15
Board schematic................................................................................................................................ 16
Mainboard schematic ................................................................................................................. 16
Control board schematic ............................................................................................................ 17
Biasboard schematic .................................................................................................................. 18
4
4.1
4.2
4.3
4.4
4.4.1
4.4.2
Typical characteristics with 600 V CoolMOS™ C7.......................................................................... 20
Critical LLC operation - hard commutation ..................................................................................... 20
Full ZVS area ...................................................................................................................................... 21
Burstmode operation ........................................................................................................................ 21
Efficiency ........................................................................................................................................... 22
Titanium Efficiency ..................................................................................................................... 22
Efficiency comparison in resonant LLC Half Bridge ................................................................... 23
5
Test/powerup procedure ............................................................................................................. 24
6
Useful material and links.............................................................................................................. 26
7
References ................................................................................................................................... 27
8
List of abbreviations..................................................................................................................... 28
Application Note
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Introduction
1
Introduction
The opportunity to significantly reduce the size of power converters by increasing the switching frequency
created by the MOSFET technology has recently focused topology development and optimization on the
reduction of switching losses of the semiconductor devices, which are perceived as the major obstacle to
maximizing the switching frequency of PWM converters.
This has triggered studies on the resonant power conversion, which allows minimizing the switching losses
through the achievement of zero-voltage (ZVS) or zero-current (ZCS) switching behavior.
An important example of resonant power conversion is provided by the LLC topology, which is able to
address the requirements of high efficiency and power density through the achievement of a true Zero
Voltage Switching. Last but not least, its bill of material is significantly reduced compared to the other very
popular soft switching topology, the phase shift Full Bridge. These arguments bring the LLC resonant
converter more and more in usage in the server/telecom market.
This document will describe an analog controlled 600 W Half Bridge (HB) LLC converter designed using
Infineon products. Order information for ISAR: EVAL_600W_12V_LLC_C7
Application Note
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HB LLC Converter Design Considerations
2
HB LLC Converter Design Considerations
In the present chapter the most relevant design decisions are explained and documented with related
calculations.
2.1
Principle of operation
The principle schematic of a Half Bridge LLC converter is shown in the Figure 1. Cr, Lr and Lm represent the so
called “resonant tank”: together with the main transformer they are the key components in the LLC design.
The primary Half Bridge and the secondary synchronous rectification are the other two stages to be defined.
Figure 1
Principle schematic of a Half Bridge LLC converter
The LLC is a resonant converter that means it operates with frequency modulation, instead of the Pulse
Width Modulation (PWM), traditional approach to power conversion.
Starting point in a resonant converter design is the definition of an energy transfer function, which can be
seen as a voltage gain function, so a mathematical relationship between input and output voltages of the
converter. Trying to get this function in an “exact” way involves several nonlinear circuital behaviors
governed by complex equations. However, under the assumption that the LLC operates in the vicinity of the
series resonant frequency important simplifications can be introduced.
In fact, under this assumption, the current circulating in the resonant tank can be considered purely
sinusoidal, ignoring all higher order harmonics: this is the so called First Harmonic Approximation Method
(FHA), which is the most common approach to the design of a LLC converter.
In the FHA the voltage gain is calculated with reference to the following equivalent resonant circuit, shown
in Figure 2.
Figure 2
First Harmonic Approximation equivalent resonant circuit
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HB LLC Converter Design Considerations
The mathematical expression of the gain K is:
K (Q, m, Fx) 
Vo _ ac( s)
Fx ²(m  1)

Vin _ ac( s)
(m  Fx ²  1)²  Fx ²  ( Fx ²  1)²  (m  1)²  Q²
(1)
where:
m
Lr  Lm
;
Lr
fr 
1
Lr  Cr
;
Fx 
fs
;
fr
Rac 
Lr
8 Np ²

 Ro ;
 ² Ns ²
Q
Cr ;
Rac
(2)
So the resonant tank gain K can be plotted in function of the normalized switching frequency fx for different
values of the Quality factor Q and any single value of the inductance factor m.
In this chapter it will be shown a design procedure for the selection of the main LLC parameters, with the
goal to achieve the best performance while fulfilling input and output regulation requirements.
At same time, Zero Voltage Switching operation of the primary Half Bridge MOSFETs must be ensured, in
order to get full benefits out of the soft switching behavior, especially at light load.
2.2
Input design data
In Table 1 an overview of the major design parameter is displayed.
Table 1
Design parameters
Description
Input Voltage
Output Voltage
Output Power
Minimum
350 VDC
11.9 VDC
Efficiency at 50% Pmax
97.5%
Switching Frequency
Dynamic Output Voltage regulation
(0-90% Load step)
Vout_ripple
90 kHz
Nominal
380 VDC
12 VDC
Maximum
410 VDC
12.1 VDC
600 W
150 kHz
250 kHz
Max. overshoot = 0.1 V
Max. undershoot= 0.3 V
150 mVpk-pk
From the table above, the first important design parameters can be derived:
Main transformer turn ratio
Minimum needed Gain
Maximum needed Gain
Application Note
n
Np
Vin _ nom

 16
Ns 2  Vout _ nom
(3)
K min(Q, m, Fx) 
n  Vo _ min
 0.95
Vin _ max
2
(4)
K max (Q, m, Fx) 
n  Vo _ max
 1.08
Vin _ min
2
(5)
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HB LLC Converter Design Considerations
2.3
Selection of the inductance factor m
The inductance factor (Equation 2) has an important impact on the converter operation. Lower values of m
achieve higher boost gain and narrower range of the frequency modulation, that means more flexible
control and regulation, which is valuable in applications with very wide input voltage range.
On the other hand, this means also smaller values of Lm which leads into significantly high magnetizing
current circulating in the primary side: this current doesn’t contribute to the power transferred, but mainly
generates conduction losses on the primary side.
In other words, there is a trade-off between flexible regulation and overall efficiency requirements,
especially at light load.
In the case of our demo board, main goal is to achieve high efficiency, so relatively high m is selected, also
because the input range is relatively narrow and in any case we rely in the bulk capacitor in case of specific
hold up time requirement at the complete AC/DC SMPS level - so in our case m≈12.
2.4
Gain curve
The resulting gain curves, Figure 3, for loads between 10% and 100% Pmax are in the following plot:
Figure 3
Gain curve
Both the Mmin and Mmax limits cross all the gain curves of our LLC converter: that means the regulation is fully
achieved in the specified ranges.
2.5
Resonant components calculation
Combining equations (1) and (2), we get a system where the unknown are Lr, Cr and Lm.
Solving it, the following values are set for the LLC converter:
n
Application Note
Np
Vin _ nom

 16  Np  16; Ns  1
Ns 2  Vout _ nom
6
(6)
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HB LLC Converter Design Considerations
m
Lr  Lm
 12  Lm  195H ; Lr  17 H
Lr
(7)
Cr  66nF
fr 
2.6
1
(8)
 150 KHz
2  Lr  Cr
(9)
The ZVS behavior: energy and time considerations
The ZVS calculations involve two kind of analysis, the one in the energy domain and the other in the time
domain. The goal is to have enough energy in the resonant tank able to discharge the output capacitance of
the primary MOSFET, but also an appropriate dead time between the turn-off of each device and the
corresponding turn-on of the one at the other side of the Half Bridge.
Co(er) is the Coss energy related component of the used High Voltage MOSFET, in our case IPP60R180C7.
Qoss is the charge stored in Coss at Vin(nom)=380 VDC
2.6.1
Energy related equations
Im ag _ min 
Enres _ min 
2 2
n  Vo
 0.672 A
2  fsw _ max  Lm
(10)
1
 ( Lm  Lr )  I ² mag _ min  95.1J
2
(11)
1
 (2Co(er )) V ² DS _ max  9J
2
(12)
 Encap _ max
(13)

Encap _ max 

 Enres _ min
2.6.2
Time related equations
It can be demonstrated that:
tdead 
tecs 2  Qoss@ Vin_nom tecs 2  Co(tr )@ Vin_nom* Vin_nom



2
2
Im,pk
Im,pk
(14)
where tdead is the dead time set between the conduction time of the two HB devices and tecs is the time when
the channel of each MOSFET is still in conduction after turning it off (linear mode operation), which is
function of device parameters like Vgs(th), Rg(tot) and Cgs/Cgd.
Using that equation, together with the min and max values of the magnetizing current:
Im ag _ min 
Application Note
2 2


n  Vo
2  fsw _ max Lm
7
 0.672 A
(10)
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HB LLC Converter Design Considerations
Im ag _ max 
tdead , min 
2 2

tecs


n  Vo
2  fsw _ min Lm
2  Qoss, @ 400V
2
tdead , max 
tecs
(11)
 130 ns
(14)
Im,ag , max

2  Qoss, @ 400V
2
2.7
 1.66 A
 311 ns
(15)
Im ag , min
The main transformer design
As explained more in details in the chapter 2.6 of the present document, the target efficiency of this design is
fixed by the 80PLUS® Titanium Standard; that means fixing certain minimum requirements for the High
Voltage DC/DC stage at 10%, 20%, 50%, 100% load conditions.
The most critical condition for the main transformer is the full load, mainly due to thermal reasons. The
selection of the core size and material is done according to this condition along with the power density (thus
switching frequency) target and the available airflow.
Keeping a margin in the design, the minimum efficiency requirement at full load is fixed for the Half Bridge
LLC converter to 97%, which means our goal is to keep the total dissipated power in that condition below
18 W.
In order to guarantee a balanced spread of power and heating, a good rule in the design of the LLC
Converter is to keep the total power dissipated on the main transformer below 1/6 of the total dissipated
power, which means the max allowed power on it shall be below 3 W. This is our first important design
input.
The max operating temperature is 55°C, as in typical server applications. Due to transformer safety
insulation approvals, the max operating temperature of the transformer must be lower than 110°C, thereof:
Ttrafo _ MAX  (110  55)C  55C
(16)
From (16) and (17) the max thermal resistance of the core shape can be easily derived:
Rth _ trafo _ MAX 
Ttrafo _ MAX 55 C

 18.3C
W
W
Ptrafo _ MAX
3
(17)
So our selected core shape must have thermal resistance lower than 18.3°C/W.
This requirement can be fulfilled with different choices: the preferred will allow maximizing the ratio
between available winding area and effective volume, of course compatibly with the eq. (18).
Also considering the power density target (in the range of 20 W/inch³), the most suitable selection is
PQ 35/35, shown in Figure 4.
The related coil form shows a minimum winding area of 1.58 cm² and a thermal resistance of 16.5°C/W, thus
able to dissipate up to 3.33 W by keeping the ΔTMAX <55°C.
Once verified that the thermal equations are fulfilled, we can proceed with the design of the primary and
secondary windings and the core material selection, with some important goals:

Fitting the geometry/overall dimensions of the core

Fulfilling the condition (16)

Try to split as much equally as possible the losses between core and windings: ideally “fifty-fifty”
should be achieved at full load, but any percentage close to it would be acceptable.
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HB LLC Converter Design Considerations
Figure 4
TDK-Epcos PQ35/35 core
The selected core material is the ferrite TDK PC95, showing a very interesting plot of Core Losses (PCV) vs.
Flux Density vs. frequency (see Figure 5 below):
The final structure of the main transformer is reported in Figure 6 below. This has been developed in
cooperation with the partner company Kaschke Components GmbH, Göttingen – Germany.
So the primary is realized in a “sandwich” technique using 16 turns of 4 layers of litz wire 45 strands 0.1 mm
diam. This allows minimizing the AC losses due to skin and proximity effect. The secondary is done with
copper band 20x0.5 mm.
Figure 5
Ferrite core material TDK PC95
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HB LLC Converter Design Considerations
With this choice, at full load condition the total copper losses will be (primary + secondary, DC+AC
components) are 1.1 W, the core losses are 1.8 W, so overall:
Ptrafo  Pcopper  Pcore  2.9W  Ptrafo _ MAX
(18)
In other words, the equation (18) fulfils the thermal equation (17).
Figure 6
Winding structure of the PQ 35/35 LLC transformer (Kaschke Components GmbH)
An important transformer parameter involved in the LLC design is the primary or magnetizing inductance
Lm, which, according to eq. (7) must be 195 µH. This value is obtained with distributed air-gap on the side
legs of the PQ core: this construction is preferred since it minimizes the effect of the so called “fringing flux”
which generates additional losses in the windings close to the inner limb.
2.8
The resonant choke design
In LLC designs with stringent power density requirements, the resonant choke is typically embedded in the
transformer, in the sense that the leakage inductance is utilized according this purpose. This technique has
the big advantage to save space and the cost of an additional magnetic component, but also some
drawbacks, like the not easy controllability of the Lr value in mass production.
In the case of the present design, it has been decided to use an external Lr.This is due to the fact that the
demo board is intended to be primarily used for test and benchmarking and therefore high power density is
not in the main focus: having the resonant inductance externally allows to change the resonant tank in a
more flexible way.
According to equation (7), the overall value of Lr shall be 17 µH, including the contribution of the transformer
leakage inductance + the external resonant choke.
The external resonant choke is realized using a RM-12 core and a winding construction illustrated in Figure 7
below and implemented by the partner company Kaschke Components GmbH, Göttingen - Germany.
Figure 7
Winding structure of the RM 12 resonant choke (Kaschke Components GmbH)
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HB LLC Converter Design Considerations
2.9
The Synchronous Rectification Stage
In applications that target high efficiency both at low and high loads –such as 80PLUS® Titanium- while
often requiring high power densities, it is critical to select for the Synchronous Rectification Stage MOSFETs
that combine multiple key characteristics.
First of all, these Sync Rec MOSFETs should exhibit very low RDS(on). Indeed, due to the low voltages observed
on the secondary side of server power supplies, large currents flow through the Sync Rec MOSFETs.
Moreover, compared with hard switching topologies such as ZVS PS FB (Zero Voltage Switching PhaseShifted Full Bridge), using LLC topology leads not only to increased peak currents for the Sync Rec MOSFETs,
but also higher root-mean-square currents IRMS.
Since the conduction losses Pcond,SR of each Sync Rec MOSFET are defined by:
Pcond _ SR  RDS , on  ( IRMS ) 2
(19)
These losses can only be mitigated through the use of a part with very low RDS(on).
Secondly, it is critical for these Sync Rec MOSFETs to exhibit low gate charges Qg:
At lower loads, the switching losses of the Sync Rec MOSFETs predominate over the already mentioned
conduction losses. In the case of LLC topology, the main contributor of these switching losses is related to
Qg.
Most of the time, a driving voltage of 12 V is applied to Sync Rec MOSFETs. Although 12 V is not necessary the
optimized driving voltage for Sync Rec MOSFETs (more on this below), this driving voltage is very popular in
server PSUs because it is readily available: there is no need to derive it from another voltage rail. Therefore,
we decided to follow this trend for this demo board by driving the Sync Rec MOSFETs with 12 V.
This requirement for low Qg puts extra-strain on MOSFET manufacturers, especially considering that Sync
Rec MOSFETs need to exhibit at the same time a very low RDS(on). Such a feat was however possible for
Infineon thanks to the new Infineon OptiMOSTM 40 V generation, whose gate charges have been significantly
reduced in comparison with the previous generation.
Thirdly, the paralleled Sync Rec MOSFETs should turn on almost simultaneously.
This can be achieved thanks to a tightening of the threshold voltage VGS(th) range. In the case new OptiMOSTM
40 V generation, its datasheet guarantees a very narrow VGS(th) range, with min and max values equal to 1.2 V
and 2.0 V respectively.
Finally, the MOSFET package is critical for a variety of reasons.
The package should exhibit low parasitic inductances in order to confine its contribution to the VDS
overshoot to a strict minimum. This is even more critical in server applications using LLC topology, due to
the limited headroom for the VDS overshoot between the transformer secondary voltage (25 V) and the 90%
derating (36 Vmax) or even 80% derating (32 Vmax) applied to the VDS of the Sync Rec MOSFETs;
Moreover, due to the conflicting requirements for high power density and high current capability, the
package should combine a minimum footprint with good power dissipation.
Because of the high current densities arising at the source pins, which can lead to electro-migration and
thereafter destruction of the Sync Rec MOSFETs, the package should provide an enlarged source
connection. While the first two sub-items are tackled by standard SuperSO8 packages, it is the addition of
source fused leads implemented in the new Infineon OptiMOSTM 40 V generation that reduces the high
current densities above mentioned.
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Board description
3
Board description
3.1
General overview
Figure 1 is the top view, bottom view and the assembly of 600W Half Bridge LLC evaluation board. Key
components are: (1) heat sink with the assembly of primary side switches IPP60R180C7 (2) Resonant
capacitor (3) LLC analog controller ICE2HS01G (4) Resonant inductor (5) Main DC-DC transformer (6) PCB
assembly of the auxiliary circuit with bias QR Flyback controller ICE2QR2280Z (7) Heat sink assembly for
cooling the synchronous rectifier (8) Output capacitor (9) Output inductor (10) Half Bridge MOSFET gate
driver 2EDL05N06PF and (11) Synchronous rectifier OptiMOS™ BSC010N04LS (12) Advanced dual-channel
Gate Drive 2EDN7524F.
12
11
10
600 W LLC Top View
1
Figure 8
2
600 W LLC Bottom
View
3
4
5
6
7
8
9
IFX 600W LLC Evaluation Board
Application Note
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600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Board description
3.2
Infineon BOM
This HB LLC 600 W demonstration board is a full Infineon solution, meeting the highest efficiency standard
80PLUS® Titanium using the following parts:
3.2.1
Primary HV MOSFETs CoolMOSTM IPP60R180C7
The 600 V CoolMOS™ C7 is the next step of Silicon improvement based on the 650 V CoolMOS™ C7. It stays
with the strategy to increased switching performance in order to enable highest efficiency in any kind of
target applications as for boost topologies like PFC’s (power factor correction) and high voltage DC/DC
stages like LLC’s (DC/DC stage with resonant tank in order to maintain zero voltage switching). Although the
600 V CoolMOS™ offers very fast switching, it also kept the ease of use level (how easy to control the switch)
of the 650 V C7 “parent technology”. Therefore the 600 V CoolMOS™ C7 is optimized device for highest
efficiency SMPS (switched mode power supply). The 600 V C7 represents the new standard of SJ MOSFET.
In LLC application, converter is in resonant operation with guaranteed ZVS even at a very light load
condition. Switching loss caused by Eoss during turn-on can be considered negligible in this topology. With
this consideration, CoolMOS™ C7 family of parts offers superior price/performance ratio with low FOMs
(Ron*Qg and Ron*QOSS), which means that MOSFET switching transitions can happen in a shorter dead time
period. This will result to a lower turn-off losses pushing further the efficiency. The following are the
additional features and benefits of CoolMOS™ C7 making it suitable and advantageous for resonant
switching topologies like LLC:
• Suitable for hard and soft switching (PFC and high performance LLC)
• Increased MOSFET dv/dt ruggedness to 120 V/ns
• Increased efficiency due to Best-in-Class FOM RDS(on)*Eoss and RDS(on) *Qg
• Best-in-class RDS(on)/package
• Qualified for industrial grade applications according to JEDEC (J-STD20 and JESD22)
3.2.2
LLC analog controller ICE2HS01G
ICE2HS01G is Infineon’s 2nd generation HalfBridge LLC controller designed especially for high efficiency Half
Bridge or FullBridge LLC resonant converter with synchronous rectification (SR) control for the secondary
side. With its new driving techniques, the synchronous rectification can be realized for LLC converter
operated with secondary switching current in both CCM and DCM conditions. No special synchronous
rectification controller IC is needed at the secondary side. The maximum switching frequency is supported
up to 1 MHz. Apart from the patented SR driving techniques, this IC provides very flexible design and
integrates full protection functions as well. It is adjustable for maximum/minimum switching frequency,
soft-start time, frequency, dead time between primary switches, turn-on and turn-off delay for secondary SR
MOSFETs. The integrated protections include input voltage brownout, primary three-levels over current,
secondary over load protection and no-load regulation. It also includes a burst mode function which offers
an operation with low quiescent current maintaining high efficiency at low output load while keeping
output ripple voltage low.
3.2.3 Half Bridge Gate Drive 2EDL05N06PF
2EDL05N06PF is one of the drivers from Infineon’s 2EDL EiceDRIVER™ Compact 600V Half Bridge gate driver
IC family with monolithic integrated low-ohmic and ultrafast bootstrap diode. Its level-shift SOI technology
supports higher efficiency and smaller form factors of applications. Based on the used SOI-technology there
is an excellent ruggedness on transient voltages. No parasitic thyristor structures are present in the device.
Hence, no parasitic latch up may occur at all temperature and voltage conditions. The two independent
Application Note
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600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Board description
drivers outputs are controlled at the low-side using two different CMOS resp. LSTTL compatible signals,
down up to 3.3 V logic. The device includes an under-voltage detection unit with hysteresis characteristic
which are optimised either for IGBT or MOSFET. 2EDL05N06PF (DSO-8) and 2EDL05N06PJ (DSO-14) are
driver ICs with undervoltage-lockout for MOSFETs. These two parts are recommended for server/telecom,
low-voltage drives, e-bike, battery charger and Half Bridge based switch mode power supply topologies.
− Individual control circuits for both outputs
− Filtered detection of under voltage supply
− All inputs clamped by diodes
− Off line gate clamping function
− Asymmetric undervoltage lockout thresholds for high side and low side
− Insensitivity of the bridge output to negative transient voltages up to -50 V given by SOI-technology
− Ultra fast bootstrap diode
3.2.4
Advanced dual-channel Gate Drive 2EDN7524F
The Fast Dual Channel 5 A Low-Side Gate Driver is an advanced dual-channel driver optimized for driving
both Standard and Superjunction MOSFETs, as well as GaN Power devices, in all applications in which they
are commonly used. The input signals are TTL compatible (CMOS 3.3 V) with an input voltage range from 3 V
to +20 V. The ability to operate with -10 VDC at the input pins protects the device against ground bounce
conditions. Each of the two outputs is able to sink and source a 5 A current utilizing a true rail-to-rail stage,
that ensures very low impedances of 0.7 Ω up to the positive and 0.55 Ω down to the negative rail
respectively. Very low channel to channel delay matching, typ. 1 ns, enables the double source and sink
capability of 10 A, by paralleling both channels. Different logic input/output configurations guarantee high
flexibility in all applications; e.g. with two paralleled switches in a boost configuration (see Figure below).
The gate driver is available in the three package options: A standard PG-DSO-8, a thin PG-WSON-8-1 and
PG-TSSOP-8-1 (minimized DSO 8 package).
Main Features
− Industry-Standard Pinout
− Two Independent Low-Side Gate Drivers
− 5 A Peak Sink/Source Output Driver at VDD = 12 V
− -10 VDC Negative Input Capability against GND-Bouncing
− Enhanced operating robustness due to High Reverse Current Capability
− True Low-Impedance Rail-To-Rail Output (0.7 Ω and 0.55 Ω)
− Very Low Propagation Delay (19 ns)
− Typ. 1 ns Channel to Channel Delay Matching
− Wide Input and Output Voltage Range up to 20 V
− Active Low Output Driver even on Low Power or Disabled Driver
− High Flexibility through Different Logic Input Configurations (LVTTL and CMOS 3.3 V)
− PG-DSO-8, PG-WSON-8-1 and PG-TSSOP-8-1 Package
− Extended Operation from -40 °C to 150 °C (Junction Temperature)
− Particularly Well-Suited for Driving Standard, Superjunction MOSFETs, IGBTs or GaN Power Devices
Application Note
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Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Board description
Typical Applications
− SMPS
− DC/DC Converters
− Motor Control
− Solar Power, Industrial Applications
3.2.5
Bias QR Flyback controller ICE2QR2280Z
ICE2QRxxxx is a second generation quasi-resonant PWM CoolSET™ with power MOSFET and startup cell in a
single package optimized for off-line power supply applications such as LCD TV, notebook adapter and
auxiliary/housekeeping converter in SMPS. The digital frequency reduction with decreasing load enables a
quasi-resonant operation till very low load. As a result, the system average efficiency is significantly
improved compared to conventional solutions. The active burst mode operation enables ultra-low power
consumption at standby mode operation and low output voltage ripple. The numerous protection functions
give a full protection of the power supply system in failure situation. Main features of ICE2QR2280Z which
make it suitable as an auxiliary converter of this LLC demonstration board are:

High voltage (650 V/800 V) avalanche rugged CoolMOS™ with startup cell

Quasi-resonant operation

Load dependent digital frequency reduction

Active burst mode for light load operation

Built-in high voltage startup cell

Built-in digital soft-start

Cycle-by-cycle peak current limitation with built-in leading edge blanking time

Foldback Point Correction with digitalized sensing and control circuits

VCC undervoltage and overvoltage protection with Autorestart mode

Over Load /open loop Protection with Autorestart mode

Built-in Over temperature protection with Autorestart mode

Adjustable output overvoltage protection with Latch mode

Short-winding protection with Latch mode

Maximum on time limitation

Maximum switching period limitation
3.2.6
Synchronous Rectification MOSFETs OptiMOSTM BSC010N04LS
For the synchronous rectification stage the selected device is BSC010N04LS, from the latest OptiMOS™ 40 V
family. SR is in fact naturally the best choice in high efficiency designs of low output voltage and high output
current LLC, as in our case. In applications that target high efficiency both at light and heavy loads – such as
80PLUS® Titanium- while often requiring high power densities, it is critical to select SR MOSFETs that
combine following key characteristics:

Very low RDS(on): BSC010N04LS provides the industry’s first 1mΩ 40 V product in SuperSO8 package.

Low gate charge Qg, which is important in order to minimize driving losses, with benefits on light load
efficiency

Very tight VGS(th) range: in fact, in case of paralleling this allows the MOSFETs to turn-on almost
simultaneously. Selected OptiMOSTM offer very close min and max of VGS(th), respectively 1.2 and 2 V.
Application Note
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Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Board description

Monolithically integrated Schottky like diode, in order to minimize the conduction losses on it.

Package; BSC010N04LS in SuperSO8 with source fused leads is able to address all the typical crucial
requirements for a suitable SR MOSFET package:
− Minimizing parasitic inductances
− Combining compact footprint with good power dissipation
− Enlarged source connection in order to minimize electro-migration occurrence.
3.3
Board schematic
3.3.1
Mainboard schematic
Figure 9
Mainboard schematic
Application Note
16
Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Board description
3.3.2
Control board schematic
Figure 10
Control board schematic
Application Note
17
Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Board description
3.3.3
Biasboard schematic
Figure 11
Biasboard schematic
Application Note
18
Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Board description
Figure 12
Mainboard PCB with Control – and Bias Board
Application Note
19
Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Typical characteristics with 600 V CoolMOS™ C7
4
Typical characteristics with 600 V CoolMOS™ C7
4.1
Critical LLC operation - hard commutation
In LLC converter, hard commutation of the body diode normally only occurs during the start-up, burst
mode, overload and short circuit condition. These conditions can be minimized if not avoided in the design
using an analog controller with proper selection of resonant components and properly setting of the
minimum and maximum operating frequency. Hard commutation happens in LLC during the commutation
period of the body diode. During this time, resonant inductor current is flowing through body diode of the
MOSFET creating ZVS condition upon this MOSFET’s turn-on. When the current is not able to change its
direction prior to the turn-on of the other MOSFET, more charges will remain in the P-N junction of that
MOSFET. When the other MOSFET turns on, a large shoot-through current will flow due to the reverserecovery current of the body diode. This results to a high reverse recovery peak current IRRM and high reverse
recovery dv/dt which sometimes could result to a MOSFET breakdown.
In this 600 W LLC analog controlled demonstration board, only the burst mode condition has the tendency
of undergoing hard commutation. In Figure 13, hard commutation at burst mode is minimal that
IPP60R180C7 was able to withstand without any problem.
528V
Ch1: VDS_LS
Ch2: VGS_LS
Ch4: IDS_LS
26V
11A
Figure 13
Hard commutation during burst mode operation, VDS_pk , VGS_max/min and IRMM
Application Note
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Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Typical characteristics with 600 V CoolMOS™ C7
The voltage spike on the gate VGS and drain VDS can be influenced by varying both turn-on and turn-off gate
resistors up to 10 ohm without affecting the efficiency, thanks to the switching behavior of the C7
technology.
Thanks to the very carefully design and control loop on this 600 W Analog LLC Demonstration board, there is
neither during start-up nor for short-circuit condition any hard commutation observed.
4.2
Full ZVS area
Nearly full ZVS is achieved on the entire output load range as shown in Figure 14.
Ch1: VDS_LS
Ch2: VGS_LS
Ch4: IDS_LS
Nearly full ZVS
achieved
starting at 5A load
Figure 14
Nearly Full Zero Voltage Switching (ZVS) starting at 5 A load
4.3
Burstmode operation
At no load or a very light load condition, LLC controller provides frequency approaching to its maximum
setting. In this condition, in order to still achieve full ZVS, magnetizing current should be high enough to
discharge the output capacitances. Due to magnetizing current limitation, switching loss especially turn-off
loss is relatively high if the devices will continue to switch at the highest frequency. In order to overcome
this phenomenon, burst mode function is enabled and implemented. This results to an effective lower
switching losses and driving losses because of the low burst frequency. Additionally, this helps to achieve
regulation even at no load condition. In Figure 15 one can see the waveform of Burst Mode Operation at noload and/or very light load condition
Application Note
21
Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Typical characteristics with 600 V CoolMOS™ C7
Ch1: VDS_LS
Ch3: VOUT
Ch4: IDS_LS
Burst Mode Operation at a Very Light Load
Condition
Ch2: VGS_LS
Figure 15
Burst Mode Operation at no-load and/or very light load condition
4.4
Efficiency
4.4.1
Titanium Efficiency
Figure 16 shows the efficiency comparison of this 600 W LLC evaluation board in relation to the Titanium
Efficiency Standard. At the most important efficiency point (50% load), this LLC board offers 0.3 % efficiency
benefit compared to the Titanium Efficiency Line.
Application Note
22
Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Typical characteristics with 600 V CoolMOS™ C7
Measurement without Auxiliary Bias
Figure 16
IFX 600 W LLC Demonstration Board Efficiency vs Titanium STD Efficiency
4.4.2
Efficiency comparison in resonant LLC Half Bridge
Figure 17 shows the efficiency comparison in a 600 W LLC circuit, Vin=380 V, Vo=12 V, running at resonant
frequency fo=157 kHz. The 0.1 % improvement across the load range is mostly related to the low turn off
losses and the low COSS dissipation, since other switching losses are minimal when operating at the resonant
frequency. Furthermore, it’s expected to gain more efficiency benefit when operating above the resonant
frequency, where turn off losses start to engage.
Figure 17
Efficiency comparison in 600W LLC Half Bridge
Application Note
23
Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Test/powerup procedure
5
Test/powerup procedure
Table 2
Test/Powerup procedure
Test
Test procedure
Condition
1. Auxiliary Circuit Turn-On
Apply 30 VDC on the input.
Vin: ~30 VDC
Orange LED will light up
Apply 350 VDC. Converter will give
Vout =12 VDC.
Vin: 350 VDC
3. Operational switching frequency Using voltage probe, monitor
switching frequency at following
test conditions:
Vin:380 VDC
2. LLC Converter Turn-On
Vout:12 V
Vout:12 V
@5 A Output Load 10%Load - ~
155 kHz*
Iout: 5 A
@25 A Output Load 50%Load - ~
142 kHz*
Iout: 25 A
@50 A Output Load 100%Load - ~
132 kHz*
Iout: 50 A
(*measure freq. at “Pri_LS_VGS“connector)
[* +/-10 kHz]
4. Fan enable
Switch the load from 50 A to 5 A.
Increase the output load current
from 11-14 A, fan should turn on.
Vin =380 VDC
Iout= 5 A
ÞFan is off
Vin =380 VDC
Iout= 11-14 A
ÞFan is on
5. Switch off Input Start-up at No
load
6. Switch off Input; Start-up at Full
load
Switch off the Input
Vin= 0 VDC
Iout= 0 A
Switch at 380 VDC on no load
output. Operation should be in
burst mode.
Vin =380 VDC
Switch off the Input
Vin= 0 VDC
Iout = 0 A
Vout = 11,5 – 12,5
Iout= 0A
Apply 380 VDC with full load @50 A Vin =380 VDC
output. Vout is in between 11.8 –
Vout: 11,8 – 12,3 VDC
12.2 VDC*
Iout = 50 A
(*measure on the board-connector)
7. Running No Load -> Output
Short Circuit
Application Note
Switch off load from 380 VDC 50 A
to 380 VDC 0 A.
Vin =380 VDC
Short circuit the load using the
short circuit function of the eload. Converter should latch.
(after short circuit) Vout = 0 VDC
24
Iout = 0 A
Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Test/powerup procedure
Test
Test procedure
Condition
8. Switch off Input & remove short
circuit
Switch off the Input.
Vin= 0 VDC
9. Running Full Load -> Over
Current Protection
Remove short circuit function on
the load.
Iout= 0 A
Apply 380 VDC 50 A with full load
output. Increase the current on
the output 1 A each step until the
converter goes into protection
starting from 50 A. OCP occurs
between 55 A and 62 A.
Vin =380 VDC
Iout = 50 A
OCP = between 55 A – 62 A
10. Running Full Load -> Output
Short Circuit
Apply 380 VDC 50 A with full load
Iout= 0 A
output. Short circuit the load
Vin =380 VDC
using the short circuit functions of
Iout = 50 A
the load. Converter should latch.
(after short circuit) Vout=0 VDC
11. Switch off Input; Start- Up ->
Output Short Circuit
Switch off the Input.
Iout= 0 A
Apply 380 VDC with output load
short circuit. Converter should be
in hiccup/latch mode.
12. Switch off Input & remove short Switch off the Input.
circuit
Remove short circuit function on
the load.
13. Dynamic Loading
Vin= 0 VDC
Vin =380 VDC
Iout = short circuit
Vout = 0 V short circuit
(hiccup/latch)
Vin= 0 VDC
Iout= 0 A
Apply 380 VDC. Set the electronic
load to dynamic loading mode
with the following settings:
Vin =380 VDC
CCDH1: Iout 5 A
Iout = 5 A…50 A
Vout = 11,5 – 12,5 VDC
CCDH2: Iout 50 A
Dwell time: 10 ms
Load slew rate: 1 A/µS
Application Note
25
Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
Useful material and links
6
Useful material and links
With the following links you can find more detailed information about the used devices from Infineon and
the magnetic components.

Primary HV MOSFETs CoolMOSTM IPP60R180C7:
http://www.infineon.com/dgdl/Infineon-IPP60R180C7DS-v02_00EN.pdf?fileId=5546d4624cb7f111014d483fe4ba707b

LLC Analog Controller ICE2HS01G
http://www.infineon.com/dgdl/ICE2HS01G_PDS_v2.1_20110524_Public.pdf?folderId=db3a304412b4079
50112b408e8c90004&fileId=db3a30432a40a650012a458289712b4c

Advanced Dual-Channel Gate Drive 2EDN7524F
http://www.infineon.com/dgdl/Infineon-2EDN752x_2EDN852x-DS-v01_00EN.pdf?fileId=5546d4624cb7f111014d672f9fbb5142

Bias QR Flyback Controller ICE2QR2280Z
http://www.infineon.com/dgdl/Datasheet_ICE2QR2280Z_v21_20110830.pdf?folderId=db3a304412b4079
50112b408e8c90004&fileId=db3a30432a7fedfc012a8d8038e00473

SR MOSFETs OptiMOSTM BSC010N04LS
http://www.infineon.com/dgdl/BSC010N04LS_rev2.0.pdf?folderId=db3a304313b8b5a60113cee8763b02
d7&fileId=db3a3043353fdc16013552c1c63647c4

Main Transformer and Resonant Choke Ferrite Cores
http://en.tdk.eu/blob/519704/download/2/ferrites-and-accessories-data-book-130501.pdf

Half Bridge Gate Drive 2EDL05N06PF
http://www.infineon.com/cms/en/product/power/gate-driver/eicedrivershigh-voltage-gate-driver-icsand-boards/gate-driver-ic-eicedriver-compact/2EDL05N06PF/power/gatedriver/2EDL05N06PF/power/gatedriver/2EDL05N06PF/productType.html?productType=db3a30443e36c802013e3c260fb915fd
Application Note
26
Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
References
7
References
[1] T. Fujihira: “Theory of Semiconductor Superjunction Devices”, Jpn. J. Appl. Phys., Vol.36, pp. 62546262, 1997
[2] Francesco Di Domenico and others: “Design of 600 W HB LLC Demo Board using 600 V CoolMOS™ P6”,
Infineon Technologies AN 2015
[3] Lawrence Lin, Gary Chang: “Consideration of Primary side MOSFET Selection for LLC topology”,
Infineon Technologies AN 2014
[4] Anders Lind: “LLC Converter Design Note”, Infineon Technologies AN 2013-03
[5] Liu Jianwei, Li Dong: “Design Guide for LLC Converter with ICE2HS01G”, Infineon Technologies AN V1.0,
July 2011
[6] F. Stückler, S. Abdel-Rahman, K. Siu: “600 V CoolMOS™ C7 Design Guide”, Infineon Technologies
Application Note
27
Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
List of abbreviations
8
List of abbreviations
Table 3
Abbreviation and symbols used
CGD ................................................................................................... internal gate drain capacitance CGD=Crss
Ciss ................................................................................................................. input capacitance Ciss=CGS+CGD
Co(er) .................................................................................................................... effective output capacitance
Cr ................................................................................................................................... resonant capacitance
di/dt ...................................................................................... steepness of current slope at turn off / turn on
DUT......................................................................................................................................... device under test
dv/dt ..................................................................................... steepness of voltage slope at turn off / turn on
Eoff ....................................................................................................................... power loss during switch off
Eon ........................................................................................................................power loss during switch on
Eoss.................................................................. stored energy in output capacitance (Coss) at typ. VDS=400V
FHA.................................................................................................... First Harmonic Approximation Method
FOM ......................................................................................................................................... Figures of Merit
fr ....................................................................................................................................... resonand frequency
ID ................................................................................................................................................... drain current
IRMS ............................................................................................................ effective root mean square current
Imag ..................................................................................................................................... magnatizing current
Im,pk.................................................................................................................................................. peak current
K ...................................................................................................................................................... gain factor
Lr ..................................................................................................................................... resonant inductance
Lm ............................................................................................................................... magnatizing inductance
m ................................................................................................................................................... voltage gain
Np ............................................................................................................................................. primary winding
NS .........................................................................................................................................secondary winding
n .................................................................................................................................... transformer turn ratio
MOSFET ........................................................................... metal oxide semiconductor field effect transistor
Pcond_SR .......................................................................................................... synchronos conduction losses
PFC .............................................................................................................................. power factor correction
PNP ....................................................................................................... bipolar transistor type (pnp vs. npn)
QOSS .........................................................................................................................Charge stored in the COSS
Q ................................................................................................................................................... quality factor
Rac ................................................................................................................................total equivalent resistor
RDS(on) ........................................................................................................... drain-source on-state resistance
Rg,tot ....................................................................................................................................... total gate resistor
Ro ................................................................................................................................................ output resistor
Rth ............................................................................................................................................. thermal resistor
tdead .....................................................................................................................................................dead time
tecs ..................................................................................................................... early channel shut down time
VDS ...................................................................................... drain to source voltage, drain to source voltage
Vgsth ............................................................................................................ drain to source threshold voltage
VO_AC ......................................................................................................... output voltage, alternating current
VIn_AC ............................................................................................................ input voltage, alternating current
Application Note
28
Revision1.2, 2015-06-24
600 W Half Bridge LLC Evaluation Board with 600 V CoolMOS™ C7
List of abbreviations
VIn_nom ........................................................................................................................... nominale input voltage
Vout_nom ..................................................................................................................................... nominale output
ZCS ................................................................................................................................ zero current switching
ZVS ................................................................................................................................zero voltage switching
Revision History
Major changes since the last revision
Page or Reference
--
Description of change
First Release
Revision 1.1
Update on Layout and Structure
Revision 1.2
Update on Section 3.2.4
Application Note
29
Revision1.2, 2015-06-24
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolGaN™, CoolMOS™, CoolSET™, CoolSiC™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, DrBLADE™,
EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, IsoPACK™, iWafer™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OPTIGA™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™,
PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, ReverSave™, SatRIC™, SIEGET™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, SPOC™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM
Limited, UK. ANSI™ of American National Standards Institute. AUTOSAR™ of AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CATiq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of
Microsoft Corporation. HYPERTERMINAL™ of Hilgraeve Incorporated. MCS™ of Intel Corp. IEC™ of Commission Electrotechnique Internationale. IrDA™ of
Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim
Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA.
muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc.
Openwave™ of Openwave Systems Inc. RED HAT™ of Red Hat, Inc. RFMD™ of RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun
Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc.
TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design
Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2014-07-17
www.infineon.com
Edition 2015-05-01
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: [email protected]
Document reference
AN_201411_PL52_007
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