Data Sheet

74HC2G66-Q100;
74HCT2G66-Q100
Dual single-pole single-throw analog switch
Rev. 1 — 18 November 2013
Product data sheet
1. General description
The 74HC2G66-Q100; 74HCT2G66-Q100 is a dual single pole, single-throw analog
switch. Each switch has two input/output terminals (nY and nZ) and a digital enable input
(nE). When nE is LOW, the analog switch is turned off. Inputs include clamp diodes that
enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Wide supply voltage range from 2.0 V to 10.0 V for 74HC2G66-Q100
 Very low ON resistance:
 41  (typ.) at VCC = 4.5 V
 30  (typ.) at VCC = 6.0 V
 21  (typ.) at VCC = 9.0 V
 High noise immunity
 Low power dissipation
 25 mA continuous switch current
 Multiple package options
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
3. Ordering information
Table 1.
Ordering information
Type number
Package
74HC2G66DP-Q100
Temperature range
Name
Description
Version
40 C to +125 C
TSSOP8
plastic thin shrink small outline package; 8
leads; body width 3 mm; lead length 0.5 mm
SOT505-2
40 C to +125 C
VSSOP8
plastic very thin shrink small outline package; 8 SOT765-1
leads; body width 2.3 mm
74HCT2G66DP-Q100
74HC2G66DC-Q100
74HCT2G66DC-Q100
4. Marking
Table 2.
Marking codes
Type number
Marking[1]
74HC2G66DP-Q100
H66
74HCT2G66DP-Q100
T66
74HC2G66DC-Q100
H66
74HCT2G66DC-Q100
T66
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
VI
1Y
1Z
nY or nZ
input
VM
1E
GND
2Z
VOH
VM
t PLH
2Y
2E
nZ or nY
output
VM
Logic symbol
74HC_HCT2G66_Q100
Product data sheet
VM
VOL
001aag497
Fig 1.
t PHL
001aaa541
Fig 2.
Logic diagram for 1 switch
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
2 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
6. Pinning information
6.1 Pinning
+&*4
+&7*4
<
9&&
=
(
(
=
*1'
<
DDD
Fig 3.
Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
1Y, 2Y
1, 5
independent input or output
1Z, 2Z
2, 6
independent input or output
GND
4
ground (0 V)
1E, 2E
7, 3
enable input (active HIGH)
VCC
8
supply voltage
7. Functional description
Table 4.
Function table[1]
Input nE
Switch
L
OFF
H
ON
[1]
H = HIGH voltage level; L = LOW voltage level.
74HC_HCT2G66_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
3 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
0.5
+11.0
V
-
20
mA
-
20
mA
-
20
mA
30
mA
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
[1]
ISK
switch clamping current
VI < 0.5 V or VI > VCC + 0.5 V
[1]
ISW
switch current
VSW > 0.5 V or VSW < VCC + 0.5 V
ICC
supply current
-
IGND
ground current
30
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
[1]
[2]
Tamb = 40 C to +125 C
per package
[2]
-
300
mW
per switch
[2]
-
100
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP8 packages: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).[1]
Symbol Parameter
Conditions
74HC2G66-Q100
74HCT2G66-Q100
Unit
Min
Typ
Max
Min
Typ
Max
2.0
5.0
10.0
4.5
5.0
5.5
V
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
VSW
switch voltage
Tamb
ambient temperature
t/V
input transition rise
and fall rate
VCC
supply voltage
VI
[1]
0
-
VCC
0
-
VCC
V
40
+25
+125
40
+25
+125
C
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
VCC = 10.0 V
-
-
35
-
-
-
ns/V
To avoid drawing VCC current out of pin nZ, when switch current flows in pin nY, the voltage drop across the bidirectional switch must not
exceed 0.4 V. If the switch current flows into pin nZ, no VCC current flows out of terminal nY. In this case, there is no limit for the voltage
drop across the switch, but the voltage at pins nY and nZ may not exceed VCC or GND.
74HC_HCT2G66_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
4 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VCC = 2.0 V
1.5
1.2
-
1.5
-
V
VCC = 4.5 V
3.15
2.4
-
3.15
-
V
VCC = 6.0 V
4.2
3.2
-
4.2
-
V
74HC2G66-Q100
VIH
VIL
II
HIGH-level
input voltage
LOW-level
input voltage
input leakage current
VCC = 9.0 V
6.3
4.7
-
6.3
-
V
VCC = 2.0 V
-
0.8
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
V
VCC = 9.0 V
-
4.3
2.7
-
2.7
V
VCC = 6.0 V
-
-
0.1
-
0.1
A
VCC = 9.0 V
-
-
0.2
-
0.2
A
nE; VI = VCC or GND
IS(OFF)
OFF-state
leakage current
nY or nZ; VCC = 9.0 V; see Figure 4
-
0.1
1.0
-
1.0
A
IS(ON)
ON-state
leakage current
nY or nZ; VCC = 9.0 V; see Figure 5
-
0.1
1.0
-
1.0
A
ICC
supply current
nE, nY and nZ = VCC or GND
VCC = 6.0 V
-
-
10
-
20
A
VCC = 9.0 V
-
-
20
-
40
A
CI
input capacitance
-
3.5
-
-
-
pF
CPD
power dissipation
capacitance
-
9
-
-
-
pF
CS(ON)
ON-state capacitance
-
8
-
-
-
pF
74HCT2G66-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
V
II
input leakage current
nE; VI = VCC or GND; VCC = 5.5 V
-
-
1.0
-
1.0
A
IS(OFF)
OFF-state
leakage current
nY or nZ; VCC = 5.5 V; see Figure 4
-
0.1
1.0
-
1.0
A
IS(ON)
ON-state
leakage current
nY or nZ; VCC = 5.5 V; see Figure 5
-
0.1
1.0
-
1.0
A
ICC
supply current
nE, nY and nZ = VCC or GND;
VCC = 4.5 V to 5.5 V
-
-
10
-
20
A
ICC
additional supply
current
nE = VCC  2.1 V; IO = 0 A;
VCC = 4.5 V to 5.5 V;
-
-
375
-
410
A
74HC_HCT2G66_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
5 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
Table 7.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
CI
input capacitance
-
3.5
-
-
-
pF
CPD
power dissipation
capacitance
-
9
-
-
-
pF
CS(ON)
ON-state capacitance
-
8
-
-
-
pF
[1]
Typical values are measured at Tamb = 25 C.
10.1 Test circuits
VCC
VCC
nE
VIL
IS
VI
nE
VIH
nY
nZ
IS
IS
GND
VI
VO
001aaj465
Product data sheet
GND
VO
VI = VCC or GND and VO = open circuit.
Test circuit for measuring OFF-state
leakage current
74HC_HCT2G66_Q100
nZ
001aaj466
VI = VCC or GND and VO = GND or VCC.
Fig 4.
nY
Fig 5.
Test circuit for measuring ON-state
leakage current
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Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
6 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
10.2 ON resistance
Table 8.
ON resistance for 74HC2G66 and 74HCT2G66
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graph see Figure 7.
Symbol
Parameter
40 C to +85 C
Conditions
40 C
to +125 C
Unit
Min
Typ[2]
Max
Min
Max
ISW = 0.1 mA; VCC = 2.0 V
-
250
-
-
-

ISW = 1.0 mA; VCC = 4.5 V
-
41
118
-
142

ISW = 1.0 mA; VCC = 6.0 V
-
30
105
-
126

ISW = 1.0 mA; VCC = 9.0 V
-
21
88
-
105

74HC2G66-Q100[1]
RON(peak) ON resistance (peak)
RON(rail)
ON resistance (rail)
VI = GND to VCC; see Figure 6 and 7
VI = GND; see Figure 6 and 7
ISW = 0.1 mA; VCC = 2.0 V
-
65
-
-
-

ISW = 1.0 mA; VCC = 4.5 V
-
28
95
-
115

ISW = 1.0 mA; VCC = 6.0 V
-
22
82
-
100

ISW = 1.0 mA; VCC = 9.0 V
-
18
70
-
80

ISW = 0.1 mA; VCC = 2.0 V
-
65
-
-
-

ISW = 1.0 mA; VCC = 4.5 V
-
31
106
-
128

ISW = 1.0 mA; VCC = 6.0 V
-
23
94
-
113

ISW = 1.0 mA; VCC = 9.0 V
-
19
78
-
95

VCC = 4.5 V
-
5
-
-
-

VCC = 6.0 V
-
4
-
-
-

VCC = 9.0 V
-
3
-
-
-

-
41
118
-
142

-
28
95
-
115

-
31
106
-
128

-
5
-
-
-

VI = VCC; see Figure 6 and 7
RON
ON resistance mismatch
between channels
VI = VCC to GND; see Figure 6 and 7
74HCT2G66-Q100
RON(peak) ON resistance (peak)
VI = GND to VCC; see Figure 6 and 7
ISW = 1.0 mA; VCC = 4.5 V
RON(rail)
ON resistance (rail)
VI = GND; see Figure 6 and 7
ISW = 1.0 mA; VCC = 4.5 V
VI = VCC; see Figure 6 and 7
ISW = 1.0 mA; VCC = 4.5 V
RON
ON resistance mismatch
between channels
VI = VCC to GND; see Figure 6 and 7
VCC = 4.5 V
[1]
At supply voltages approaching 2 V, the ON resistance becomes extremely non-linear. Therefore it is recommended that these devices
be used to transmit digital signals only, when using this supply voltage.
[2]
Typical values are measured at Tamb = 25 C.
74HC_HCT2G66_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
7 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
10.3 ON resistance test circuit and graphs
mnb006
60
RON
(Ω)
VSW
VCC = 4.5 V
40
VCC
VCC = 6.0 V
nE
VIH
nY
VI
20
nZ
VCC = 9.0 V
GND
ISW
0
0
2
4
6
8
Tamb = 25 C.
RON = VSW / ISW.
Fig 6.
10
VI (V)
001aaj467
Test circuit for measuring ON resistance
Fig 7.
Typical ON resistance as a function of
input voltage
11. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 10.
Symbol Parameter
40 C to +85 C
Conditions
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VCC = 2.0 V
-
6.5
65
-
80
ns
VCC = 4.5 V
-
2
13
-
15
ns
VCC = 6.0 V
-
1.5
11
-
14
ns
VCC = 9.0 V
-
1.2
10
-
12
ns
VCC = 2.0 V
-
40
125
-
150
ns
VCC = 4.5 V
-
12
29
-
30
ns
VCC = 6.0 V
-
10
21
-
26
ns
-
7
16
-
20
ns
74HC2G66-Q100
tpd
ten
propagation delay nY to nZ or nZ to nY; RL =  ;
see Figure 8
enable time
nE to nY or nZ; see Figure 9
[2]
[2]
VCC = 9.0 V
tdis
disable time
nE to nY or nZ; see Figure 9
[2]
VCC = 2.0 V
-
21
145
-
175
ns
VCC = 4.5 V
-
12
29
-
35
ns
VCC = 6.0 V
-
11
28
-
33
ns
-
10
23
-
27
ns
-
9
-
-
-
pF
VCC = 9.0 V
CPD
power dissipation VI = GND to VCC
capacitance
74HC_HCT2G66_Q100
Product data sheet
[3]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
8 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 10.
Symbol Parameter
40 C to +85 C
Conditions
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
-
2
15
-
18
ns
-
13
30
-
36
ns
-
13
44
-
53
ns
-
9
-
-
-
pF
74HCT2G66-Q100
propagation delay nY to nZ or nZ to nY; RL =  ;
see Figure 8
tpd
[2]
VCC = 4.5 V
ten
enable time
nE to nY or nZ; see Figure 9
tdis
disable time
nE to nY or nZ; see Figure 9
[2]
VCC = 4.5 V
[2]
VCC = 4.5 V
power dissipation VI = GND to VCC  1.5 V
capacitance
CPD
[1]
[2]
[3]
All typical values are measured at Tamb = 25 C.
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3]
CPD is used to determine the dynamic power dissipation PD (W).
PD = CPD  VCC2  fi + ((CL  CSW)  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CSW = maximum switch capacitance in pF (see Table 7);
VCC = supply voltage in volts;
((CL  CSW)  VCC2  fo) = sum of outputs.
11.1 Waveforms and test circuit
VI
nY or nZ
input
VM
VM
GND
t PLH
t PHL
VOH
nZ or nY
output
VM
VM
VOL
001aaa541
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8.
Input (nY or nZ) to output (nZ or nY) propagation delays
74HC_HCT2G66_Q100
Product data sheet
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Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
9 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
VI
nE input
VM
GND
t PLZ
t PZL
VCC
nY or nZ
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
t PZH
t PHZ
nY or nZ
output
HIGH-to-OFF
OFF-to-HIGH
VOH
VY
VM
GND
switch
enabled
switch
disabled
switch
enabled
001aaa542
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9.
Table 10.
Enable and disable times
Measurement points
Type
Input
Output
VM
VM
VX
VY
74HC2G66-Q100
0.5VCC
0.5VCC
VOL + 10 %
VOH  10 %
74HCT2G66-Q100
1.3 V
1.3 V
VOL + 10 %
VOH  10 %
74HC_HCT2G66_Q100
Product data sheet
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© NXP B.V. 2013. All rights reserved.
10 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
tW
VI
90 %
negative
pulse
VM
VM
10 %
0V
VI
tf
tr
tr
tf
90 %
positive
pulse
VM
VM
10 %
0V
tW
VCC
VCC
VI
G
VO
RL
S1
open
DUT
CL
RT
001aad983
Test data is given in Table 11.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 10. Test circuit for measuring switching times
Table 11.
Test data
Type
Input
Load
[1]
S1 position
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
GND to VCC
6 ns
50 pF
1 k
open
GND
VCC
74HCT2G66-Q100 GND to 3 V
6 ns
50 pF
1 k
open
GND
VCC
74HC2G66-Q100
[1]
There is no constraint on tr, tf with a 50 % duty factor when measuring fmax.
74HC_HCT2G66_Q100
Product data sheet
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Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
11 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
11.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics for 74HC2G66 and 74HCT2G66
GND = 0 V; tr = tf = 6.0 ns; CL = 50 pF; unless otherwise specified. All typical values are measured at Tamb = 25 C.
Symbol
Parameter
Conditions
Min
THD
total harmonic
distortion
fi = 1 kHz; RL = 10 k; see Figure 11
Typ
Max
Unit
%
VCC = 4.5 V; VI = 4.0 V (p-p)
-
0.04
-
%
VCC = 9.0 V; VI = 8.0 V (p-p)
-
0.02
-
%
VCC = 4.5 V; VI = 4.0 V (p-p)
-
0.12
-
%
VCC = 9.0 V; VI = 8.0 V (p-p)
-
0.06
-
%
VCC = 4.5 V
-
180
-
MHz
VCC = 9.0 V
-
200
-
MHz
VCC = 4.5 V
-
50
-
dB
VCC = 9.0 V
-
50
-
dB
VCC = 4.5 V
-
110
-
mV
VCC = 9.0 V
-
220
-
mV
VCC = 4.5 V
-
60
-
dB
VCC = 9.0 V
-
60
-
dB
fi = 10 kHz; RL = 10 k; see Figure 11
f(3dB)
iso
3 dB frequency
response
isolation (OFF-state)
crosstalk voltage
Vct
Xtalk
RL = 50 ; CL = 10 pF;
see Figure 12 and 13
RL = 600 ; fi = 1 MHz;
see Figure 14 and 15
between digital input and switch (peak
to peak value); RL = 600 ; fi = 1 MHz;
see Figure 16
between switches; RL = 600 ;
fi = 1 MHz; see Figure 17
crosstalk
11.3 Test circuits and graphs
VCC
VCC
VCC
nE
VIH
10 μF
nY/nZ
fi
nE
VIH
2RL
2RL
0.1 μF
nZ/nY
VO
2RL
CL
D
VCC
nY/nZ
fi
001aaj468
nZ/nY
VO
2RL
CL
dB
001aaj469
With fi = 1 MHz, adjust the switch input voltage for a
0 dBm level at the switch output (0 dBm = 1 mW into
50 ). Then Increase the input frequency until the dB
meter reads 3 dB.
Fig 11. Test circuit for measuring total harmonic
distortion
74HC_HCT2G66_Q100
Product data sheet
Fig 12. Test circuit for measuring the 3 dB frequency
response
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
12 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
mna083
5
(dB)
0
−5
10
102
103
104
105
106
fi (kHz)
Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 ; RSOURCE = 1 k.
Fig 13. Typical 3 dB frequency response
VCC
VCC
nE
VIL
2RL
0.1 μF
nY/nZ
fi
nZ/nY
VO
CL
2RL
dB
001aaj470
Adjust the switch input voltage for a 0 dBm level (0 dBm = 1 mW into 600 )
Fig 14. Test circuit for measuring isolation (OFF-state)
74HC_HCT2G66_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
13 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
mna082
0
(dB)
−20
−40
−60
−80
−100
10
102
103
104
105
106
fi (kHz)
Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 ; RSOURCE = 1 k.
Fig 15. Typical isolation (OFF-state) as a function of frequency
VCC
nE
VCC
VCC
GND
2RL
2RL
nY/nZ
nZ/nY
DUT
2RL
2RL
CL
oscilloscope
GND
mnb011
a. Circuit
V(p−p)
mnb012
b. Crosstalk voltage
Adjust the switch input voltage for a 0 dBm level (0 dBm = 1 mW into 600 )
Fig 16. Test circuit for measuring crosstalk voltage (between the digital input and the switch)
74HC_HCT2G66_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
14 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
VCC
1E
VIH
0.1 μF
RL
2RL
1Y or 1Z
1Z or 1Y
CHANNEL
ON
fi
2RL
CL
V
VO1
V
VO2
2E
VIL
VCC
VCC
2RL
2RL
2Y or 2Z
2RL
2Z or 2Y
CHANNEL
OFF
2RL
CL
001aai846
Adjust the switch input voltage for a 0 dBm level (0 dBm = 1 mW into 600 )
Fig 17. Test circuit for measuring crosstalk (between the switches)
74HC_HCT2G66_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
15 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
12. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
Fig 18. Package outline SOT505-2 (TSSOP8)
74HC_HCT2G66_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
16 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
REFERENCES
IEC
JEDEC
JEITA
MO-187
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
Fig 19. Package outline SOT765-1 (VSSOP8)
74HC_HCT2G66_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
17 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
13. Abbreviations
Table 13.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
DUT
Device Under Test
14. Revision history
Table 14.
Revision history
Document ID
Release date
74HC_HCT2G66_Q100 v.1 20131118
74HC_HCT2G66_Q100
Product data sheet
Data sheet status
Change notice
Supersedes
Product data sheet
-
-
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
18 of 21
74HC2G66-Q100; 74HCT2G66-Q100
NXP Semiconductors
Dual single-pole single-throw analog switch
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT2G66_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
19 of 21
NXP Semiconductors
74HC2G66-Q100; 74HCT2G66-Q100
Dual single-pole single-throw analog switch
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74HC_HCT2G66_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
20 of 21
NXP Semiconductors
74HC2G66-Q100; 74HCT2G66-Q100
Dual single-pole single-throw analog switch
17. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.3
11
11.1
11.2
11.3
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ON resistance test circuit and graphs. . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms and test circuit . . . . . . . . . . . . . . . . 9
Additional dynamic characteristics . . . . . . . . . 12
Test circuits and graphs . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 18 November 2013
Document identifier: 74HC_HCT2G66_Q100