Low-power configurable multiple function gate

74AUP1G97
Low-power configurable multiple function gate
Rev. 9 — 17 September 2015
Product data sheet
1. General description
The 74AUP1G97 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR,
NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G97 has Schmitt trigger inputs making it capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT is defined as the input
hysteresis voltage VH.
2. Features and benefits
 Wide supply voltage range from 0.8 V to 3.6 V
 High noise immunity
 ESD protection:
 HBM JESD22-A114F exceeds 5000 V
 MM JESD22-A115-A exceeds 200 V
 CDM JESD22-C101E exceeds 1000 V
 Low static power consumption; ICC = 0.9 A (maximum)
 Latch-up performance exceeds 100 mA per JESD 78 Class II
 Inputs accept voltages up to 3.6 V
 Low noise overshoot and undershoot < 10 % of VCC
 IOFF circuitry provides partial power-down mode operation
 Multiple package options
 Specified from 40 C to +85 C and 40 C to +125 C
74AUP1G97
NXP Semiconductors
Low-power configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AUP1G97GW
40 C to +125 C
SC-88
plastic surface-mounted package; 6 leads
SOT363
74AUP1G97GM
40 C to +125 C
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1  1.45  0.5 mm
74AUP1G97GF
40 C to +125 C
XSON6
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1  1  0.5 mm
74AUP1G97GN
40 C to +125 C
XSON6
extremely thin small outline package; no leads;
6 terminals; body 0.9  1.0  0.35 mm
SOT1115
74AUP1G97GS
40 C to +125 C
XSON6
extremely thin small outline package; no leads;
6 terminals; body 1.0  1.0  0.35 mm
SOT1202
74AUP1G97GX
40 C to +125 C
X2SON6
plastic thermal extremely thin small outline package;
no leads; 6 terminals; body 1  0.8  0.35 mm
SOT1255
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP1G97GW
aV
74AUP1G97GM
aV
74AUP1G97GF
aV
74AUP1G97GN
aV
74AUP1G97GS
aV
74AUP1G97GX
aV
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
$
%
&
Fig 1.
<
DDG
Logic symbol
74AUP1G97
Product data sheet
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Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74AUP1G97
NXP Semiconductors
Low-power configurable multiple function gate
6. Pinning information
6.1 Pinning
$83*
$83*
%
&
*1'
9&&
$
<
%
&
*1'
9&&
$
<
DDH
7UDQVSDUHQWWRSYLHZ
DDG
Fig 2.
Pin configuration SOT363
Fig 3.
Pin configuration SOT886
$83*
$83*
%
%
&
*1'
9&&
$
<
*1'
&
$
<
DDH
DDD
7UDQVSDUHQWWRSYLHZ
Fig 4.
9&&
7UDQVSDUHQWWRSYLHZ
Pin configuration SOT891, SOT1115 and
SOT1202
Fig 5.
Pin configuration SOT1255 (X2SON6)
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
B
1
data input
GND
2
ground (0 V)
A
3
data input
Y
4
data output
VCC
5
supply voltage
C
6
data input
74AUP1G97
Product data sheet
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Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 23
74AUP1G97
NXP Semiconductors
Low-power configurable multiple function gate
7. Functional description
Function table[1]
Table 4.
Input
Output
C
B
A
Y
L
L
L
L
L
L
H
L
L
H
L
H
L
H
H
H
H
L
L
L
H
L
H
H
H
H
L
L
H
H
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
7.1 Logic configurations
Table 5.
Function selection table
Logic function
Figure
2-input MUX
see Figure 6
2-input AND
see Figure 7
2-input OR with one input inverted
see Figure 8
2-input NAND with one input inverted
see Figure 8
2-input AND with one input inverted
see Figure 9
2-input NOR with one input inverted
see Figure 9
2-input OR
see Figure 10
Inverter
see Figure 11
Buffer
see Figure 12
9&&
9&&
%
&
%
<
$
&
$
$
<
$
<
&
<
&
DDH
DDH
Fig 6.
2-input MUX
74AUP1G97
Product data sheet
Fig 7.
2-input AND gate
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Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 23
74AUP1G97
NXP Semiconductors
Low-power configurable multiple function gate
9&&
$
&
<
$
&
<
$
9&&
&
%
&
<
%
&
%
<
<
DDH
Fig 8.
&
<
DDH
2-input NAND gate with input A inverted or
2-input OR gate with input C inverted
Fig 9.
2-input NOR gate with input B inverted or
2-input AND gate with input C inverted
9&&
9&&
%
%
&
<
&
&
<
<
&
<
DDH
DDH
Fig 10. 2-input OR gate
Fig 11. Inverter
9&&
%
%
<
<
DDH
Fig 12. Buffer
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
VI < 0 V
[1]
VO < 0 V
[1]
Min
Max
Unit
0.5
+4.6
V
50
-
0.5
+4.6
50
-
0.5
+4.6
V
-
20
mA
mA
V
mA
VO
output voltage
Active mode and Power-down
mode
IO
output current
VO = 0 V to VCC
ICC
supply current
-
50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
74AUP1G97
Product data sheet
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Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74AUP1G97
NXP Semiconductors
Low-power configurable multiple function gate
Table 6.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Ptot
Parameter
Conditions
total power dissipation
Tamb = 40 C to +125 C
Min
Max
Unit
-
250
mW
[2]
[1]
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For X2SON6 and XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 7.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VO
output voltage
Tamb
ambient temperature
Conditions
Min
Max
Unit
0.8
3.6
V
0
3.6
V
0
VCC
V
0
3.6
V
40
+125
C
Active mode
Power-down mode; VCC = 0 V
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC  0.1
-
-
V
IO = 1.1 mA; VCC = 1.1 V
0.75VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
1.11
-
-
V
Tamb = 25 C
VOH
VOL
HIGH-level output voltage
LOW-level output voltage
VI = VT+ or VT
IO = 1.9 mA; VCC = 1.65 V
1.32
-
-
V
IO = 2.3 mA; VCC = 2.3 V
2.05
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.9
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.72
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.6
-
-
V
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3VCC
V
VI = VT+ or VT
IO = 1.7 mA; VCC = 1.4 V
-
-
0.31
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.31
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.31
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.44
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.31
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.44
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.1
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.2
A
74AUP1G97
Product data sheet
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Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 23
74AUP1G97
NXP Semiconductors
Low-power configurable multiple function gate
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.2
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.5
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
40
A
CI
input capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
-
1.1
-
pF
CO
output capacitance
VO = GND; VCC = 0 V
-
1.7
-
pF
[1]
Tamb = 40 C to +85 C
VOH
HIGH-level output voltage
VI = VT+ or VT
IO = 20 A; VCC = 0.8 V to 3.6 V
VOL
LOW-level output voltage
VCC  0.1
-
-
V
IO = 1.1 mA; VCC = 1.1 V
0.7VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
1.03
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.30
-
-
V
IO = 2.3 mA; VCC = 2.3 V
1.97
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.85
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.67
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.55
-
-
V
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.37
V
VI = VT+ or VT
IO = 1.9 mA; VCC = 1.65 V
-
-
0.35
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.33
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.45
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.33
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.45
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.5
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.5
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.6
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.9
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
50
A
74AUP1G97
Product data sheet
[1]
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Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
7 of 23
74AUP1G97
NXP Semiconductors
Low-power configurable multiple function gate
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +125 C
VOH
HIGH-level output voltage
VI = VT+ or VT
IO = 20 A; VCC = 0.8 V to 3.6 V
LOW-level output voltage
VOL
VCC  0.11
-
-
V
IO = 1.1 mA; VCC = 1.1 V
0.6VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
0.93
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.17
-
-
V
IO = 2.3 mA; VCC = 2.3 V
1.77
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.67
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.40
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.30
-
-
V
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.11
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.33VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.41
V
VI = VT+ or VT
IO = 1.9 mA; VCC = 1.65 V
-
-
0.39
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.36
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.50
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.36
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.50
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.75
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.75
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.75
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
1.4
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
75
A
[1]
[1]
One input at VCC  0.6 V, other input at VCC or GND.
74AUP1G97
Product data sheet
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Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74AUP1G97
NXP Semiconductors
Low-power configurable multiple function gate
11. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter
25 C
Conditions
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
-
23.0
-
-
-
-
VCC = 1.1 V to 1.3 V
2.8
6.6
12.6
2.5
13.0
13.2
ns
VCC = 1.4 V to 1.6 V
2.3
4.7
7.6
2.5
8.2
8.6
ns
VCC = 1.65 V to 1.95 V
2.2
3.9
6.2
2.0
6.8
7.2
ns
VCC = 2.3 V to 2.7 V
2.0
3.2
4.5
1.7
5.1
5.3
ns
VCC = 3.0 V to 3.6 V
1.9
2.9
3.9
1.5
4.1
4.3
ns
-
26.6
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
3.2
7.4
14.3
2.9
14.9
15.2
ns
VCC = 1.4 V to 1.6 V
2.6
5.3
8.7
2.8
9.4
9.8
ns
VCC = 1.65 V to 1.95 V
2.5
4.5
7.0
2.3
7.8
8.2
ns
VCC = 2.3 V to 2.7 V
2.4
3.7
5.2
2.1
5.9
6.1
ns
VCC = 3.0 V to 3.6 V
2.3
3.4
4.6
1.9
4.9
5.1
ns
-
30.1
-
-
-
-
ns
Max
Max
(85 C) (125 C)
CL = 5 pF
tpd
propagation delay A, B, C to Y; see Figure 13
[2]
VCC = 0.8 V
ns
CL = 10 pF
tpd
propagation delay A, B, C to Y; see Figure 13
[2]
VCC = 0.8 V
CL = 15 pF
tpd
propagation delay A, B, C to Y; see Figure 13
VCC = 0.8 V
74AUP1G97
Product data sheet
[2]
VCC = 1.1 V to 1.3 V
3.6
8.2
16.0
3.2
16.7
17.0
ns
VCC = 1.4 V to 1.6 V
2.9
5.9
9.6
3.1
10.4
10.9
ns
VCC = 1.65 V to 1.95 V
2.8
5.0
7.8
2.5
8.7
9.1
ns
VCC = 2.3 V to 2.7 V
2.7
4.2
5.8
2.4
6.5
6.9
ns
VCC = 3.0 V to 3.6 V
2.5
3.8
5.1
2.2
5.5
5.7
ns
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Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 23
74AUP1G97
NXP Semiconductors
Low-power configurable multiple function gate
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter
25 C
Conditions
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
-
38.3
-
-
-
-
ns
4.6
10.5
20.9
4.0
21.8
22.2
ns
Max
Max
(85 C) (125 C)
CL = 30 pF
propagation delay A, B, C to Y; see Figure 13
tpd
[2]
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
3.7
7.4
12.2
3.8
13.3
14.0
ns
VCC = 1.65 V to 1.95 V
3.5
6.3
9.9
3.2
11.1
11.8
ns
VCC = 2.3 V to 2.7 V
3.4
5.3
7.4
3.1
8.3
8.8
ns
VCC = 3.0 V to 3.6 V
3.2
4.9
6.6
2.8
7.0
7.4
ns
VCC = 0.8 V
-
2.6
-
-
-
-
pF
VCC = 1.1 V to 1.3 V
-
2.8
-
-
-
-
pF
VCC = 1.4 V to 1.6 V
-
2.9
-
-
-
-
pF
VCC = 1.65 V to 1.95 V
-
3.1
-
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
3.7
-
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
4.3
-
-
-
-
pF
CL = 5 pF, 10 pF, 15 pF and 30 pF
power dissipation
capacitance
CPD
fi = 1 MHz; VI = GND to VCC
[1]
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPLH and tPHL
[3]
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of the outputs.
74AUP1G97
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 17 September 2015
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NXP Semiconductors
Low-power configurable multiple function gate
12. Waveforms
9,
$%&LQSXW
90
90
*1'
W 3+/
W 3/+
92+
90
<RXWSXW
90
92/
W 3/+
W 3+/
92+
<RXWSXW
90
90
92/
DDE
Measurement points are given in Table 10.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 13. Input A, B and C to output Y propagation delay times
Table 10.
Measurement points
Supply voltage
Output
Input
VCC
VM
VM
VI
tr = tf
0.8 V to 3.6 V
0.5VCC
0.5VCC
VCC
 3.0 ns
74AUP1G97
Product data sheet
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Rev. 9 — 17 September 2015
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NXP Semiconductors
Low-power configurable multiple function gate
9&&
9(;7
Nȍ
*
9,
92
'87
&/
57
5/
DDF
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 14. Test circuit for measuring switching times
Table 11.
Test data
Supply voltage
Load
VEXT
[1]
VCC
CL
RL
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF
5 k or 1 M
[1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
open
GND
2VCC
For measuring enable and disable times RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1 M.
13. Transfer characteristics
Table 12. Transfer characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 14.
Symbol Parameter
VT+
VT
25 C
Conditions
Typ
Max
Min
Max
(85 C)
Max
(125 C)
0.30
-
0.60
0.30
0.60
0.62
V
VCC = 1.1 V
0.53
-
0.90
0.53
0.90
0.92
V
VCC = 1.4 V
0.74
-
1.11
0.74
1.11
1.13
V
VCC = 1.65 V
0.91
-
1.29
0.91
1.29
1.31
V
VCC = 2.3 V
1.37
-
1.77
1.37
1.77
1.80
V
VCC = 3.0 V
1.88
-
2.29
1.88
2.29
2.32
V
negative-going
see Figure 15 and Figure 16
threshold voltage
VCC = 0.8 V
Product data sheet
Unit
Min
positive-going
see Figure 15 and Figure 16
threshold voltage
VCC = 0.8 V
74AUP1G97
40 C to +125 C
0.10
-
0.60
0.10
0.60
0.60
V
VCC = 1.1 V
0.26
-
0.65
0.26
0.65
0.65
V
VCC = 1.4 V
0.39
-
0.75
0.39
0.75
0.75
V
VCC = 1.65 V
0.47
-
0.84
0.47
0.84
0.84
V
VCC = 2.3 V
0.69
-
1.04
0.69
1.04
1.04
V
VCC = 3.0 V
0.88
-
1.24
0.88
1.24
1.24
V
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Low-power configurable multiple function gate
Table 12. Transfer characteristics …continued
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 14.
Symbol Parameter
VH
25 C
Conditions
40 C to +125 C
Unit
Min
Typ
Max
Min
Max
(85 C)
Max
(125 C)
VCC = 0.8 V
0.07
-
0.50
0.07
0.50
0.50
V
VCC = 1.1 V
0.08
-
0.46
0.08
0.46
0.46
V
VCC = 1.4 V
0.18
-
0.56
0.18
0.56
0.56
V
VCC = 1.65 V
0.27
-
0.66
0.27
0.66
0.66
V
VCC = 2.3 V
0.53
-
0.92
0.53
0.92
0.92
V
VCC = 3.0 V
0.79
-
1.31
0.79
1.31
1.31
V
(VT+  VT); see Figure 15,
Figure 16, Figure 17 and
Figure 18
hysteresis
voltage
14. Waveforms transfer characteristics
92
9,
97
97
9+
92
9,
9+
97
97
Fig 15. Transfer characteristic
74AUP1G97
Product data sheet
PQD
PQD
VT+ and VT limits at 70 % and 20 %.
Fig 16. Definition of VT+, VT and VH
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Rev. 9 — 17 September 2015
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NXP Semiconductors
Low-power configurable multiple function gate
DDG
,&&
—$
9,9
Fig 17. Typical transfer characteristics; VCC = 1.8 V
DDG
,&&
—$
9,9
Fig 18. Typical transfer characteristics; VCC = 3.0 V
74AUP1G97
Product data sheet
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Rev. 9 — 17 September 2015
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Low-power configurable multiple function gate
15. Package outline
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74AUP1G97
Product data sheet
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Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Low-power configurable multiple function gate
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74AUP1G97
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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NXP Semiconductors
Low-power configurable multiple function gate
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74AUP1G97
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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NXP Semiconductors
Low-power configurable multiple function gate
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74AUP1G97
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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NXP Semiconductors
Low-power configurable multiple function gate
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74AUP1G97
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Low-power configurable multiple function gate
16. Abbreviations
Table 13.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
17. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AUP1G97 v.9
20150917
Product data sheet
-
74AUP1G97 v.8
Modifications:
74AUP1G97 v.8
Modifications:
74AUP1G97 v.7
•
Added type number 74AUP1G97GX (SOT1255/X2SON6).
20120815
•
Product data sheet
-
74AUP1G97 v.7
Package outline drawing of SOT886 (Figure 20) modified.
20111128
Product data sheet
-
74AUP1G97 v.6
74AUP1G97 v.6
20110110
Product data sheet
-
74AUP1G97 v.5
74AUP1G97 v.5
20101020
Product data sheet
-
74AUP1G97 v.4
74AUP1G97 v.4
20090623
Product data sheet
-
74AUP1G97 v.3
74AUP1G97 v.3
20090518
Product data sheet
-
74AUP1G97 v.2
74AUP1G97 v.2
20090327
Product data sheet
-
74AUP1G97 v.1
74AUP1G97 v.1
20061107
Product data sheet
-
-
74AUP1G97
Product data sheet
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18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AUP1G97
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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NXP Semiconductors
Low-power configurable multiple function gate
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet
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Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Low-power configurable multiple function gate
20. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
11
12
13
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Logic configurations . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Transfer characteristics . . . . . . . . . . . . . . . . . 12
Waveforms transfer characteristics. . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 September 2015
Document identifier: 74AUP1G97