Data Sheet

74AHC2G241-Q100;
74AHCT2G241-Q100
Dual buffer/line driver; 3-state
Rev. 1 — 12 November 2013
Product data sheet
1. General description
The 74AHC2G241-Q100 and 74AHCT2G241-Q100 are high-speed Si-gate CMOS
devices. They provide a dual non-inverting buffer/line driver with 3-state outputs. The
3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at
pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW level at
pin 2OE causes output 2Y to assume a high-impedance OFF-state. Schmitt-trigger action
at all inputs makes the circuit highly tolerant for slower input rise and fall times.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Symmetrical output impedance
 High noise immunity
 Low power dissipation
 Balanced propagation delays
 Multiple package options
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
74AHC2G241-Q100; 74AHCT2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
74AHC2G241DP-Q100
Temperature range
Name
Description
Version
40 C to +125 C
TSSOP8
plastic thin shrink small outline package;
8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
40 C to +125 C
VSSOP8
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
74AHCT2G241DP-Q100
74AHC2G241DC-Q100
74AHCT2G241DC-Q100
4. Marking
Table 2.
Marking
Marking code[1]
Type number
74AHC2G241DP-Q100
A241
74AHCT2G241DP-Q100
C241
74AHC2G241DC-Q100
A41
74AHCT2G241DC-Q100
C41
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
1OE
2
1A
2
1Y
6
1
7
2OE
1
6
EN1
5
5
2A
2Y
3
7
2
EN2
001aaa409
Fig 1.
Logic symbol
74AHC_AHCT2G241_Q100
Product data sheet
3
001aaa408
Fig 2.
IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
© NXP B.V. 2013. All rights reserved.
2 of 16
NXP Semiconductors
74AHC2G241-Q100; 74AHCT2G241-Q100
Dual buffer/line driver; 3-state
6. Pinning information
6.1 Pinning
$+&*4
$+&7*4
2(
9&&
$
2(
<
<
*1'
$
DDD
Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
1OE
1
output enable input (active LOW)
1A
2
data input
2Y
3
data output
GND
4
ground (0 V)
2A
5
data input
1Y
6
data output
2OE
7
output enable input (active HIGH)
VCC
8
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
Output
Input
Output
1OE
1A
1Y
2OE
2A
2Y
L
L
L
H
L
L
L
H
H
H
H
H
H
X
Z
L
X
Z
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74AHC_AHCT2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
© NXP B.V. 2013. All rights reserved.
3 of 16
74AHC2G241-Q100; 74AHCT2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
VI
Conditions
Min
Max
Unit
supply voltage
0.5
+7.0
V
input voltage
0.5
+7.0
V
20
-
mA
-
20
mA
input clamping current
VI < 0.5 V
[1]
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
[1]
0.5 V < VO < VCC + 0.5 V
IIK
IO
output current
-
25
mA
ICC
supply current
-
75
mA
IGND
ground current
75
-
mA
Tstg
storage temperature
65
+150
C
-
250
mW
total power dissipation
Ptot
[1]
[2]
Tamb = 40 C to +125 C
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74AHC2G241-Q100
74AHCT2G241-Q100
Unit
Min
Typ
Max
Min
Typ
Max
2.0
5.0
5.5
4.5
5.0
5.5
V
input voltage
0
-
5.5
0
-
5.5
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
t/V
input transition rise
and fall rate
VCC
supply voltage
VI
74AHC_AHCT2G241_Q100
Product data sheet
40
+25
+125
40
+25
+125
VCC = 3.3 V  0.3 V
-
-
100
-
-
-
ns/V
VCC = 5.0 V  0.5 V
-
-
20
-
-
20
ns/V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
C
© NXP B.V. 2013. All rights reserved.
4 of 16
NXP Semiconductors
74AHC2G241-Q100; 74AHCT2G241-Q100
Dual buffer/line driver; 3-state
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
-
-
1.5
-
1.5
-
V
VCC = 3.0 V
2.1
-
-
2.1
-
2.1
-
V
VCC = 5.5 V
3.85
-
-
3.85
-
3.85
-
V
VCC = 2.0 V
-
-
0.5
-
0.5
-
0.5
V
VCC = 3.0 V
-
-
0.9
-
0.9
-
0.9
V
VCC = 5.5 V
-
-
1.65
-
1.65
-
1.65
V
HIGH-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 50 A; VCC = 3.0 V
2.9
3.0
-
2.9
-
2.9
-
V
IO = 50 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 4.0 mA; VCC = 3.0 V
2.58
-
-
2.48
-
2.40
-
V
IO = 8.0 mA; VCC = 4.5 V
3.94
-
-
3.8
-
3.70
-
V
LOW-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 3.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA; VCC = 4.5 V
-
-
0.36
-
0.44
-
0.55
V
74AHC2G241-Q100
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
IOZ
OFF-state
VI = VCC or GND;
output current VCC = 5.5 V
-
-
0.25
-
2.5
-
10
A
II
input leakage
current
-
-
0.1
-
1.0
-
2.0
A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
1.0
-
10
-
40
A
CI
input
capacitance
-
1.5
10
-
10
-
10
pF
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
74AHCT2G241-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 50 A
4.4
4.5
-
4.4
-
4.4
-
V
3.94
-
-
3.8
-
3.70
-
V
-
0
0.1
-
0.1
-
0.1
V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA
VOL
LOW-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 50 A
IO = 8.0 mA
74AHC_AHCT2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
© NXP B.V. 2013. All rights reserved.
5 of 16
NXP Semiconductors
74AHC2G241-Q100; 74AHCT2G241-Q100
Dual buffer/line driver; 3-state
Table 7.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
IOZ
OFF-state
VI = VCC or GND;
output current VCC = 5.5 V
-
-
0.25
-
2.5
-
10
A
II
input leakage
current
-
-
0.1
-
1.0
-
2.0
A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
1.0
-
10
-
40
A
ICC
additional
per input pin; VI = 3.4 V;
supply current other inputs at VCC or GND;
IO = 0 A; VCC = 5.5 V
-
-
1.35
-
1.5
-
1.5
mA
CI
input
capacitance
-
1.5
10
-
10
-
10
pF
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
11. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; for test circuit see Figure 7.
Symbol Parameter
25 C
Conditions
Min
Typ
40 C to +85 C 40 C to +125 C Unit
Max
Min
Max
Min
Max
74AHC2G241-Q100
tpd
propagation
delay
nA to nY; see Figure 4
[1]
VCC = 3.0 V to 3.6 V
[2]
CL = 15 pF
-
4.7
8.0
1.0
9.5
1.0
11.5
ns
CL = 50 pF
-
6.6
11.5
1.0
13.0
1.0
14.5
ns
-
3.4
5.5
1.0
6.5
1.0
7.0
ns
-
4.7
7.5
1.0
8.5
1.0
9.5
ns
-
5.0
8.0
1.0
9.5
1.0
11.5
ns
-
6.9
11.5
1.0
13.0
1.0
14.5
ns
-
3.6
5.1
1.0
6.0
1.0
6.5
ns
-
4.9
7.5
1.0
8.5
1.0
9.5
ns
-
4.9
8.0
1.0
9.5
1.0
10.0
ns
-
7.0
11.5
1.0
13.0
1.0
14.5
ns
CL = 15 pF
-
3.6
5.6
1.0
6.3
1.0
7.0
ns
CL = 50 pF
-
5.4
8.0
1.0
9.0
1.0
9.5
ns
VCC = 4.5 V to 5.5 V
[3]
CL = 15 pF
CL = 50 pF
ten
enable time
1OE to 1Y; see Figure 5
[1]
VCC = 3.0 V to 3.6 V
[2]
CL = 15 pF
CL = 50 pF
VCC = 4.5 V to 5.5 V
[3]
CL = 15 pF
CL = 50 pF
2OE to 2Y; see Figure 6
[1]
VCC = 3.0 V to 3.6 V
[2]
CL = 15 pF
CL = 50 pF
VCC = 4.5 V to 5.5 V
74AHC_AHCT2G241_Q100
Product data sheet
[3]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
© NXP B.V. 2013. All rights reserved.
6 of 16
NXP Semiconductors
74AHC2G241-Q100; 74AHCT2G241-Q100
Dual buffer/line driver; 3-state
Table 8.
Dynamic characteristics …continued
GND = 0 V; for test circuit see Figure 7.
Symbol Parameter
tdis
25 C
Conditions
disable time 1OE to 1Y; see Figure 5
VCC = 3.0 V to 3.6 V
CL = 50 pF
2OE to 2Y; see Figure 6
[1]
VCC = 3.0 V to 3.6 V
[2]
CL = 15 pF
CL = 50 pF
power
dissipation
capacitance
Max
Min
Max
Min
Max
-
6.0
9.7
1.0
11.5
1.0
12.5
ns
-
8.3
13.2
1.0
15.0
1.0
16.5
ns
-
4.1
6.8
1.0
8.0
1.0
8.5
ns
-
5.7
8.8
1.0
10.0
1.0
11.0
ns
-
6.3
9.7
1.0
11.5
1.0
12.5
ns
-
9.0
13.2
1.0
15.0
1.0
16.5
ns
[3]
CL = 15 pF
CPD
Typ
[2]
CL = 50 pF
VCC = 4.5 V to 5.5 V
Min
[1]
CL = 15 pF
VCC = 4.5 V to 5.5 V
40 C to +85 C 40 C to +125 C Unit
[3]
CL = 15 pF
-
4.3
6.8
1.0
8.0
1.0
8.5
ns
CL = 50 pF
-
6.1
8.8
1.0
10.0
1.0
11.0
ns
-
10
-
-
-
-
-
pF
CL = 15 pF
-
3.4
5.5
1.0
6.5
1.0
7.0
ns
CL = 50 pF
-
4.7
7.5
1.0
8.5
1.0
9.5
ns
CL = 15 pF
-
3.9
5.1
1.0
6.0
1.0
6.5
ns
CL = 50 pF
-
5.1
7.5
1.0
8.5
1.0
9.5
ns
CL = 15 pF
-
3.4
5.6
1.0
6.3
1.0
6.5
ns
CL = 50 pF
-
4.8
7.5
1.0
9.0
1.0
9.5
ns
per buffer;
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[4]
nA to nY; see Figure 4
[1]
VCC = 4.5 V to 5.5 V
[3]
74AHCT2G241-Q100
tpd
ten
propagation
delay
enable time
74AHC_AHCT2G241_Q100
Product data sheet
1OE to 1Y; see Figure 5
[1]
VCC = 4.5 V to 5.5 V
[3]
2OE to 2Y; see Figure 6
[1]
VCC = 4.5 V to 5.5 V
[3]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
© NXP B.V. 2013. All rights reserved.
7 of 16
74AHC2G241-Q100; 74AHCT2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
Table 8.
Dynamic characteristics …continued
GND = 0 V; for test circuit see Figure 7.
Symbol Parameter
tdis
25 C
Conditions
CL = 15 pF
CL = 50 pF
2OE to 2Y; see Figure 6
[1]
VCC = 4.5 V to 5.5 V
[3]
CL = 15 pF
CL = 50 pF
[1]
Typ
Max
Min
Max
Min
Max
-
4.5
6.8
1.0
8.0
1.0
8.5
ns
-
6.1
8.8
1.0
10.0
1.0
11.0
ns
-
4.0
6.8
1.0
8.0
1.0
8.5
ns
-
5.7
8.8
1.0
10.0
1.0
11.0
ns
-
10
-
-
-
-
-
pF
[3]
VCC = 4.5 V to 5.5 V
power
dissipation
capacitance
Min
[1]
disable time 1OE to 1Y; see Figure 5
CPD
40 C to +85 C 40 C to +125 C Unit
[4]
per buffer;
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[2]
Typical values are measured at VCC = 3.3 V.
[3]
Typical values are measured at VCC = 5.0 V.
[4]
CPD is used to determine the dynamic power dissipation PD (W).
PD = CPD  VCC2  fi +  (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V.
12. Waveforms and test circuit
9,
90
Q$LQSXW
*1'
W3+/
W3/+
92+
90
Q<RXWSXW
92/
PQD
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4.
The input (nA) to output (nY) propagation delays
74AHC_AHCT2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
© NXP B.V. 2013. All rights reserved.
8 of 16
NXP Semiconductors
74AHC2G241-Q100; 74AHCT2G241-Q100
Dual buffer/line driver; 3-state
VI
1OE input
VM
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VOL + 0.3 V
VOL
tPHZ
VOH
tPZH
VOH − 0.3 V
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
enabled
outputs
disabled
001aaa411
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
The input (1OE) to output (1Y) enable and disable times
VI
2OE input
VM
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VOL + 0.3 V
VOL
tPHZ
VOH
tPZH
VOH − 0.3 V
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aaa410
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
Table 9.
The input (2OE) to output (2Y) enable and disable times
Measurement points
Type
Input
Output
VM
VM
74AHC2G241-Q100
0.5VCC
0.5VCC
74AHCT2G241-Q100
1.5 V
0.5VCC
74AHC_AHCT2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
© NXP B.V. 2013. All rights reserved.
9 of 16
74AHC2G241-Q100; 74AHCT2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
9,
W:
QHJDWLYH
SXOVH
90
9
WI
WU
WU
WI
9,
SRVLWLYH
SXOVH
9
90
90
90
W:
9&&
9&&
9,
*
92
5/
6
RSHQ
'87
&/
57
DDG
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 7.
Table 10.
Test circuit for measuring switching times
Test data
Type
Input
Load
S1 position
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
VCC
 3 ns
15 pF, 50 pF
1 k
open
GND
VCC
74AHCT2G241-Q100 3 V
 3 ns
15 pF, 50 pF
1 k
open
GND
VCC
74AHC2G241-Q100
74AHC_AHCT2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
© NXP B.V. 2013. All rights reserved.
10 of 16
74AHC2G241-Q100; 74AHCT2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
13. Package outline
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74AHC_AHCT2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
© NXP B.V. 2013. All rights reserved.
11 of 16
74AHC2G241-Q100; 74AHCT2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
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Package outline SOT765-1 (VSSOP8)
74AHC_AHCT2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
© NXP B.V. 2013. All rights reserved.
12 of 16
74AHC2G241-Q100; 74AHCT2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AHC_AHCT2G241_Q100 v.1
20131112
Product data sheet
-
-
74AHC_AHCT2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
© NXP B.V. 2013. All rights reserved.
13 of 16
NXP Semiconductors
74AHC2G241-Q100; 74AHCT2G241-Q100
Dual buffer/line driver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
Definition
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AHC_AHCT2G241_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
© NXP B.V. 2013. All rights reserved.
14 of 16
NXP Semiconductors
74AHC2G241-Q100; 74AHCT2G241-Q100
Dual buffer/line driver; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2013
© NXP B.V. 2013. All rights reserved.
15 of 16
NXP Semiconductors
74AHC2G241-Q100; 74AHCT2G241-Q100
Dual buffer/line driver; 3-state
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms and test circuit . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 November 2013
Document identifier: 74AHC_AHCT2G241_Q100