ATS635LSE and ATS636LSE Datasheet

ATS636LSE
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: December 1, 2015
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, refer to the ATS128.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, LLC reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
ATS636LSE
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
Features and Benefits
Description
▪Chopper Stabilization
▫Extremely low switchpoint drift over temperature
▪On-chip Protection
▫Supply transient protection
▫Output short-circuit protection
▫Reverse-battery protection
▪True Zero-Speed Operation
▪True Power-On State
▪Single-chip Sensing IC for High Reliability
▪Optimized Magnetic Circuit
▪Wide Operating Voltage Range
▪Internal Regulator
The ATS636LSE programmable, true power-on state (TPOS),
device is optimized Hall-effect IC and rare-earth pellet
combinations that switch in response to magnetic signals
created by ferromagnetic targets in gear-tooth sensing and
proximity applications.
The device is externally programmable. A wide range of
programmability is available on the magnetic operate point
(BOP) while the hysteresis remains fixed. This advanced
feature allows for optimization of the circuit switchpoint and
can drastically reduce the effects of mechanical placement
tolerances found in production environments .
A proprietary dynamic offset cancellation technique, with
an internal high-frequency clock, reduces the residual offset
voltage, which is normally caused by device overmolding,
temperature dependencies, and thermal stress. Having the Hall
element and amplifier in a single chip minimizes many problems
normally associated with low-level analog signals.
Package: 4-pin SIP (suffix SE)
This device is ideal for use in gathering speed or position
information using gear-tooth-based configurations, or for
proximity sensing with ferromagnetic targets.
Continued on the next page…
Not to scale
Functional Block Diagram
VCC
Program / Lock
Reg
Programmming
Logic
To all
subcircuits
Offset Adjust
OUT
AMP
S/H
LPF
Current
Limit
Clock/Logic
GND
635LSE-DS, Rev. 6
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Description (continued)
The ATS636LSE has the opposite polarity and switches low in the
presence of a ferromagnetic target or tooth and switches high in
the presence of a target valley, window, or when the ferromagnetic
target is removed.
Selection Guide
Part Number
Output
(Tooth)
These devices are lead (Pb) free, with 100% matte tin leadframe
plating.
Packing*
ATS636LSETN-T
Low
for additional packing options.
13-in. reel, 450 pieces/reel
*Contact Allegro™
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Fault conditions that produce supply voltage
transients will be clamped by an internal Zener
diode. These conditions can be tolerated but
should be avoided.
Rating
Unit
28
V
Supply Voltage
VCC
Reverse Supply Voltage
VRCC
–18
V
ICC
100
mA
26.5
V
20
mA
Unlimited
–
Overvoltage Supply Current
Output Off Voltage
VOUT
Output Sink Current
IOUT
Magnetic Flux Density
B
Package Power Dissipation
PD
Operating Ambient Temperature
TA
Internal current limiting is intended to protect
the device from output short circuits, but is not
intended for continuous operation.
Range L
See Graph
–
–40 to 150
ºC
Junction Temperature
TJ
165
ºC
Storage Temperature Range
Tstg
–65 to 170
ºC
Pin-out Diagram
1 2
3
4
Terminal List
Number
Name
Function
1
VCC
Device supply
2
VOUT
Device output
3
NC
4
GND
No connect
Device ground
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
ELECTRICAL CHARACTERISTICS over operating voltage and junction temperature range; unless otherwise noted
Characteristics
Symbol
Test Conditions
Supply Voltage2
VCC
Operating
Power-Up State
POS
After programming VCC = 0 × VCC (min), t > tON
: B < BOP
Low Output Voltage
Output Current Limit3
VOUT(SAT)
IOUTM
Output Leakage Current
IOFF
Supply Current
ICC
Reverse Supply Current
Power-On Delay4
Output Rise Time
Output Fall Time
Min.
Typ.1
Max.
Unit
4.2
–
24
V
High
High
High
–
Output on, IOUT = 20 mA
–
175
400
mV
Pulse test method, output on
30
50
90
mA
Output off, VOUT = 24 V
–
–
10
µA
Output off (high)
–
2.5
5.5
mA
Output on (low)
–
2.5
5.5
mA
IRCC
VRCC = –18 V
–
–
–5
mA
tON
Output off, VCC > VCC(min)
–
35
50
µs
tr
RL = 820 Ω, CL = 10 pF
–
1.2
5
µs
tf
RL = 820 Ω, CL = 10 pF
–
1.2
5
µs
–
250
–
kHz
ICC = ICC(max) + 3 mA, TA = 25°C
28
–
–
V
Sampling Frequency
fsample
Supply Zener Voltage
VZsupply
Output Zener Voltage
VZoutput
IOUT = 3 mA, TA = 25°C
30
–
–
V
Supply Zener Current5
IZsupply
VS = 28 V
–
–
8.5
mA
Output Zener Current
IZoutput
VO = 30 V
–
–
3
mA
1Typical
data is at VCC = 12 V and TA = 25°C.
not exceed the maximum thermal junction temperature: see power derating curve.
3Short circuit protection is not intended for continuous operation and is tested using pulses.
4The Power-On Delay is the time that is necessary before the output signal is valid.
5The maximum spec limit for this parameter is equivalent to I
CC (max) + 3 mA.
2Do
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115 Northeast Cutoff
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3
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
MAGNETIC CHARACTERISTICS over operating voltage and junction temperature range using reference target; unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
–
7
–
bit
Switchpoint Polarity
–
1
–
bit
Programming Lock
–
1
–
bit
Temperature = 25°C, Code = –127
2.5
–
–
mm
Switchpoint
Number of Programming Bits
Gear Tooth / Proximity Characteristics (Low switchpoint only)
Programming Air Gap Range1
AGRange
Temperature = 25°C, Code = +127
–
–
1.5
mm
Programming Resolution
AGRes
Temperature = 25°C Program Air Gap = 2.5 mm
–
0.05
–
mm
Air Gap Drift Over Full Temperature
Range2
AGDrift
Device programmed to 2.5 mm
–
0.2
–
mm
Over tooth (ATS636LSE)
–
Low
–
–
Over valley (ATS636LSE)
–
High
–
–
Polarity
P
1The
switchpoint will vary over temperature. A sufficient margin obtained through customer testing is required to guarantee functionality over
temperature. Programming at larger air gaps leaves no safety margin for switchpoint drift. See the applications note Proximity Sensing
Programming Technique on the Allegro website at http://www.allegromicro.com for additional information.
2The switchpoint will vary over temperature, proportionally to the programmed air gap. This parameter is based on characterization data and is not
a tested parameter in production. Switchpoint air gap generally drifts downward as temperature increases.
1000
800
600
400
200
0
0
30
60
90
120 150 180 210 240 270 300 330 360
Position (º)
Reference Target Flux Density vs. Position: Typical
1400
Reference Target Tooth
Reference Target Valley
1200
Flux Density [Gauss]
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
5.25
5.50
5.75
6.00
1200
Flux Density (Gauss)
Tooth and Valley Field vs. Air Gap
Reference Target
Reference Target Flux Density vs. Position
1400
1000
800
600
400
200
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Air Gap [mm]
Reference Target Tooth and Valley Field vs. Air Gap
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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4
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Characteristic Performance
Data taken from 3 lots, 30 pieces/lot
Reference Target 8x
I CC OFF
6
5
5
4
4
ICC (mA)
6
3
4V
15V
24V
2
3
4V
15V
24V
2
1
1
0
-50
-25
0
25
50
75
100
125
150
0
-50
175
-25
0
25
TEMPERATURE (°C)
50
75
100
125
150
175
TEMPERATURE (°C)
V SAT
500
400
VSAT (mV)
I CC (mA)
ICC ON
300
200
20mA
100
0
-50
-25
0
25
50
75
100
125
150
175
TEMPERATURE (°C)
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5
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Data taken from 3 lots, 30 pieces/lot
Reference Target 8x
B OP/BRP vs. Program Code
7
6
AIR GAP (mm)
5
Code -8 BOP
Code -8 BRP
Code 0 BOP
Code 0 BRP
4
Code +32 BOP
Code +32 BRP
3
Code +127 BOP
Code +127 BRP
2
1
0
-50
0
50
100
150
200
TEMPERATURE (°C)
Notes:
• Air gaps for Code 127 at 150°C are interpolated due to test limitations at minimum air gap.
• These graphs are intended to provide an understanding of how the program codes affect the switchpoints. In a production
environment, individual devices would be programmed to individual codes to ensure all devices switch at the same air gap.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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6
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
REFERENCE TARGET DIMENSIONS
Target
Outside Diameter
(Do)
Face Width
(F)
Circular Tooth Length
(T)
Circular Valley Length
(PC – T)
Tooth Whole Depth
(ht)
Reference Target
120 mm
6 mm
23.5 mm
23.5 mm
5 mm
Reference Target
Reference Target
Gear Parameters for Correct Operation
Characteristic
Description
Min.
Typ.
Max.
Unit
Tooth Whole Depth (ht)
Depth of Target Valley
5
–
–
mm
Circular Valley Length (Pc – T)
Length of Target Valley
13
–
–
mm
Circular Tooth Length (T)
Length of Target Tooth
5
–
–
mm
Face Width (F)
Thickness or Width of Target Tooth
5
–
–
mm
Material: CRS 1018
Electromagnetic Capability (EMC) Performance
Please Contact Allegro MicroSystems for EMC Performance
Test Name
Reference Specification
ESD – Human Body Model
AEC-Q100-002
ESD – Machine Model
AEC-Q100-003
Conducted Transients
ISO 7637-1
Direct RF Injection
ISO 11452-7
Bulk Current Injection
ISO 11452-4
TEM Cell
ISO 11452-3
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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7
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Functional Description
Chopper-Stabilized Technique
The basic Hall element is a small sheet of semiconductor material
in which a constant bias current will flow when a constant voltage source is applied. The output will take the form of a voltage
measured across the width of the sheet and will have negligible
value in the absence of a magnetic field. When a magnetic field
with flux lines at right angles to the Hall current is applied, a
small signal voltage directly proportional to the strength of the
magnetic field will occur at the output terminals.
This signal voltage is proportionally small relative to the offset
produced at the input of the chip. This makes it very difficult
to process the signal and maintain an accurate, reliable output
over the specified temperature and voltage range. Therefore, it is
important to reduce any offset on the signal that could be amplified when the signal is processed.
Chopper stabilization is a unique approach used to minimize
input offset on the chip. This technique removes a key source of
output drift with temperature and stress, and produces a 3× reduction in offset over other conventional methods.
This offset reduction chopping technique is based on a signal
modulation-demodulation process. The undesired offset signal is
separated from the magnetically induced signal in the frequency
domain. The offset (and any low frequency noise) component of
the signal can be seen as signal corruption added after the signal
modulation process has taken place. Therefore, the DC offset is
not modulated and remains a low frequency component. Consequently, the signal demodulation process acts as a modulation
process for the offset causing the magnetically induced signal
to recover its original spectrum at baseband while the DC offset
becomes a high frequency signal. Then, using a low pass filter,
the signal passes while the modulated DC offset is suppressed.
The advantage of this approach is significant offset reduction,
which desensitizes the chip against the effects of temperature and
stress. The disadvantage is that this technique features a demodulator that uses a sample and hold block to store and recover the
signal. This sampling process can slightly degrade the signal-tonoise Ratio (SNR) by producing replicas of the noise spectrum at
the baseband. The degradation is a function of the ratio between
the white noise spectrum and the sampling frequency. The effect
of the degradation of the SNR is higher jitter, a.k.a. signal repeatability. In comparison to a continuous time device, the jitter spec
can be increased by a factor of five.
Regulator
Amplifier
Sample/
Hold
Clock
Hall Element
Figure 1. Concept of Chopper-Stabilization Algorithm
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115 Northeast Cutoff
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8
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Addressing / Programming Protocol
t d(1)
VPL
td(0)
0
Figure 2. Addressing Pulses: Positive Polarity
td(1)
Code -N
(Up to -127)
Code -3
Polarity
Key
VPP
VPH
VPL
0
Code N
(Up to 127)
V PH
Code N-1
Code N-2
Code 3
VPP
Code 2
Code 1
Addressing with positive polarity The magnetic operate point, BOP , is adjustable using 7 bits or 128 addresses. The
addresses are sequentially selected (figure 2) until the required
operate point is reached. The first address must be selected with
Code -(N-1)
Addressing with negative polarity The magnetic operate
point, BOP , is adjustable with negative polarity using 7 bits or
128 addresses. To invert the polarity it is necessary to first apply
a keying sequence (figure 3). The polarity key contains a VPP
pulse and at least 1 VPH pulse, but no more than 6 VPH pulses;
the key in figure 3 shows 2 VPH pulses. The addresses are then
sequentially selected until the required operate point is reached.
The first address must be selected with a high voltage pulse, VPP ,
while the remaining pulses should be VPH pulses.
Code -(N-2)
Addressing BOP is programmable in both the positive and
negative direction from its initial value. Addressing is used to
determine the desired code, while programming is used to lock
the code. A unique key is needed to blow fuses, while addressing
as described below does not allow for the device to be programmed accidentally.
Code -1
a high voltage pulse, VPP , while the remaining pulses should
be VPH pulses. Note that the difference between BOP and the
magnetic release point, BRP , the hysteresis, BHYS , is fixed for all
addresses.
Code -2
The ATS636LSE magnetic operate point, BOP , is programmed by
serially addressing the devices through the supply terminal (1).
After the correct operate point is determined, the device programming bits are selected and blown, then a lock bit is selected and
blown to prevent any further (accidental) programming.
td(0)
Figure 3. Addressing Pulses: Negative Polarity
PROGRAMMING PROTOCOL Valid over operating temperature range, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
4.5
5
5.5
V
Programming Protocol (TA = 25°C)
VPL
Programming
Voltage1,2
Programming Current
Pulse Width
Minimum voltage range during programming
VPH
8.5
–
15
V
VPP
25
–
27
V
IPP
Maximum supply current during programming
–
500
–
mA
td(0)
Off-time between bits
20
–
–
μs
td(1)
Enable, address, program, or lock bit on-time
20
–
–
μs
tdP
Program pulse on-time
100
300
–
μs
Pulse Rise Time
tr
VPL to VPH or VPP
–
–
11
μs
Pulse Fall Time
tf
VPH or VPP to VPL
–
–
5
μs
1Programming
voltages are measured at pin 1 (VCC) of the SIP. A minimum capacitance of 0.1 μF must be connected from VCC to GND of the SIP to
provide the current necessary to blow the fuse.
2Testing is the only method that guarantees successful programming.
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9
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
3 need to be programmed. A bit is programmed by addressing
the code and then applying a VPP pulse, the programming is not
reversible. An appropriate sequence for blowing code 5 is shown
in figure 5.
Program Enable To program the device, a keying sequence
is used to activate / enable the programming mode as shown in
figure 4. This program key sequence consisting of a VPP pulse, at
least seven VPH pulses, and a VPP pulse with no supply interruptions. The sequence is designed to prevent the device from being
programmed accidentally (e.g., as a result of noise on the supply
line).
Polarity Bit Programming If the desired switchpoint has
negative polarity, the polarity bit must be programmed. To do this
it is necessary to first apply the polarity key sequence before the
program key sequence (figure 6). Finally a VPP pulse of duration
tdP must be applied to program this bit, the programming is not
reversible. The polarity bit is for adjusting programming range
only and will not affect the output polarity.
Code Programming After the desired switchpoint code is
selected (0 through 127), each bit of the corresponding binary
address should be programmed individually, not at the same
time. For example, to program code 5 (binary 000101), bits 1 and
VPP
PROGRAM ENABLE
7 or More Pulses
(8 Pulses Shown)
V PH
VPL
0
td(1)
td(1)
td(0)
0
td(1)
td(1)
td(0)
tdP
Bit 1 Program
Bit 1 Address
Program Enable
000001
Code 1
Figure 5. Code Programming Example
Polarity
Key
VPH
VPL
Bit 3 Address
000100
Code 4
Program Enable
Polarity Bit
Program
VPP
Bit 3 Program
Figure 4. Program Enable Pulse Sequence
VPP
Program Enable
VPH
VPL
0
td(1)
td(1)
td(0)
tdP
Figure 6. Polarity Bit Programming
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10
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
Lock-Bit Programming After the desired code is programmed, the
lock bit (code 128), can be programmed (figure 7) to prevent further
programming of the device. Again, programming is not reversible.
See Allegro website at http://www.allegromicro.com for extensive
V PP
information on device programming as well as programming
products. Programming hardware is available for purchase and
programming software is available for free.
Lock Bit
Address
128 Pulses
Program Enable
V PH
Lock Bit
Program
ATS636LSE
VPL
0
t d(1)
t d(1)
t d(0)
tdP
Figure 7. Lock -Bit Programming Pulse Sequence
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115 Northeast Cutoff
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11
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Typical Application Circuit
For applications it is strongly recommended that an external
ceramic bypass capacitor in the range of 0.01 µF to 0.1 µF be
connected between the supply and ground of the device to reduce
both external noise and noise generated by the chopper-stabilization technique. (The diagram below shows a 0.1 µF bypass
capacitor.)
The series resistor RS in combination with the bypass capacitor
creates a filter for EMC pulses. The series resistor will have a
drop of approximately 800 mV, this must be considered for the
minimum VCC requirement of the ATS636LSE. The small capacitor on the output of the device improves the EMC performance
of the device. The pull-up resistor should be chosen to limit the
current through the output transistor; do not exceed the maximum
continuous output current of the device.
Note: This circuit cannot be used to program the device, as the
series resistance is too large, and a minimum capacitance of
0.1 µF must be connected from VCC to GND of the SIP to provide the current necessary to blow the fuse.
Extensive applications information on magnets and Halleffect ICs including chopper stabilization is available in
the Allegro Electronic Data Book CD, or at the website:
http://www.allegromicro.com.
RS
100 Ohm
5V
1
VCC
RL
1.2k Ohm
ATS636
VSupply
2
VOUT
0.1 µF
120 pF
GND
4
Typical Application:
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115 Northeast Cutoff
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12
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Power Derating – SE Package
Due to internal power consumption, the junction temperature
of the IC (junction temperature, TJ) is higher than the ambient
environment temperature, TA. To ensure that the device does not
operate above the maximum rated junction temperature use the
following calculations:
∆T = PD × RqJA
Where: PD = VCC × ICC
\∆T = VCC × ICC × RqJA
Power Dissipation versus Ambient Temperature
Where DT denotes the temperature rise resulting from the IC’s
power dissipation.
4500
3500
Typical TJ calculation:
TA = 25°C
VCC = 5 V
ICC(on) = 5.5 mA
PD = VCC × ICC = 5 V × 5.5 mA = 27.5 mW
DT = PD × RqJA = 27.5 mW × 77°C/W = 2.0°C
TJ = TA + DT = 25°C + 2.0°C = 27.0°C
Maximum Allowable Power Dissipation Calculation:
TJ = TA + DT
TJ(max) = 165°C, if TA = 150°C
Power Dissipation, PD (m W)
TJ = TA + DT
RqJA = 77°C/W
TJ(max) = 165°C
4000
3000
2-layer PCB
(RθJA = 77 ºC/W)
2500
2000
1500
1000
500
0
20
40
60
80
100
120
Temperature (°C)
140
160
180
then:
165 = 150 + DT
DT = 15°C
DT = PD × RqJA (RqJA = 77°C/W)
\ PD(max) = 15°C / 77°C/W = 195 mW at TA = 150°C
Maximum VCC for PD(max) = 111 mW at TA = 150°C
PD = VCC × ICC , ICC = 10 mA (max) at 150°C
VCC = PD / ICC = 195 mW / 5.5 mA = 35.4 V
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Package SE 4-Pin SIP
7.00±0.05
B
E
10.00±0.05
LLLLLLL
NNN
YYWW
3.3±0.1
F
Branded
Face
D
= Supplier emblem
L = Lot identifier
N = Last three numbers of device part number
Y = Last two digits of year of manufacture
W = Week of manufacture
1.3±0.1
A
6.23±0.10
4.9±0.1
1
2
3
Standard Branding Reference View
4
0.9±0.1
+0.06
0.38 –0.04
24.65±0.10
0.60±0.10
For Reference Only, not for tooling use (reference DWG-9001)
Dimensions in millimeters
A Dambar removal protrusion (16X)
11.60±0.10
B Metallic protrusion, electrically connected to pin 4 and substrate (both sides)
1.0 REF
C Thermoplastic Molded Lead Bar for alignment during shipment
D Branding scale and appearance at supplier discretion
2.00±0.10
E Active Area Depth, 0.43 mm
F Hall element (not to scale)
1.0 REF
A
1.60±0.10
1.27±0.10
C
0.71±0.10
0.71±0.10
5.50±0.10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Revision History
Revision
Revision Date
5
January 30, 2012
Update product availability
Description of Revision
6
December 1, 2015
Product status updated to discontinued
Copyright ©2005-2015, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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