Data Sheet ICL5101

ICL5101
Resonant controller IC with PFC for
LED driver
Dat as he et
Rev. 1.3, 2016-01-15
Po wer Ma nage m ent & M ul ti m ark et
ICL5101
Resonant controller IC with PFC for LED driver
Product highlights

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Resonant Controller and PFC within one IC
Supports universal input and wide output range
Low count of external components supporting
small form factors and improved reliability
All parameters set by simple resistors only
Supports outdoor use by extended junction
temperature range from -40 °C to +125 °C
Stable low load operation mode down to 0.1 %
of nominal power rating
Comprehensive set of protection to increase
system safety
Ultra-fast time to light < 200 ms
Power Factor Correction > 99 %, THD < 5 %
High efficiency up to 94 %
PG-DSO-16-23
Applications


PFC feature set



PFC in CrCM mode during nominal load and
DCM mode in low load condition down to 0.1 %
for operation without audible noise
Adjustable THD compensation of AC input
current even in DCM operation for lowest THD
Adjustable PFC current limitation
Description
The LED Resonant controller ICL5101
is designed to control resonant converter
topologies. The PFC stage operates in CrCM and
DCM mode, supporting low load conditions.
Integrated high and low side drivers assure a low
count of external components, enabling small form
factor designs.
ICL5101 parameters are adjusted by simple
resistors only, this being the ideal choice to ease
the design-in process. A comprehensive set of
protection features ensures that the LED driver
detects fault conditions, protecting both the LED
driver and the LED load. Figure 1shows a typical
application circuit of a 110 W constant voltage LED
driver.
Resonant half bridge feature set


OTP
n.a.
n.a.
ϑ R11
RFM
VCC
R8
GND
ICL5101
VR1

Fully integrated 650 V high-side driver
Self-adaptive dead time control of the integrated
half bridge driver 500 ns – 1.0 µs
Detection of capacitive operation, overload,
short circuitry, output overvoltage and external
over temperature protection to detecting hot
spots in system
Improved operation control in magnetic
saturation during start-up
Advanced error detection control
OVP


LED driver, e.g. commercial or residential
lighting systems > 50 W
Integrated electronic control gear for LED
luminaires
Figure 1 Typical Application
Product type
ICL5101
Datasheet
Package
PG-DSO-16-23
2
Rev. 1.3, 2016-01-15
ICL5101
Table of Contents
Table of Contents
Resonant controller IC with PFC for LED driver.................................................................................................2
1
1.1
1.2
1.3
1.4
Pin Configuration and Description...................................................................................................4
PG-DSO-16-23 Package......................................................................................................................4
PIN Configuration for PG-DSO-16-23 ..................................................................................................4
PIN Set-Up ...........................................................................................................................................5
PIN Functionality ..................................................................................................................................6
2
2.1
2.1.1
2.1.2
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
Functional Description ....................................................................................................................10
Introduction.........................................................................................................................................10
UVLO to Soft Start..............................................................................................................................13
Soft Start to Run Mode.......................................................................................................................14
Detection Stage..................................................................................................................................15
Detection of Over Temperature..........................................................................................................15
Detection of Output Overvoltage........................................................................................................15
Detection of Capacitive Mode Operation ...........................................................................................15
Surge Protection.................................................................................................................................16
Self-Adapting Dead Time during Gate Drive Activity between HS and LS ........................................17
Short Term Bus Under voltage...........................................................................................................18
Long-Term Bus Under voltage ...........................................................................................................19
PFC Preconverter...............................................................................................................................20
Operation Modes of the PFC Converter ............................................................................................20
PFC Bus Overvoltage and Open Loop...............................................................................................21
PFC Bus Voltage Levels 95 % and 75 %...........................................................................................21
PFC Structure of Mixed Signals .........................................................................................................22
THD Correction via Zero Crossing Detection Signal..........................................................................23
State Diagram ....................................................................................................................................26
Monitoring of Features versus Operating Mode.................................................................................26
Fault Condition – Flow Chart Fault F: Latch OFF after Single Restart ..............................................27
Fault Condition – Flow Chart Fault A: Auto Restart ...........................................................................28
Fault Condition – Flow Chart Fault U: BUS Voltage ..........................................................................29
Protection Matrix ................................................................................................................................30
3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.6
Electrical Characteristics ................................................................................................................31
Absolute Maximum Ratings ...............................................................................................................31
Operating Range ................................................................................................................................33
Characteristics Power Supply Section ...............................................................................................34
Characteristics of PFC Section ..........................................................................................................34
PFC Current Sense (PFCCS) ............................................................................................................34
PFC Zero Current Detection (PFCZCD) ............................................................................................35
PFC Voltage Sensing Bus (PFCVS) ..................................................................................................35
PFC PWM Generation .......................................................................................................................35
PFC Gate Drive (PFCGD) ..................................................................................................................36
Characteristics of Inverter Section .....................................................................................................36
Low-Side Current Sense (LSCS) .......................................................................................................36
Low-Side Gate Drive (LSGD).............................................................................................................37
Inverter Minimum Run Frequency (RFM) ..........................................................................................37
Overtemperature Protection (OTP) ....................................................................................................38
Overvoltage Protection (OVP)............................................................................................................38
High Side Gate Drive (HSGD)............................................................................................................39
Timer Section .....................................................................................................................................39
4
4.1
Application Example ........................................................................................................................40
Schematic...........................................................................................................................................40
5
Outline Dimensions .........................................................................................................................41
Datasheet
3
Rev. 1.3, 2016-01-15
ICL5101
Pin Configuration and Description
1
Pin Configuration and Description
The pin configuration is shown in Figure 2 and PIN Functionality
Table 1. Short pin functionality is described below in 1.2.
1.1
PG-DSO-16-23 Package
Figure 2 Pin Configuration
1.2
Symbol
PIN Configuration for PG-DSO-16-23
Pin
Function
LSGD
1
Low-side gate drive
LSCS
2
Low-side current sense signal
VCC
3
Chip supply voltage
GND
4
IC GND
PFCGD
5
PFC gate drive
PFCCS
6
PFC current sense signal
PFCZCD
7
PFC zero crossing detection
PFCVS
8
PFC voltage sensing
RFM
9
Set RUN frequency
n.a.
10
NOT APPLICABLE: Leave PIN OPEN
n.a.
11
NOT APPLICABLE: SET to GND
OVP
12
Overvoltage protection of secondary output
OTP
13
Over temperature protection
HSGND
14
High-side GND
HSVCC
HSGD
15
16
High-side supply voltage
High-side gate drive
Datasheet
4
Rev. 1.3, 2016-01-15
ICL5101
Pin Configuration and Description
1.3
PIN Set-Up
ICL5101
The PIN set-up of ICL5101 is shown in Figure 3.
Figure 3 PIN Set-Up
The schematic in Figure 3 shows a typical PIN set-up for a PFC / LLC converter
Datasheet
5
Rev. 1.3, 2016-01-15
ICL5101
Pin Configuration and Description
1.4
PIN Functionality
Table 1. Pin Definitions and Functions
Symbol
Pin
LSGD
1
LSCS
2
VCC
3
Datasheet
Function
Low-side gate drive
The gate of the low-side MOSFET in a RESONANT inverter topology is
controlled by this pin. There is an active L-level during UVLO (under voltage
lockout) and a limitation of the max H-level at 11.0 V during normal
operation. In order to turn on the MOSFET softly (with a reduced diDRAIN/dt),
the gate voltage rises typically within 245 ns from L-level to H-level. The fall
time of the gate voltage is less than 50 ns in order to turn off quickly. This
measure produces different switching speeds during turn-on and turn-off as it
is usually achieved with a diode parallel to a resistor in the gate drive loop. It
is recommended to use a resistor of typically 10 Ω between the drive pin and
gate in order to avoid oscillations and in order to shift the power dissipation
when discharging the gate capacitance into this resistor. The typical dead
time between the LSGD signal and HSGD signal is self-adapting between
500 ns and 1.0 µs.
Low-side current sense signal
This pin is directly connected to the shunt resistor, which is located between
the source terminal of the low-side MOSFET of the inverter and ground.
Internal clamping structures and filtering measures allow sensing of the
source current for the low side inverter MOSFET without additional filter
components.
There is a first threshold of 0.8 V. If this threshold is exceeded for longer
than 500 ns during run mode, an inverter overcurrent is detected, which
causes a latched shutdown of the IC. The saturation control is activated if the
sensed slope at the LSCS pin reaches typical values of 205 mV/µs ±
25 mV/µs and exceeds the 0.8 V threshold. The saturation regulator is now
continuously monitored by the LSCS pin during saturation control mode. In
saturation control mode, the regulator is designed to handle a choke
operation in saturation. If the sensed current signal exceeds a second
threshold of 1.6 V for longer than 500 ns before entering the run mode, the
IC changes over into a latched shutdown.
There are further thresholds active at this pin during run mode that detects
capacitive mode operation. A voltage level below -50 mV before the highside gate is on indicates faulty operation (operation below resonance).
A second threshold at 2.0 V senses even short over currents during turn-on
of the high-side MOSFET such as is typical for reverse recovery currents of
a diode. If one of these comparator thresholds indicates incorrect operating
conditions for longer than 620 µs in run mode, the IC turns off the gates and
changes to fault mode due to detected capacitive mode operation (non-zero
voltage switching).
The threshold of -50 mV is also used to adjust the dead time between turnoff and turn-on of the RESONANT drivers in a range of 500 ns to 1.0 µs
during all operating modes.
Chip supply voltage
This pin provides the power supply of the ground-related section of the IC.
There is a turn-on threshold at 14.0 V and a UVLO threshold at 10.6 V. The
upper supply voltage level is 17.5 V. There is an internal Zener diode
clamping VCC at 16.3 V (at IVCC = 2 mA typically). The maximum Zener
current is internally limited to 5 mA. An external Zener diode is required for
higher current levels. Current consumption during UVLO and during fault
mode is less than 170 µA. A ceramic capacitor close to the supply and GND
pin is required in order to act as a low-impedance power source for gate
drive and logic signal currents. In the event of a short interruption to the
mains supply, feed the start-up current (160 µA) from the bus voltage.
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Rev. 1.3, 2016-01-15
ICL5101
Pin Configuration and Description
Symbol
Pin
GND
4
PFCGD
5
PFCCS
6
PFCZCD
7
Datasheet
Function
IC GND
This pin is connected to ground and represents the ground level of the IC for
the supply voltage, gate drive and sense signals.
PFC gate drive
The gate of the MOSFET in the PFC preconverter designed in boost
topology is controlled by this pin. There is an active L-level during UVLO and
a limitation of the max H-level at 11.0 V during normal operation. In order to
turn on the MOSFET softly (with a reduced diDRAIN/dt), the gate drive voltage
rises within 245 ns from L-level to H-level. The fall time of the gate voltage is
less than 50 ns in order to turn off quickly. A resistor of typically 10 Ω is
recommended between the drive pin and gate in order to avoid oscillations
and in order to shift the power dissipation when discharging the gate
capacitance into this resistor. The PFC section of the IC controls a boost
converter as a PFC preconverter in discontinuous conduction mode (DCM).
Typically, the control starts with gate drive pulses with a fixed on-time of
typically 4.0 µs at VACIN = 230 V, increasing up to 24 µs and with an off-time
of 47 µs. As soon as sufficient zero current detector (ZCD) signals are
available, the operation mode changes from fixed frequency operation to
operation with variable frequency. The PFC works in critical conduction
mode operation (CrCM) when rated and/or medium load conditions are
present. That means triangular-shaped currents in the boost converter choke
without gaps and variable operating frequency. During low load (detected by
an internal compensator) we obtain operation with discontinuous conduction
mode (DCM) – that means triangular-shaped currents in the boost converter
choke with gaps when reaching the zero current level and variable operating
frequency in order to avoid steps in the consumed line current.
PFC current sense signal
The voltage drop across a shunt resistor located between the source of the
PFC MOSFET and GND is sensed with this pin. If the level exceeds a
threshold of 1.0 V for longer than 200 ns, the PFC gate drive is turned off as
long as the zero current detector (ZCD) enables a new cycle. If no ZCD
signal is available within 52 µs after turn-off of the PFC gate drive, a new
cycle is initiated from an internal start-up timer.
PFC zero crossing detection
This pin senses the point of time when the current through the boost inductor
becomes zero during the off-time of the PFC MOSFET in order to initiate a
new cycle.
The moment of interest appears when the voltage of the separate ZCD
winding changes from positive to negative level, which represents a voltage
of zero at the inductor windings and therefore the end of current flow from
the lower input voltage level to the higher output voltage level. There is a
threshold with hysteresis, 1.5 V for increasing level, 0.5 V for decreasing
level, which detects the change in inductor voltage. A resistor connected
between the ZCD winding and PIN 7 limits the sink and source current of the
sense pin when the voltage of the ZCD winding exceeds the internal
clamping levels (typically 6.3 V and -2.9 V @ 5 mA) of the IC. If the sensed
voltage level of the ZCD winding is not sufficient (e.g. during start-up), an
internal start-up timer will initiate a new cycle every 52 µs after turn-off of the
PFC gate drive. The source current out of this pin during the on-time of the
PFC-MOSFET indicates the voltage level of the AC supply voltage. During
low input voltage levels, the on-time of the PFC-MOSFET is enlarged in
order to minimize gaps in the line current during zero crossing of the line
voltage and improve the THD (Total Harmonic Distortion) of the line current.
Optimization of the THD is possible by trimming of the resistor between this
pin and the ZCD winding in combination with the inductance and used PFC
MOSFET.
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Rev. 1.3, 2016-01-15
ICL5101
Pin Configuration and Description
Symbol
Pin
Function
PFCVS
8
RFM
9
PFC voltage sensing
The intermediate circuit voltage (bus voltage) at the smoothing capacitor is
sensed by a resistive divider at this pin. The internal reference voltage for the
rated bus voltage is 2.5 V. There are further thresholds at 0.3125 V (12.5 %
of the rated bus voltage) for detection of open control loop and at 1.875 V
(75 % of the rated bus voltage) for detection of under voltage, and at 2.725 V
(109 % of the rated bus voltage) for detection of overvoltage. The
overvoltage threshold operates with a hysteresis of 100 mV (4 % of the rated
bus voltage). The bus voltage is sensed at 95 % (2.375 V) for detection of a
successful start-up. It is recommended to use a small capacitor between this
pin and GND as a spike suppression filter.
In run mode, PFC overvoltage stops the PFC gate drive within 5 µs. As soon
as the bus voltage is less than 105 % of the rated level, the gate drives are
enabled again. If the overvoltage lasts for longer than 625 ms, an inverter
overvoltage is detected and turns off the inverter gate drives also. This
causes a power-down and a power-up when VBUS < 109 %.
A bus under- (VBUS > 75 %) or inverter overvoltage during run mode is
handled as FAULT BUS. In this situation the IC changes to power-down
mode and generates a delay of 100 ms with an internal timer. Then start-up
conditions are checked and if valid, a further start-up is initiated. If start-up
conditions are not valid, a further delay of 100 ms is generated.
This procedure is repeated a maximum of seven times. If a start-up is
successful within these seven cycles, the situation is interpreted as a short
interruption of the mains supply.
Set minimum RUN frequency
A resistor from this pin to ground sets the operating frequency of the inverter
during run mode. The typical run frequency range is 20 kHz to 120 kHz @ 40°C and 130kHz @ - 25°C. The set resistor R_RFM can be calculated
based on the run frequency fRFM according to the equation:
RRFM 
5  10 8 Hz
f RUN
n.a.
10
NOT Applicable: Leave PIN Open
n.a.
11
OVP
12
OTP
13
NOT Applicable: SET to IC GND as short as possible
Over voltage protection of OUTPUT Voltage
In order to prevent overvoltage at the output stage – in the case of a floating
LED –overvoltage protection at pin 12 can be activated. Use a resistor and a
ceramic capacitor connected to the auxiliary winding in order to sense the
voltage level at the auxiliary winding. During run mode, the auxiliary winding
is monitored by a sensing current proportional to the auxiliary voltage. If the
peak-to-peak voltage at this pin exceeds a threshold of 210 µApp for longer
than 620 µs, overvoltage is detected. This function can be disabled by
setting pin 12 to GND.
Over temperature protection
In order to prevent over temperature of the system, activate the over
temperature protection at the OTP pin. Use a temperature-dependent
resistor and a ceramic capacitor connected to GND for activation. There is a
threshold of 3.2 V at the OTP pin during active run mode. If the voltage rises
above this threshold for longer than 620 µs, the IC detects over temperature
and changes to the latched fault mode. The latch mode is ended
automatically by power-up or UVLO. This function can be disabled by setting
pin 13 to GND.
Datasheet
8
Rev. 1.3, 2016-01-15
ICL5101
Pin Configuration and Description
Symbol
Pin
Function
HSGND
14
HSVCC
15
HSGD
16
High-side GND
This pin is connected to the source terminal of the high-side MOSFET, which
is also the node of high-side and low-side MOSFET. This pin represents the
floating ground level of the high-side driver and the high-side supply.
High-side supply voltage
This pin provides the power supply of the high-side ground-related section of
the IC. An external capacitor between pins 14 and 15 acts like a floating
battery, which has to be recharged cycle by cycle via a high-voltage diode
from the low-side supply voltage during the on-time of the low-side MOSFET.
A UVLO threshold with hysteresis enables the high-side section at 10.4 V
and disables it at 8.6 V.
High-side gate drive
The gate of the high-side MOSFET in an RESONANT inverter topology is
controlled by this pin. There is an active L-level during UVLO and a limitation
of the max H-level at 11.0 V during normal operation. The switching
characteristics are the same as described for LSGD (pin 1). It is
recommended to use a resistor of about 10 Ω between the drive pin and gate
in order to avoid oscillations and in order to shift the power dissipation when
discharging the gate capacitance into this resistor. The dead time between
the LSGD signal and HSGD signal is self-adapting between 500 ns and
1.0 µs (typically).
Datasheet
9
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2
Functional Description
The functional description provides an overview of the integrated functions, features and their relationships. The
parameters and equations provided are based on typical values at TA = 25 °C. The corresponding minimum and
maximum values are shown in the Electrical Characteristics.
2.1
Introduction
The ICL5101 is a high-performance mixed-signal controller for LED and SMPS applications. The IC is designed
for a Power Factor Correction (PFC) close to 1, low THD below 5 %, a maximum efficiency up to 94 % PLUS
and a minimal design-in phase due to use resistors only for setting up the IC. The IC is designed to working in
ultra-wide and narrow range designs. Furthermore, all parameters are valid in an extended temperature range
from –40 °C up to 125 °C – especially frequency and timing. The controller utilizes a variety of protection
features, including saturation control during start-up of the resonant converter, external adjustable over
temperature, along with open and short load conditions. The ICL5101 includes also a surge protection feature,
provides together with the CoolMOS technology a maximum protection against surges and safe components on
board. Nevertheless CoolMOS P6 increases the efficiency by a 30% reduced gate charge and the internal gate
resistor improves an easy use. For the half bridge is also a 500V CE CoolMOS recommended.
Datasheet
10
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
Operating FLOW Chart ICL5101
Vcc < 10.6V
UVLO
Vcc < 10.6V
Icc < 130µA
Vcc > 10.6V
Monitoring
Vcc > 10.6V
Icc < 160µA
Vcc < Vccon(14.0V)
OTP Detection
Power-up
VBUS < 12,5%
or VBUS > 105%
Gate Drives off
Vcc > 14.0V
Icc approx 6.0mA
See
Timing and Handling of
Fault Conditions
after 130µs
& VBUS > 12,5%
& VBUS< 105%
Start-up
Inverter Gates ON
PFC Gate ON
17.5V> Vcc >10.6V
f_Inv = f_FIXED
f = 135kHz
(fixed)
Frequency:
f = 135kHz (fix)
t_Start-uptyp ~ 12ms
VBUS > 95%
within 80ms
Softstart
f = 135kHz
(fixed)
See
Protection
Functions
Fault
17.5V> Vcc >10.6V
Icc < 170µA
Gate Drives off
17.5V> Vcc >10.6V
f_FIXED => f_RUN
Frequency DECREASE:
f = 135kHz to f_RUN (SET)
t_SS = 11mstyp (digital)
Saturation
Control
f = f_RUN
(SET)
Timeout 237ms
17.5V> Vcc >10.6V
f = f_RUN
t_SaturationControltyp = 45ms
Extended Sat
Control
17,5V> Vcc >10.6V
f = f_RUN
NO Impact on Time to Light
t_Blanking = 625ms
after
t_Blanking
Run
17.5V> Vcc >10.6V
f = f_RUN
Complete Monitoring
Figure 4 Operating Flowchart for LED Applications
Datasheet
11
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
Start-Up
The device is powered through the VCC pin. All device supply voltages are internally generated from VCC
voltage. Typical Start-Up Procedure below Figure 5 shows a typical start-up procedure of the device. The
following subsections describe the phases in detail.
Frequency /
Output Voltage
fStartUp_FIX
135 kHz
VOUT = 100%
VOUT = 90%
fRUN_SET
45 kHz
60ms
35ms
10-80ms
11ms
625ms
40 - 237ms
Mode /
Time
0 kHz
VPFCVS
VPFCVS
100 %
VDCIN
Mode /
Time
VLSGD / VCC
VCC = 17.5 V
VCC
VCC = 14.1 V
VCC = 10.6 V
Low Side Gate Drive
Mode /
Time
VCC = 0 V
UVLO
Monitoring
Saturation Control
Run Mode
Figure 5 Typical Start-Up Procedure
Datasheet
12
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.1.1
UVLO to Soft Start
This section describes the operating flow from UVLO to soft start in detail – Start-Up Procedure from UVLO to
Soft Start Figure 6. The control of the LED ballast is able to start the operation in less than 100 ms (Time to
Light IC is in active mode). This is achieved by the low current consumption during UVLO (IVCC = 130 µA) and
start-up hysteresis (IVCC = 160 µA – defines the start-up resistor) phases. The chip supply stage of the IC is
protected against overvoltage via an internal Zener clamping network, which clamps the voltage at 16.3 V and
allows a current of 2.5 mA. For clamping currents above 2.5 mA, an external Zener diode from VCC to GND is
required.
Frequency /
VOUT
fStartUp
135 kHz
VOUT = 90%
VPFCVS
100 %
95 %
VPFCVS
30 %
VCC
17.5 V
16.0 V
14.0 V
10.6 V
UVLO
Monitoring
Start Up Soft Start
IVCC
< 6.0 mA + IGate
< 160 µA
130 µA
VOTP
1.6 V
- 21.3 µA
IOTP
IOVP
< 210µApp
> 18 µA
Figure 6 Start-Up Procedure from UVLO to Soft Start
If VCC exceeds the 10.6 V level and stays below 14.0 V (start-up hysteresis), the IC checks whether the pcb
temperature is experiencing over temperature or an output overvoltage is present. Over temperature is checked
from a source current of typically IOTP3 = - 21.3 µA out of pin 13 OTP (IOTP). This current produces a voltage drop
of VOTP < 1.6 V (temperature is ok). Over temperature is detected if the voltage at the OTP pin exceeds the VOTP
> 1.6V threshold (VOTP).
The output overvoltage is checked by a current of typically IOVP > 12 µA via resistors R12 into the OVP pin 12.
Output overvoltage is detected if there is no sink current into the OVP pin. This causes a higher source current
out of the OTP pin (typically 42.6 µA / 35.4 µA) in order to exceed VOTP > 1.6 V. In the case of over temperature
or overvoltage, the IC keeps monitoring until there is an adequate voltage from the OTP or OVP pin.
Datasheet
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Rev. 1.3, 2016-01-15
ICL5101
Functional Description
When VCC exceeds the 14.0 V threshold – by the end of the start-up hysteresis – the IC waits for 80 µs and
senses the bus voltage. When the rated bus voltage is in the corridor of 12.5 % < VBUSrated < 105 %, the IC
powers up. The IC initiates an UVLO when the chip supply voltage is below VCC < 10.6 V. As soon as the
condition of a power-up is fulfilled, the IC starts the inverter gate operation with an internal fixed start-up
frequency of 135 kHz. The PFC gate drive starts with a delay of app. 300 µs. Then the bus voltage will be
checked for a rated level above 95 % for duration of 80 ms. Now, the IC enters the soft start phase and shifts
the frequency from the internal fixed start-up frequency of 135 kHz down to the set RUN frequency.
2.1.2
Soft Start to Run Mode
This section describes the operating flow from soft start to run mode in detail. After the soft start phase is
finished, the saturation control phase is entered.
Figure 7 Start-Up Procedure from Soft Start to Run Mode
During saturation control ( Start-Up Procedure from Soft Start to Run ModeFigure 7), the operating frequency of
the inverter is shifted downward in ttyp = 40 ms to the run frequency set by a resistor at the pin RFM to GND.
The saturation control is activated if the sensed slope at the LSCS pin reaches typically 205 mV/µs ± 25 mV/µs
and exceeds the 0.8 V threshold. This stops the frequency decreasing and signifies waiting for an adequate
output voltage. The saturation control is now continuously monitored by the LSCS pin. The maximum duration of
the saturation control procedure is limited to 237 ms. If there is still saturation within this time frame, the
saturation control is disabled and the IC changes over to the latched fault mode. Furthermore, in order to reduce
the choke size, the saturation control is designed to operate with a choke in magnetic saturation of the
RESONANT during start-up. For an operation in magnetic saturation during saturation control mode, the voltage
at the shunt at the LSCS pin 2 has to be VLSCS = 0.80 V when the output voltage is reached. If the saturation
control mode is successfully passed, the IC enters the extended saturation mode The extended saturation mode
is a safety mode used in order to prevent a malfunction of the IC due to an instable system. After 625 ms, the IC
changes to the run mode (Figure 7). The run mode monitors the complete system regarding bus over- and
under voltage, open loop, overcurrent of PFC and/or inverter, output overvoltage, over temperature and
capacitive load operation.
Datasheet
14
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.2
Detection Stage
2.2.1
Detection of Over Temperature
Force a shut-off of the IC due to over temperature by using a PTC to GND on pin 13. In the event of an over
temperature of the system (in run mode), the current out of the OTP pin 13 IOTP3 = - 21.3 µA charges up a
capacitor. If the voltage at the OTP pin 13 exceeds the VOTP3 = 3.2V threshold, the controller detects an over
temperature and stops the gate drives after a delay of t = 620µs set by an internal timer. The system restarts
automatically. The possibility of a latch of the system is happen when it cools down and heat up within 200ms.
When system is too hot before startup, the system prevents a power up.
2.2.2
Detection of Output Overvoltage
Overvoltage is detected by measuring the peak levels of the voltage at the AUX winding via an AC current fed
into the OVP pin 12. If the sensed AC current exceeds 210 µAPP for longer than 620 µs, the status of
overvoltage is detected. The OVP fault results in a latched power-down mode (after trying a single restart). The
controller continuously monitors the status until the overvoltage status changes.
2.2.3
Detection of Capacitive Mode Operation
RESONANT converter designs should avoid working in capacitive mode operation – not even under abnormal
conditions. ICL5101 provides capacitive mode operation detection and latch-off of the system after a single
restart for error verification. Resonant converters work in capacitive mode when their switching frequency falls
below a critical value. This depends on the loading condition and the input-to-output ratio. They are especially
prone to enter capacitive mode when the input voltage is lower than the minimum specified and/or the output is
overloaded or shorted. In order to prevent a malfunction in the area of capacitive load during run mode due to
certain deviations from the normal load, the IC senses only via the LSCS pin 2.
Capacitive load operation is detected if the voltage at the LSCS pin drops below a first threshold of VLSCSCap1 = –
50 mV directly before the high-side MOSFET is turned on or exceeds a second threshold of VLSCSCap2 = 2.0 V
during ON switching of the high-side MOSFET (Figure 8). If this overcurrent is present for longer than 620 µs,
the IC results a latched power-down mode after trying a single restart.
Figure 8 Capacitive Mode Operation
Datasheet
15
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.2.4
Surge Protection
Description SURGE Protection
In case of a surge event, the voltage at the BUS capacitors C5 & C8 rises up, the driver stages of the ICL5101
are shut off when VLSCS > 0.8V and VBUS > 109% for longer than 500ns. After the surge the controller restarts
automatically when VBUS drops below 109% of the rated voltage. This feature allows driving 500V MOSFETs at
the half bridge stage when adequate EMI and DC LINK networking is present. For an effective protection use
TM
CooMOS technology.
SURGE Detection
If the bus voltage exceeds:
VBUS > 109%
and the voltage at the low side current sense pin 2 exceeds:
VLSCS > 0.8V
for longer than
t = 500ns
SURGE Protection
All Gate Drives OFF
Auto Restart:
VBUS < 109%
Measurement
Surge Event of 1.7kV WITHOUT Varistor VR1
Figure 9: SURGE 1.7kV / FULL Load / Detail
L  N / Phase: 90°
Ch 1 dark blue: VLSCS LS Current Sense to IC GND
Ch 2 blue: VBUS to Power GND
Ch 3 magenta: VLSDS LS Drain to Power GND
Ch 4 green: VPFCDS PFC Drain to Power GND
Figure 10: SURGE 1.7kV / FULL Load / Auto Restart
L  N / Phase: 90°
Ch 1 dark blue: VLSCS LS Current Sense to IC GND
Ch 2 blue: VBUS to Power GND
Ch 3 magenta: VLSDS LS Drain to Power GND
Ch 4 green: VPFCDS PFC Drain to Power GND
Surge Event: VBUS > 109% & VLSCS > 800mV
Auto Restart:VBUS < 109%
Datasheet
16
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.2.5
Self-Adapting Dead Time during Gate Drive Activity between HS and LS
The dead time between the turn OFF and turn ON of the RESONANT drivers is self-adapting and is detected by
means of switch-off of the high-side MOSFET and the –50 mV threshold of the LSCS voltage (see Figure 11).
The typical range of the dead time adjustment is 500 ns up to 1.0 µs during all operating modes. The start of the
dead time measurement is the OFF switching of the high-side MOSFET. The dead time measurement finishes
when VLSCS drops below -50 mV for longer than typically 300 ns (internal fixed propagation delay). This time will
be stored, the low-side gate driver switches ON. The high-side gate driver turns ON again after OFF switching
of the low-side switch and the stored dead time (see copied dead time in Figure 11).
Normal Operation in RUN Mode
VDSLS
VLSCS
VLSCS = -50mV
END of Dead Time
Measurement
Gate LS
Gate HS
Dead Time
START of Dead Time
Measurement
Dead Time
300 ns
Propagation Delay
Stored Dead Time
Copied Dead Time
Figure 11 Dead Time ON and OFF of the Inverter Gate Drivers
Datasheet
17
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.2.6
Short Term Bus Under voltage
Short-term PFC bus under voltage (Figure 12) is detected if the duration of the under voltage does not exceed
800 ms (timer remains below t < 800 ms). In this case, the PFC and inverter drivers are immediately switched
off and the controller continuously monitors the status of the bus voltage in a latched power-down mode (ICC <
170 µA). If the signal at the OVP PIN exceeds 18 µA and the rated bus voltage is above 12.5 % while the timer
is below t < 800 ms, the controller restarts from power-up. The timer resets to 0 when entering the run mode.
Saturation Control
Figure 12 Bus Under voltage – Short
Datasheet
18
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.2.7
Long-Term Bus Under voltage
If the bus under voltage exceeds t > 800 ms (Figure 13) the controller forces an under voltage lock-out (UVLO).
The chip supply voltage drops below VCC = 10.6 V and the chip supply current is below ICC < 130 µA. When the
Vcc voltage exceeds the 10.6 V threshold again, the IC current consumption is below ICC < 160 µA. In this case,
the controller resets the timer and restarts with the full start-up procedure, including monitoring, power-up, startup, soft start, saturation control, extended saturation mode and run mode.
Bus Voltage Drop for t > 800 ms
Restart with full Start Procedure
VBUSRated
Interrupt for t > 800 ms
95%
UVLO
Monitoring
Power UP
Start Up
Soft Start
75%
RUN Mode
Power Down Mode
Saturation Extended Saturation Run Mode
Control
Control
VCC
16V
UVLO @ 10.6V
ICC
< 6 mA + IGate
<160 µA
< 160 µA
< 6 mA + IGate
Timer
t = 800ms
IOUT
Figure 13 Bus Under voltage – Long
Datasheet
19
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.3
PFC Preconverter
2.3.1
Operation Modes of the PFC Converter
The digitally controlled PFC pre-converter starts with an internally fixed ON time of typically tON = 4.0µs and
variable frequency. The ON time is increased every 280 µs (typical) up to a maximum ON time of 24 µs. The
control switches quite immediately from discontinuous conduction mode (DCM) to critical conduction mode
(CrCM) as soon as a sufficient ZCD signal becomes available. The frequency range in CrCM is 22 kHz up to
500 kHz, depending on the power (Figure 14) with a variation in the ON time of 24 µs > tON > 0.5µs.
Discontinuous Conduction Mode (DCM) <> Critical Condution Mode (CritCM)
100,00
100,00
10,00
PFC - ON Time [µs]
PFC Frequency [kHz] 50% Duty Cycle
1000,00
10,00
1,00
1,00
0,10
0,01
0,01
0,10
0,10
1,00
10,00
100,00
Normalized Output Power [% ]
Frequency DCM
Frequency CritCM
Ton DCM
Ton CritCM
Figure 14 PFC DCM / CrCM vs Power and ON Time
1
For lower loads (POUTNorm < 8 % of the normalized load ) the controller operates in discontinuous conduction
mode (DCM) with an ON time of 4.0 µs and increasing OFF time. The frequency during DCM is variable in a
range from 144 kHz down to typically 22 kHz @ 0.1 % load. With this control method, the PFC converter
enables stable operation from a 100 % load down to 0.1 %. Figure 14 shows the ON time range in DCM and
CrCM (Critical Conduction Mode) operation. In the overlapping area of CrCM and DCM there is a hysteresis of
the ON time, which causes a negligible frequency change.
1
Normalized Power @ Low Line Input Voltage and maximum Lload
Datasheet
20
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.3.2
PFC Bus Overvoltage and Open Loop
The bus voltage loop control is completely integrated (Figure 15) and provided by an 8-bit sigma-delta A/D
converter with a typical sampling rate of 280 µs and a resolution of 4 mV/bit. After leaving monitoring, the IC
starts to power up (VCC > 14.0 V). After power-up, the IC senses the bus voltage below 12.5 % (open loop) or
above 105 % (bus overvoltage) for 80 µs – 130 µs. In the case of bus overvoltage (VBUSrated > 109 %) or open
loop (VBUSrated < 12.5 %), the IC shuts off the gate drives of the PFC within 5 µs or 1 µs respectively. In this case,
the PFC restarts automatically when the bus voltage is within the corridor (12.5 % < VBUSrated < 105 %) again. If
the bus voltage is valid after the 130 µs, the bus voltage sensing is set to 12.5 % < VBUSrated < 109 %. If these
thresholds are departed from for longer than 1 µs (open loop) or 5 µs (overvoltage), the PFC gate drive stops
working until the voltage drops below 105 % or exceeds the 12.5 % level. If the bus overvoltage (> 109 %) lasts
for longer than 625 ms in run mode, the inverter gates also shut off and a power-down with complete restart is
attempted (Figure 15).
Figure 15 PFC Bus Voltage Operating and Error Levels
2.3.3
PFC Bus Voltage Levels 95 % and 75 %
When the rated bus voltage is in the corridor of 12.5 % < VBUSrated < 109 %, the IC will check whether the bus
voltage exceeds the 95 % threshold (Figure 15) within 80 ms before entering soft start phase. Another threshold
is activated when the IC enters the run mode. If the rated bus voltage drops below 75 % for longer than 84 µs, a
power-down with a complete restart is attempted if a counter exceeds 800 ms. In the case of short-term bus
under voltage (the bus voltage reaches its working level in run mode before exceeding typically 800 ms - min.
500 ms) the IC skips phases and starts up directly in saturation control. The internal reference level of the bus
voltage sense VPFCVS is 2.5 V (100 % of the rated bus voltage) with a high accuracy. Surge protection is
activated in the case of a rated bus voltage of VBUS > 109 % and a low-side current sense voltage of VLSCS >
1.6 V in extended saturation mode or of VLSCS > 0.8 V in run mode for longer than 500 ns in RUN Mode.
Datasheet
21
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.3.4
PFC Structure of Mixed Signals
A digital NOTCH filter eliminates the input voltage ripple independent of the mains frequency. A subsequent
error amplifier with PI characteristic ensures stable operation of the PFC pre-converter (Figure 16)
Figure 16 PFC Mixed Signal Structure
The zero current detection (ZCD) is sensed by the PFC ZCD. Indication of finished current flow during
demagnetization is required in CrCM and in DCM as well. The input is equipped with a special filtering, including
an extended saturation of typically 500 ns and a large hysteresis of typically VPFCZCD between 0.5 V and 1.5 V.
Datasheet
22
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.3.5
THD Correction via Zero Crossing Detection Signal
An additional feature is the THD correction (Figure 17). In order to optimize the THD (especially in the zones A
shown in Figure 17, ZCD @ AC input voltage), there is a possibility to extend the pulse width of the gate signal
(blue part of the PFC gate signal) via the variable PFC ZCD resistor from the ZCD pin to the PFC choke in
addition to the gate signal controlled by the VPFCVS signal (gray part of the PFC gate signal).
ZCD @ AC Input Voltage
ZCD @ DC Input Voltage
Rectified
AC Input Voltage
A
B
DC Input Voltage
A
0
Voltage at
ZCD-Winding
0
PFC Gate Drive
Voltage
0
PFC gate signal (gray) controlled by the VPFCVS
PFC gate signal (blue) controlled by the ZCD
Figure 17 THD Improvement – Automatic Pulse Width Extension
In the case of DC input voltage, the pulse width gate signal is fixed as a combination of the gate signal
controlled by the VPFCVS pin (gray) and the additional pulse width signal controlled by the ZCD pin (blue) ZCD @
DC input voltage.
The PFC current limitation at pin PFCCS interrupts the ON time of the PFC MOSFET if the voltage drop at the
PFC shunt resistors exceeds VPFCCS = 1.0 V. This interrupt will restart after the next sufficient signal from ZCD
becomes available (auto restart). The first value of the resistor can be calculated as the ratio of the PFC mains
choke and ZCD winding times the bus voltage to a current of typically 1.5 mA (Equation 1). An adjustment of the
ZCD resistor causes an optimized THD.
RZCD
N ZCD
* V BUS
N PFC

1.5mA
Equation 1: RZCD – A Good Practical Value
Datasheet
23
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
THD Adujstment
OTP
n.a.
ϑ R11
n.a.
RFM
VCC
R8
GND
ICL5101
VR1
OVP
Introduction:
In order to provide an excellent THD result, the THD of the ICL5101 is adjustable. Especially at high line input
voltage and low load condition, the THD is a critical value. It doesn´t matter in which condition:
- Line input voltage
- Stable load
- Load variation
the ICL5101 is providing best results for all cases – only by trimming a resistor R3 see Figure 18.
ICL5101
Figure 18 Principle Schematic ICL5101
Figure 19 PIN SetUP ICL5101
Datasheet
24
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
How to do:
To improve the THD the resistor – see R3 Figure 18 or red signed resistor in Figure 19 – at ZCD PIN 7 can be
trimmed to an optimal value (several k-ohm ~ 20 up to 100k) in order to reach best THD results.
Step one is to define the inductivity of the PFC choke and the MOSFET. After fixing PFC choke and transistor,
two scenarios are happen:
1/ operation in stable load condition e.g. lamp ON / OFF
SET nominal load condition and vary the value of the resistor until you get the best THD results. Outcome sees
Figure 20 black curve
2/ operation with load variation e.g. dimming of an LED
Choose a resistor and vary the load. Change value up or down in order to get your best result over the whole
load range – outcome sees Figure 20 red curve.
Mechanism:
The controller operates in two modes:
- Critical Conduction Mode (CrCM) in a wide load range
- Wait Cycle Mode (WCM – a kind of DCM) for low load
Switch from CrCM into WCM):
The ICL5101 has an integrated logic which can be regulated via the resistor at the ZCD PIN 7 in varying the
value of the resistor.
Limit:
The digital logic of the controller is limited. At high line input voltages, the controller reduces the ON time of the
PFC gate driver. If the minimum ON time is reached – physically given by the internal digital stage – the
controller switches over from the critical conduction mode CrCM into the wait cycle mode WCM. This switch
over can be seen in the THD measurement shown in Figure 20 black curve. Depending on the load (stable or
variable) the optimum configuration can be found as shown in Figure 20 red curve. This effect can be prevented
by trimming the resistor at the ZCD PIN 7 – lower the resistance leads to a smother cross over from CrCM into
WCM (red curve) but increases slightly the THD.
THD vs. Load @ VACIN = 230 using diff. R ZCD 110W Board
45
40
35
THD [%]
30
RZCD = 51kΩ ideal for stable Load Conditions
25
Mode change from CritCM into WCM
20
Limit starting THD is higher
15
10
5
RZCD = 39kΩ ideal for vary Load Conditions
Smooth mode change
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
Load[%]
THD [%] 39kΩ
THD [%] 51kΩ
Figure 20 Mode switching in stable or vary load condition
Datasheet
25
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.4
State Diagram
2.4.1
Monitoring of Features versus Operating Mode
Figure 21 Monitoring of Features versus Operation Mode
Datasheet
26
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.4.2
Fault Condition – Flow Chart Fault F: Latch OFF after Single Restart
Fault A
Start-up
Auto Restart
Inverter Gates ON
PFC Gate ON
17.5V> Vcc >10.6V
f_Inv = f_FIXED
Surge
Time OUT Start Up
(VBUS < 95%
for t > 80 ms)
N
t > 80ms?
from Power-Up
INVERTER and PFC Gate OFF
Only at Inverter Over Current PFC Gate OFF
appr. 150µs Delayed
Power down Icc < 160µA
N
VBUS > 95%?
Y
Y
Fault A
Timeout 80ms
Start-up
End
Start-up
Wait 200ms
Delay Timer 1
Fault Counter
<2
Y
N
Y
Wait for
VOTP > 1.3V
VOTP < 3.2V
VOTP < 1.3V
VOTP > 3.2V
N
VOTP > 1.3V
VOTP < 3.2V
wait 100ms
Vcc > 14.0V?
N
Reset
Flag Skip
Start Up Procedure
Y
Vcc < 10.6V?
N
Y
UVLO
Power-up
Reset all Latches
& Counters
Figure 22 Fault Condition F – Latch OFF after Single Restart
Datasheet
27
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.4.3
Fault Condition – Flow Chart Fault A: Auto Restart
Fault A
Start-up
Auto Restart
Inverter Gates ON
PFC Gate ON
17.5V> Vcc >10.6V
f_Inv = f_FIXED
Surge
Time OUT Start Up
(VBUS < 95%
for t > 80 ms)
N
t > 80ms?
from Power-Up
INVERTER and PFC Gate OFF
Only at Inverter Over Current PFC Gate OFF
appr. 150µs Delayed
Power down Icc < 160µA
N
VBUS > 95%?
Y
Y
Fault A
Timeout 80ms
Start-up
End
Start-up
Wait 200ms
Delay Timer 1
Fault Counter
<2
Y
N
N
Wait for
VOTP < 1.3V
VOTP < 1.3V
Y
VOTP < 1.3V
wait min 100ms
Vcc > 14.0V?
N
Reset
Flag Skip
Start Up Procedure
Y
Vcc < 10.6V?
N
Y
UVLO
Power-up
Reset all Latches
& Counters
Figure 23 Fault Condition A – Auto Restart
Datasheet
28
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
2.4.4
Fault Condition – Flow Chart Fault U: BUS Voltage
Figure 24 Fault Condition U – BUS Voltage
Datasheet
29
Rev. 1.3, 2016-01-15
ICL5101
Functional Description
Protection Matrix
U 625ms
Under voltage
U 84µs
Consequence
Run mode
Open loop
detection
Open loop
detection
Shutdown option
Ext. Sat. Con.
625ms
Bus voltage < 12.5% of rated
level 10µs after power up
Bus voltage < 12.5%
of rated level
Bus voltage < 12.5%
of rated level
Bus voltage < 75%
of rated level
add. shut down delay 120µs
Bus voltage < 95% of rated
level during start-up
Bus voltage > 105% of rated
level 10µs after power up
Bus voltage > 109% of rated
level in active operation
Bus voltage > 109% of rated
level in active operation
peak level of output voltage
at Pin OVP above threshold
Capacitive Load
operation below resonance
Voltage at PFCCS pin > 1.0V
Saturation control
40 ms typ.
Below start-up
S 1µs
threshold
Below UVLO
S 5µs
threshold
Overtemperature S 100µs
Power-up 130µs
Start-up until
VBUS > 95%
Softstart
11ms
Operating Mode Detection is
active
Minimum
duration
of effect
Supply voltage Vcc < 14.1V
before power up
Supply voltage Vcc < 10.6V
after power up
Voltage at OTP pin > 1.6V
before power up
Voltage at OTP pin > 3.2V
Type of fault
Characteristics of Fault
Name of fault
Description of Fault
Monitoring
2.4.5
Prevents power up
X
X X
X
X
X
X
X
X
Overtemperature F 620µs
X
S 1µs
X
X
X
X
X
X
X
Timeout max
start-up time
PFC overvoltage
A 80ms
S 5µs
PFC overvoltage
N 5µs
Power down, latched
fault mode, 1 restart
Keep gate drives off, restart after Vcc hysteresis
X
N 1µs
Power down,
Reset failure latch
Prevents power up
X
Stops PFC FET until
VBUS > 12.5%
Power down, restart
when VBUS> 12.5%
Power down, 100ms
delay, restart directly
with saturation control
Power down, 200ms
delay, restart
Keep gate drives off, restart after Vcc hysteresis
X
Stops PFC FET until
VBUS< 105%
Inverter
U 625ms
Power down, restart
X
overvoltage
when VBUS<105%
Output
F 620µs
Power down, latched
X
overvoltage
fault mode, 1 restart
Overload
F 620µs
Power down, latched
X
fault mode, 1 restart
PFC
N 200ns
Stops on-time of PFC
X
X
X
X
X
overcurrent
FET immediately
Voltage at LSCS pin > 0.8V
Inverter
N 200ns
Activates
X
current lim
saturation control
Voltage at LSCS pin > 1.2V
Saturation
F 237ms
Power down, latched
X
& 205mV/µs Slope in 0.8V
Time OUT
fault mode, 1 restart
Voltage at LSCS pin > 0.8V
Ext. Sat. Time
F 625ms
Power down, latched
X
& 205mV/µs Slope
OUT
fault mode, 1 restart
Voltage at LSCS pin > 0.8V
Inverter
F 500ns
Power down, latched
X
overcurrent
fault mode, 1 restart
Voltage at LSCS pin > 1.6V
Inverter
F 500ns
Power down, latched
X
X
X
X
overcurrent
fault mode, 1 restart
Voltage at LSCS pin > 0.8V
Inverter
A 500ns
Power down, restart
X
X
& VBUS > 109% (Surge)
overcurrent
when VBUS<109%
After jump into latched fault mode F wait
200ms A single restart attempt after delay of internal timer
Reset of failure latch in run mode after
40s
Reset of failure latch by UVLO or 40s in run mode
S = Start-up condition,
N = No fault,
A = Auto restart ,
U = Under voltage
F = Fault with a single restart, a second F leads to a latched fault / Note: all values @ typical 50 Hz mains frequency
Datasheet
X
30
X
X
X
X
Rev. 1.3, 2016-01-15
ICL5101
Electrical Characteristics
3
Electrical Characteristics
Note: All voltages without the high-side signals are measured with respect to ground (pin 4). The high-side
voltages are measured with respect to pin 17. The voltage levels are valid if other ratings are not
violated.
3.1
Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which if exceeded may lead to destruction of the integrated
circuit. For the same reason make sure that any capacitor connected to pin 3 (VCC) and pin 18 (HSVCC) is
discharged before assembling the application circuit.
Parameter
Symbol
Limit Values
min.
max.
Unit
Remarks
LSCS Voltage
VLSCS
-5
6
V
LSCS Current
ILSCS
-3
3
mA
LSGD Voltage
VLSGD
- 0.3
Vcc+0.3
V
LSGD Peak Source Current
ILSGDsomax
- 75
5
mA
< 500 ns
LSGD Peak Sink Current
ILSGDsimax
- 50
400
mA
< 100 ns
VVCC
- 0.3
18.0
V
VCC Zener Clamp Current
IVCCzener
-5
5
mA
PFCGD Voltage
VPFCGD
- 0.3
Vcc+0.3
V
PFCGD Peak Source Current
IPFCGDsomax
- 150
5
mA
< 500 ns
PFCGD Peak Sink Current
IPFCGDsimax
- 100
700
mA
< 100 ns
PFCCS Voltage
VPFCCS
-5
6
V
PFCCS Current
IPFCCS
-3
3
mA
PFCZCD Voltage
VPFCZCD
-3
6
V
PFCZCD Current
IPFCZCD
-5
5
mA
PFCVS Voltage
VPFCVS
- 0.3
5.3
V
RFM Voltage
VRFM
- 0.3
5.3
V
OTP Voltage
VOTP
- 0.3
5.3
V
OVP Voltage
VOVP
-6
7
V
OVP Current1
IOVP_1
-1
1
mA
IC in Power Down Mode
OVP Current2
IOVP_2
-3
3
mA
IC in active mode
VHSGND
- 650
650
V
dVHSGND /dt
- 40
40
V/ns
18.0
V
VCC Voltage
HSGND Voltage
HSGND Voltage Transient
HSVCC Voltage
1)
VHSVCC
- 0.3
Limitation due to voltage capability in end test
Datasheet
31
Internally clamped to 11V
IC in Power Down Mode
Referring to GND 1)
Referring to HSGND
Rev. 1.3, 2016-01-15
ICL5101
Electrical Characteristics
Parameter
Symbol
Limit Values
Unit
Remarks
Internally clamped to 11V
min.
max.
VHSGD
- 0.3
VHSVCC+0.3
V
HSGD Peak Source Current
IHSGDsomax
- 75
0
mA
< 500ns
HSGD Peak Sink Current
IHSGDsimax
0
400
mA
< 100ns
Junction Temperature
TJ
- 40
150
°C
Storage Temperature
TS
- 55
150
°C
Maximum Power Dissipation
PTOT
—
1
W
Thermal Resistance (2 Chips)
Junction - Ambient
RthJA
—
125
K/W
Soldering Temperature Wave
—
260
°C
Wave Soldering1)
Soldering Temperature Reflow
—
2)
°C
Reflow Soldering
HSGD Voltage
PG_DSO-16-23 /
Tamb=25°C
PG_DSO-16-23 @ TA =
85°C & PCB Area >
30x20mm
ESD Capability HBM
VESD_HBM
—
2
kV
Human Body Model3)
ESD Capability CDM
VESD_CDM
—
1
kV
Charged Device Model4)
2.33
2.43
V
Rated Bus Voltage (95%)
VPFCVS95
1)
According to JESD22A111
2)
According to J-STD-020D
3)
According to EIA/JESD22-A114-B
4)
According to JESD22-C101
Datasheet
32
Rev. 1.3, 2016-01-15
ICL5101
Electrical Characteristics
3.2
Operating Range
The IC operates as described in the functional description once the values listed here lie within the operating
range.
Parameter
Symbol
Limit Values
Unit
min.
Max.
Remarks
HSVCC Supply Voltage
VHSVCC
VHSVCCOff
17.5
V
Referring to HSGND
HSGND Voltage
VHSGND
- 650
650
V
Referring to GND1)
VCC Voltage @ 25°C
VVCC
VVCCOff
17.5
V
TJ = 25°C
VCC Voltage @ 125°C
VVCC
VVCCOff
18.0
V
TJ = 125°C
LSCS Voltage Range
VLSCS
-4
5
V
In active mode
PFCVS Voltage Range
VPFCVS
0
4
V
PFCCS Voltage Range
VPFCCS
-4
5
V
PFZCD Current Range
IPFCZCD
-3
3
mA
OVP Voltage Range
VOVP
6
-6
2)
In active mode
In active mode
V
OVP, Current Range
IOVP
3)
OVP, Current Range
IOVP
- 2.5
2.5
mA
Junction Temperature
Tj
- 40
125
°C
Adjustable Run Frequency
fRFM
20
120
kHz
Range set by RFM
Adjustable Run Frequency
fRFM
20
130
kHz
@ - 25°C
Set Resistor for Run Freq.
RRFM
4.1
25
kΩ
Mains Frequency
fMains
45
65
Hz
210
µA
IC Power Down Mode
IC active mode
NOTCH Filter Operation
1)
Limitation due to creeping distance between the HS & LS Pins (CTT 900V inside)
Limited by maximum of current range at OVP
3)
Limited by minimum of voltage range at OVP
2)
Datasheet
33
Rev. 1.3, 2016-01-15
ICL5101
Electrical Characteristics
3.3
Characteristics Power Supply Section
Note: The electrical characteristics involve the spread of values given within the specified supply voltage and junction
temperature range TJ from -40 °C to 125 °C. Typical values represent the median values, which are given in
reference to 25 °C. If not otherwise stated, a supply voltage of 15 V and VHSVCC = 15 V is assumed and the IC
operates in active mode. Furthermore, all voltages refer to GND if not otherwise mentioned.
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
VCC Quiescent Current1
IVCCqu1
—
90
130
µA
VVCC = VVCCOff – 0.5V
VCC Quiescent Current2
IVCCqu2
—
120
160
µA
VVCC = VVCCOn – 0.5V
IVCCSupply
—
4.2
6.0
mA
VPFCVS > 2.725V
1)
VCC Supply Current
VCC Supply Current in
Latched Fault Mode
LSVCC Turn-On Threshold
LSVCC Turn-Off Threshold
LSVCC Turn-On/Off Hyst.
VCC Zener Clamp Voltage
IVCCLatch
—
110
170
µA
VOTP = 5V
VVCCOn
VVCCOff
VVCCHys
VVCCClamp
13.48
10.0
3.2
15.5
14.0
10.6
3.6
16.3
14.5
11.0
4.0
16.9
V
V
V
V
Hysteresis
IVCC = 2mA/VOTP = 5V
VCC Zener Clamp Current
IVCCZener
2.5
—
5.05
mA
VVCC = 17.5V/VOTP = 5V
High Side Leakage Current
IHSGNDleak
—
0.01
2
µA
VHSGND = 650V, VGND=0V
HSVCC Quiescent Current
2)
IHSVCCqu1
2)
IHSVCCqu2
2)
VHSVCCOn
2)
VHSVCCOff
2)
VHSVCCHy
—
190
280
µA
VHSVCC = VHSVCCOn – 0.5V
0.26
9.75
8.08
1.4
0.65
10.4
8.6
1.7
1.2
11.0
9.3
2.03
mA
V
V
V
VHSVCC > VHSVCCOn
1)
HSVCC Quiescent Current
HSVCC Turn-On Threshold
HSVCC Turn-Off Threshold
HSVCC Turn-On/Off Hyst.
Low Side Ground
1)
2)
Hysteresis
GND
With inactive gate
Refers to high-side ground (HSGND)
3.4
Characteristics of PFC Section
3.4.1
PFC Current Sense (PFCCS)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Turn-off threshold
Overcurrent blanking +
1)
propagation delay
VPFCCSOff
0.95
1.0
1.05
V
tPFCCSOff
140
200
262
ns
Leading-edge blanking
tBlanking
180
250
315
ns
IPFCCSBias
- 0.5
—
0.5
µA
PFCCS bias current
1)
Propagation Delay = 50 ns
Datasheet
34
Test Condition
Pulse width when VPFCCS
> 1.0V
VPFCCS = 1.5V
Rev. 1.3, 2016-01-15
ICL5101
Electrical Characteristics
3.4.2
PFC Zero Current Detection (PFCZCD)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Zero crossing upper thr.
1)
VPFCZCDUp
1.4
1.5
1.6
V
Zero crossing lower thr.
2)
VPFCZCDLow
0.4
0.5
0.6
V
Zero crossing hysteresis
VPFCZCDHys
—
1.0
—
V
Clamping of pos. voltages
VPFCZCDpclp
4.1
4.6
5.12
V
IPFCZCDSink = 2mA
Clamping of neg. voltages
VPFCZCDnclp
- 1.69
- 1.4
- 1.0
V
IPFCZCDSource = - 2mA
PFCZCD bias current
IPFCZCDBias
- 0.5
—
5.0
µA
VPFCZCD = 1.5V
PFCZCD bias current
IPFCZCDBias
- 0.5
—
0.5
µA
VPFCZCD = 0.5V
tRingsup
350
500
660
ns
Δt
498
700
900
pAxs
3)
PFCZCD ringing su. time
Limit value for ON time
extension
1)
Turn-OFF threshold
2)
Turn-ON threshold
3)
Ringing suppression time
3.4.3
x IZCD
PFC Voltage Sensing Bus (PFCVS)
Parameter
Symbol
Limit Values
min.
Typ.
max.
Unit
Trimmed reference voltage
VPFCVSRef
2.468
2.50
2.53
V
Overvoltage turn-off (109 %)
VPFCVSRUp
2.677
2.73
2.78
V
Overvoltage turn-on (105 %)
VPFCVSLow
2.567
2.63
2.68
V
Overvoltage hysteresis
VPFCVSHys
70
100
130
mV
Under voltage (75 %)
VPFCVSUV
1.832
1.88
1.915
V
Under voltage (12.5 %)
VPFCVSUV
0.237
0.31
0.387
V
Rated bus voltage (95 %)
VPFCVS95
2.320
2.38
2.425
V
PFCVS bias current
IPFCVSBias
- 1.0
—
1.0
µA
3.4.4
Initial ON time
VPFCVS = 2.5V
Off time
Symbol
Limit Values
min.
Typ.
max.
Unit
Test Condition
1)
tPFCON_initial
—
4.0
—
µs
VPFCZCD = 0V
2)
tPFCON_max
18.0
24.0
28.6
µs
0.45V < VPFCVS < 2.45V
tPFCON_min
160
270
370
ns
tPFCRep
47
52
57
µs
tPFCOff
42
47
52.5
µs
Max. ON time
Switch threshold from CrCM
to DCM
1)
Repetition time
2)
4 % rated bus voltage
PFC PWM Generation
Parameter
1)
Test Condition
VPFCZCD = 0V
When missing zero crossing signal
At the maximum of the AC line input voltage
Datasheet
35
Rev. 1.3, 2016-01-15
ICL5101
Electrical Characteristics
3.4.5
PFC Gate Drive (PFCGD)
Parameter
PFCGD Low Voltage
PFCGD High Voltage
Symbol
VPFCGDLow
VPFCGDHigh
Limit Values
Unit
Test Condition
min.
Typ.
max.
0.4
0.7
0.92
V
IPFCGD = 5mA
0.4
0.75
1.12
V
IPFCGD = 20mA
- 0.2
0.3
0.62
V
IPFCGD = -20mA
10.0
11.0
11.6
V
IPFCGD = -20mA
8.98
—
—
V
IPFCGD = -1mA / VVCC
1)
8.47
—
—
V
IPFCGD = -5mA / VVCC
1)
PFCGD active Shut Down
VPFCGASD
0.4
0.75
1.12
V
IPFCGD = 20mA VVCC=5V
PFCGD UVLO Shut Down
VPFCGDuvlo
0.3
1.0
1.56
V
IPFCGD = 5mA VVCC=2V
PFCGD Peak Source Current
IPFCGDSouce
—
- 100
—
mA
2) + 3)
2) + 3)
PFCGD Peak Sink Current
PFCGD Voltage during sink
Current
IPFCGDSink
—
500
—
mA
VPFCGDHigh
11.0
11.7
12.3
V
IPFCGDSinkH = 3mA
PFC Rise Time
tPFCGDRise
80
245
500
ns
2V > VLSGD > 8V
2)
PFC Fall Time
tPFCGDFall
20
45
72
ns
8V > VLSGD > 2V
2)
1)
VVCC = VVCCOff + 0.3V
RLoad = 4Ω and CLoad = 3.3nF
3)
The parameter is not subject to production testing – verified by design/characterization
2)
3.5
Characteristics of Inverter Section
3.5.1
Low-Side Current Sense (LSCS)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Overcurrent shutdown volt.
VLSCSOvC1
1.5
1.6
1.7
V
1)
Overcurrent shutdown Volt.
VLSCSOvC2
0.75
0.8
0.85
V
2)
tLSCSOvC
450
600
700
ns
Capacitive mode det. Level1
VLSCSCap1
- 70
- 50
- 27
mV
Capacitive mode duration1
tLSCSCap1
—
280
—
ns
Capacitive mode det. Level2
VLSCSCap2
1.8
2.0
2.2
V
Duration of overcurrent
3)
Capacitive mode duration2
tLSCSCap2
—
50
—
ns
4)
LSCS bias current
ILSCSBias
-1.0
—
1.0
µA
@ VLSCS = 1.5 V
1)
Overcurrent voltage threshold active during start-up, soft start, saturation control
Overcurrent voltage threshold active during run mode
3)
Active before turn-ON of the HSGD in run mode
4)
Active during turn-ON of the HSGD in run mode
2)
Datasheet
36
Rev. 1.3, 2016-01-15
ICL5101
Electrical Characteristics
3.5.2
Low-Side Gate Drive (LSGD)
Parameter
LSGD low voltage
LSGD high voltage
Symbol
VLSGDLow
VLSGDHigh
Limit Values
Unit
Test Condition
min.
typ.
max.
0.4
0.7
1.02
V
ILSGD = 5 mA
0.4
0.8
1.22
V
ILSGD = 20 mA
- 0.3
0.2
0.53
V
ILSGD = - 20 mA (source)
10.0
10.8
11.6
V
2)
8.98
—
—
V
3)
8.47
—
—
V
4)
1)
1)
VCC = 5 V / ILSGD =
1)
20 mA
VCC = 2 V / ILSGD = 5 mA
LSGD active shutdown
VLSGDASD
0.4
0.75
1.12
V
LSGD UVLO shutdown
VLSGDUVLO
0.3
1.0
1.6
V
LSGD peak source current
ILSGDSource
—
- 50
—
mA
5) + 6)
LSGD peak sink current
ILSGDSink
—
300
—
mA
5) + 6)
LSGD voltage during 1)
VLSGDHigh
—
11.7
—
V
ILSGDsinkH = 3 mA
LSGD rise time
tLSGDRise
80
245
500
ns
2 V < VLSGD < 8 V
5)
LSGD fall time
tLSGDFall
20
35
61
ns
8 V > VLSGD > 2 V
5)
1)
1)
Sink current
ILSGD = –20 mA source current
3)
VCCOFF + 0.3 V and ILSGD = –1 mA source current
4)
VCCOFF + 0.3 V and ILSGD = –5 mA source current
5)
Load: RLoad = 10 Ω and CLoad = 1 nF
6)
The parameter is not subject to production testing – verified by design/characterization
2)
3.5.3
Inverter Minimum Run Frequency (RFM)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Fixed start-upfrequency
fStartUp
120
135
148.5
kHz
Duration of soft start
tSoftStart
9
11
13.56
ms
RFM voltage in run mode
VRFM
—
2.5
—
V
Run frequency
fRFM
49
50
51.1
kHz
RRFM = 10kΩ
fRFM1
—
20
—
kHz
IRFM= - 100 µA
2)
fRFM2
—
40
—
kHz
IRFM= - 200 µA
2)
fRFM3
—
100
—
kHz
IRFM= - 500 µA
2)
fRFM4
—
120
—
kHz
IRFM= - 600 µA
2)
fRFM-25°C
—
130
—
kHz
IRFM= - 650 µA
3)
IRFMmax
—
-1000
- 612
µA
@ VRFM = 0V
2)
Adjustable run frequency
RFM max. current range
1)
@ 100µA<IRFM<600µA
2)
1)
Shift start-up frequency to run frequency
Run frequency @ - 40°C
3)
Run frequency @ - 25°C
2)
Datasheet
37
Rev. 1.3, 2016-01-15
ICL5101
Electrical Characteristics
3.5.4
Overtemperature Protection (OTP)
Parameter
Over Temperature Detection
OTP Current Source
3.5.5
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
VOTP1
1.546
1.60
1.65
V
VOTP2
1.247
1.30
1.35
V
VOTP3
—
3.2
—
V
Run Mode
IOTP1
- 53.2
-42.6
-30.5
µA
VOTP = 1V ; OVP = 5µA
IOTP2
-44.2
-35.4
-25.1
µA
VOTP = 2V ; OVP = 5µA
IOTP3
- 26.6
-21.3
- 15.0
µA
VOTP = 1V ; OVP = 30µA
IOTP4
- 22.1
-17.7
-12.3
µA
VOTP = 2V ; OVP = 30µA
Unit
Test Condition
UVLO, VCC < VCCON
Overvoltage Protection (OVP)
Parameter
Symbol
Source Current before Start-Up
Enable Monitoring
Limit Values
min.
typ.
max.
IOVPEnable
- 5.0
- 3.0
- 1.9
µA
VOVP = 0V / VCC < 14.0V
VOVPEnable
350
530
750
mV
1)
IOVPSink
7.0
12.0
18.0
µA
VCC < 14.0V
Positive Clamping Voltage
VOVPClamp
—
6.5
—
V
@ IOVP = 300µA
AC OVP Current Threshold
IOVPSource
186
210
230
µApp
Positive OVP Current Thr.
IOVPDCPos
34
42
50
µApp
Neative OVP Current Thr.
IOVPDCNeg
- 50
- 42
- 34
µApp
Sink Current for OVP
1) If VOVP < VOVPEnable monitoring is disabled
Datasheet
38
Rev. 1.3, 2016-01-15
ICL5101
Electrical Characteristics
3.5.6
High Side Gate Drive (HSGD)
Parameter
HSGD Low Voltage
Symbol
VHSGDLow
Limit Values
Unit
Test Condition
Min.
typ.
max.
0.018
0.05
0.1
V
IHSGD = 5mA (sink)
0.46
1.1
2.5
V
IHSGD = 100mA (sink)
- 0.4
- 0.2
- 0.04
V
9.7
10.5
11.2
V
7.8
—
—
V
HSGD active Shut Down
VHSGDASD
0.041
0.22
0.5
V
HSGD Peak Source Current
IHSGDSource
—
- 50
—
mA
ILSGD = - 20mA (source)
VCCHS=15V
IHSGD = - 20mA (source)
VCCHSOFF + 0.3V
IHSGD = - 1mA (source)
VCCHS=5V
IHSGD = 20mA (sink)
RLoad = 10Ω+CLoad = 1nF 1)
HSGD Peak Sink Current
IHSGDSink
—
300
—
mA
RLoad = 10Ω+CLoad = 1nF 1)
HSGD Rise Time
THSGDRise
120
220
300
ns
HSGD Fall Time
THSGDFall
19
35
70
ns
HSGD High Voltage
1)
VHSGDHigh
2V < VLSGD < 8V
RLoad = 10Ω+CLoad = 1nF
8V > VLSGD > 2V
RLoad = 10Ω+CLoad = 1nF
The parameter is not subject to Production Test – verified by Design / Characterization
3.6
Timer Section
Delay Timer 1
tTIMER1
70
100
163.6
ms
For Fault Detection
Delay Timer 2
74
100
84
130
94
163
ms
µs
For VBUS > 95%
Inverter Time
tTIMER2
tInv
Inverter Dead Time Max
tDeadMax
0.85
1.05
1.25
µs
Inverter Dead Time Min
tDeadMin
400
500
650
ns
V_GD_th =2V
RLoad = 10Ω+CLoad = 1nF
V_GD_th =2V
RLoad = 10Ω+CLoad = 1nF
Δ Inverter Dead Time Max
tDeadMax
- 200
—
200
ns
Δ Inverter Dead Time Min
tDeadMin
- 200
—
200
ns
Min. Duration of Sat. Control
tSaturationmin
34
40
48
ms
Max. Duration of Sat. Control
tSaturationmax
197
—
236
ms
tExtSat
565
625
685
ms
Duration of Ext. Sat. Mode
Datasheet
39
Rev. 1.3, 2016-01-15
ICL5101
Application Example
4
Application Example
4.1
Schematic
D1
Fuse
L1
BR1
D2
R3
L2
C1
R5 IC1
R6
Q1
85 ...
325 VAC
R4
R12
R9
Q2
PFCZCD
HSGD
R13
HSGND
C2
PFCVS
C4
R1
LSGD
PFCCS
Cr
C7
HSVCC
PFCGD
Lr
Q3
R14
L4_3
D8
C11
L4_4
D9
R20
R23
D6 L4_2
LSCS
D4
R2
R19
R15
C5 R7
C6
R17
R22 C12
OT1
C8
D5
D3
R21
R16
R10
C3
L4_1
C9
IC2
R24
R18
Q4
Figure 25 Schematic LED Driver using PFC / LLC Topology for 110W / 54V
Datasheet
40
Rev. 1.3, 2016-01-15
ICL5101
Outline Dimensions
5
Outline Dimensions
Outline dimensions are shown in Figure 26.
Figure 26 PG-DSO-16-23
Notes
1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/products.
2. Dimensions in mm.
Datasheet
41
Rev. 1.3, 2016-01-15
Edition 2013-11-08
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The infromation given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
infromation regarding the application of the device, Infineon Technologies hereby disclaims any and all
warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual
property rights of any third party.
Infromation
For further infromation on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For infromation on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the
failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life
support devices or systems are intended to be implanted in the human body or to support and/or maintain and
sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.
ICL5101
Revision History: 2016-01-15
Previous Revision: 2015-09-23
Page or Item
Subjects (major changes since previous revision)
Page 8 / 30 / 34 RUN Frequency: 120 kHz @ - 40 °C / 130 kHz @ - 25 °C
All
Deleted Confidential
3.5.5
OVP: wrong Value Deleting / Index Adjustment
All
Complete Review
Pages: 2 / 40
Figure Updates: 1 / 25 replacement of D7
Page: 24
Figure Updates: 18 replacement of D7 / 19 update
All
Complete Review
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COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™
of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™
of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR
STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS
Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of
Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems
Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc.
SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software
Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc.
TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™
of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™
of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2011-11-11
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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