TLE983x
Microcontroller with LIN and power switches for Automotive Applications
User’s Manual
Rev. 1.0, 2011-12-23
Automotive Power
TLE983x
Revision History
Page or Item
Subjects (major changes since previous revision)
Rev. 1.0, 2011-12-23
Initial version
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™,
EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™,
PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™,
SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™
of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc.,
OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc.
RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc.
SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden
Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA.
UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™
of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of
Diodes Zetex Limited.
Last Trademarks Update 2011-02-24
User’s Manual
2
Rev. 1.0, 2011-12-23
TLE983x
1
1.1
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2
2.1
2.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
3.1
3.1.1
3.1.1.1
3.1.2
3.1.2.1
3.1.2.2
3.1.2.3
3.1.3
3.1.3.1
3.1.3.2
3.1.4
3.1.4.1
3.1.5
3.1.5.1
3.1.5.2
3.1.5.3
3.1.6
3.1.6.1
3.2
3.2.1
3.2.2
3.2.3
3.2.3.1
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structure of the Power Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PMU Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Generation (PSG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulator 5.0V (VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulator 1.5V (VDDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Control Unit - Fail Safe Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-up Management Unit (WMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cyclic Management Unit (CYCMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cyclic Sense Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cyclic Wake Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Voltage Regulator 5.0V (VDDEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDDEXT Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
28
28
29
31
32
33
34
34
37
39
40
52
52
54
54
60
63
66
66
66
67
68
4
4.1
4.1.1
4.1.2
4.1.2.1
4.1.2.2
4.1.3
4.1.3.1
4.1.3.2
4.1.3.3
4.1.3.4
4.1.3.5
4.1.3.6
4.1.3.7
4.1.3.8
4.1.4
4.1.4.1
4.1.5
4.1.6
4.1.6.1
System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Precision Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Precision Oscillator Circuit (OSC_HP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Input Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Crystal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase-Locked Loop (PLL) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL VCO Lock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Oscillator (OSC_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Watchdog Event or PLL Loss of Lock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Watchdog Event or Loss of Lock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Startup Control for System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Oscillator Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
69
70
70
70
70
71
71
72
77
77
77
77
78
78
80
82
82
82
82
User’s Manual
3
Rev. 1.0, 2011-12-23
TLE983x
4.1.6.2
4.1.6.3
4.1.6.4
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.4.1
4.2.4.2
4.2.4.3
4.2.4.4
4.2.4.5
4.2.5
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.3.3
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.1.3
4.4.2
4.4.3
4.4.3.1
4.4.4
4.5
4.5.1
4.5.2
4.6
4.6.1
4.7
4.8
4.8.1
4.8.2
4.9
4.9.1
4.9.2
4.10
4.10.1
4.10.2
4.11
4.11.1
4.11.2
4.12
PLL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
System Clock Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
External Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Types of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Functional Description of Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Power-On / Brown-out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Wake-up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
WDT1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
WDT / Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Slow Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Internal Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Extended Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Interrupt Node Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Interrupt Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Interrupt Event Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
NMI Event Flags Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
General Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Input Pin Function Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Port Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Flexible Peripheral Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Peripheral Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Module Suspend Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
XRAM Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Access to XRAM Using the DPTR (16-bit addressing mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Access to XRAM Using the Register R0/R1 (8-bit addressing mode) . . . . . . . . . . . . . . . . . . . . . . 117
Error Detection and Correction Control for Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Error Detection and Correction Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Error Detection and Correction Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Miscellaneous Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Bit Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5
System Control Unit - Power Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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5.1
5.2
5.3
5.3.1
5.3.1.1
5.3.2
5.4
5.4.1
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.4.1
5.5.4.2
5.6
5.6.1
5.7
5.7.1
5.7.2
5.7.3
Structure of the power modules system control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Control Unit (RCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation Unit (CGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fail Safe Functionality of Clock Generation Unit (Clock Watchdog) . . . . . . . . . . . . . . . . . . . . . . .
Functional Description of Clock Watchdog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation Unit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supplement Unit (SPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supplement Control Unit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Unit (ICU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structure of PREWARN_SUP_NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structure of XINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Behavior of Analog Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Unit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Unit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Unit - Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Status Unit (SSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Control Unit for Power Modules (PCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VS-Overvoltage System Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overtemperature System Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Control Unit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
128
129
129
130
131
133
138
140
141
141
142
144
145
145
151
154
156
161
163
163
165
6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.3
6.3.1
6.4
6.4.1
6.4.2
6.4.3
6.5
XC800 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFRs of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Operation Register (EO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Control Register (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFRs of The Core Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Extension Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Extension Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
168
168
170
170
170
170
170
171
172
173
173
173
173
173
173
173
175
176
7
7.1
7.2
7.2.1
7.2.2
7.2.2.1
7.2.2.2
7.3
7.4
7.4.1
7.5
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Access to External Data Memory Using the DPTR (16-Bit addressing mode) . . . . . . . . . . . . .
Access to External Data Memory using the Register R0/R1 (8-Bit addressing mode) . . . . . . .
Error Correction Code (ECC) in Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
182
183
183
183
183
183
184
184
185
187
194
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7.6
7.6.1
7.6.2
7.6.2.1
7.6.2.2
Program and XRAM Data Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Protection Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot ROM Protection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVM Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
195
195
195
196
8
8.1
8.2
8.2.1
8.2.1.1
8.2.1.2
8.2.1.3
8.2.1.4
8.2.1.5
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.2.11
8.3
8.3.1
8.3.2
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.6
8.6.1
Embedded Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Block Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Cell Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Map-RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM and SFR block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFR Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tearing-Safe Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Address Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linearly Mapped Sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disturb Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hot Spot Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Properties of Error Correcting Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Fetch from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Reads from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Writes to Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Correcting Codes (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Aborted Program/Erase Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Margin Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommendations for Optimized Flash Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Code and Constant Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
200
200
201
202
202
203
203
203
203
203
203
204
204
204
204
205
205
206
206
207
207
207
208
208
209
209
210
211
211
211
211
211
211
211
9
9.1
9.2
9.2.1
9.2.2
9.2.2.1
Watchdog Timer (WDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
213
213
213
213
214
217
10
10.0.1
10.0.2
Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
11
11.1
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
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11.2
11.2.1
11.2.2
11.3
11.4
11.5
11.6
11.7
11.7.1
11.7.2
11.7.3
11.7.4
11.8
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Structure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Structure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Node Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Flag Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
229
229
230
231
231
232
233
235
235
237
239
242
244
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.3
12.4
12.5
12.5.1
12.5.2
12.5.3
12.6
12.6.1
Multiplication/Division Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Division Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normalize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Busy Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDU Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operand and Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDU Module Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interfaces of the MDU Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
246
246
247
247
248
248
248
248
248
249
250
251
252
254
255
255
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.3
13.3.1
13.3.1.1
13.3.1.2
13.3.1.3
13.3.2
13.3.2.1
13.3.2.2
13.3.2.3
13.3.3
13.3.3.1
13.3.3.2
GPIO Ports and Peripheral I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Drain Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pull-Up/Pull-Down Device Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Input Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Output Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLE983x Port Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 0 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 0 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
256
256
259
260
260
261
261
263
263
264
264
264
265
267
270
270
271
273
276
276
277
User’s Manual
7
Rev. 1.0, 2011-12-23
TLE983x
13.3.3.3
13.3.4
14
14.1
14.2
14.3
14.4
14.5
14.6
14.6.1
14.6.2
14.6.3
14.6.4
14.7
14.8
Port 2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Run Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interfaces of the Timer 0 and Timer 1 Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
282
282
282
282
282
283
283
284
284
285
287
288
291
15
Timer2 and Timer21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.1
Auto-Reload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.1.1
Up/Down Count Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.1.2
Up/Down Count Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.2
Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.3
Count Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.4
Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.5
Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.5.1
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.5.2
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.5.3
Timer 2 Reload/Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.5.4
Timer 2 Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2
Timer2 and Timer21 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.1
Interfaces of the Timer2 and Timer21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.2
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.2.1
Timer2 and Timer21 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
292
292
292
292
293
295
295
296
296
296
298
300
301
302
302
304
304
16
16.1
16.2
16.3
16.4
16.5
16.5.1
16.5.2
16.5.3
16.5.4
16.5.5
16.5.6
16.5.7
16.6
16.6.1
Timer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 1a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 1c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 3a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 3b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
306
306
306
306
307
307
309
310
311
312
313
314
315
316
316
17
17.1
17.1.1
Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Feature Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
User’s Manual
8
Rev. 1.0, 2011-12-23
TLE983x
17.1.2
17.2
17.2.1
17.2.2
17.2.2.1
17.2.2.2
17.2.2.3
17.2.3
17.2.3.1
17.2.3.2
17.2.3.3
17.2.4
17.2.4.1
17.2.4.2
17.2.4.3
17.2.5
17.2.6
17.2.7
17.3
17.3.1
17.3.2
17.3.2.1
17.3.2.2
17.3.2.3
17.3.2.4
17.3.3
17.3.4
17.3.5
17.4
17.5
17.6
17.6.1
17.6.2
17.6.3
17.6.4
17.7
17.7.1
17.8
17.8.1
17.9
17.9.1
17.9.2
17.9.3
17.9.4
17.9.5
17.9.6
17.9.7
17.9.8
17.10
17.10.1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Timer T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T12 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T12 Counting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Edge-Aligned / Center-Aligned Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T12 Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compare Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel State Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hysteresis-Like Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compare Mode Output Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dead-Time Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Modulation and Level Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T12 Capture Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T12 Shadow Register Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer T12 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Timer T13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T13 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T13 Counting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T13 Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization to T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T13 Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compare Mode Output Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T13 Shadow Register Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trap Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hall Sensor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hall Pattern Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hall Pattern Compare Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hall Mode Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hall Mode for Brushless DC-Motor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCU6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 12 – Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 13 – Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capture/Compare Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Modulation Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Channel Modulation Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLE983x Module Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interfaces of the CCU6 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
User’s Manual
9
326
327
328
330
330
331
333
334
334
334
339
340
340
342
343
345
349
350
350
351
353
353
354
354
355
357
359
360
362
364
366
367
369
369
371
373
373
375
375
376
377
379
382
389
392
401
405
410
420
420
Rev. 1.0, 2011-12-23
TLE983x
18.1
18.1.1
18.1.2
18.1.3
18.1.4
18.2
18.3
18.4
18.4.1
18.5
18.5.1
18.5.2
18.5.3
18.5.4
18.5.5
18.5.6
18.6
18.6.1
18.6.2
18.6.3
18.7
18.8
UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 0, 8-Bit Shift Register, Fixed Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 1, 8-Bit UART, Variable Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2, 9-Bit UART, Fixed Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 3, 9-Bit UART, Variable Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud-rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN Support in UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Synchronization to the Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization of Break/Synch Field Detection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Range Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN Baud Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud-rate Generator Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud-rate Generator Timer/Reload Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interfaces of UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
422
422
423
425
425
427
427
428
428
430
430
431
431
433
433
435
436
436
437
438
440
441
19
19.1
19.2
19.2.1
19.2.2
19.2.3
19.2.4
19.2.5
19.3
LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN Transceiver Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slope Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN Transceiver Status for Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN Transceiver Slope Mode Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
442
442
443
443
446
446
448
448
449
20
20.1
20.2
20.2.1
20.2.2
20.2.3
20.2.4
20.2.4.1
20.2.5
20.2.6
20.3
20.4
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
20.5
20.5.1
High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Input Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Timer Reload Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLE983x Module Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interfaces of the SSC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
453
453
454
455
456
459
459
460
461
462
464
465
465
465
470
470
471
471
471
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10
Rev. 1.0, 2011-12-23
TLE983x
20.5.2
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
21
Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2
Measurement Functions Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.1
8-Bit - 10 Channel ADC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.1.1
8-Bit ADC Channel Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.1.2
Transfer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.1.3
8-Bit - 10 Channel Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.2
Monitoring Inputs Voltage Attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.2.1
Monitoring Attenuators Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.3
Supply Voltage Sense Attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.3.1
Supply Voltage Sense Attenuators Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.4
Central and Low Side Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.4.1
Temperature Sensor Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.5
Supplement Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.5.1
Supplement Modules Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
473
473
475
475
475
476
476
477
477
479
480
481
482
483
484
22
Measurement Core Module - ADC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.1.1
Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.1.1.1
ADC2 - Core (8-Bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.1.1.2
Channel Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.1.1.3
Calibration Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.1.1.4
IIR-Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.1.1.5
Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.1.1.6
Start-up behavior after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.1.1.7
Measurement Core response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.1.1.8
Response time calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.1.1.9
Postprocessing Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
487
487
487
488
488
511
521
538
570
570
572
572
23
23.1
23.2
23.3
23.4
23.4.1
23.4.2
23.4.3
23.4.3.1
23.4.3.2
23.4.4
23.4.4.1
23.4.4.2
23.4.4.3
23.4.4.4
23.4.4.5
23.4.4.6
23.4.5
23.4.5.1
23.4.5.2
23.4.5.3
23.4.6
574
574
574
575
576
576
576
577
577
578
579
579
579
580
580
580
580
581
581
581
582
583
Analog Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structure of Digital Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Part: Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Request Source Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arbiter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Start Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Request Pending Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source Function Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Autoscan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sequential Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Stage Sequential Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sequential Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait-for-Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User’s Manual
11
Rev. 1.0, 2011-12-23
TLE983x
23.4.7
23.4.8
23.4.8.1
23.4.8.2
23.4.8.3
23.4.8.4
23.4.9
23.4.9.1
23.4.9.2
23.5
23.6
23.7
23.7.1
23.7.2
23.7.3
23.7.4
23.7.5
23.7.6
23.7.7
23.7.8
23.7.9
23.7.10
23.7.11
23.7.12
23.7.13
23.7.14
23.7.15
23.7.16
23.7.17
23.7.18
23.7.19
23.7.20
23.7.21
23.7.22
23.7.23
23.7.24
23.7.25
23.7.26
23.7.27
23.7.28
23.8
23.8.1
23.8.2
23.8.3
Conversion Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Result Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Result Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Reduction Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Result Register View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Event Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLE983x Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Multiplexer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Priority and Arbitration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Trigger Select/Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Class Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Request Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Request Pending Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Request Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Queue Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Queue Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Queue 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Queue Backup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Queue Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Valid Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Result Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Interrupt Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Channel Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Channel Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Interrupt Node Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Event Interrupt Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Event Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Event Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Event Interrupt Node Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Multiplexer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limit Check Boundary Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Module Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
583
584
584
584
586
586
588
589
590
591
592
594
594
595
595
597
598
600
601
602
603
604
606
607
608
609
610
611
614
615
616
616
616
617
617
618
619
620
621
623
624
624
625
626
24
24.1
24.2
24.3
24.3.1
High-Voltage Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
627
627
627
630
630
25
High Side Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
User’s Manual
12
Rev. 1.0, 2011-12-23
TLE983x
25.1
25.2
25.2.1
25.2.2
25.2.3
25.2.4
25.2.5
25.3
25.3.1
25.3.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cyclic Switching in Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sub-Module ON-State Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sub-Module OFF-State Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Side Switch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Side Switch 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
640
641
641
642
642
642
643
644
644
647
26
26.1
26.2
26.2.1
26.2.1.1
26.2.1.2
26.2.2
26.2.2.1
26.3
26.3.1
Low Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Detection and Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overtemperature Detection and Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation of Low Side Switch in PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Requirement for Low Side Switch in PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Side Switches Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
651
651
652
652
652
653
653
655
656
656
27
27.1
27.2
27.2.1
27.2.2
27.3
27.3.1
PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM - Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM - Switches Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM-Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
659
659
660
660
661
663
663
28
28.1
28.1.1
28.2
28.3
28.4
Switched Capacitor Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Amplifier Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SC-Amplifier Transfer Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Code Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational Amplifier Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
670
670
671
671
672
672
29
29.1
29.2
29.2.1
29.2.2
On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCDS Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
674
674
675
676
676
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TLE983x
Introduction
1
Introduction
The rapidly growing area of embedded control applications is representing one of the most time-critical operating
environments for today’s microcontroller based systems. Complex control algorithms have to be processed based
on a large number of digital as well as analog input signals, and the appropriate output signals must be generated
within a defined maximum response time. Embedded control applications also are sensitive to board space,
weight, power consumption, and overall system cost.
Embedded control applications therefore require microcontroller systems, which:
•
•
•
•
offer a high level of system integration
eliminate the need for additional peripheral devices and the associated software overhead
provide system security and fail-safe mechanisms
provide effective means to control and reduce the device’s power consumption
Addressing these goals Infineon developed the TLE983x family of embedded power single chip solutions that
integrates a high performance 8-bit microcontroller derived from the established XC800 family with application
specific power drivers, control and communication modules. Information about specific versions and derivatives
will be made available with the devices data sheets themselves. Contact your Infineon representative for up-todate material or refer to http://www.infineon.com/embedded-power
About this Manual
This manual describes the functionality of a number of embedded power types of the Infineon TLE983x
derivatives. These embedded power devices provide identical functionality to a large extent, but each device type
has specific unique features. The descriptions in this manual cover a superset of the provided features. For
simplicity, the various device types are referred to by the collective term TLE983x throughout this manual. The
complete conforming designations including electrical characteristics are listed in the respective Data Sheets. For
the features of a particular derivative please refer to this device data sheet.
Complete Development Support
For the development tool support of its embedded power devices, Infineon follows a clear third party concept. A
lot of tool suppliers world-wide, ranging from local niche manufacturers to multinational companies with broad
product portfolios, offer powerful development tools for the Infineon TLE983x embedded power devices, providing
a remarkable variety of price-performance classes as well as early availability of high quality key tools such as
compilers, assemblers, debuggers or flash programming tools. Infineon incorporates its strategic tool partners
very early into the product development process, making sure embedded system developers get reliable, welltuned tool solutions, which help them unleash the power of Infineon embedded power products in the most
effective way and with the shortest possible learning curve.
The tool environment for the Infineon 8-bit embedded power devices includes the following tools:
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•
•
•
•
Compilers (C/C++)
Macro-assemblers, linkers, locators, library managers, format-converters
HLL debuggers
Evaluation boards
Starter kits
Low level driver software (LIN LLD)
Chip code generation tool (DAVETM)
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TLE983x
Introduction
1.1
Abbreviations
The following acronyms and terms are used within this document (see in Table 1).
Table 1
Acronyms
Acronyms
Name
100TP
100 Time Programmable Memory
ALU
Arithmetic Logic Unit
CCU6
Capture Compare Unit 6
CGU
Clock Generation Unit
CMU
Cyclic Management Unit
DAP
Device Access Port
DPP
Data Post Processing
ECC
Error Correction Code
ECU
Electronic Control Unit
EEPROM
Electrically Erasable Programmable Read Only Memory
GPIO
General Purpose Input Output
FSM
Finite State Machine
FSR
Full Scale Range
FW
Firmware (BootROM Software, e.g. executed after power up)
IIR
Infinite Impulse Response Filter
ICU
Interrupt Control Unit
IRAM
Internal Random Access Memory - Internal Data Memory
LDO
Low DropOut voltage regulator
LHVIO
LIN High Voltage Input / Output Mode
LIN
Local Interconnect Network
LLD
Low Level Driver (Software)
LNM
LIN Normal Mode
LROM
LIN Receive-Only Mode
LSLM
LIN Sleep Mode
LSB
Least Significant Bit
MBIST
Memory Built In Self Test
MCM
Memory Constant Mode (XC800 Core)
MCM
Multi Channel Mode (CCU6)
MCM
Measurement Core Module (Measurment Unit)
MCU
Micro Controller Unit
MDU
Multiplication Division Unit
MMC
Monitor Mode Control
MSB
Most Significant Bit
NMI
Non Maskable Interrupt
OCDS
On Chip Debug Support
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TLE983x
Introduction
Table 1
Acronyms
Acronyms
Name
OTP
One Time Programmable
OSC
Oscillator
PC
Program Counter
PCU
Power Control Unit
PD
Pull Down
PGU
Power supply Generation Unit
PLL
Phase Locked Loop
PMU
Power Management Unit
PSW
Program Status Word
PU
Pull Up
PWM
Pulse Width Modulation
RAM
Random Access Memory
RCU
Reset Control Unit
RMU
Reset Management Unit
ROM
Read Only Memory
SCK
SSC Clock
SFR
Special Function Register
SOW
Short Open Window (for WDT1)
SPI
Serial Peripheral Interface
SSC
Synchronous Serial Channel
SSU
System Status Unit
TMS
Test Mode Select
UART
Universal Asynchronous Receiver Transmitter
UDIG
Universal Digital Controller for ADC1
VBG
Voltage reference Band Gap
WDT
Watchdog timer
WMU
Wake-up Management Unit
XRAM
On-Chip eXternal Data Memory
XSFR
On-Chip eXternal Special Function Register
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TLE983x
Introduction
1.2
Naming Conventions
The diverse bitfields used for control functions and status indication and the registers housing them are equipped
with unique names wherever applicable. Thereby these control structures can be referred to by their names rather
than by their location. This makes the descriptions by far more comprehensible. To describe regular structures
(such as ports) indices are used instead of a plethora of similar bit names, so bit 3 of port 5 is referred to as P5.3.
Where it helps to clarify the relation between several named structures, the next higher level is added to the
respective name to make it unambiguous. The term SYSCON0.SYSCLKSEL clearly identifies bitfield
SYSCLKSEL as part of register SYSCON0.
User’s Manual
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TLE983x
Overview
2
Overview
2.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High performance XC800 core
– compatible to standard 8051 core
– up to 40 MHz clock frequency
– two clocks per machine cycle architecture
– two data pointers
On-chip memory
– 20, 32, 44 or 60 kByte + 4 kByte Flash for program code and data (4 kByte EEPROM emulation built-in)
– 512 Byte One Time Programmable Memory (OTP)
– 512 Byte 100 Time Programmable Memory (100TP)
– 256 Byte RAM
– 3 kByte XRAM
– BootROM for startup firmware and Flash routines
Core logic supply at 1.5 V
On-chip OSC and PLL for clock generation
– Loss of clock detection with fail safe mode for LSS, HSS and LIN
Watchdog timer (WDT) with programmable window feature for refresh operation and warning prior to overflow
General-purpose I/O Port (GPIO) with wake-up capability
Multiplication/division unit (MDU) for arithmetic calculation
Software libraries to support floating point and MDU calculations
Five 16-Bit timers - Timer 0, Timer 1, Timer 2, Timer 21 and Timer 3
Capture/compare unit for PWM signal generation (CCU6) and Hall Sensor measurement with Timer 12 and
Timer 13
Full duplex serial interface (UART) with LIN support
Synchronous serial channel (SSC)
On-chip debug support via 2-wire Device Access Port (DAP)
LIN Bootstrap loader (LIN BSL)
LIN transceiver compliant to LIN 1.3, LIN 2.0 and LIN 2.1
2 x Low Side Switches with clamping capability incl. PWM functionality, e.g. as relay driver
1 or 2 x High Side Switches with cyclic sense option and PWM functionality, e.g. for LED or powering of
switches
High Voltage Monitor Input pins for wake-up and with cyclic sense and analog measurement option
Measurement unit with 10 channels, 8-Bit A/D Converter (ADC2) and data post processing
8 channels, 10-Bit A/D Converter (including battery voltage and supply voltage measurement) (ADC1)
Single power supply from 3.0 V to 27 V
Low-dropout voltage regulators (LDO)
Dedicated 5 V voltage regulator for external loads (e.g. hall sensor)
Programmable window watchdog (WDT1) with independent on-chip clock source
Optional Operational amplifier for current sensing
Power saving modes
– MCU slow-down mode
– Stop Mode
– Sleep Mode
– Cyclic wake-up and cyclic sense during Stop Mode and Sleep Mode
Power-on and undervoltage/brownout reset generator
Overtemperature protection
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TLE983x
Overview
•
•
•
•
•
Overcurrent protection with shutdown
Supported by a full range of development tools including C compilers, macroassembler packages, emulators,
evaluation boards, HLL debuggers, programming tools, software packages
Temperature Range TJ: -40 °C up to 150 °C
Package PG-VQFN-48
Green package (RoHS compliant)
2.2
Functional Description
This highly integrated circuit contains analog and digital functional blocks. For system and interface control an
embedded 8-Bit state-of-the-art microcontroller, compatible to the standard 8051 core with On-Chip Debug
Support (OCDS), is available. For internal and external power supply purposes, on-chip low drop-out regulators
are existent. An internal oscillator provides a cost effective and suitable clock in particular for LIN slave nodes. As
communication interface, a LIN transceiver and several High Voltage Monitor Inputs with adjustable threshold and
filters are available. Furthermore two High Side Switches (e.g. for driving LEDs or cyclic powering of switches),
two Low Side Switches (e.g. for relays) and several general purpose input/outputs (GPIO) with pulse-width
modulation (PWM) capabilities are available.
The Micro Controller Unit (MCU) supervision and system protection including reset feature is controlled by a
programmable window watchdog. A cyclic wake-up circuit, supply voltage supervision and integrated temperature
sensors are available on-chip.
All relevant modules offer power saving modes in order to support terminal 30 connected automotive applications.
A wake-up from the power saving mode is possible via a LIN bus message, via the monitoring inputs, via the GPIO
ports or repetitive with a programmable time period (cyclic wake-up).
The integrated circuit is available in a VQFN-48 package with 0.5 mm pitch and is designed to withstand the
severe conditions of automotive applications.
User’s Manual
19
Rev. 1.0, 2011-12-23
Figure 1
User’s Manual
XTAL2
XTAL1
P2.1, P2.3 … P2.5, P2.7
(AN1, AN3 … AN5, AN7)
ADCGND
VAREF
P1.0 … P1.4
P0.1 … P0.5
DAP
TMS
P0.0
8 Bit - MCU
6
7
20
3kB XRAM
256 Byte-RAM
MCU
PLL
Memories
LP_CLK
20MHz
LP_CLK2
100kHz
Power Down Supply
8-ch.
10-bit ADC
Flash
24 … 64kByte
BootROM
MAP
RAM
WMU
VREF5V
RC-Oscillator
5MHz
VMON 1...5
0
2
Mux
GPIO
Ports
5V
VS_SENSE
VBAT_SENSE
TLE983x
VS
WDT
Timer
0/1
XSFR-BUS
UART
Timer 2/21
CCU6 (Capture
Compare Unit)
SSC (Synchr. Serial
Channel)
Debug (DAP)
Port Control
IRQ
XC800
EWARP Core
DPP
CTRL
Trigger
OA_IN_P
Operational Amplifier
0
1
2
3
5
8-Bit ADC
6
7
8
9
4
OA_IN_N
VS_SENSE
VBAT_SENSE
VDDP_SENSE
VDDC_SENSE
OA_SENSE
LS1_SENSE
LS2_SENSE
T_SENSE
TS_LS_SENSE
REF_SENSE
BG
CMU
CLK_GEN
WDT1
Timer 3
TSENSE
Measurement Unit
Power-Control
AP_SUB_CTRL
PMU/
PCU
IR
RCU
SCU_PM
CYCMU
CGU
PREWARN_SUP_NMI
XINT
PMU
VDDP
PMU/
PCU
MISC
MDU (Multiply /
Division Unit)
BRG
MISC
Control
LIN
Control
SCU
RMU
VPRE
VDDEXT
VDDEXT
VDDP
Attenuator
Attenuator
Wake
Wake
LIN Transceiver
Low Side 2
Low Side 1
High Side 2
High Side 1
PWM-Unit
VS_SENSE
VBAT_SENSE
VDDP_SENSE
VDDC_SENSE
VMON 1..5
MON
PMU-XSFR
VDDC
VDDC
LINGND
LIN
LS2
LSGND
LS1
HS 2
HS 1
VBAT_SENSE
MON5
MON1
.
.
TLE983x
Overview
Block Diagram
XSFR-BUS
SFR-BUS
Block Diagram
The TLE983x has several operational modes mainly to support low power consumption requirements. The low
power modes and state transitions are depicted in Figure 2 below.
Rev. 1.0, 2011-12-23
TLE983x
Overview
Power-up
VS > 3V
Reset
WDT1 reset
(error_wdt++)
Transition by software Transition by external event
VDDC stable &
error_supp < 5
VDDC fail
(error_supp++)
Safety Fallback
Safety fallback
error_supp = 5
Cyclic wake
LIN wake or
MON wake or
GPIO wake
Active Mode
Cyclic wake
LIN wake or
MON wake
STOP command
Stop Mode
Transition by internal event
SLEEP command
Safety fallback
error_wdt = 5
Sleep Mode
Cyclic-sense
Cyclic-sense
PCU_state_diagram_simple_Cus.vsd
Figure 2
Power Control State Diagram
Reset Mode
The Reset Mode is a transition mode e.g. during power-up of the device after a power-on reset. In this mode the
on-chip power supplies are enabled and all other modules are initialized. Once the core supply VDDC is stable,
the Active Mode is entered. In case the watchdog timer WDT1 fails for more than four times, a fail-safe transition
to the Sleep Mode is done.
Active Mode
In Active Mode all modules are activated and the TLE983x is fully operational.
Stop Mode
The Stop Mode is one out of two low power modes. The transition to the low power modes is done by setting the
respective Bits in the Power Mode Control Register (PMCON0). In Stop Mode the embedded microcontroller is
still powered allowing faster wake-up reaction times. A wake-up from this mode is possible by LIN bus activity, the
High Voltage Monitor Input pins or the respective 5V GPIOs.
Sleep Mode
The Sleep Mode is the second low-power mode. The transition to the low-power modes is done by setting the
respective Bits in the Power Mode Control Register (PMCON0) . In Sleep Mode the embedded microcontroller
power supply is deactivated allowing the lowest system power consumption, but the wake-up time is longer
compared to the Stop Mode. A wake-up from this mode is possible by LIN bus activity or the High Voltage Monitor
Input pins. A wake-up from Sleep Mode behaves similar to a power-on reset.
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TLE983x
Overview
Cyclic Wake-up Mode
The cyclic wake-up mode is a special operating mode of the Sleep Mode and the Stop Mode. The transition to the
cyclic wake-up mode is done by first setting the respective Bits in the PMU Wake-up Control Register
(PMU_WAKEUP_CTRL) followed by the SLEEP or STOP command. Additional to the cyclic wake-up behavior
(wake-up after a programmable time period), the wake-up sources of the normal Stop Mode and Sleep Mode are
available.
Cyclic Sense Mode
The cyclic sense mode is a special operating mode of the Sleep Mode and the Stop Mode. The transition to the
cyclic sense mode is done by first setting the respective Bits in the PMU Wake-up Control Register
(PMU_WAKEUP_CTRL) followed by the STOP or SLEEP command. In cyclic sense mode the High Side Switch
can be switched on periodically for biasing some switches for example. The wake-up condition is configurable,
when the sense result of defined monitor inputs at a window of interest changed compared to the previous wakeup period or reached a defined state respectively. In this case the Active Mode is entered immediately. For cyclic
sense in Stop Mode VDDEXT can be switched on periodically. Furthermore cyclic sense allows to sense dedicated
GPIO port states and transitions when in Stop Mode.
The following table shows the possible power mode configurations of each major module or function respectively.
Table 2
Power mode configurations
Module/function
Active Mode Stop Mode
Sleep Mode
Comment
VDD1V5PD
ON
ON
ON
–
VPRE, VDDP, VDDC
ON
ON (no dynamic
load)
OFF
–
VDDEXT
ON/OFF
ON (no dynamic
load)/OFF
cyclic ON/OFF
OFF
–
HSx
ON/OFF
cyclic ON/OFF
cyclic ON/OFF
cyclic sense
LSx
ON/OFF
OFF
OFF
–
PWM GEN.
ON/OFF
OFF
OFF
–
LIN TRx
ON/OFF
wake-up only/
OFF
wake-up only/
OFF
–
MON1 - MON5 (wake-up)
n.a.
disabled/static/cyclic disabled/static/
cyclic
cyclic: combined with
HS=on
MON1 - MON5
(measurement)
ON/OFF
OFF
OFF
available on four
channels
VS sense
ON/OFF
brownout
detection
brownout detection
brownout
detection
brownout detection
done in PCU
VBAT_SENSE
ON/OFF
OFF
OFF
–
GPIO 5V (wake-up)
n.a.
disabled/static/cyclic OFF
–
GPIO 5V (active)
ON
ON
OFF
–
WDT1
ON
OFF
OFF
–
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TLE983x
Overview
Table 2
Power mode configurations
Module/function
Active Mode Stop Mode
Sleep Mode
CYCLIC Modes
n.a.
cyclic wake-up/
cyclic sense/OFF
cyclic wake-up/
cyclic sense with HS,
cyclic sense/OFF VDDEXT; wake-up
from cyclic wake
needs MC for
entering Sleep Mode /
Stop Mode again
Measurement Unit
ON1)
OFF
OFF
–
2)
Comment
MCU
ON/slowdown/HALT
STOP
OFF
–
CLOCK GEN (MC)
ON
OFF
OFF
–
LP_CLK (20 MHz)
ON
OFF
OFF
WDT1
LP_CLK2 (100 kHz)
ON
ON
ON
for cyclic wake-up
1) Should not be switched off due to safety reasons
2) MC PLL clock disabled, MC supply reduced to 0.9 V
Wake-up Source Prioritization
All wake-up sources have the same priority. In order to handle the asynchronous nature of the wake-up sources,
the first wake-up signal will initiate the wake-up sequence. Nevertheless all wake-up sources are latched in order
to provide all wake-up events to the application software. The software can clear the wake-up source flags. It is
ensured, that no wake-up event is lost.
As default wake-up sources, the LIN and MON inputs are activated after power-on reset only. GPIO ports as wakeup sources are disabled by default after power-on reset. The application software can reconfigure the wake-up
sources according to the application needs.
Wake-up Levels and Transitions
The wake-up can be triggered by rising, falling or both signal edges for each monitor and GPIO input individually.
User’s Manual
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TLE983x
Power Management
3
Power Management
3.1
Power Management Unit (PMU)
The purpose of the power management unit is to ensure the fail safe behavior of embedded automotive systems.
Therefore the power management unit controls all system modes including the corresponding transitions. The
power management unit is responsible for generating all needed voltage supplies for the embedded MCU (VDDC,
VDDP) and the external supply (VDDEXT). Additionally, the PMU provides well defined sequences for the system
mode transitions and generates hierarchical reset priorities. The reset priorities control the reset behavior of all
system functionalities especially the reset behavior of the embedded MCU. All these functions are controlled by
finite state machines. The system master functionality of the PMU requires the generation of an independent logic
supply and system clock. Therefore the PMU has a module internal logic supply and system clock which works
independently of the MCU clock.
The following state diagram shows the available modes of the device.
Vs > 3V
start-up
LIN-wake |
MON-wake |
cyclic _wake
VDDC =stable &
error_supp<5
error_sup=5
sleep
VDDC = fail
Sleep command (from MCU) |
WDT1_SEQ_FAIL = 1
active
LIN-wake |
MON-wake |
GPIO-wake |
cyclic _wake |
PMU_PIN = 1 |
SUP_TMOUT = 1
PMU_PIN = 1 |
PMU_SOFT = 1 |
(PMU_Ext_WDT = 1 &
WDT1_SEQ_FAIL= 0)
stop
command
(from MCU)
stop
PMU_System _Modes _Cus.vsd
Figure 3-1 Power Management Unit System Modes
Active Mode
In Active Mode the Power Management Unit releases the reset of the embedded MCU and the application
software takes control of the system. Now the PMU is responsible for supplying and supervising the embedded
system only. The supervision functionality of the PMU monitors the output voltage/current of the generated
supplies and the status information of the system watchdog (WDT1).
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TLE983x
Power Management
Under normal operating conditions (exceptions see Chapter Power Control Unit - Fail Safe Scenarios) the
power save modes are set by the user software only. The PMU gets the respective command; sleep, stop and
slow down by setting the corresponding bit in the Power Mode Control Register (PMCON0). After a certain time
delay the corresponding ready signal will follow. The user software has to write the command to the power mode
control register (PMCON0) of the SCU. As a consequence the SCU sends the MCU in data retention mode and
accepts this with the respective ready signal.
Sleep Mode
The Sleep Mode is the power saving mode where the lowest power consumption is achieved. In this mode the
PMU resets all system functionalities and switches off all voltage supplies (VDDP, VDDC, VDD5_EXT) which are
generated in the PMU. The only submodules of the PMU which stay active are the ones responsible for controlling
the wake-up procedure of the system. Figure 3-2 shows the Sleep Mode entry procedure.
PMCON0
xxh
02h
CLK_100KHz
CLK_20MHz
VDDC
1. 5V
SYSTEM_STATE
Active
Sleep
Figure 3-2 Sleep Mode Entry Timing
The Sleep Mode is terminated by a LIN dominant pulse or a corresponding (rising edge / falling edge) activity at
one of the enabled MON inputs (up to five). These events are triggered outside of the PMU. The PMU itself
processes the wake-up information in an independent FSM which starts the PMU internal system clock to process
the following startup sequences in a synchronous way. A successful startup sequence enters the startup Mode
automatically. The wake-up procedure described is the default setup of the PMU.
The Sleep Mode can be terminated by synchronous wake-up events too. If this is desired, the PMU must be
configured by setting the corresponding XSFRs. A synchronous wake-up can be configured using the Cyclic
Sense and Cyclic Wake feature. If these synchronous wake-up events are configured then the power consumption
of the PMU increases in Sleep Mode. The increased current consumption is caused by an oscillator which
generates the needed time base (typ. 100 kHz). If Cyclic Sense is configured then the PMU may periodically
activate the High Side switches. This current source may bias the switches which are connected to MON pins.
Figure 3-3 illustrates the wake-up procedure via LIN.
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TLE983x
Power Management
LIN_WAKE
LP_CLK
VDDP
5V
3V
VDDC
1.5V
fail
SUPPLY _STATUS
ok
stable
RESET _PIN
PMU_RST_STS
xxh
SYSTEM_STATE
Sleep
Start-up
04h
Active
Figure 3-3 Sleep Mode LIN Wake-up Timing
The wake-up procedure from Sleep Mode via MONx pins (instead of LIN) follows the same sequence as shown
in the figure above.
Stop Mode
The objective of the Stop Mode is to provide a data retention feature for the embedded MCU and the special
function registers (XSFRs). In the Stop Mode the core supply voltage VDDC goes from 1.5 V to 0.9 V with the
objective to reduce leakage current as much as possible. During the Stop Mode the dynamic behavior (load jumps)
of the PMU internally generated voltage supplies are very limited. The corresponding limitation is given by the
external buffer capacitor at the VDDC/VDDP pin. In case of a 330 nF buffer capacitor at VDDC the allowable load
jump is 300µA/ms. The figure below shows the Stop Mode entry sequence.
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TLE983x
Power Management
PMCON0
xxh
04h
LP_CLK2
LP_CLK
VDDC
1.5V
0.9V
SWITCHABLE SUPPLY
1.5V
SYSTEM_STATE
Active
Stop
Figure 3-4 Stop Mode Entry Timing
The wake-up features to terminate the Stop Mode are equivalent to those which are used for Sleep-exit. The
asynchronous wake-up works using a LIN message or an event (rising edge/falling edge) at one of the MON
inputs. In addition to the asynchronous wake-up over high-voltage inputs (MONs) the Stop Mode terminates by an
event at one of the GPIO pins. The wake-up configuration of every MON and GPIO input is stored in the
corresponding XSFR. The configuration for the high-voltage inputs (MONs) are used for Stop-exit and Sleep-exit
(same XSFR). Generally the synchronous wake-up features are equivalent to the Sleep Mode exit. The Stop Mode
terminates by using one of the synchronous wake-up features. The synchronous wake-up features are separated
in Cyclic Sense and wake-up after time-out (Cyclic Wake). Both of these wake-up procedures work similarly to the
Sleep-exit. In Cyclic Sense mode, both the MONx inputs as well as the GPIOs can be evaluated and a transition
will cause a termination of the Stop Mode. The sensing period for MONx inputs and GPIOs is generated with the
same time base (typ. 100 kHz). The sensing period is set in the CNF_CYC_SENSE. To bias the external load of
the GPIOs, the supply voltage VDDEXT may switch on for the sensing time. Only during this sensing time the PMU
evaluates the corresponding GPIO. In case of a valid wake-up signal the PMU goes to Active Mode and the
application software takes control over the system. If no valid wake-up information is available, then the external
supply VDDEXT switches off until the configured sensing period starts again.
User’s Manual
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TLE983x
Power Management
3.1.1
Structure of the Power Management Unit
3.1.1.1
PMU Submodules
VS
Figure 3-5 shows the structure of the Power Management Unit. Table 3-1 describes the submodules more
detailed.
Power Down Supply
VDDP
Power Supply Generation
(PSG)
e.g. for WDT1
e.g. for cyclic
wake and
sense
VDDC
CLK_20MHz
Peripherals
External VREG
CLK_100KHz
I
N
T
E
R
N
A
L
PMU-XSFR
B
U
S
VDD_EXT
PMU-CYCMU
PMU-CMU
PMU-PCU
PMU-RMU
MON 1... 5
LIN
PMU-WMU
P0.0….P0.5
P1.0….P1.5
PMU-Control
Power Management Unit
Figure 3-5 Power Management Unit Block Diagram
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Table 3-1
Description of PMU Submodules
Mod.
Name
Modules
Functions
Power Down
Supply
Independent Supply Voltage
Generation for PMU
This supply is only dedicated to the PMU to ensure an
independent operation from generated power supplies
(VDDP, VDDC).
LP_CLK
(= 20 MHz)
- Clock Source for all PMU
submodules
- Backup Clock Source for System
- Clock Source for WDT1
This ultra low power oscillator generates the clock for the
PMU.
This clock is also used as backup clock for the system in
case of PLL Clock failure and as independent clock source
for WDT1.
LP_CLK2
(= 100 kHz)
Clock Source for PMU
This ultra low power oscillator generates the clock for the
PMU mainly in Stop Mode and in the cyclic modes.
Peripherals
Peripheral Blocks of PMU
These blocks include all relevant peripherals to ensure a
stable and fail safe PMU startup and operation.
Power Supply
Generation
Unit (PGU)
Voltage regulators for VDDP and
VDDC
This block includes the voltage regulators for the pad
supply (VDDP) and the core supply (VDDC) including all
diagnosis and safety features.
VDDEXT(Hall
Sensor
Supply)
Voltage regulator for VDDEXT to
supply external modules (e.g. Hall
Sensors)
This voltage regulator is a dedicated supply for external
modules and can also be used for cyclic sense operations
(e.g. with hall sensor).
PMU-XSFR
All PMU relevant Extended Special
Function Registers
This module contains all PMU relevant registers, which
are needed to control and monitor the PMU.
PMU-PCU
Power Control Unit of the PMU
This block is responsible for controlling all power related
actions within the PGU Module.
PMU-WMU
Wake-up Management Unit of the
PMU
This block is responsible for controlling all Wake-up
related actions within the PMU Module.
PMU-CYCMU
Cyclic Management Unit of the PMU This block is responsible for controlling all actions within
cyclic mode.
PMU-CMU
Clock Management Unit of the PMU This block is responsible for controlling complete clocking
within the PMU.
PMU-RMU
Reset Management Unit of the PMU This block is responsible for generating all system
required resets.
3.1.2
Power Supply Generation (PSG)
As shown in the diagram below the Power Supply Generation consists of the following modules:
Submodules of PSG are:
•
•
•
•
•
Power Down Supply: independent analog supply voltage generation for Power Control Unit logic, for VDDP
Regulator and for VDDC Regulator.
VPRE: analog supply voltage pre-regulator. Purpose of this regulator is the power dissipation reduction for the
following regulator stages.
VDDP: 5V digital voltage regulator used for internal modules and all GPIOs.
VDDC: 1.5V digital voltage regulator used for internal microcontroller modules and core logic.
PCU: Power Control Unit responsible for supervising and controlling 5V regulator and 1.5V regulator.
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VS
VPRE
VDDP
VDDP
5V
Power Down Supply
CVDDP
VSSP
VDDC
VDDC
1.5V
PMU-PCU
C VDDC
VSSC
Power Supply Generation
(PSG)
Power Supply Generation
Figure 3-6 Power Supply Generation Block Diagram
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3.1.2.1
Voltage Regulator 5.0V (VDDP)
Features
•
•
•
•
•
•
•
•
5 V low-drop voltage regulator
Current limitation
Overcurrent Monitoring and Shutdown with MCU signalling (Interrupt)
Overvoltage monitoring with MCU signalling (Interrupt)
Undervoltage / Overload monitoring with MCU signalling (Interrupt)
Pre-regulator for VDDC Regulator
GPIO Supply
Pull-Down Current Source at the output for Sleep Mode only (100 μA)
3.1.2.1.1
Functional Description
This module represents the 5 V voltage regulator, which serves as pad supply for the 8-bit µC and other 5 V analog
functions (e.g. LIN Transceiver).
The output capacitor CVDDP is mandatory to ensure a proper regulator functionality.
VDDP Regulator
VDDP-5V
VS
CVS
C VDDP
5V LDO
PMU_5V_OVERVOLT
PMU_5V_OVERCURR
PMU_5V_OVERLOAD
Supervision
Figure 3-7 Module Block Diagram of VDDP Voltage Regulator
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3.1.2.2
Voltage Regulator 1.5V (VDDC)
Features
•
•
•
•
•
•
•
1.5 V low-drop voltage regulator
Optional 0.9 V in Stop Mode
Current limitation
Overcurrent monitoring and shutdown with MCU signalling (interrupt)
Overvoltage monitoring with MCU signalling (interrupt)
Undervoltage / Overload monitoring with MCU signalling (interrupt)
Pull-Down current source at the output for Sleep Mode only (100 μA)
3.1.2.2.1
Functional Description
This module represents the 1.5 V voltage regulator, which serves as core supply for the 8-bit µC and other chip
internal analog 1.5 V functions (e.g. 8 Bit ADC). To further reduce the current consumption of the 8-bit MCU during
Stop Mode the output voltage can be lowered to 0.9 V.
The output capacitor CVDDC is mandatory to ensure a proper regulator functionality.
VDDC Regulator
VDDC-1.5V
VDDP-5V
CVDDP
CVDDC
1.5 / 0.9V
LDO
PMU_1V5_OVERVOLT
PMU_1V5_OVERCURR
PMU_1V5_OVERLOAD
Supervision
Figure 3-8 Module Block Diagram of VDDC Voltage Regulator
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3.1.2.3
Register Definition
Table 3-2
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
01H
00xx 00xxB
Register Definition, Power Supply Generation Register
PMU_SUPPLY_STS
Voltage Reg Status Register
The registers are addressed bytewise.
3.1.2.3.1
Power Supply Generation Register
The following register is dedicated to control the voltage regulators VDDP, VDDC. It provides an overview about
the status of the two voltage supplies.
Voltage Reg Status Register
The PMU_SUPPLY_STS register shows the overvoltage and overload condition of VDDP and VDDC. To use this
information as interrupt sources it must be selected explicitly in this register. The register is reset by
RESET_TYPE_0.
PMU_SUPPLY_STS
Voltage Reg Status Register
Offset
Reset Value
01H
00xx 00xxB
7
6
5
4
3
2
1
0
Res
PMU_5V_
FAIL_EN
PMU_5V_
OVERLOA
D
PMU_5V_
OVERVOL
T
Res
PMU_1V5
_FAIL_E
N
PMU_1V5
_OVERLO
AD
PMU_1V5
_OVERVO
LT
r
rw
r
r
r
rw
r
r
Field
Bits
Type
Description
Res
7
r
Reserved
Always read as 0
PMU_5V_FAIL_EN
6
rw
Enabling of VDDP status information as interrupt
source
0B
No interrupts are generated
1B
Interrupts are generated
PMU_5V_OVERLOAD
5
r
Overload at VDDP regulator
0B
No overload
1B
Overload
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Field
Bits
Type
Description
PMU_5V_OVERVOLT
4
r
Overvoltage at VDDP regulator
0B
No overvoltage
1B
Overvoltage
Res
3
r
Reserved
Always read as 0
PMU_1V5_FAIL_EN
2
rw
Enabling of VDDC status information as interrupt
source
0B
No interrupts are generated
1B
Interrupts are generated
PMU_1V5_OVERLOAD
1
r
Overload at VDDC regulator
0B
No overload
1B
Overload
PMU_1V5_OVERVOLT
0
r
Overvoltage at VDDC regulator
0B
No overvoltage
1B
Overvoltage
3.1.3
Power Control Unit
The Power Control Unit is the controlling instance of the system power supply generation (PSG). It offers some
important fail safe features, which will be described in the next chapter.
3.1.3.1
Power Control Unit - Fail Safe Scenarios
The PMU handles several different failure scenarios, listed below and described in the following chapters:
•
•
•
•
•
•
Fail safe mode (Sleep Mode) in case of power failure.
Fail safe mode (Sleep Mode) in case of watchdog service failure.
Fail safe mode (Sleep Mode) in case of overcurrent on voltage regulators VDDP or VDDC.
2 level monitoring (prewarning and reset) of voltage regulators output voltages (VDDP, VDDC, VDDEXT).
Wake-up from Stop Mode with cyclic sense in case of VDDEXT regulator failures.
Wake-up from Stop Mode in case of hardware reset on RESET pin.
3.1.3.1.1
Power Supervision Function of PCU
The power supervision feature of the PCU is mainly responsible for monitoring the voltage regulators VDDP and
VDDC. In case of voltage regulator malfunction, the PCU restarts the voltage regulators (VDDP and VDDC). Each
time this happens the error counter “error_supp” is incremented. If the counter reaches the value 5, the PCU
supervision function will set the device into Sleep Mode. In this case the device is still wakeable by LIN and all HVMonitoring inputs.
After a wake-up, if the PMU can be successfully restarted and code execution will be possible, the user is able to
determine the occurred failure scenario by checking the corresponding SYS_FAIL_STS register. In this case bit
SUPP_TMOUT is set.
If there is a short circuit at the VDDC/VDDP voltage regulator during startup, the reset of the embedded MCU is
set and the system goes to startup mode. The error counter “error_supp” is increased by one. After this the PCU
itself tries to go to Active Mode again using the power-on sequence. If the short circuit still exists then the
procedure is repeated. This procedure will run, as already described above, only 5 times. After reaching the value
5, the PCU sends the system into Sleep Mode.
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If a successful startup after wake-up from Sleep Mode is possible, the user is able to verify the failure, by reading
the SUPP_TMOUT flag in the SYS_FAIL_STS register.
If one of these fallback procedures is started then all XSFR registers in the PMU will be reset.
3.1.3.1.2
Watchdog (WDT1) Fail Safe
The PCU supervises the failure information of the system watchdog (WDT1). In case the watchdog is not serviced
or serviced in a wrong way (in the following denominated as “not serviced Watchdog”) the MCU is reset and the
error counter “error_wdt” is increased by one. The PMU itself stays in the Active Mode and after the reset the
application software takes over the system control. If the software doesn’t service the system watchdog then the
described procedure starts again. After the watchdog is not serviced five times during one Active Mode period the
PMU sends the embedded system to Sleep Mode. The PMU detects the transition to the Sleep Mode as safety
fallback and the Sleep Mode can be terminated only by a LIN-wake or by a rising/falling edge at a MON pin. The
error counter is reset when the system is sent to Sleep Mode or Stop Mode by a corresponding software
command.
If the system can be successfully restarted, the cause of failure can be again checked by reading the
SYS_FAIL_STS register. The bit WDT1_SEQ_FAIL signals the described failure.
If one of these fallback procedures is started then all XSFR registers in the PMU will be reset.
3.1.3.1.3
Main Regulators Fail Safe
If one of the voltage regulators needs to deliver too much current, it cannot be guaranteed that the supply voltage
will stay constant and stable. In this case the overcurrent detection of VDDP and VDDC will ensure that the system
will enter Sleep Mode.
If the Overcurrent condition is gone, a wake-up can be invoked, then the system will startup and work properly.
Afterwards the corresponding failure flags PMU_1V5_OVL and PMU_5V_OVL can be checked.
3.1.3.1.4
VDDEXT Fail Safe
If VDDEXT is used in combination with the GPIOs as a current source, there are several error cases possible,
which are: Overvoltage, overload and short circuit to GND. Those error cases may lead to the generation of false
wake-up events or to missed wake-up events. To avoid these scenarios, errors on the VDDEXT voltage regulator
would automatically revive the system from Stop Mode. The errors are signalled in the WAKE_STS_FAIL register.
3.1.3.1.5
Wake-Up from Stop Mode with Reset Fail Safe
One fail safe measure to wake-up the embedded system from the Stop-Mode can be executed by hardware reset.
If there is a reset request on the reset-pin then the PMU goes to Active Mode. Simultaneously, the embedded
system gets a reset which is shown by forcing the bidirectional reset-pin. The reset-pin goes high again if the PMU
releases the MCU reset . This event is shown in the reset status register as a hard-reset together with a wake-up
reset. In case of a fail condition at one of the voltage regulators the PMU also goes to Active Mode. After that the
PMU starts the supply fail-safe procedure which is described in the Active Mode section. The described sequence
can be seen in the picture below.
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MONx
LP_CLK
VDDC
1.5V
0.9V
PMU_RST_STS
xxh
02h
RESET _PIN
SYSTEM_STATE
Stop
Active
Figure 3-9 Stop Mode Exit Timing
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3.1.3.2
Register Definition
Table 3-3
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
1CH
0000 0000B
20H
0000 0000B
Register Definition, PMU System Fail Register
SYS_FAIL_STS
System Fail Status Register
Register Definition, PMU Wake Fail Register
WAKE_STS_FAIL
Wake Status Fail Register
The registers are addressed bytewise.
3.1.3.2.1
PMU System Fail Register
This register is dedicated for the control of the PMU Peripherals
System Fail Status Register
The register is reset by RESET_TYPE_2. All flags in this register will be cleared by read.
SYS_FAIL_STS
System Fail Status Register
Offset
Reset Value
1CH
0000 0000B
7
6
5
4
3
2
1
0
Res
WDT1_SE
Q_FAIL
SYS_OT
LOSS_OF
_GND
PMU_5V_
OVL
PMU_1V5
_OVL
SUPP_TM
OUT
Res
r
rh
rh
rh
rh
rh
rh
r
Field
Bits
Type
Description
Res
7
r
Reserved
Always read as 0
WDT1_SEQ_FAIL
6
rh
External Watchdog (WDT1) Sequential Fail
Indicates that Watchdog is not serviced 5 times
0B
No Fail System working properly
1B
Sequential Watchdog Fail 5 consecutive watchdog fails
SYS_OT
5
rh
System Overtemperature Indication Flag
Indicates System Overtemperature Condition
0B
No Overtemperature System ok
1B
Overtemperature System Overtemperature
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Field
Bits
Type
Description
LOSS_OF_GND
4
rh
Loss of Ground Indication Flag
Indicates Loss of Ground Condition
0B
No Loss of Ground Ground Connection ok
1B
Loss of Ground Ground not connected
PMU_5V_OVL
3
rh
VDDP Overload Flag
Indicates Overload Condition at VDDP
0B
No Overload VDDP ok
1B
Overload VDDP Overload
PMU_1V5_OVL
2
rh
VDDC Overload Flag
Indicates Overload Condition at VDDC
0B
No Overload VDDC ok
1B
Overload Hall VDDC Overload
SUPP_TMOUT
1
rh
Supply Time Out
Indicates the status of the Main Supply (VDDP & VDDC) after a
certain time of Power-on reset
0B
Main Supply ok VDDP or VDDC are in expected range
1B
Main Supply fail VDDP or VDDC do not have stable
operating point
Res
0
r
Reserved
Always read as 0
3.1.3.2.2
PMU Wake Fail Register
This register is dedicated for the control of the PMU Peripherals
Wake Status Fail Register
The register is reset by RESET_TYPE_2.
WAKE_STS_FAIL
Wake Status Fail Register
Offset
Reset Value
20H
0000 0000B
7
3
2
1
0
Res
VDDEXTS
HORT
VDDEXTO
VERL
SUPPFAI
L
r
r
r
r
Field
Bits
Type
Description
Res
7:3
r
Reserved
Always read as 0
VDDEXTSHORT
2
r
Stop-Exit due to short circuit at the VDDEXT Supply
0B
No short circuit
1B
Short circuit
VDDEXTOVERL
1
r
Stop-Exit due to overload at the VDDEXT Supply
0B
No overload
1B
Overload
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Field
Bits
Type
Description
SUPPFAIL
0
r
Stop-Exit due to overvoltage at the VDDEXT Supply
0B
No overvoltage
1B
Module suspend enabled
3.1.4
Wake-up Management Unit (WMU)
The Wake-up Management Unit (WMU) is mainly responsible for handling the wake-up events on LIN, HVMonitoring Inputs (MON1 to MON5), Hardware reset and all GPIOs belonging to Port 0 and Port 1. Following wake
scenarios are possible:
•
•
•
•
•
Wake-up over Port 0 and Port 1 pins: they can be configured for rising edge triggered and falling edge
triggered wake-up events. This configuration can be used to wake-up the device from normal Stop Mode and
Stop Mode with cyclic sense option. To bias the GPIOs, VDDEXT as current source can be used. The wakeup feature from Sleep Mode in combination with GPIOs is not possible.
Wake-up over Hardware reset pin: It can be used to wake-up the device from Stop Mode. The wake-up
feature from Sleep Mode is not possible.
Wake-up over MONx Pins: the MONx Pins can be configured for rising edge triggered and falling edge
triggered wake-up events. This setup can be used to wake-up the device from Stop Mode with or without cyclic
sense, but also a wake-up from Sleep Mode with or without cyclic sense is possible. In this case the High Side
drivers can be used as a current source.
LIN: is a normal wake-up source and has no configuration possibilities.
Wake-up on VDDEXT fail from Stop Mode: will be performed in case of VDDEXT failures described in
Chapter Power Control Unit - Fail Safe Scenarios.
Note:
•
•
Port 2 pins cannot invoke any wake-up.
None of the GPIOs is supplied during Sleep Mode, therefore wake-up is not possible through them.
T Cyc
P0.X,
P1.X
PMU_WMU
WMU_Principle_ Customer.vsd
Figure 3-10 Block diagram of Wake-up Management Unit in Cyclic Sense mode with VDDEXT.
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3.1.4.1
Register Definition
These registers are for wake-up control of all wake-up capable general purpose inputs outputs
The WMU is fully controllable by the below listed XSFR Registers.
Table 3-4
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
WAKE_CONF_GPIOP0 Wake Configuration Port 0 Rising Edge Register
_RI
24H
0000 0000B
WAKE_CONF_GPIOP0 Wake Configuration Port 0 Falling Edge Register
_FA
25H
0000 0000B
WAKE_CONF_GPIOP1 Wake Configuration Port 1 Rising Edge Register
_RI
26H
0000 0000B
WAKE_CONF_GPIOP1 Wake Configuration Port 1 Falling Edge Register
_FA
27H
0000 0000B
WAKE_CNF_GPIO0_C
YC
Wake Port 0 Cycle Enable Register
28H
0000 0000B
WAKE_CNF_GPIO1_C
YC
Wake Port 1 Cycle Enable Register
29H
0000 0000B
PMU_WAKEUP_TIMIN
G
PMU Wake-up Timing Register
2BH
0000 0000B
Register Definition, PMU Wake Up Configuration Register
Register Definition, PMU Wake Up Status Register
WAKE_STATUS
Main wake status Register
00H
00xx xxxxB
WAKE_STS_MON
Wake Status MON Input Register
21H
0000 0000B
WAKE_STS_GPIO0
Wake Status GPIO 0 Register
22H
0000 0000B
WAKE_STS_GPIO1
Wake Status GPIO 1 Register
23H
0000 0000B
The registers are addressed bytewise.
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3.1.4.1.1
PMU Wake Up Configuration Register
This register is dedicated for the control of the PMU Peripherals
Wake Configuration Port 0 Rising Edge Register
The register is reset by RESET_TYPE_3.
WAKE_CONF_GPIOP0_RI
Offset
Reset Value
24H
0000 0000B
Wake Configuration Port 0 Rising Edge
Register
7
6
5
4
3
2
1
0
Res
GPIO0_R
I_5
GPIO0_R
I_4
GPIO0_R
I_3
GPIO0_R
I_2
GPIO0_R
I_1
GPIO0_R
I_0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Res
7:6
r
Reserved
Always read as 0
GPIO0_RI_5
5
rw
Port 0_5 Wake-up on Rising Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO0_RI_4
4
rw
Port 0_4 Wake-up on Rising Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO0_RI_3
3
rw
Port 0_3 Wake-up on Rising Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO0_RI_2
2
rw
Port 0_2 Wake-up on Rising Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO0_RI_1
1
rw
Port 0_1 Wake-up on Rising Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO0_RI_0
0
rw
Port 0_0 Wake-up on Rising Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
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Wake Configuration Port 0 Falling Edge Register
The register is reset by RESET_TYPE_3.
WAKE_CONF_GPIOP0_FA
Offset
Reset Value
25H
0000 0000B
Wake Configuration Port 0 Falling Edge
Register
7
6
5
4
3
2
1
0
Res
GPIO0_F
A_5
GPIO0_F
A_4
GPIO0_F
A_3
GPIO0_F
A_2
GPIO0_F
A_1
GPIO0_F
A_0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Res
7:6
r
Reserved
Always read as 0
GPIO0_FA_5
5
rw
Port 0_5 Wake-up on Falling Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO0_FA_4
4
rw
Port 0_4 Wake-up on Falling Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO0_FA_3
3
rw
Port 0_3 Wake-up on Falling Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO0_FA_2
2
rw
Port 0_2 Wake-up on Falling Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO0_FA_1
1
rw
Port 0_1 Wake-up on Falling Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO0_FA_0
0
rw
Port 0_0 Wake-up on Falling Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
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Wake Configuration Port 1 Rising Edge Register
The register is reset by RESET_TYPE_3.
WAKE_CONF_GPIOP1_RI
Offset
Reset Value
26H
0000 0000B
Wake Configuration Port 1 Rising Edge
Register
7
5
4
3
2
1
0
Res
GPIO1_R
I_4
GPIO1_R
I_3
GPIO1_R
I_2
GPIO1_R
I_1
GPIO1_R
I_0
r
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Res
7:5
r
Reserved
Always read as 0
GPIO1_RI_4
4
rw
Port 1_4 Wake-up on Rising Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO1_RI_3
3
rw
Port 1_3 Wake-up on Rising Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO1_RI_2
2
rw
Port 1_2 Wake-up on Rising Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO1_RI_1
1
rw
Port 1_1 Wake-up on Rising Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO1_RI_0
0
rw
Port 1_0 Wake-up on Rising Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
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Wake Configuration Port 1 Falling Edge Register
The register is reset by RESET_TYPE_3.
WAKE_CONF_GPIOP1_FA
Offset
Reset Value
27H
0000 0000B
Wake Configuration Port 1 Falling Edge
Register
7
5
4
3
2
1
0
Res
GPIO1_F
A_4
GPIO1_F
A_3
GPIO1_F
A_2
GPIO1_F
A_1
GPIO1_F
A_0
r
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Res
7:5
r
Reserved
Always read as 0
GPIO1_FA_4
4
rw
Port 1_4 Wake-up on Falling Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO1_FA_3
3
rw
Port 1_3 Wake-up on Falling Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO1_FA_2
2
rw
Port 1_2 Wake-up on Falling Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO1_FA_1
1
rw
Port 1_1 Wake-up on Falling Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
GPIO1_FA_0
0
rw
Port 1_0 Wake-up on Falling Edge enable
1B
ENABLE wake-up enabled
0B
DISABLE wake-up disabled
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Power Management
Wake Port 0 Cycle Enabled Register
The register is reset by RESET_TYPE_3.
WAKE_CNF_GPIO0_CYC
Offset
Reset Value
28H
0000 0000B
Wake Port 0 Cycle Enable Register
7
6
5
4
3
2
1
0
Res
GPIO0_C
YC_5
GPIO0_C
YC_4
GPIO0_C
YC_3
GPIO0_C
YC_2
GPIO0_C
YC_1
GPIO0_C
YC_0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Res
7:6
r
Reserved
Always read as 0
GPIO0_CYC_5
5
rw
GPIO0_5 input for cycle sense enable
1B
ENABLE input for cycle sense enabled
0B
DISABLE input for cycle sense disabled
GPIO0_CYC_4
4
rw
GPIO0_4 input for cycle sense enable
1B
ENABLE input for cycle sense enabled
0B
DISABLE input for cycle sense disabled
GPIO0_CYC_3
3
rw
GPIO0_3 input for cycle sense enable
1B
ENABLE input for cycle sense enabled
0B
DISABLE input for cycle sense disabled
GPIO0_CYC_2
2
rw
GPIO0_2 input for cycle sense enable
1B
ENABLE input for cycle sense enabled
DISABLE input for cycle sense disabled
0B
GPIO0_CYC_1
1
rw
GPIO0_1 input for cycle sense enable
1B
ENABLE input for cycle sense enabled
0B
DISABLE input for cycle sense disabled
GPIO0_CYC_0
0
rw
GPIO0_0 input for cycle sense enable
1B
ENABLE input for cycle sense enabled
0B
DISABLE input for cycle sense disabled
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Power Management
Wake Port 1 Cycle Enable Register
The register is reset by RESET_TYPE_3.
WAKE_CNF_GPIO1_CYC
Offset
Reset Value
29H
0000 0000B
Wake Port 1 Cycle Enable Register
7
5
4
3
2
1
0
Res
GPIO1_C
YC_4
GPIO1_C
YC_3
GPIO1_C
YC_2
GPIO1_C
YC_1
GPIO1_C
YC_0
r
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Res
7:5
r
Reserved
Always read as 0
GPIO1_CYC_4
4
rw
GPIO1_4 input for cycle sense enable
1B
ENABLE input for cycle sense enabled
0B
DISABLE input for cycle sense disabled
GPIO1_CYC_3
3
rw
GPIO1_3 input for cycle sense enable
1B
ENABLE input for cycle sense enabled
0B
DISABLE input for cycle sense disabled
GPIO1_CYC_2
2
rw
GPIO1_2 input for cycle sense enable
1B
ENABLE input for cycle sense enabled
0B
DISABLE input for cycle sense disabled
GPIO1_CYC_1
1
rw
GPIO1_1 input for cycle sense enable
1B
ENABLE input for cycle sense enabled
DISABLE input for cycle sense disabled
0B
GPIO1_CYC_0
0
rw
GPIO1_0 input for cycle sense enable
1B
ENABLE input for cycle sense enabled
0B
DISABLE input for cycle sense disabled
PMU Wake-up Timing Register
This register controls the wake-up filter time for Stop Mode and Sleep Mode (only LIN and MON inputs) of the
wake-up capable inputs
The register is reset by RESET_TYPE_2.
PMU_WAKEUP_TIMING
PMU Wake-up Timing Register
7
Offset
Reset Value
2BH
0000 0000B
4
3
Res
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46
2
1
0
CNF_GPIO_FT
CNF_MON
_FT
CNF_LIN
_FT
rw
rw
rw
Rev. 1.0, 2011-12-23
TLE983x
Power Management
Field
Bits
Type
Description
CNF_GPIO_FT
3:2
rw
Wake-up filter time for GPIOs
Selects the filter time for the Wake-up /cyclic sense period
00B 10_us 10 µs filter time
01B 20_us 20 µs filter time
10B 40_us 40 µs filter time
11B 5_us 5 µs filter time
CNF_MON_FT
1
rw
Wake-up filter time for Monitoring Inputs
Selects the filter time for the Wake-up /cyclic sense period
0B
20_us 20 µs filter time
1B
40_us 40 µs filter time
CNF_LIN_FT
0
rw
Wake-up filter time for LIN WAKE
Selects the filter time for the Wake-up /cyclic sense period
0B
30_us 30 µs filter time
1B
50_us 50 µs filter time
3.1.4.1.2
PMU Wake Up Status Register
Main wake status Register
The register is reset by RESET_TYPE_2.
WAKE_STATUS
Main wake status Register
7
6
Offset
Reset Value
00H
00xx xxxxB
5
4
3
2
1
0
Res
FAIL
CYC_WAK
E
GPIO1
GPIO0
MON
LIN
r
r
rh
r
r
r
rh
Field
Bits
Type
Description
Res
7:6
r
Reserved
Always read as 0
FAIL
5
r
Wake-up after VDDEXT Fail
0B
No Wake-up occurred
1B
Wake-up occurred
CYC_WAKE
4
rh
Wake-up caused by Cyclic Wake
0B
No Wake-up occurred
1B
Wake-up occurred
GPIO1
3
r
Wake-up via GPIO1 which is a logical OR
combination of all Wake_STS_GPIO1 bits
0B
No Wake-up occurred
1B
Wake-up occurred
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Power Management
Field
Bits
Type
Description
GPIO0
2
r
Wake-up via GPIO0 which is a logical OR
combination of all Wake_STS_GPIO0 bits
No Wake-up occurred
0B
1B
Wake-up occurred
MON
1
r
Wake-up via MON which is a logical OR combination
of all Wake_STS_MON bits
0B
No Wake-up occurred
1B
Wake-up occurred
LIN
0
rh
Wake-up via LIN- Message
0B
No Wake-up occurred
1B
Wake-up occurred
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Power Management
Wake Status MON Input Register
The register is reset by RESET_TYPE_2. All flags in this register will be cleared by read.
WAKE_STS_MON
Wake Status MON Input Register
7
5
Offset
Reset Value
21H
0000 0000B
4
3
2
1
0
Res
MON5_WA
KE_STS
MON4_WA
KE_STS
MON3_WA
KE_STS
MON2_WA
KE_STS
MON1_WA
KE_STS
r
rh
rh
rh
rh
rh
Field
Bits
Type
Description
Res
7:5
r
Reserved
Always read as 0
MON5_WAKE_STS
4
rh
Status of MON5
0B
No wake-up detected
1B
wake-up detected
MON4_WAKE_STS
3
rh
Status of MON4
0B
No wake-up detected
1B
wake-up detected
MON3_WAKE_STS
2
rh
Status of MON3
0B
No wake-up detected
1B
wake-up detected
MON2_WAKE_STS
1
rh
Status of MON2
0B
No wake-up detected
wake-up detected
1B
MON1_WAKE_STS
0
rh
Status of MON1
0B
No wake-up detected
1B
wake-up detected
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Power Management
Wake Status GPIO 0 Register
The register is reset by RESET_TYPE_2. All flags in this register will be cleared by read.
WAKE_STS_GPIO0
Offset
Reset Value
22H
0000 0000B
Wake Status GPIO 0 Register
7
6
5
4
3
2
1
0
Res
GPIO0_S
TS_5
GPIO0_S
TS_4
GPIO0_S
TS_3
GPIO0_S
TS_2
GPIO0_S
TS_1
GPIO0_S
TS_0
r
rh
rh
rh
rh
rh
rh
Field
Bits
Type
Description
Res
7:6
r
Reserved
Always read as 0
GPIO0_STS_5
5
rh
Status of GPIO0_5
0B
No wake-up detected
1B
wake-up detected
GPIO0_STS_4
4
rh
Status of GPIO0_4
0B
No wake-up detected
1B
wake-up detected
GPIO0_STS_3
3
rh
Status of GPIO0_3
0B
No wake-up detected
1B
wake-up detected
GPIO0_STS_2
2
rh
Status of GPIO0_2
0B
No wake-up detected
wake-up detected
1B
GPIO0_STS_1
1
rh
Status of GPIO0_1
0B
No wake-up detected
1B
wake-up detected
GPIO0_STS_0
0
rh
Status of GPIO0_0
0B
No wake-up detected
1B
wake-up detected
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Power Management
Wake Status GPIO 1 Register
The register is reset by RESET_TYPE_2. All flags in this register will be cleared by read.
WAKE_STS_GPIO1
Offset
Reset Value
23H
0000 0000B
Wake Status GPIO 1 Register
7
5
4
3
2
1
0
Res
GPIO1_S
TS_4
GPIO1_S
TS_3
GPIO1_S
TS_2
GPIO1_S
TS_1
GPIO1_S
TS_0
r
rh
rh
rh
rh
rh
Field
Bits
Type
Description
Res
7:5
r
Reserved
Always read as 0
GPIO1_STS_4
4
rh
Wake GPIO1_4
0B
No wake-up detected
1B
wake-up detected
GPIO1_STS_3
3
rh
Wake GPIO1_3
0B
No wake-up detected
1B
wake-up detected
GPIO1_STS_2
2
rh
Wake GPIO1_2
0B
No wake-up detected
1B
wake-up detected
GPIO1_STS_1
1
rh
Wake GPIO1_1
0B
No wake-up detected
wake-up detected
1B
GPIO1_STS_0
0
rh
Wake GPIO1_0
0B
No wake-up detected
1B
wake-up detected
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Power Management
3.1.5
Cyclic Management Unit (CYCMU)
The cyclic management unit is responsible for controlling the timing sequence in cyclic sense or cyclic wake
operation. The unit operates with the LP_CLK2 clock.
3.1.5.1
Cyclic Sense Mode
To select a dedicated MONx pin for cyclic sense mode, the bit MONx_CYC must be set in the corresponding
MONx_CTRL_STS register. In this configuration the wake-up information of this MON pin is only accepted during
the sensing time where the HS_CYC_ON (internal HSx_ON gating signal) is high (see Figure 3-11). The sensing
time where the enable signal is active, will be set in the CNF_CYC_SENSE and CNF_CYC_SAMPLE_DELXSFR. The flags inside CNF_CYC_SENSE register are used to configure the dead time (TDead). The
CNF_CYC_SAMPLE_DEL register is used to program the sample delay of the wake inputs and thus the on-time
(TOn)
After a valid wake-up event the startup sequence is similar to the asynchronous wake-up and the system enters
the startup Mode automatically too. If the PMU detects a wake-up during Cyclic Sense then the enable signal of
the current source (HS) stays active as long the application software doesn’t disable these signals.
Figure 3-11 illustrates the principle of the cyclic sense mode. Here a High Side switch is used as current source
together with a MONx pin as a wake-up source. The same timing flow can also be applied for cyclic operation with
VDDEXT and all GPIOs from Port 0 and Port 1 during Stop Mode.
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Power Management
TOn
TDead
Cycle Sense
MONx
LP_CLK
VDDC
1.5V
0.9V
xxh
PMU_RST_STS
02h
RESET PIN
HS_ON
HS_CYC_ON
HS_State
SYSTEM_STATE
OFF
ON
ON
OFF
Stop
Stop
Activ
e
Figure 3-11 Timing Diagram for Cyclic Sense
3.1.5.1.1
Configuration of Cyclic Sense Mode
The configuration of cyclic sense mode is shown in Figure 3-12.
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Power Management
Configure MONx for Cyclic
Sense (set
MONx_CTRL_STS)
Configure Cyclic Sense
timer (set
CNF_CYC_SENSE ==
8'hxx)
Enable cyclic sense mode
(set PMU_WAKEUP_CTRL
== 8'h08)
Enable and turn on hs
switch (HS1_CTRL ==
8'h05)
Sleep Mode
No
Wakeup has
occoured?
Yes
Execute Highside Cyclic Sense Handover
by enabling High Side Driver (HS1_CTRL
== 8'h05)
Figure 3-12 Configuration Flow of cyclic sense mode
3.1.5.2
Cyclic Wake Mode
Cyclic Wake mode provides a synchronous wake-up after a predefined time interval in Sleep Mode or Stop Mode.
Once the time interval is elapsed the PMU enters the Startup Mode and proceeds to Active Mode where the
software takes over the system control. The cyclic wake interval is set in the CNF_CYC_WAKE-XSFR.
3.1.5.3
Register Definition
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Table 3-5
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Register Definition, Cyclic Sense and Cyclic Wake Configuration Registers (CYCMU)
PMU_WAKEUP_CTRL
PMU Wake-up Control Register
08H
0000 0000B
CNF_CYC_SENSE
Dead Time Cyclic Sense Register
0AH
0000 0000B
CNF_CYC_WAKE
Dead Time Cyclic Wake Register
0BH
0000 0000B
0CH
0000 0000B
CNF_CYC_SAMPLE_D Sample Delay Cyclic Sense Register
EL
The registers are addressed bytewise.
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Power Management
3.1.5.3.1
Cyclic Sense and Cyclic Wake Configuration Registers (CYCMU)
PMU Wake-up Control Register
The register is reset by RESET_TYPE_2.
PMU_WAKEUP_CTRL
PMU Wake-up Control Register
7
Offset
Reset Value
08H
0000 0000B
4
3
2
1
0
Res
CYC_SEN
SE_EN
CYC_WAK
E_EN
EN_0V9_
N
WAKE_W_
RST
r
rw
rw
rw
rw
Field
Bits
Type
Description
Res
7:4
r
Reserved
Always read as 0
CYC_SENSE_EN
3
rw
Enabling Cyclic Sense
This bit enables the cyclic sense feature for the power
save modes.
0B
Cyclic Sense disabled
1B
Cyclic Sense enabled
CYC_WAKE_EN
2
rw
Enabling Cyclic Wake
This bit enables the cyclic wake feature for the power
save modes.
0B
Cyclic Wake disabled
1B
Cyclic Wake enabled
EN_0V9_N
1
rw
Disables the reduction of the VDDC regulator output
to 0.9 V during Stop-Mode
0B
Output voltage reduction enabled
1B
Output voltage reduction disabled
WAKE_W_RST
0
rw
Wake-up with reset execution
Enables the Stop-Exit with reset execution
0B
Stop-Exit without reset execution
1B
Stop-Exit with reset execution
Dead Time Cyclic Sense Register
The register is reset by RESET_TYPE2.
The dead time of Cyclic Sense will be configured in the CNF_CYC_SENSE.
The following formula shows how the dead time for Cyclic Sense mode will be calculated:
4 ( E1E 0 ) ⋅ (M 3M 2M1M 0 + 1) ⋅ 2ms
E1E0 represents the register flags CYC_SENSE_E01 and M3M2M1M0 represents the register flags
CYC_SENSE_M03.
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CNF_CYC_SENSE
Dead Time Cyclic Sense Register
5
Offset
Reset Value
0AH
0000 0000B
7
6
4
3
0
OSC_100
kHz_EN
Res
CYC_SENSE_E01
CYC_SENSE_M03
rw
r
rw
rw
Field
Bits
Type
Description
OSC_100kHz_EN
7
rw
100 kHz Oscillator Enable
Enables the 100 kHz Oscillator output from the PMU to
be provided to Timer 3
0B
DISABLE Oscillator output is disabled
1B
ENABLE Oscillator output is enabled
Res
6
r
Reserved
Always read as 0
CYC_SENSE_E01
5:4
rw
Exponent
00B Exponent value is 0
01B Exponent value is 1
10B Exponent value is 2
11B Exponent value is 3
CYC_SENSE_M03
3:0
rw
Mantissa
0000B Mantissa value is 0
...B
...
1111B Mantissa value is 15
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Power Management
Dead Time Cyclic Wake Register
The register is reset by RESET_TYPE2.
The dead time of Cyclic Wake will be configured in the CNF_CYC_SENSE register.
The following formula shows how the dead time for Cyclic Wake mode will be calculated:
.
4 ( E1E 0 ) ⋅ (M 3M 2M1M 0 + 1) ⋅ 2ms
E1E0 represents the register flags CYC_WAKE_E01 and M3M2M1M0 represents the register flags
CYC_WAKE_M03.
CNF_CYC_WAKE
Dead Time Cyclic Wake Register
7
6
5
Offset
Reset Value
0BH
0000 0000B
4
3
0
Res
CYC_WAKE_E01
CYC_WAKE_M03
r
rw
rw
Field
Bits
Type
Description
Res
7:6
r
Reserved
Always read as 0
CYC_WAKE_E01
5:4
rw
Exponent
00B Exponent value is 0
01B Exponent value is 1
10B Exponent value is 2
11B Exponent value is 3
CYC_WAKE_M03
3:0
rw
Mantissa
0000B Mantissa value is 0
...B
...
1111B Mantissa value is 15
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Power Management
Sample Delay Cyclic Sense Register
This register is reset by RESET_TYPE_2.
(M 3M 2 M 1M 0 + 1) ⋅ 10 μs
M3M2M1M0 represents the register flags M03.
CNF_CYC_SAMPLE_DEL
Sample Delay Cyclic Sense Register
7
Offset
Reset Value
0CH
0000 0000B
4
3
0
Res
M03
r
rw
Field
Bits
Type
Description
Res
7:4
r
Reserved
Always read as 0
M03
3:0
rw
Mantissa
0000B variable value M3M2M1M0 is 0
...B
...
1111B variable value M3M3M1M0 is 15
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Power Management
3.1.6
Reset Management Unit (RMU)
The RMU controls the reset behavior of the entire device. The master reset of the device is the power-on reset of
the PMU itself. This reset is generated by the Power Down Supply and it is released when the battery voltage (Vs)
reaches the minimum supply voltage for Active Mode. Then the PMU starts the sequence to power-up the supply
generation module which ends with the release of the MCU reset. If this status is reached then the embedded
system will work in Active Mode. This scenario is signalled by the PMU_1V5DidPOR flag in the PMU_RST_STS.
The figure below shows the power-on reset behavior.
Vs
3V
Power Down_POR_N
LP_CLK
VDDP
5V
3V
VDDC
1.5V
fail
SUPPLY_STATUS
ok
stable
RESET _PIN
PMU_RST_STS
SYSTEM_STATE
xxh
Down
Start-up
80h
Active
Figure 3-13 Power-On and Startup Behavior of Reset
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In case of a Sleep Mode exit a similar sequence used for battery ramp-up starts. If this sequence ends successfully
then the PMU also releases the reset of the MCU. From the MCU point of view there is no difference to the battery
ramp-up. Only inside of the RMU the identification bit PMU_SleepEx is set instead of the power-on identification
bit.
In the default configuration the wake-up from Stop Mode works without reset. To wake-up with reset the
corresponding XSFR bit WAKE_W_RST inside the PMU_WAKEUP_CTRL register must be configured. With this
configuration the wake-up signal sets the dedicated identification bit PMU_WAKE which can be checked by the
application software.
The third hardware related reset source is the pin-reset. The pad itself is supplied by the VDDP domain which is
available in Active Mode and Stop Mode. Therefore the reset-pin can be used in Active Mode and Stop Mode only.
Due to the bidirectional use of the pin itself the pin-reset request is gated during the execution of another reset
request (e.g. soft-reset). For this purpose the pin-reset request must be stable for more than 500 ns (see
Figure 3-11). In case of a pin-reset request during Stop Mode the PMU goes to Active Mode and sends the wakeup signal to the MCU. At this time the reset status register also gets an update by setting bit PMU_PIN, which
signals the described reset source. All other reset sources can only have an impact on the system behavior in
Active Mode.
The reset request caused by a system watchdog, which was not serviced is also processed as a hardware related
reset although this reset request is implicitly controlled by user software. The system watchdog only works in
Active Mode. In this case it expects a periodic trigger (window watchdog) from the user software. If the trigger is
missing then the PMU gets the signal that the watchdog was not serviced which sets the identification bit
PMU_ExtWDT from WDT1. After some clock cycles of the PMU internal oscillator LP_CLK the PMU resets the
MCU. The prioritization of the described reset sources is done according to the architecture and the functionality
of the embedded system itself.
The software-reset and the reset request caused by the MCU internal watchdog are controlled explicitly by user
software and can be used only in Active Mode. From the system point of view both of these reset sources have
the lowest priority. The software related reset is executed within two MCU clock cycles which is required by the
CPU architecture. The system clock of the PMU works independently of the MCU clock. Due to these system
conditions the PMU processes the software related resets asynchronously to its internal system clock. The
software-reset is flagged by the PMU_SOFT bit. The MCU internal watchdog is signalled by the PMU_IntWDT bit.
Both flags are located in the above mentioned PMU_RST_STS register.
Another reset source is the PSG module. In case the main voltage regulators (VDDP and VDDC) will fail, the
system will execute a system reset and enter Sleep Mode afterwards. This case is flagged by setting the indication
bit PMU_FAIL.
Reset types are combinations of the above described resets. The reset of an XSFR register is depending on the
corresponding reset type. Other registers (all SFRs except NMI status flags) are always reset independent of the
reset type. The figure below shows this combination of resets.
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Reset-Type 1
x
Reset-Type 2
x
Reset-Type 3
x
x
WDT_INT
SOFT
WDT_EXT
Pin-Reset
error_wdt=5
x
error_sup=5
Reset-Type 0
Sleep-Mode
SoC power-on
Power Management
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Figure 3-14 Reset Types of SFRS and XSFRS provided by the RMU
Out of these above listed resets mainly five reset types are derived:
•
•
•
•
Reset-Type 0 contains:
– PMU_1V5DidPOR: this reset is issued when the power down supply detects undervoltage
Reset-Type 1 is an OR of:
– PMU_1V5DidPOR
– PMU_FAIL: this reset is issued when the VDDC or VDDP supply have a failure
– WDT_FAIL: this reset is issued when when WDT1 is not triggered consecutively 5 times properly
Reset-Type 2 is an OR of:
– PMU_1V5DidPOR
– PMU_PIN: this reset is issued when the RESET-Pin is pulled down
– PMU_ExtWDT: this reset is a WDT1 related reset
– PMU_IntWDT: this reset is an internal WDT issued reset
– PMU_SOFT: this reset is a software related reset
– PMU_Wake: this reset is a stop wake-up related reset
– PMU_FAIL
– WDT_FAIL
Reset-Type 3 is an OR of:
– PMU_1V5DidPOR
– PMU_PIN
– PMU_ExtWDT
– PMU_IntWDT
– PMU_SOFT
– PMU_Wake
– PMU_SleepEx: this reset is a sleep wake-up related reset
– PMU_FAIL
– WDT_FAIL
Every register has its own reset type listed. In the Power Management Unit XSFRs following reset types are used:
•
•
•
•
Reset-Type 0
Reset-Type 1
Reset-Type 2
Reset-Type 3
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3.1.6.1
Register Definition
Table 3-6
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Register Definition, Reset Management Unit Registers (RMU)
PMU_RST_STS
Reset Status Register
04H
1000 0000H
PMU_RST_CTRL
Reset Control Register
05H
0000 0000H
RESPIN_BLIND_TIME
Reset Pin Blind Time Register
1BH
0000 0000H
The registers are addressed bytewise.
3.1.6.1.1
Reset Management Unit Registers (RMU)
Reset Pin Blind Time Register
The Reset Pin is a bidirectional signal. Every reset will be signaled on that pin for a few 100 ns. In order to avoid
any reset deadlock situation there is a programmable reset blind time, where no hardware pin reset will be
recognized. The reset blind time envelopes the phase, where the reset pin acts as an active reset output. The
register is reset by RESET_TYPE_2.
RESPIN_BLIND_TIME
Reset Pin Blind Time Register
Offset
Reset Value
1BH
0000 0000H
7
2
1
0
Res
RST_TFB
r
rw
Field
Bits
Type
Description
Res
7:2
r
Reserved
Always read as 0
RST_TFB
1:0
rw
Reset Pin Blind Time Selection Bits
These bits select the blind time for the reset input sampling.
00B RST_TFB_0 0,5 µs typ.
01B RST_TFB_1 1 µs typ.
10B RST_TFB_2 5 µs typ.
11B RST_TFB_3 31 µs typ.
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Power Management
Reset Status Register
The PMU_RST_STS register shows every executed reset request. The PMU writes the corresponding register bit
of an executed reset. To clear the information of the PMU_RST_STS register the user must overwrite the
corresponding bit with a logic zero. The register is reset by RESET_TYPE_0.
PMU_RST_STS
Offset
Reset Value
04H
1000 0000H
Reset Status Register
7
6
5
4
3
2
1
0
PMU_1V5
DidPOR
PMU_PIN
PMU_Ext
WDT
PMU_Int
WDT
PMU_SOF
T
PMU_Sle
epEX
PMU_WAK
E
SYS_FAI
L
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type
Description
PMU_1V5DidPOR
7
rwh
Power-On Reset Flag
0B
No Power-On reset executed
1B
Power-On reset executed
PMU_PIN
6
rwh
PIN-Reset Flag
0B
No PIN-Reset executed
1B
PIN-Reset executed
PMU_ExtWDT
5
rwh
External Watchdog Reset Flag
0B
No External Watchdog reset executed
1B
External Watchdog reset executed
PMU_IntWDT
4
rwh
Internal Watchdog Reset Flag
0B
No Internal Watchdog reset executed
1B
Internal Watchdog reset executed
PMU_SOFT
3
rwh
Soft-Reset Flag
0B
No Soft-Reset executed
1B
Soft-Reset executed
PMU_SleepEX
2
rwh
Flag which indicates a reset caused by Sleep-Exit
0B
No reset caused by Sleep-Exit executed
1B
Reset caused by Sleep-Exit executed
PMU_WAKE
1
rwh
Flag which indicates a reset caused by Stop-Exit
Note: Stop-Exit with reset must be configured explicitly in
the PMU_WAKE-UP_CTRL register1)
0B
1B
SYS_FAIL
0
rwh
No reset caused by Stop-Exit executed
Reset caused by Stop-Exit executed
Flag which indicates a reset caused by a System Fail
reported in the corresponding Fail Register
0B
No reset caused by System Fail executed
1B
Reset caused by System Fail executed
1) Otherwise this flag is not set. The flag is always set in case of pin reset in Stop Mode (in combination with the flag
PMU_PIN).
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Power Management
Reset Control Register
With the PMU_RST_CTRL register a software reset can be initiated. The register is reset by RESET_TYPE_0.
PMU_RST_CTRL
Reset Control Register
Offset
Reset Value
05H
0000 0000H
7
1
Res
PMU_SOF
T_RST
r
rw
Field
Bits
Type
Description
Res
7:1
r
Reserved
Always read as 0
PMU_SOFT_RST
0
rw
Soft-Reset Bit
0B
No Soft-Reset
1B
Soft-Reset
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Power Management
3.2
External Voltage Regulator 5.0V (VDDEXT)
3.2.1
Features
•
•
•
•
•
•
•
•
Switchable +5 V, 20 mA low-drop voltage regulator
Switch-on overcurrent blanking time in order to drive small capacitive loads
Short circuit robust
Overvoltage monitoring with MCU interrupt signalling
Undervoltage / Overload monitoring with MCU interrupt signalling
Selectable switch-on slew-rate 0.95 V/µs max. @10 mA supply current, 10 nF capacitive load
Pull-Down Current Source at the output for Sleep Mode only (100 μA)
Cyclic sense option together with GPIOs
3.2.2
Description
The external voltage regulator provides 5 V output voltage in order to supply external circuitry like LEDs, hall
sensors or potentiometers.
In case of overcurrent, which is signalled by the flag VDDEXT_SHORT, the voltage regulator will be shut down. It
can be enabled again by clearing the VDDEXT_SHORT Bit. In this case the flag VDDEXT_ENABLE remains
unchanged.
The flags VDDEXT_OVERVOLT and VDDEXT_OVERLOAD are warning flags only and do not switch off the
voltage regulator.
The switch-on overcurrent blanking time is fixed and can not be configured.
The output capacitor CVDDEXT is mandatory to ensure a proper regulator functionality.
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Power Management
VDDEXT Regulator
VDDEXT-5V
VS
CVS
CVDDEXT
VDDEXT
LDO
VDDEXT_SHORT
VDDEXT_OVERVOLT
VDDEXT_OVERLOAD
Supervision
Figure 3-15 Module Block Diagram
3.2.3
Register Definition
Table 3-7
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
02H
xxxx x000B
Register Definition, VDDEXT Control Register
VDDEXT_CTRL
VDDEXT Control
The registers are addressed wordwise.
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Power Management
3.2.3.1
VDDEXT Control Register
VDDEXT Control Register
The register is reset by RESET_TYPE_3.
The register is clocked by LP2_CLK, powered by V_PD and reset by RESET_TYPE_3.
VDDEXT_CTRL
VDDEXT Control
Offset
Reset Value
02H
xxxx x000B
7
6
5
4
3
2
1
0
VDDEXT_
STABLE
VDDEXT_
OK
VDDEXT_
OVERLO*
VDDEXT_
OVERVO*
VDDEXT_
SHORT
VDDEXT_
FAIL_EN
VDDEXT_
CYC_EN
VDDEXT_
ENABLE
r
r
r
r
rwh
rw
rw
rw
Field
Bits
Type
Description
VDDEXT_STABLE
7
r
VDDEXT Supply works inside its specified range 1
1B
VDDEXT Voltage inside of specified range
0B
VDDEXT Voltage outside of specified range
VDDEXT_OK
6
r
VDDEXT Supply works inside its specified range 2
1B
VDDEXT in low drop mode
0B
VDDEXT not in low drop mode
VDDEXT_OVERLOAD
5
r
VDDEXT Supply Overload
0B
VDDEXT not in overload condition
VDDEXT in overload condition
1B
VDDEXT_OVERVOLT
4
r
VDDEXT Supply Overvoltage
0B
VDDEXT not in overvoltage condition
1B
VDDEXT in overvoltage condition
VDDEXT_SHORT
3
rwh
VDDEXT Supply Shorted Output
0B
VDDEXT no short circuit
1B
VDDEXT short circuit
VDDEXT_FAIL_EN
2
rw
Enabling of VDDEXT Supply status information as
interrupt source
0B
VDDEXT fail interrupt are disabled
1B
VDDEXT fail Interrupt are enabled
VDDEXT_CYC_EN
1
rw
VDDEXT Supply for Cyclic Sense Enable
Note: To use VDDEXT Supply for cyclic sense the bits
VDDEXT_CYC_EN AND VDDEXT_ENABLE must
be set
0B
1B
VDDEXT_ENABLE
User’s Manual
0
rw
VDDEXT for cyclic sense disable
VDDEXT for cyclic sense enable
VDDEXT Supply Enable
0B
VDDEXT Supply disabled
1B
VDDEXT supply enabled
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System Control Unit
4
System Control Unit
The System Control Unit (SCU) supports all central control tasks of the TLE983x. The SCU is made up of the
following sub-modules:
•
•
•
•
•
•
•
•
•
•
•
•
Clock System and Control (see Section 4.1 on Page 4-69)
Reset Control (see Section 4.2 on Page 4-89)
Power Management (see Section 4.3 on Page 4-93)
Interrupt Management (see Section 4.4 on Page 4-98)
General Port Control (see Section 4.5 on Page 4-103)
Flexible Peripheral Management (see Section 4.6 on Page 4-110)
Module Suspend Control (see Section 4.7 on Page 4-111)
Watchdog Timer (see Section 4.8 on Page 4-112)
XRAM Addressing Modes (see Section 4.9 on Page 4-117)
Error Detection and Correction in Data Memory (see Section 4.10 on Page 4-117)
Miscellaneous Control (see Section 4.11 on Page 4-120)
Register Mapping (see Section 4.12 on Page 4-126)
4.1
Clock Generation Unit
The Clock Generation Unit (CGU) allows a very flexible clock generation for TLE983x. During user program
execution the frequency can be programmed for an optimal ratio between performance and power consumption.
Therefore the power consumption can be adapted to the actual application state.
The CGU of TLE983x consists of one oscillator circuit (OSC_HP), a Phase-Locked Loop (PLL) module including
an internal oscillator (OSC_PLL) and a Clock Control Unit (CCU). The CGU can convert a low-frequency
input/external clock signal to a high-frequency internal clock.
The system clock fSYS is generated out of the following selectable clocks:
•
•
•
PLL clock output fPLL
Direct clock from oscillator OSC_HP fOSC
Low precision clock fLP_CLK (HW-enabled for startup after reset and during Stop Mode wake-up sequence)
The PLL has another clock output fMI which is provided directly at the SCU-PCU interface to the PCU and its
peripherals.
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System Control Unit
CGU
PLLCON
OSC_CON
HPOSCCON
OSC_HP
fOSC
PLL
SYSCON0
f PLL
XTAL1
CMCON
fSYS
XTAL2
CCU
f LP_CLK
LP_CLK
CGU_block
Figure 3
Clock Generation Unit Block Diagram
The following sections describe the different parts of the CGU.
4.1.1
Low Precision Clock
The clock source LP_CLK is a low-precision RC oscillator (LP-OSC) with a nominal frequency of 20 MHz that is
enabled by hardware as an independent clock source for the TLE983x startup after reset and during the Stop
Mode wake-up sequence. There is no user configuration possible on fLP_CLK.
4.1.2
High Precision Oscillator Circuit (OSC_HP)
The high precision oscillator circuit, designed to work with both an external crystal oscillator or an external stable
clock source, consists of an inverting amplifier with XTAL1 as input, and XTAL2 as output.
Figure 4 shows the recommended external circuitries for both operating modes, External Crystal Mode and
External Input Clock Mode.
4.1.2.1
External Input Clock Mode
When supplying the clock signal directly, not using an external crystal and bypassing the oscillator, the input
frequency needs to be equal or greater than 4 MHz if the PLL VCO part is used.
When using an external clock signal it must be connected to XTAL1. XTAL2 is left open (disconnected).
4.1.2.2
External Crystal Mode
When using an external crystal, its frequency can be within the range of 4 MHz to 25 MHz. An external oscillator
load circuitry must be used, connected to both pins, XTAL1 and XTAL2. It consists normally of the two load
capacitances C1 and C2, for some crystals a series damping resistor might be necessary. The exact values and
related operating range are dependent on the crystal and have to be determined and optimized together with the
crystal vendor using the negative resistance method. As starting point for the evaluation, the following load cap
values may be used:
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System Control Unit
Table 3
External CAP Capacitors
Fundamental Mode Crystal Frequency (approx., MHz) Load Caps C1, C2 (pF)
4
33
8
18
12
12
16
10
20
10
25
8
VDDP
XTAL1
4 - 25
MHz
VDDP
f OSC
External Clock
Signal
OSC_HP
OSC_HP
XTAL2
C1
f OSC
XTAL1
XTAL2
C2
Fundamental
Mode Crystal
VSS
VSS
External Crystal Mode
External Input Clock Mode
ext_osc
Figure 4
TLE983x External Circuitry for the OSC_HP
4.1.3
Phase-Locked Loop (PLL) Module
This section describes the TLE983x PLL module.
The clock fPLL and fMI is generated in one of the following PLL configured modes:
•
•
•
Prescaler Mode, also called VCO Bypass Mode
Normal Mode
Freerunning Mode
4.1.3.1
Features
Following is an overview of the PLL features/functions:
•
•
•
•
•
•
•
•
Programmable clock generation PLL
Loop filter
Input frequency: fOSC = 4 to 16 MHz
VCO frequency: fVCO = 48 MHz to 160 MHz (select by range)
VCO lock detection
Oscillator run detection
Output frequency: fPLL = 46.87 kHz to 80 MHz
Provided: Fixed input divider P = 1
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System Control Unit
•
•
•
•
•
•
•
•
•
•
•
•
Provided: 4-bit feedback divider N
Provided: 2-bit output divider K2 and 1-bit output divider K1
An additional K3 output divider for fMI, which is set up by hardware based on NDIV setting
Oscillator Watchdog
Prescaler Mode
Freerunning Mode
Normal Mode
Sleep Mode, also automatically activated during device power-save mode
Glitchless switching between both K-Dividers
Glitchless switching between Normal Mode and Prescaler Mode
Internal Oscillator for oscillator watchdog
Internal Oscillator as clock source
4.1.3.2
PLL Functional Description
The following figure shows the PLL block structure.
Internal
Oscillator
f
K1Divider
IN T
M
U
X
fOS C
fR
OSC
WDG
M
U
X
f
REF
LockDetection
NDivider
K2Divider
fP LL
fK 2
fV CO
PLL_CON.
VCOBYP
fDIV
VCO
Core
PLL_CON.
OSCDISC
OSC_CON.
OSCSS
Figure 5
PDivider
fP
fK 1
P LL_block
PLL Block Diagram
The reference frequency fR can be selected to be taken either from the internal oscillator fINT or from an external
clock source fOSC.
The PLL uses up to three dividers to manipulate the reference frequency in a configurable way. Each of the three
dividers can be bypassed corresponding to the PLL operating mode (based on fPLL):
•
•
•
Bypassing P, N and K2 dividers; this defines the Prescaler Mode
Bypassing K1 divider; this defines the Normal Mode
Bypassing K1 divider and ignoring the P divider; this defines the Freerunning Mode
The PLL alternate clock output fMI uses P, N and K3 dividers independent of the PLL operating mode. The only
exception is when PLL is in Freerunning Mode where P divider is ignored. Note that even with the same setting
for K-divider, fMI is not synchronized to fPLL in terms of clock skew.
Table 4 shows the selectable clock source options.
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System Control Unit
Table 4
Clock Option Selection
VCOBYP
OSCDISC
Mode Selected
0
0
Normal Mode
1
x
Prescaler Mode
0
1
Freerunning Mode
Normal Mode
In Normal Mode the reference frequency fR is divided down by a factor P, multiplied by a factor N and then divided
down by a factor K2.
The output frequency is given by:
N
f PLL = ---------------- ⋅ f R
(1)
P ⋅ K2
The Normal Mode is selected by the following settings
•
PLL_CON.VCOBYP = 0
The Normal Mode is active when
•
•
•
•
PLL_CON.VCOBYP = 0
PLL_CON.OSCDISC = 0
PLL_CON.LOCK = 1
If fPLL is selected as the clock source for system frequency fSYS, the user should enable PLL in normal mode as
default.
In case of fMI, replace K2 with K3.
Prescaler Mode (VCO Bypass Mode)
In Prescaler Mode the reference frequency fR is only divided down by a factor K1.
The output frequency is given by
fR
f PLL = ------
(2)
K1
The Prescaler Mode is selected by the following settings
•
•
PLL_CON.VCOBYP = 1
PLL_CON.OSCDISC = 0
The Prescaler Mode is active when
•
•
•
•
PLL_CON.VCOBYP = 1
PLL_CON.OSCDISC = 0
OSC_CON.OSC2L = 0 if fOSC is provided as fR (OSC_CON.OSCSS = 01B)
In case of fMI, the formula per Normal Mode applies.
Freerunning Mode
In Freerunning Mode the base frequency output of the Voltage Controlled Oscillator (VCO) fVCObase is only divided
down by a factor K2.
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System Control Unit
The output frequency is given by
f VCObase
f PLL = --------------------
(3)
K2
The Freerunning Mode is enabled by the following settings/conditions
•
PLL_CON.VCOBYP = 0 and PLL_CON.LOCK = 0
or
•
PLL_CON.VCOBYP = 1 and OSC_CON.OSCSS = 1 and OSC_CON.OSC2L = 1
or
•
PLL_CON.VCOBYP = 0 and PLL_CON.OSCDISC = 1
The Freerunning Mode is active when
•
•
•
•
PLL_CON.VCOBYP = 0
PLL_CON.OSCDISC = 1
PLL_CON.LOCK = 0
In case of fMI, replace K2 with K3.
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System Control Unit
General Configuration Overview
The divider values and all necessary other values can be configured via the PLL configuration registers.
In TLE983x, the P factor is fixed to 1. Table 5 gives the valid output frequency range for the P divider dependent
on fR frequency range:
Table 5
P-Divider Factor = 1
P
fP for fR =
4 MHz
5 MHz
10 MHz
16 MHz
25 MHz
1
4
5
10
16
not allowed
Note: The whole range in between two fR columns in the above table is allowed. E.g. for a range fR = 10 to 16,
fP = 10 to 16 MHz.
The P-divider output frequency fP is fed to the Voltage Controlled Oscillator (VCO).The VCO is a part of PLL with
a feedback path. A divider in the feedback path (N divider) divides the VCO frequency. The fVCO range is defined
by configuration of VCOSEL.
Table 6
VCO Range
VCOSEL
fVCOmin
fVCOmax
fVCObase1)
Unit
0
48
112
approx. max. 38
MHz
1
96
160
approx. max. 76
MHz
1) fVCObase is the free running operation frequency of the PLLVCO, when no input reference clock is available.
The following table shows the possible N loop division rates and gives the valid output frequency range for fREF
depending on N and the VCO frequency range:
Table 7
N Loop Division Rates
fDIV for fVCO =
N
48
72
96
112
136
160
1)
8
6.00
9.00
12.00
14.00
not allowed
9
5.33
8.00
10.66
12.44
15.11
not
allowed1)
10
4.80
7.20
9.60
11.20
13.60
16.00
11
4.36
6.54
8.72
10.18
12.36
14.54
12
4.00
6.00
8.00
9.33
11.33
13.33
5.54
7.38
8.62
10.46
12.31
14 …17
…
…
…
…
…
18
4.00
5.33
6.22
7.55
8.88
5.05
5.89
7.16
8.42
…
…
…
…
4.00
4.66
5.66
6.66
4.48
5.44
6.40
26 …27
…
…
…
28
4.00
4.86
5.71
13
19
1)
not allowed
1)
not allowed
20 …23
24
25
1)
not allowed
Note: The whole range in between two fVCO columns in the above table is allowed.
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The N-divider output frequency fDIV is then compared with fREF in the phase detector logic, within the VCO logic.
The phase detector determines the difference between the two clock signals and accordingly controls the output
frequency of the VCO, fVCO.
Note: Due to this operation, the VCO clock of the PLL has a frequency which is a multiple of fDIV. The factor for this
is controlled through the value applied to the N-divider in the feedback path. For this reason this factor is
often called a multiplier, although it actually controls division.
The output frequency of the VCO, fVCO, is divided by K2 to provide the final desired output frequency fPLL. Table 8
shows the output frequency range depending on the K2 divisor and the VCO frequency range:
Table 8
K2 Divisor Table
fPLL for fVCO =
K2
48
72
96
112
136
160
Duty Cycle
[%]
2
24.0
36.0
48.0
56.0
68.0
80.0
50
3
16.0
24.0
32.0
37.3
45.3
53.3
46 - 54
4
12.0
18.0
24.0
28.0
34.0
40.0
50
5
9.6
14.4
19.2
22.4
27.2
32.0
48.5 - 51.5
Notes
1. The whole range in between two fvco columns in the above table is allowed.
2. For divider factors that cause duty cycles far off of 50%, not only the cycle time has to be checked, but also
the minimum clock pulse width.
For the K3-divider the same table is valid as for the K2-divider. The resultant fMI based on the K3-divider settings
apply similarly per Table 8. K3DIV setting is automatically configured by the hardware based on the NDIV setting.
Since K3DIV and K2DIV settings may differ (and even if both have the same setting), fMI and fPLL cannot be
expected to be synchronized and to have exactly the same duty cycle.
For the K1-divider the same table is valid as for the K2-divider. The only difference is that not fVCO is used as
reference, fR is used instead.
Table 9
K1 Divisor Table
fPLL for fR =
K1
5
8
16
Duty Cycle
[%]
1
5.0
8.0
16.0
40 - 60
2
2.5
4.0
8.0
50
For different source oscillator, the selection of fPLL = 24 MHz or 40 MHz is shown in Table 10.
Table 10
System Frequency
fPLL Selected
Oscillator
fOSC
N
P
K
Actual fSYS
40 MHz
On-chip
5 MHz
16
1
2
40 MHz (default)
External
10 MHz
8
1
2
40 MHz
8 MHz
10
1
2
40 MHz
On-chip
5 MHz
24
1
5
24 MHz
External
12 MHz
8
1
4
24 MHz
8 MHz
12
1
4
24 MHz
6 MHz
12
1
3
24 MHz
24 MHz
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System Control Unit
For the TLE983x, the value of P is fixed to 1. In order to obtain the required fPLL, the values of VCOSEL, N and K
can be chosen respectively by the bits VCOSEL, NDIV and KDIV (either K2DIV or K1DIV) for different oscillator
input frequency.
4.1.3.3
Oscillator Watchdog
The oscillator watchdog monitors the external incoming clock fOSC. Only incoming frequencies that are too low
(below 300 kHz) to enable a stable operation of the VCO circuit are detected.
As reference clock the internal oscillator (OSC_PLL) frequency fINT is used and therefore the internal oscillator
must be put into operation.
By setting bit OSC_CON.OSCWDTRST the detection can be restarted without a reset of the complete PLL. The
detection status output is only valid after some cycles of fINT.
4.1.3.4
PLL VCO Lock Detection
The PLL has a lock detection that supervises the VCO part of the PLL in order to differentiate between stable and
instable VCO circuit behavior. The lock detector marks the VCO circuit and therefore the output fVCO of the VCO
as instable if the two inputs fREF and fDIV differ too much. Changes in one or both input frequencies below a level
are not marked by a loss of lock because the VCO can handle such small changes without any problem for the
system. Table 11 shows values below that the lock is not lost for different input values.
Table 11
Loss of VCO Lock Definition
Maximum Allow Changing
d f DIV
------------- for
dt
fREF =
(4)
4 MHz
10 MHz
16 MHz
20 MHz
25 MHz
40 MHz
≤ 0.6
kHz/µs
≤ 3.7
kHz/µs
≤ 9.5
kHz/µs
≤ 14.9
kHz/µs
≤ 23.2
kHz/µs
≤ 59.5
kHz/µs
4.1.3.5
Internal Oscillator (OSC_PLL)
The PLL internal oscillator is used for two different purposes:
Operating the Oscillator Watchdog
The input frequency for the PLL direct from OSC_HP (XTAL), is supervised using the OSC_PLL as reference
frequency. For more information see Section 4.1.3.3.
Providing an Input Clock to the PLL
The OSC_PLL can be used as input clock for all PLL modes. This is controlled and configured via
OSC_CON.OSCSS.
OSC_PLL operates at nominal frequency of 5 MHz.
4.1.3.6
Switching PLL Parameters
The following restriction applies when changing PLL parameters via the PLL_CON register:
•
•
•
Prescaler Mode (VCO bypass) may be enabled at any time, however, it has to be ensured that the maximum
operating frequency of the device (see data sheet) will not be exceeded.
Before switching NDIV, the Prescaler Mode has to be selected.
VCOSEL and KDIV may be switched at any time, however, it has to be ensured that the maximum operating
frequency of the device will not be exceeded.
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•
•
•
•
Only one parameter should be switched at one register write operation.
Before switching the input clock source via OSC_CON.OSCSS, the Prescaler Mode has to be selected. Due
to a following potential oscillator watchdog event, the PLL may switch to Freerunning Mode. The procedure to
set up the PLL in normal operation follows that as stated in Section 4.1.3.8.
Before deselecting the Prescaler Mode, the RESLD bit has to be set and then the LOCK flag has to be
checked. Only when the LOCK flag is set again, the Prescaler Mode may be deselected.
Before changing VCOSEL, the Prescaler Mode must be selected.
4.1.3.7
Oscillator Watchdog Event or PLL Loss of Lock Detection
In case of detection of too low frequency of the external clock source fOSC, the OSC-Too-Low flag
(OSC_CON.OSC2L) is set. If enabled by NMICON.NMIOWD, a trap request to the CPU is activated
correspondingly only in these two cases: 1) When PLL is in Prescaler Mode and OSCSS = 01 selecting fOSC as
PLL input clock source and SYSCON0.SYSCLKSEL selects PLL clock output as the system frequency, or 2)
When SYSCON0.SYSCLKSEL selects fOSC as the system frequency. With these 2 cases and the OSC2L
condition, the OWD NMI flag FNMIOWD in NMISR is set.
Note: Do not restart the oscillator watchdog detection by setting bit OSC_CON.OSCWDTRST while PLL is in
Prescaler Mode, as the detection status (OSC_CON.OSC2L) takes some time to be stable.
An oscillator watchdog event normally leads to a following PLL loss-of-lock detection.
If PLL is not the system clock source (SYSCON0.SYSCLKSEL deselects PLL or PLL is in Prescaler Mode) when
the loss-of-lock is detected, only the lock flag is reset (PLL_CON.LOCK = 0). No loss-of-lock NMI is generated and
no further action is taken. Otherwise if PLL is selected as clock source for system frequency and VCOBYP = 0,
the PLL loss-of-lock NMI flag FNMIPLL in NMISR is set. If enabled by NMICON.NMIPLL, an NMI trap request to
the CPU is activated. In addition, the lock flag is reset. Note that in the first place, the LOCK flag has to be set first
before a loss-of-lock NMI request is generated. This avoids a potential PLL loss-of-lock NMI request after device
power-on reset.
On an oscillator watchdog event when PLL is in Prescaler Mode and external clock (OSC_HP) is selected as PLL
clock input; or on PLL loss-of-lock detection when PLL is in Normal Mode, the PLL will be switched to run in the
Freerunning Mode on the VCO base frequency divided by K2, which is enforced by hardware until the Prescaler
Mode is (re-)selected.
Due to the above, the PLL shall only run in Prescaler Mode when changing the PLL configuration or switching
between PLL operation modes.
4.1.3.8
Oscillator Watchdog Event or Loss of Lock Recovery
In case of oscillator watchdog NMI, user software can first check if the PLL remains locked. If not, the clock system
can be reconfigured again by executing the following sequence as the OWD NMI routine:
1. Restart the oscillator watchdog detection by setting bit OSC_CON.OSCWDTRST
2. Wait until OSC_CON.OSC2L is clear
3. When bit OSC_CON.OSC2L is cleared, then
a) The Prescaler Mode has to be selected (PLL_CON.VCOBYP = 1)
b) Setting the restart lock detection bit PLL_CON.RESLD = 1
c) Waiting until the PLL VCO part becomes locked (PLL_CON.LOCK = 1)
d) When the LOCK is set again, the Prescaler Mode can be deselected (PLL_CON.VCOBYP = 0) and normal
PLL operation is resumed.
4. Clear the OWD NMI flag FNMIOWD.
In the general case of PLL loss-of-lock or to re-configure the PLL settings, user software can try to configure the
clock system again by executing the following sequence:
1. If input clock source is from XTAL (fOSC from OSC_HP), ensure the input frequency is above threshold by
checking OSC_CON.OSC2L.
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2.
3.
4.
5.
6.
The Prescaler Mode has to be selected (PLL_CON.VCOBYP = 1)
If desired, (re-)configure the PLL divider settings.
Setting the restart lock detection bit PLL_CON.RESLD = 1
Waiting until the PLL VCO part becomes locked (PLL_CON.LOCK = 1)
When the LOCK is set again, the Prescaler Mode can be deselected (PLL_CON.VCOBYP = 0) and normal
PLL operation is resumed.
7. Clear the PLL loss-of-lock NMI flag FNMIPLL.
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4.1.4
Clock Control Unit
The Clock Control Unit (CCU) receives the clock from the PLL fPLL, or the external input clock fOSC, or the lowprecision input clock fLP_CLK. The system frequency is derived from one of these clock sources.
CCU
SYSCLKSEL
f
f
PLL
M
U
X
OSC
f LP_CLK
f SYS
CCU_block
Figure 6
Clock Inputs to Clock Control Unit
The CCU generates all necessary clock signals within the microcontroller from the system clock. It consists of:
•
•
Clock slow down circuitry
Centralized enable/disable circuit for clock control
In normal running mode, the main module frequencies (synchronous unless otherwise stated) are as follows:
•
•
•
•
System frequency, fSYS = up to 40 MHz (measurement interface clock MI_CLK is derived from this clock)
CPU clock (CCLK, SCLK) = up to 40 MHz (divide-down of NVM access clock)
NVM access clock (NVMACCCLK) = up to 40 MHz
Peripheral clock (PCLK, PCLK2, NVMCLK) = up to 40 MHz (equals CPU clock)
Some peripherals are clocked by PCLK, others clocked by PCLK2 and the NVM is clocked by both NVMCLK and
NVMACCCLK. During normal running mode, PCLK = PCLK2 = NVMCLK = CCLK. On wake-up from Stop Mode,
PCLK2 is restored similarly like NVMCLK, whereas PCLK is restored only after PLL is locked.
For optimized NVM access (read/write) with reduced wait state(s) and with respect to system requirements on
CPU operational frequency, bit field NVMCLKFAC is provided for setting the frequency factor between the NVM
access clock NVMACCCLK and the CPU clock CCLK. For details, refer to the separate NVM documentation.
For the slow down mode, the operating frequency is reduced using the slow down circuitry with clock divider
setting at the bit field CLKREL. Bit field CLKREL is only effective when slow down mode is enabled via SFR bit
PMCON0.SD bit. Note that the slow down setting of bit field CLKREL correspondingly reduces the NVMACCCLK
clock. Slow down setting does not influence the erase and write cycles for the NVM.
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ANACLKFAC
MI_CLK
Clock
Control Unit
(XTAL ) f
f
f
PCLK2
NVMCLKFAC
CLKREL
PCLK
Analog
Subsystem
Measurement
Interface
Peripherals
Peripherals
SCLK
OSC
M
U
X
PLL
LP_CLK
f
f
SYS
CCLK
CCLK
CORE
NVMCLK
NVM
NVMACCCLK
CORDIC
COREL
TLEN
Toggle
Latch
CLKOUT
LP-OSC
Watchdog
Timer
COUTS1
COUTS0
Figure 7
Clock Generation from fsys; CLKOUT Generation
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4.1.4.1
Startup Control for System Clock
Typically when the TLE983x starts up after reset, the LP_CLK is selected by hardware to provide the system
frequency fSYS. CPU runs based on this system frequency during startup operation by boot firmware (unless
otherwise specified and configured by firmware). Meanwhile, the system clock input is switched to the PLL output.
With user boot configuration, the PLL is configured with internal oscillator (5 MHz) as input, by default. User code
can modify the default PLL configuration as required.
The exception to the above is with resets that do not reset the clock system, which are watchdog timer (WDT)
reset and soft reset. With these resets, the previous user configuration of PLL and clock system is retained across
the reset.
Note: In the event the PLL fails to lock during startup operation, the LP_CLK continues to provide the system clock
input. The system clock input source is indicated by the register bit field SYSCON0.SYSCLKSEL.
4.1.5
External Clock Output
An external clock output is provided as CLKOUT. This output clock can be enabled/disabled via bit COCON.EN.
One of three clock sources (fCCLK or fSYS/n or fOSC) can be selected for output, configured via bit fields
COCON.COUTS1 and COUTS0.
If COUTS1 = 0 (independent on COUTS0), the output clock is fCCLK. Otherwise, if COUTS0 = 0, the output clock
is from oscillator output frequency; if COUTS0 = 1, the clock output frequency is chosen by the bit field COREL
which selects the n divider factor on fSYS. Under this selection, the clock output frequency can further be divided
by 2 using a toggle latch (TLEN = 1), the resulting output frequency has 50% duty cycle. See Figure 7.
4.1.6
CGU Registers
The registers of the clock generation unit for PLL and oscillator control are not affected by the watchdog timer
(WDT) reset and soft reset. Therefore the system clock configuration and frequency is maintained across these
types of reset.
Unless otherwise stated, the reset value as stated for the following registers apply only with Power-On reset,
Brown-Out reset, Hard reset, WDT1 reset or Wake-up reset.
4.1.6.1
PLL Oscillator Register
These registers control the setting and trimming of OSC_PLL, the Power Down of XTAL (OSC_HP) and the control
and status monitor of oscillator watchdog.
OSC_CON
OSC Control Register
7
Reset Value: 0001 0000B
6
5
4
3
2
1
0
OSCTRIM
[8]
0
XPD
OSC2L
OSCWDTRST
OSCSS
rw
r
rw
rh
rwh
rw
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Field
Bits
Type
Description
OSCSS
[1:0]
rw
Oscillator Source Select
00B PLL internal oscillator OSC_PLL (fINT) is selected
synchronously as fR.
01B XTAL (fOSC from OSC_HP) is selected synchronously as fR.
1XB PLL internal oscillator OSC_PLL (fINT) is selected
asynchronously as fR.
The OSCSS bit is a protected bit. When the Protection Scheme is
activated, this bit cannot be written directly. For more information on
Protection Scheme, see Section 4.11.
Note: Synchronous switching of clock source to internal oscillator is
not possible when XPD = 1 or no external clock is available
(check bit OSC2L).
Note: Use the 1X option only when the external clock is not available.
OSCWDTRST
2
rwh
Oscillator Watchdog Reset
Setting this bit will reset the OSC2L status flag to 1 and restart the
oscillator detection. This bit will be automatically reset to 0 and thus
always be read back as 0.
0B
No effect.
1B
Reset OSC2L flag and restart the oscillator watchdog of the
PLL.
OSC2L
3
rh
OSC-Too-Low Condition Flag
The Oscillator Watchdog monitors the fOSC.
0B
fOSC is above threshold.
1B
fOSC is below threshold.
On OSC-too-low detection (OSC2L: 0 →1) and VCOBYP = 1 and
OSCSS = 01, PLL switches to freerunning mode.
On above condition, and when fOSC is selected as the system clock
source, hardware switches the system clock source to PLL
(SYSCON0.SYSCLKSEL is also updated).
Note: OWD NMI request is activated on OSC-too-low condition only
in two cases: 1) when VCOBYP = 1 and OSCSS = 01 and
SYSCLKSEL selects PLL clock as system clock source; 2)
when SYSCLKSEL selects fOSC as system clock source.
XPD
4
rw
XTAL (OSC_HP) Power Down Control
0B
XTAL (OSC_HP) is not powered down.
1B
XTAL (OSC_HP) is powered down.
The XPD bit is a protected bit. When the Protection Scheme is
activated, this bit cannot be written directly. For more information on
Protection Scheme, see Section 4.11.
Note: When XPD is set, switch of clock source to internal oscillator
has to be done asynchronous.
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Field
Bits
Type
Description
OSCTRIM[8]
7
rw
OSC_PLL Trim Configuration Bit [8]
This bit field enables the trimming for the OSC_PLL.
User should always set this bit with any write.
This bit is a protected bit. When the Protection Scheme is activated,
this bit cannot be written directly. For more information on Protection
Scheme, see Section 4.11.
0
[6:5], 1
r
Reserved
Returns 0 if read.
4.1.6.2
PLL Registers
These registers control the PLL configuration or settings.
PLL_CON
PLL Control Register
7
Reset Value: 0110 0100B
6
5
4
3
2
1
0
NDIV
VCOBYP
OSCDISC
RESLD
LOCK
rw
rwh
rwh
rwh
rh
Field
Bits
Type
Description
LOCK
0
rh
PLL Lock Status Flag
0B
The frequency difference of fREF and fDIV is greater than
allowed. The VCO part of the PLL can not lock on a target
frequency.
1B
The frequency difference of fREF and fDIV is small enough to
enable a stable VCO operation.
Notes
1. In case of a loss of VCO lock the fVCO goes to the upper boundary
of the selected VCO band if the reference clock input is greater
as expected.
2. In case of a loss of VCO lock the fVCO goes to the lower boundary
of the selected VCO band if the reference clock input is lower as
expected.
3. On loss-of-lock detection (LOCK: 1 →0) and when VCOBYP = 0,
PLL switches to freerunning mode.
4. Loss-of-lock NMI request is activated only on loss-of-lock
detection when VCOBYP = 0 and SYSCON0.SYSCLKSEL
selects PLL clock as system frequency.
RESLD
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rwh
Restart Lock Detection
Setting this bit will reset the PLL lock status flag and restart the lock
detection. This bit will be automatically reset to 0 and thus always be
read back as 0.
0B
No effect.
1B
Reset lock flag and restart lock detection.
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Field
Bits
Type
Description
OSCDISC
2
rwh
Oscillator Disconnect
Oscillator is connected to the PLL
0B
1B
Oscillator is disconnected from the PLL.
By default after power-on reset, PLL is running in Freerunning Mode
(osc is disconnected).
VCOBYP
3
rwh
PLL VCO Bypass Mode Select
0B
Normal (or freerunning) operation (default)
1B
Prescaler Mode; VCO is bypassed (PLL output clock is derived
from input clock divided by K1-divider)
This bit is cleared by hardware when PLL switches to freerunning
mode.
When the bit value changes from 0 to 1, bit OSCDISC = 0.
NDIV
[7:4]
rw
PLL N-Divider
0000B
N=8
0001B
N=9
0010B
N = 10
0011B
N = 12
0100B
N = 14
0101B
N = 15
0110B
N = 16 (default)
0111B
N = 18
1000B
N = 20
1001B
N = 21
1010B
N = 22
1011B
N = 24
1100B
N = 25
1101B
N = 26
N = 27
1110B
1111B
N = 28
The NDIV bit is a protected bit. When the Protection Scheme is
activated, this bit cannot be written directly. For more information on
Protection Scheme, see Section 4.11.
CMCON
Clock Control Register
Reset Value: 00H
7
6
VCOSEL
K1DIV
K2DIV
CLKREL
rw
rw
rw
rw
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Field
Bits
Type
Description
CLKREL
[3:0]
rw
Slow Down Clock Divider for fCCLK Generation
0000B
fsys
0001B
fsys/2
0010B
fsys/3
0011B
fsys/4
0100B
fsys/8
0101B
fsys/16
0110B
fsys/24
0111B
fsys/32
1000B
fsys/48
1001B
fsys/64
1010B
fsys/96
1011B
fsys/128
1100B
fsys/192
1101B
fsys/256
1110B
fsys/384
1111B
fsys/512
This setting is effective only when the device is enabled in Slow
Down Mode.
Note: fSYS is further divided by the NVMCLKFAC factor to generate
fCCLK.
K2DIV
[5:4]
rw
PLL K2-Divider
00B K2 = 2
01B K2 = 3
10B K2 = 4
11B K2 = 5
The K2DIV bit is a protected bit. When the Protection Scheme is
activated, this bit cannot be written directly. For more information on
Protection Scheme, see Section 4.11.
Note: Depending on VCOSEL, the user has to set the K2-divider
factor large enough to ensure the PLL output frequency in
freerunning mode is never higher than that specified for the
device.
K1DIV
6
rw
PLL K1-Divider
0B
K1 = 2
1B
K1 = 1
The K1DIV bit is a protected bit. When the Protection Scheme is
activated, this bit cannot be written directly. For more information on
Protection Scheme, see Section 4.11.
VCOSEL
7
rw
VCOSEL Setting
0B
VCOSEL = 0
VCOSEL = 1
1B
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4.1.6.3
System Clock Control Registers
The clock source for the system is selected via register SYSCON0.
SYSCON0
System control Register 0
7
6
Reset Value: See Table 12
5
4
3
2
1
0
SYSCLKSEL
NVMCLKFAC
IMODE
0
0
RMAP
rwh
rw
rw
r
r
rw
Field
Bits
Type
Description
SYSCLKSEL
[7:6]
rwh
System Clock Select
This bit field defines the clock source that is used as system clock for
the system operation.
00B The PLL clock output signal fPLL is used
01B The direct clock input from fOSC is used
1XB The direct low-precision clock input from fLP_CLK is used.
The MSB of SYSCLKSEL bit field is protected such that software is
not allowed to set it to 1. However, in the unlikely event PLL fails to
lock and the LP_CLK remains as the system clock source
(SYSCLKSEL = 1XB), software is allowed to clear the MSB to 0 to
select either the PLL output or direct fOSC input.
The SYSCLKSEL bit field is a protected bit field. When the
Protection Scheme is activated, this bit field cannot be written
directly. For more information on Protection Scheme, see
Section 4.11.
Note: In normal application, it is expected that the system is running
on the PLL clock output.
NVMCLKFAC
Table 12
[5:4]
rw
NVM Access Clock Factor
This bit field defines the factor by which the system clock is divided
down, with respect to the synchronous NVMACCCLK clock.
00B Divide by 1
01B Divide by 2
The NVMCLKFAC bit is a protected bit. When the Protection
Scheme is activated, this bit cannot be written directly. For more
information on Protection Scheme, see Section 4.11.
Reset Value of Register SYSCON0
Reset Source
Reset Value
Power-On Reset/Brown-out Reset/WDT1 Reset/Wake-up
Reset/Hardware Reset
C0H
Watchdog Timer Reset/Soft Reset
U0H
(U = unchanged)
4.1.6.4
External Clock Control Register
This register controls the setting of external clock for CLKOUT.
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COCON
Clock Output Control Register
Reset Value: 00H
7
6
5
4
3
2
1
EN
COUTS1
TLEN
COUTS0
COREL
rw
rw
rw
rw
rw
0
Field
Bits
Type
Description
COREL
[3:0]
rw
Clock Output Divider
0000B
fsys
0001B
fsys/2
0010B
fsys/3
0011B
fsys/4
0100B
fsys/6
0101B
fsys/8
0110B
fsys/10
0111B
fsys/12
1000B
fsys/14
1001B
fsys/16
1010B
fsys/18
1011B
fsys/20
1100B
fsys/24
1101B
fsys/32
1110B
fsys/36
1111B
fsys/40
COUTS0
4
rw
Clock Out Source Select Bit 0
This bit is effective only if COUTS1 is set to 1.
0B
Oscillator output frequency is selected.
1B
Clock output frequency is chosen by the bit field COREL.
TLEN
5
rw
Toggle Latch Enable
Enable this bit if 50% duty cycle is desired on CLKOUT.
This bit is only applicable when both COUTS1 and COUTS0 are set
to 1.
0B
Toggle Latch is disabled. Clock output frequency is chosen by
the bit field COREL.
1B
Toggle Latch is enabled. Clock output frequency is half of the
frequency that is chosen by the bit field COREL. The resulting
output frequency has 50% duty cycle.
COUTS1
6
rw
Clock Out Source Select Bit 1
0B
fCCLK is selected.
1B
Based on setting of COUTS0.
EN
7
rw
CLKOUT Enable
0B
No external clock signal is provided
1B
The configured external clock signal is provided
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4.2
Reset Control
This section describes the types of reset and the effects of each reset on the TLE983x.
4.2.1
Types of Reset
The following reset types are recognized by the TLE983x.
•
•
•
•
•
•
•
Power-on reset
– Requested asynchronously and released by supply voltage VS reaching the upper threshold. Indication is a
direct analysis of VS undervoltage.
Brown-out reset
– Is not differentiated by system with power-on reset.
Wake-up reset
– Requested asynchronously by wake-up event during power save mode.
Hardware reset
– Requested asynchronously by event on external reset input (pin).
WDT1 reset
– Activated asynchronously by external WDT1 reset event.
SCU Watchdog Timer (WDT) reset
– Requested by WDT reset event.
Soft reset
– Requested synchronously by soft reset event.
4.2.2
Overview
When the TLE983x is first powered up or with brown-out condition triggered by supply voltage input(s) going below
the threshold, proper voltage thresholds must be reached before the MCU system starts operation with the release
of the MCU, CPU and NVM resets. With all resets (except soft and SCU watchdog timer resets), the boot
configuration is latched. The CPU starts to execute from the Boot ROM firmware with the release of MCU reset.
If the system is in power save mode, it is possible to wake-up with reset. Wake-up reset is basically equivalent to
power-on reset except that it is a ‘warm’ reset and certain settings or configuration of the system are maintained
across the reset. A wake-up via hard reset pin while in power save mode is effected as wake-up reset.
The hardware reset function via pin can be used anytime to restart the system.
The external watchdog timer (WDT1) can trigger a WDT1 reset on the system, if the timer is not refreshed before
it overflows.
Likewise, the SCU watchdog timer (WDT) can trigger a watchdog timer reset on the system if the timer is not
refreshed before it overflows.
Soft reset can be triggered by application software where applicable.
Note that the boot configuration is only latched with the power-on, brown-out, WDT1, wake-up and hardware
resets.
4.2.3
Module Reset Behavior
Table 13 gives an overview on how the various modules or functions of the TLE983x are affected with respect to
the reset type. A “n” means that the module/function is reset to its default state. Refer to Table 3 for effective reset
as priority.
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Table 13
Effect of Reset on Modules/Functions
Module/
Function
Power-On/
Brown-Out
Reset
Wake-up
Reset1)
Hardware
Reset1)
WDT1 Reset1) WDT Reset
Soft Reset
CPU Core
n
n
n
n
n
n
SCU
n
except reset
indication bit
n
n
except reset
except
indication bits indication bit
n
except reset
indication bit
n
n
except certain except certain
status bits2)
status bits2)
Peripherals
n
n
n
n
n
n
Debug System
n
n
n
n
n
n
Port Control
n
n
n
n
n
n
FW Startup
Execution
Executes all
INIT
Sleep:
Executes all
INIT;
Stop: Except
MBIST+
Executes
most INIT,
except
MBIST+
Executes
most INIT,
except
MBIST+
Skips not
required INIT
Skips not
required INIT
Sleep:
Initialized to
0;
Stop: Not
affected3)
Not affected
Not
affected3)4)
Not affected3) Not affected3)
On-Chip Static Initialized to 0
RAM
3)4)
Memory
Extension
Stack RAM
Affected
Affected
Affected
Affected
Affected
Affected
NVM
n
n
n
n
n
except
MapRAM
n
except
MapRAM
Clock System
incl. PLL
n
n
n
n
Not affected5) Not affected5)
1) MCU sub-system: Hardware reset, WDT1 reset and wake-up reset (from Stop Mode or Sleep Mode) are generally HWequivalent to power-on/brown-out reset, any exceptions are mainly due to power-on reset being a ‘cold’ start.
2) These bits include the reset requestor indication bit, the last power-on/brown-out/WDT1/wake-up reset latched boot
configuration, and NMI status flags e.g. NMISR.
3) Not affected = Reset has no direct effect on RAM contents.
4) If the reset happens during a write to SRAM, the byte in the targeted write address may be corrupted.
5) All configuration including trim settings.
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4.2.4
Functional Description of Reset Types
This section describes the definition and controls depending on the reset source.
4.2.4.1
Power-On / Brown-out Reset
Power-on reset is the highest level reset whereby the whole system is powered up and reset. Brown-out reset
occurs when any required voltage drops below its minimum threshold.
In user mode, the system clock is switched to the PLL output at the defined frequency of the device.
4.2.4.2
Wake-up Reset
Wake-up reset occurs due to enabled event on defined functional input pins leading to a reset of the device while
the device was in power-save mode. Wake-up reset from Sleep Mode and Stop Mode is differentiated by
respective indicator bits. In case of wake-up from Sleep Mode, reset is always effected.
Wake-up reset has the next highest priority after power-on/brown-out reset.
In user mode, the system clock is switched to the PLL output at the defined frequency of the device.
4.2.4.3
Hardware Reset
Hardware reset is requested asynchronously by event on external RESET input pin, and has the next highest
priority after wake-up reset.
In case of the hardware reset is applied while the device is in any power down mode, the device wakes up and
performs a Pin-Reset. This is effectively a wake-up reset.
In user mode, the system clock is switched to the PLL output at the defined frequency of the device.
For details of programming the filter time of the external RESET input pin see the corresponding reset pin blind
time register, RESPIN_BLIND_TIME.
4.2.4.4
WDT1 Reset
WDT1 reset occurs due to WDT1 timer overflow or when servicing in a closed window, and has the next highest
priority after hardware reset.
In user mode, the system clock is switched to the PLL output at the defined frequency of the device.
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4.2.4.5
WDT / Soft Reset
WDT reset occurs due to WDT timer overflow; Soft reset occurs due to software set of the soft reset request bit.
These two resets are at the same priority level (same effect on system) and have the lowest priority level. With
these resets, the device continues running on the previous clock system configuration.
4.2.5
Booting Scheme
After any power-on reset, brown-out reset, hardware reset, WDT1 reset or wake-up reset, the pins TMS, P0.0
together choose different modes. Table 14 shows the boot selection options available in the TLE983x.
Table 14
1)
TLE983x Boot Options
TMS /D
AP1
P0.0/ P0.1
DAP0
P0.2
P2.7
P2.1
MODE
0
x
x
x
x
x
User Mode / BSL Mode2)3)
1
1
x
0
x
x
OCDS Mode with DAP port2)
1
15)
x
1
x
x
OCDS Mode with DAP port2)6);
no Config Sector download (safe test mode entry)
1) When TMS is latched high (1) upon reset, DAP pins will be enabled by hardware. When TMS = 1, P0.0 must be 1. The
hardware enable of DAP pins cannot be changed by port control.
2) On-chip OSC is selected as PLL input. System running on PLL output.
3) Boot in user mode or (UART/LIN) BSL mode depends on the NAC word in user memory (NVM). Refer to BSL description
for details.
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4.3
Power Management
This section describes the features and functionality provided for power management of the device.
4.3.1
Overview
The TLE983x power-management system allows software to configure the various processing units so that they
automatically adjust to draw the minimum necessary power for the application.
There are five power modes: Active Mode, Idle Mode, Slow Down Mode, Stop Mode and Sleep Mode, as shown
in Figure 8. Sleep Mode is a special case which can only be exited with a system reset.
The operation of the system components in each of these states can be configured by software. The power modes
provide flexible reduction of power consumption through a combination of techniques, including:
•
•
•
•
•
Stopping the CPU clock
Stopping the clocks of other system components individually
Clock-speed reduction of some peripheral components
Stop Mode of the entire system with fast restart capability
Reducing or removing the power supply to power domains
set SL
bit
ACTIVE
any interrupt
& SD=0
set PD
bit
set IDLE
bit
set SD
bit
IDLE
clear SD
bit
POWER-DOWN
set PD
bit
set IDLE
bit
any interrupt
& SD=1
Figure 8
Wake-up event
& SD=0
SLOW-DOWN
SLEEP
(wake up with device reset)
Wake-up event
& SD=1
set SL
bit
Transition between Various Modes of Operation (without reset)
In Idle mode, the Core is stopped with its clock disabled. Peripherals, with respective input clocks not disabled,
are still functional. Watchdog timer, however, must be disabled by user before the system enters into Idle Mode;
otherwise, it will generate a reset when an overflow occurs and this will disrupt the Idle Mode. The Idle Mode is
terminated automatically when any enabled interrupt signal is detected.
In Slow Down mode, the clock generation unit is instructed to reduce its clock frequency so that the clock to the
system, i.e. Core and peripheral, will be divided by a programmable factor.
In Stop Mode, the clock is turned off. Hence, it cannot be awakened by an interrupt or the Watchdog Timer. It will
be awakened only when it receives an external wake-up signal or reset signal. The application must be prepared
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that the TLE983x is served with one of these signals. A wake-up circuit is used to detect enabled wake-up signal(s)
and activate the Stop Mode wake-up. During Stop Mode, this circuit remains active.
In Sleep Mode, the power supply to the whole MCU subsystem is removed. On detection of wake-up event, a
system reset is generated and the MCU is reset to default configuration then restart operation as initialized.
The priority for entry to the power-save modes starting from the highest is Sleep Mode, Stop Mode, then Idle Mode.
Slow Down Mode can be enabled concurrently with Idle Mode.
4.3.2
Functional Description
This section describes the power-save modes, their operations, and entry and exit. It also describes the respective
behavior of TLE983x system components.
4.3.2.1
Idle Mode
Software requests Idle Mode by setting the bit PCON.IDLE to 1.
The power management state machine (PMSM) posts an idle request signal to the CPU. The CPU finishes its
current operation, sends an acknowledge signal back to the PMSM, and then enters into an inactive state in which
the CPU clock (CCLK) is disabled.
The system returns to Active Mode on any of the following conditions:
•
•
An incoming interrupt request to an enabled interrupt node.
Hardware reset signal (RESET) is activated.
Interrupt to the CPU causes the CCLK to recover. Upon RETI instruction, the CPU will return to execute the next
instruction following the instruction which sets the IDLE bit to 1.
Note: The user is advised to disable watchdog timer prior to entering the Idle Mode.
4.3.2.2
Slow Down Mode
The Slow Down Mode is used to reduce the power consumption by decreasing the internal clock in the device.
The Slow Down Mode is activated by setting the bit SD in SFR PMCON0. The bit field CMCON.CLKREL is used
to select different slow down frequency. The CPU and peripherals are clocked at this lower frequency. The Slow
Down Mode is terminated by clearing bit SD.
The Slow Down Mode can be combined with the Idle Mode by performing the following sequence:
1. The Slow Down Mode is activated by setting the bit PMCON0.SD.
2. The Idle Mode is activated by setting the bit PCON.IDLE.
There are two ways to terminate the combined Idle and Slow Down Mode:
•
•
The Idle Mode can be terminated by activation of any enabled interrupt. CPU operation is resumed, and the
interrupt will be serviced. The next instruction to be executed after the RETI instruction will be the one following
the instruction that had set the bit IDLE. Nevertheless, the slow-down mode stays enabled and if required
termination must be done by clearing the bit SD in the corresponding interrupt service routine or at any point
in the program where the user no longer requires the slow-down mode.
The other possibility of terminating the combined idle and slow-down mode is with a reset.
4.3.2.3
Stop Mode
In the Stop Mode, the NVM is put into NVM shutdown mode (analog and digital except MapRAM shut down). The
5 V power supply to the analog modules ADC and PLL & internal oscillator is removed. The MCU digital and NVM
MapRAM is powered by an external low power regulator (0.9 V). All functions of the microcontroller are stopped
while the contents of the NVM, on-chip RAM, XRAM, and the SFRs are maintained. As for the external ports, all
digital pads are still powered.
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In Stop Mode, the clock is turned off. Hence, the system cannot be awakened by an interrupt or the Watchdog
Timer. It will be awakened only when it receives an external wake-up signal (with or without a following system
reset) or with reset by asserting the hard reset pin.
Software requests Stop Mode by setting the bit PMCON0.PD to 1.
Exiting Stop Mode
Stop Mode can be exited by active edge on the enabled wake-up pin(s) or by asserting the hard reset pin.
The wake-up circuitry will perform a sequence of predefined actions such as restore all supply voltages, restore
modules to operational mode including the oscillator and PLL. On stable clock per user configuration is restored,
peripheral clock gating, CPU clock gating is removed and the CPU starts to run from the instruction following the
one that sets the PD bit. It is required of user code to insert three NOP instructions following the one that sets the
PD bit.
Note that if user has selected the PLL output as system clock (typical usage) but lock status of the PLL cannot be
achieved, the device cannot wake up and shall hang in this state until a device reset.
4.3.2.4
Sleep Mode
In the Sleep Mode, the supply to the whole MCU subsystem including the ADC, PLL and NVM is removed. The
wake-up detection circuitry remains supplied. Only contents of non-volatile memory are retained. As for the
external ports, only the wake-up pads are still powered. The supply to ADC pads is removed.
Sleep Mode is always exited with a system reset, which is triggered by active edge on the enabled wake-up pin(s).
It is not possible to exit Sleep Mode by asserting the hard reset pin as the digital 5 V pads will not be powered.
Software requests Sleep Mode by setting the bit PMCON0.SL to 1.
Exiting Sleep Mode
Sleep Mode can only be exited with a system reset, triggered by active edge on the enabled wake-up pin(s).
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4.3.3
Register Description
PMCON0
Power Mode Control Register 0
7
6
Reset Value: 00H
5
4
3
2
1
0
0
SD
PD
SL
XTAL_ON
r
rw
rwh
rwh
rw
Field
Bits
Type
Description
XTAL_ON
0
rw
OSC_HP Operation in Stop Mode
0B
OSC_HP (XTAL) will be put to Stop Mode by hardware in
power save mode.
1B
OSC_HP (XTAL) continues to operate in Stop Mode, if
enabled by OSC_CON.XPD.
This provides user the option for reduced power consumption in the
Stop Mode. It must be noted that the startup time of OSC_HP can be
in the range of some milliseconds.
Alternatively for fast wake-up from Stop Mode while avoiding this
power consumption, the user can selectively enable internal
oscillator as clock source and disable OSC_HP before enable Stop
Mode.
SL
1
rwh
Sleep Mode Enable. Active High.
Setting this bit will cause the chip to go into Sleep Mode. Reset by
wake-up circuit.
The SL bit is a protected bit. When the Protection Scheme is
activated, this bit cannot be written directly. For more information on
Protection Scheme, see Section 4.11.
PD
2
rwh
Stop Mode (Power Down) Enable. Active High.
Setting this bit will cause the chip to go into a Stop Mode. Reset by
wake-up circuit.
The PD bit is a protected bit. When the Protection Scheme is
activated, this bit cannot be written directly. For more information on
Protection Scheme, see Section 4.11.
SD
3
rw
Slow Down Mode Enable. Active High.
Setting this bit will cause the chip to go into slow down mode. Reset
by user.
The SD bit is a protected bit. When the Protection Scheme is
activated, this bit cannot be written directly. For more information on
Protection Scheme, see Section 4.11.
0
[7:4]
r
Reserved
Returns 0 if read.
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PCON (Note: This register is located within XC800 core with SFR address 87H)
Power Control Register (Not bit-addressable)
7
6
5
4
Reset Value: 00H
3
2
1
0
0
0
0
0
0
IDLE
r
r
r
r
r
rw
Field
Bits
Type
Description
IDLE
0
rw
Idle Mode Enable
0B
Do not enter Idle Mode
1B
Enter Idle Mode
0
[7:1]
r
Reserved
Returns 0 if read.
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4.4
Interrupt Management
This section describes the management of interrupts by the system control unit.
4.4.1
Overview
The Interrupt Management sub-module in the SCU controls the non-core-generated interrupt requests to the core.
The core has one non-maskable interrupt (NMI) node and total 14 maskable interrupt nodes. Figure 9 shows the
block diagram of the Interrupt Management sub-module.
Maskable Interrupt
Unit
Non-Maskable
Interrupt Unit
Interrupt Management
Figure 9
Interrupt Management Block Diagram
The non-maskable interrupt unit controls the NMI requests. Incoming NMI request is not maskable and in this
sense, differs from the regular interrupts. In addition, NMI request always has the highest priority to be serviced.
In the TLE983x, eight different sources can generate a NMI: watchdog timer prewarning, PLL loss-of-lock,
oscillator watchdog event, NVM map error, Memory ECC error, NVM operation complete, OCDS user IRAM event
and supply prewarning. Some NMI sources can be triggered by one of several events. These NMI sources are
ORed to generate a NMI interrupt directly to the core. The triggering NMI sources/events are indicated in the NMI
Status Register (NMISR), and in some cases the event flags are located in the peripheral register. The NMI node
source control is via the NMI Control Register (NMICON).
There are generally 3 types of maskable inputs into the core: internal, external and extended interrupts. The
maskable interrupt unit will generate the respective interrupt node request to the core and will maintain
corresponding SCU flags and control. In general, to support all types of peripheral interrupts, an interrupt node of
the core may be shared among several interrupt sources.
4.4.1.1
Internal Interrupts
There are in total two internal interrupts, which separately come from Timer 0 and Timer 1 within the core. These
interrupt request signals are controlled directly by the interrupt flag generated within the core. These interrupts do
not go through Interrupt Management Unit in the SCU.
4.4.1.2
External Interrupts
The generation of interrupt request from an external source by edge detection in SCU is shown in Figure 10.
External interrupts can be positive, negative or double edge triggered. Register EXICON0 specifies the active
edge for the external interrupt. Among the external interrupts, external interrupt 0 and external interrupt 1 may be
selected to bypass edge detection in SCU, as direct input to the core’s NINT0 and NINT1.
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SCU
EINTx
EXINTx
NINTx
IEx
TCON
IRCONy
ITx
EXINTx
INTx
IEN0/1
TCON
EXICON0/1
Blue part exist only for external interrupt 0 and 1
Figure 10
Interrupt Request Generation of External Interrupts
4.4.1.3
Extended Interrupts
Extended interrupts are for non-core on-chip peripherals for core-external trigger of interrupt requests to the core.
There are nine such interrupt.
Interrupt signals from such on-chip peripherals are pulse triggered and active for two clock cycles. These interrupt
signals belonging to the same interrupt node will be latched as one direct interrupt request to the core. IRCONx
(where x = 0-1, 3-4) or peripheral registers hold the interrupt event flags for these extended and external interrupt
events. Corresponding bits in the Interrupt Enable Registers (IEN) within the core may block or transfer these
interrupt requests to the core interrupt controller. An enabled interrupt request is acknowledged when the core
vectors to the interrupt routine. The software routine should clear the interrupt flags in the IRCONx registers.
As there are more peripheral interrupts than interrupt nodes supported by the core, some interrupts are
multiplexed to the same interrupt node. Where possible and necessary, critical peripheral interrupts (e.g. SSC)
have their own dedicated interrupt node.
In addition, user may select one of two interrupt modes (with slightly different interrupt behavior) via the bit
SYSCON0.IMODE. Refer to Chapter 11, Interrupt System.
4.4.2
Interrupt Node Assignment
Table 15 shows the interrupt node assignment of the TLE983x.
Table 15
Interrupt Node Assignment
Interrupt
Node
Vector Address
Assignment for TLE983x
NMI
0073H
Watchdog Timer, PLL, NVM Operation Complete, OCDS, Oscillator
Watchdog, NVM map error, ECC error, Supply pre-warning
XINTR0
0003H
External Interrupt 0
XINTR1
000BH
Timer 0
XINTR2
0013H
External Interrupt 1
XINTR3
001BH
Timer 1
XINTR4
0023H
UART
XINTR5
002BH
Timer2, LIN
XINTR6
0033H
ADC
XINTR7
003BH
SSC
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Table 15
Interrupt Node Assignment (cont’d)
Interrupt
Node
Vector Address
Assignment for TLE983x
XINTR8
0043H
External Interrupt 2, MDU, Timer21
XINTR9
004BH
XINT
XINTR10
0053H
CCU6 INP0
XINTR11
005BH
CCU6 INP1
XINTR12
0063H
CCU6 INP2
XINTR13
006BH
CCU6 INP3
Interrupt Handling by SCU
EXT_ INT[1 -0]
Generate
Interrupt
Signal
NINT0 &
NINT1
Edge
Detect
EXICON 0
IRCON 0
MDU
T21
NINT0
NINT1
EXICON0
EXT_INT[2]
MDU[1:0]
T21_IRQ
Edge /
Pulse
Detect/
generate
Circuit
IREQ_N[8 ]
IRCON 0
XINT
IREQ_ N[9]
SSC
TIR
RIR
EIR
IRCON 1
IREQ_N[10]
CCU6
INP0
INP1
INP2
INP3
IREQ_N[11]
IREQ_N[12]
Interrupt pulse generator
IREQ_ N[7]
XINTR_
SRC
[13:5]
9
XINTR_
ACK
[13:5]
9
IREQ_N[13 ]
IRCON 3/4
ADC
ADCSRC[1:0]
Pulse
Detect/
generate
Circuit
IREQ_ N[6]
IRCON1
T2
LIN
T2_IRQ
EOFSYN
ERRSYN
IREQ_ N[5]
Failsave
WDT-NMI
PLL-NMI
NVM-NMI
NMI
OCDS-NMI
OWD-NMI
NMI
NMI_
ACK
NVMMAP- NMI
ECC-NMI
SUP- NMI
MICLKWDT-NMI
NMISR
Figure 11
Interrupt Node Assignment and Handling by SCU
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4.4.3
Interrupt Related Registers
Several interrupt related registers are located in the SCU.
4.4.3.1
Interrupt Event Enable Control
The two interrupt events of UART and three interrupt events of SSC module are of interrupt structure 2 which is
described in Chapter 11.2. As there is no enable/disable bit(s) for these interrupt events within the module, bits
are defined in the SCU register MODIEN to provide for this purpose.
MODIEN
Peripheral Interrupt Enable Register
7
6
5
TIEN
RIEN
0
rw
rw
r
Reset Value: C7H
4
3
r
2
1
0
RIREN
TIREN
EIREN
rw
rw
rw
r
Field
Bits
Type
Description
EIREN
0
rw
SSC Error Interrupt Enable
0B
Error interrupt is disabled
1B
Error interrupt is enabled
TIREN
1
rw
SSC Transmit Interrupt Enable
0B
Transmit interrupt is disabled
1B
Transmit interrupt is enabled
RIREN
2
rw
SSC Receive Interrupt Enable
0B
Receive interrupt is disabled
1B
Receive interrupt is enabled
RIEN
6
rw
UART Receive Interrupt Enable
0B
Receive interrupt is disabled
1B
Receive interrupt is enabled
TIEN
7
rw
UART Transmit Interrupt Enable
0B
Transmit interrupt is disabled
1B
Transmit interrupt is enabled
0
[5:3]
r
Reserved
Returns 0 if read.
Other Interrupt Related Registers
The following interrupt related registers are located in the SCU:
•
•
•
•
•
NMICON
NMISR
IRCON0, IRCON1,IRCON3, IRCON4
EXICON0
MODIEN
All registers, except MODIEN, are described in the Interrupt System Chapter 11.7.
4.4.4
NMI Event Flags Handling
Each NMI event and status flag is retained across these resets: 1) WDT reset, 2) soft reset. Specifically, these
include all the flags of NMISR register: FNMIWDT, FNMIPLL, FNMINVM, FNMIOCDS, FNMIOWD, FNMIMAP and
indirectly, FNMIECC and FNMISUP. In the case of watchdog resets, the requestor can be identified via the reset
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indicator bits WDT1RST and WDTRST. The ECC NMI is indicated by the respective event flags of SFR
EDCSTAT.IRDBE, XRDBE and NVMDBE. Likewise, the supply prewarning NMI and MI_CLK WDT NMI is
indicated by the respective event flags located in XSFR space.
These NMI event and status flags are otherwise reset to default value with all other resets i.e. power-on, brownout, hardware, WDT1 (except WDT1RST) and wakeup reset.
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4.5
General Port Control
The SCU contains control registers for the selection of:
•
•
alternate input functions of UART, Timers and External Interrupts (Section 4.5.1)
port output driver strength and temperature compensation (Section 4.5.2)
For functional description of GPIO ports, refer to Chapter 13.
4.5.1
Input Pin Function Selection
MODPISELx registers control the selection of the input pin functions. For UART, the selection of the RXD line also
enables the corresponding TXD line.
MODPISEL
Peripheral Input Select Register
Reset Value: 00H
7
6
5
4
3
2
1
0
0
URIOS
EXINT2IS
EXINT1IS
EXINT0IS
r
rw
rw
rw
rw
Field
Bits
Type
Description
EXINT0IS
[1:0]
rw
External Interrupt 0 Input Select
00B External Interrupt Input EXINT0_0 is selected.
01B External Interrupt Input EXINT0_1 is selected.
10B External Interrupt Input EXINT0_2 is selected.
11B External Interrupt Input EXINT0_3 is selected.
EXINT1IS
[3:2]
rw
External Interrupt 1 Input Select
00B External Interrupt Input EXINT1_0 is selected.
01B External Interrupt Input EXINT1_1 is selected.
10B External Interrupt Input EXINT1_2 is selected.
11B External Interrupt Input EXINT1_3 is selected.
EXINT2IS
[5:4]
rw
External Interrupt 2 Input Select
00B External Interrupt Input EXINT2_0 is selected.
01B External Interrupt Input EXINT2_1 is selected.
10B External Interrupt Input EXINT2_2 is selected.
11B External Interrupt Input EXINT2_3 is selected.
URIOS
6
rw
UART Input/Output Select
0B
UART Receiver Input RXD_0 and Transmitter Output TXD_0
is selected.
1B
UART Receiver Input RXD_1 and Transmitter Output TXD_1
is selected.
Note: To select TXD_1 as the Transmitter output, the Port ALTSELx
registers need to be configured additionally.
0
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r
Reserved
Returns 0 if read.
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MODPISEL1
Peripheral Input Select Register 1
Reset Value: 00H
7
6
5
4
3
2
1
0
T21EXCON
T2EXCON
0
T1IS
T0IS
rw
rw
r
rw
rw
Field
Bits
Type
Description
T0IS
[1:0]
rw
Timer 0 Input Select
00B Timer 0 Input T0_0 is selected.
01B Timer 0 Input T0_1 is selected.
10B Timer 0 Input T0_2 is selected.
11B Reserved
T1IS
[3:2]
rw
Timer 1 Input Select
00B Timer 1 Input T1_0 is selected.
01B Timer 1 Input T1_1 is selected.
10B Timer 1 Input T1_2 is selected.
11B Reserved
T2EXCON
6
rw
Timer 2 External Input Control
0B
Timer 2 Input T2EX is selected by bit field MODPISEL.T2EXIS.
1B
Timer 2 Input T2EX is connected to signal from analog
subsystem.
T21EXCON
7
rw
Timer 2 External Input Control
0B
Timer 21 Input T21EX is selected by bit field
MODPISEL.T2EXIS.
1B
Timer 21 Input T21EX is connected to signal from analog
subsystem.
0
[5:4]
r
Reserved
Returns 0 if read.
MODPISEL2
Peripheral Input Select Register 2
7
6
Reset Value: 00H
5
4
3
2
1
0
T21EXIS
T2EXIS
T21IS
T2IS
rw
rw
rw
rw
Field
Bits
Type
Description
T2IS
[1:0]
rw
Timer 2 Input Select
00B Timer 2 Input T2_0 is selected.
Others: Reserved
T21IS
[3:2]
rw
Timer 21 Input Select
00B Timer 21 Input T21_0 is selected.
01B Timer 21 Input T21_1 is selected.
10B Timer 21 Input T21_2 is selected.
11B Reserved.
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Field
Bits
Type
Description
T2EXIS
[5:4]
rw
Timer 2 External Input Select
00B Timer 2 Input T2EX_0 is selected.
01B Timer 2 Input T2EX_1 is selected.
Others: Reserved
Note: This selection takes effect only when
MODPISEL1.T2EXCON = 0.
T21EXIS
[7:6]
rw
Timer 21 External Input Select
00B Timer 21 Input T21EX_0 is selected.
01B Timer 21 Input T21EX_1 is selected.
10B Timer 21 Input T21EX_2 is selected.
11B Timer 21 Input T21EX_3 is selected.
Note: This selection takes effect only when
MODPISEL1.T21EXCON = 0.
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4.5.2
Port Output Control
Px_POCONy registers controls the output driver strength for each of the bidirectional port pins through the bit field
PDMn, where x denotes the port number and n denotes the pin number.
P0_POCON0
Port Output Control Register
7
Reset Value: 11H
6
5
4
3
2
1
0
PDM1
0
PDM0
r
rw
r
rw
Field
Bits
Type
Description
PDMn
(n = 0 - 1)
[2:0] or
[6:4]
rw
P0.n Port Driver Mode
Code Driver Strength1) and Edge Shape2)
000B Strong driver and sharp edge mode
001B Strong driver and medium edge mode
010B Strong driver and soft edge mode
011B Weak driver
100B Medium driver
101B Medium driver
110B Medium driver
111B Weak driver
0
7, 3
r
Reserved
Returns 0 if read.
0
1) Defines the current the respective driver can deliver to the external circuitry.
2) Defines the switching characteristics to the respective new output driver. This also influences the peak currents through
the driver when producing an edge, i.e. when changing the output level.
P0_POCON1
Port Output Control Register
7
Reset Value: 11H
6
5
4
3
2
1
0
PDM3
0
PDM2
r
rw
r
rw
Field
Bits
Type
Description
PDMn
(n = 2 - 3)
[2:0] or
[6:4]
rw
P0.n Port Driver Mode
Code Driver Strength1) and Edge Shape2)
000B Strong driver and sharp edge mode
001B Strong driver and medium edge mode
010B Strong driver and soft edge mode
011B Weak driver
100B Medium driver
101B Medium driver
110B Medium driver
111B Weak driver
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Field
Bits
Type
Description
0
7, 3
r
Reserved
Returns 0 if read.
1) Defines the current the respective driver can deliver to the external circuitry.
2) Defines the switching characteristics to the respective new output driver. This also influences the peak currents through
the driver when producing an edge, i.e. when changing the output level.
P0_POCON2
Port Output Control Register
7
6
Reset Value: 11H
5
4
3
2
1
0
PDM5
0
PDM4
r
rw
r
rw
Field
Bits
PDMn
(n = 4 - 5)
[2:0] or rw
[6:4]
Type
P0.n Port Driver Mode
Code Driver Strength1) and Edge Shape2)
000B Strong driver and sharp edge mode
001B Strong driver and medium edge mode
010B Strong driver and soft edge mode
011B Weak driver
100B Medium driver
101B Medium driver
110B Medium driver
111B Weak driver
0
7, 3
Reserved
Returns 0 if read; should be written with 0.
r
0
Description
1) Defines the current the respective driver can deliver to the external circuitry.
2) Defines the switching characteristics to the respective new output driver. This also influences the peak currents through
the driver when producing an edge, i.e. when changing the output level.
P1_POCON0
Port Output Control Register
7
6
Reset Value: 11H
5
4
3
2
1
0
PDM1
0
PDM0
r
rw
r
rw
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Field
Bits
Type
Description
PDMn
(n = 0 - 1)
[2:0] or
[6:4]
rw
P1.n Port Driver Mode
Code Driver Strength1) and Edge Shape2)
000B Strong driver and sharp edge mode
001B Strong driver and medium edge mode
010B Strong driver and soft edge mode
011B Weak driver
100B Medium driver
101B Medium driver
110B Medium driver
111B Weak driver
0
7, 3
r
Reserved
Returns 0 if read.
1) Defines the current the respective driver can deliver to the external circuitry.
2) Defines the switching characteristics to the respective new output driver. This also influences the peak currents through
the driver when producing an edge, i.e. when changing the output level.
P1_POCON1
Port Output Control Register
7
Reset Value: 11H
6
5
4
3
2
1
0
PDM3
0
PDM2
r
rw
r
rw
Field
Bits
Type
Description
PDMn
(n = 2 - 3)
[2:0] or
[6:4]
rw
P1.n Port Driver Mode
Code Driver Strength1) and Edge Shape2)
000B Strong driver and sharp edge mode
001B Strong driver and medium edge mode
010B Strong driver and soft edge mode
011B Weak driver
100B Medium driver
101B Medium driver
110B Medium driver
111B Weak driver
0
7, 3
r
Reserved
Returns 0 if read.
0
1) Defines the current the respective driver can deliver to the external circuitry.
2) Defines the switching characteristics to the respective new output driver. This also influences the peak currents through
the driver when producing an edge, i.e. when changing the output level.
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P1_POCON2
Port Output Control Register
7
6
Reset Value: 01H
5
4
3
2
1
0
PDM4
r
rw
Field
Bits
Type
Description
PDM4
[2:0]
rw
P1.4 Port Driver Mode
Code Driver Strength1) and Edge Shape2)
000B Strong driver and sharp edge mode
001B Strong driver and medium edge mode
010B Strong driver and soft edge mode
011B Weak driver
100B Medium driver
101B Medium driver
110B Medium driver
111B Weak driver
0
[7:3]
r
Reserved
Returns 0 if read.
0
1) Defines the current the respective driver can deliver to the external circuitry.
2) Defines the switching characteristics to the respective new output driver. This also influences the peak currents through
the driver when producing an edge, i.e. when changing the output level.
The TCCR register controls the temperature compensation of all the output port pins with strong drivers, i.e. on a
device level. The TCCR register has no effect on output port pIns that operate in the weak and medium driver
modes.
TCCR
Temperature Compensation Control Register
7
6
5
Reset Value: 03H
4
3
2
1
0
0
TCC
r
rw
Field
Bits
Type
Description
TCC
[1:0]
rw
Temperature Compensation Control
The slew rate of the output driver is kept stable over the selected
temperature range:
00B TJ: -40 °C to 0 °C
01B TJ: 0 °C to 40 °C
10B TJ: 40 °C to 80 °C
11B TJ: 80 °C to 150 °C
0
[7:2]
r
Reserved
Returns 0 if read.
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4.6
Flexible Peripheral Management
The Flexible Peripheral Management sub-module provides the system designer greater control on the operational
status of each individual peripheral. Peripherals which are not required for a particular functionality can be disabled
by programming the assigned register bits which would gate off the clock inputs. This would further reduce overall
power consumption of the microcontroller.
Each register bit controls one peripheral. When this bit is set, the request signal to gate the peripheral clock is
activated. The peripheral will then synchronize the gating off of the clock to the peripheral.
4.6.1
Peripheral Management Registers
PMCON1
Peripheral Management Control Register 1
7
6
Reset Value: 00H
5
4
3
2
1
0
0
MDU_DIS
T21_DIS
T2_DIS
CCU_DIS
SSC_DIS
ADC_DIS
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
ADC_DIS
0
rw
ADC Disable Request. Active high.
0B
ADC is in normal operation. (default)
1B
Request to disable the ADC.
SSC_DIS
1
rw
SSC Disable Request. Active high.
0B
SSC is in normal operation. (default)
1B
Request to disable the SSC.
CCU_DIS
2
rw
CCU Disable Request. Active high.
0B
CCU is in normal operation. (default)
1B
Request to disable the CCU.
T2_DIS
3
rw
T2 Disable Request. Active high.
0B
T2 is in normal operation. (default)
1B
Request to disable the T2.
T21_DIS
4
rw
T21 Disable Request. Active high.
0B
T21 is in normal operation. (default)
1B
Request to disable the T21.
MDU_DIS
5
rw
MDU Disable Request. Active high.
0B
MDU is in normal operation. (default)
1B
Request to disable the MDU.
0
[7:6]
r
Reserved
Returns 0 if read.
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4.7
Module Suspend Control
When the On-Chip Debug Support (OCDS) is in Monitor Mode (MMCR2.MODE = 1) and the Debug-Suspend
signal is active (MMCR2.DSUSP = 1), timers in certain modules in TLE983x can be suspended based on the
settings of their corresponding module suspend bits in register MODSUSP. When suspended, only the timer stops
counting as the counter input clock is gated off. The module is still clocked so that module registers are accessible.
MODSUSP
Module Suspend Control Register
7
6
WDT1SUSP
0
rw
r
5
r
Reset Value: 81H
4
3
2
1
0
T21SUSP
T2SUSP
T13SUSP
T12SUSP
WDTSUSP
rw
rw
rw
rw
rw
Field
Bits
Type
Description
WDTSUSP
0
rw
SCU Watchdog Timer Debug Suspend Bit
0B
WDT will not be suspended.
1B
WDT will be suspended.
T12SUSP
1
rw
Timer 12 Debug Suspend Bit
0B
Timer 12 in Capture/Compare Unit will not be suspended.
1B
Timer 12 in Capture/Compare Unit will be suspended.
When suspended, additionally the T12 PWM outputs are set to
inactive level and capture inputs are disabled.
T13SUSP
2
rw
Timer 13 Debug Suspend Bit
0B
Timer 13 in Capture/Compare Unit will not be suspended.
1B
Timer 13 in Capture/Compare Unit will be suspended.
When suspended, additionally the T13 PWM output is set to inactive
level.
T2SUSP
3
rw
Timer2 Debug Suspend Bit
0B
Timer2 will not be suspended.
1B
Timer2 will be suspended.
T21SUSP
4
rw
Timer21 Debug Suspend Bit
0B
Timer21 will not be suspended.
1B
Timer21 will be suspended.
WDT1SUSP
7
rw
Watchdog Timer 1 Debug Suspend Bit
0B
WDT1 will not be suspended.
1B
WDT1 will be suspended.
0
5, 6
r
Reserved
Returns 0 if read.
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4.8
Watchdog Timer
There are two watchdog timers in the system: SCU Watchdog Timer (WDT) within TLE983x, and external
watchdog timer (WDT1). The description in this section refers to the SCU WDT.
The Watchdog Timer is a sub-module in the System Control Unit (SCU). The Watchdog Timer (WDT) provides a
highly reliable and secure way to detect and recover from software or hardware failures. The WDT helps to abort
an accidental malfunction of the TLE983x in a user-specified time period. When enabled, the WDT will cause the
TLE983x system to be reset if the WDT is not serviced within a user-programmable time period. The CPU must
service the WDT within this time interval to prevent the WDT from causing an TLE983x system reset. Hence,
routine service of the WDT confirms that the system is functioning properly.
The WDT is by default disabled.
In debug mode, the WDT is default suspended and stops counting (its debug suspend bit is default set i.e.,
MODSUSP.WDTSUSP = 1). Therefore during debugging, there is no need to refresh the WDT.Section 4.7
Features
•
•
•
•
16-bit Watchdog Timer
Programmable reload value for upper 8 bits of timer
Programmable window boundary
Selectable input frequency of fPCLK/2 or fPCLK/128
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4.8.1
Functional Description
The Watchdog Timer is a 16-bit timer, which is incremented by a count rate of fPCLK/2 or fPCLK/128. This 16-bit timer
is realized as two concatenated 8-bit timers. The upper 8 bits of the Watchdog Timer can be preset to a userprogrammable value via a watchdog service access in order to vary the watchdog expire time. The lower 8 bits
are reset on each service access. Figure 12 shows the block diagram of the watchdog timer unit.
WDT
Control
Clear
1:2
MUX
f PCLK
WDTREL
WDT Low Byte
WDT High Byte
1:128
Overflow/Time-out Control &
Window-boundary control
WDTIN
ENWDT
WDTTO
WDTRST
Logic
ENWDT_P
Figure 12
WINBCNT
WDT Block Diagram
If the Watchdog Timer is enabled by setting bit WDTEN to 1, the timer is set to a user-defined start value and
begins counting up. It must be serviced before the counter overflows. Servicing is performed through refresh. This
reloads the timer with the start value, and normal operation continues.
If the WDT is not serviced before the timer overflows, a system malfunction is assumed and normal mode is
terminated. A Watchdog Timer NMI request (WDTTO) is asserted and Prewarning is entered. The Prewarning
lasts for 30H count. During the Prewarning period, refreshing of the Watchdog Timer is ignored and the Watchdog
Timer cannot be disabled. A reset (WDTRST) of the TLE983x is imminent and can no longer be stopped. If refresh
happens at the same time an overflow occurs, Watchdog Timer will not go into Prewarning period.
The Watchdog Timer must be serviced periodically so that its count value will not overflow. Servicing the
Watchdog Timer clears the low byte and reloads the high byte with the preset value in bit field WDTREL. Servicing
the Watchdog Timer also clears the bit WDTRS.
The Watchdog Timer has a ‘programmable window boundary’, it disallows refresh during the Watchdog Timer’s
count-up. A Refresh during this window-boundary will cause the Watchdog Timer to activate WDTRST. The
window boundary is from 0000H to (WDTWINB,00H). This feature can be enabled by WINBEN.
After being serviced, the Watchdog Timer continues counting up from the value (<WDTREL> * 28). The time period
for an overflow of the Watchdog Timer is programmable in two ways:
•
•
the input frequency to the Watchdog Timer can be selected via bit WDTIN in register WDTCON to be either
fPCLK/2 or fPCLK/128.
the reload value WDTREL for the high byte of WDT can be programmed in register WDTREL.
The period PWDT between servicing the Watchdog Timer and the next overflow can be determined by the
following formula:
2 ( 1 + WDTIN × 6 ) × ( 2 16 – WDTREL × 2 8 )
P WDT = --------------------------------------------------------------------------------------------------
(5)
f PCLK
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If the Window-Boundary Refresh feature of the Watchdog Timer is enabled, the period PWDT between servicing
the Watchdog Timer and the next overflow is shortened if WDTWINB is greater than WDTREL. See also
Figure 13. This period can be calculated by the same formula by replacing WDTREL with WDTWINB. In order for
this feature to be useful, WDTWINB cannot be smaller than WDTREL.
Count
FFFF H
WDTWINB
WDTREL
time
No refresh
allowed
Figure 13
Refresh allowed
Watchdog Timer Timing Diagram
Table 16 lists the possible ranges for the watchdog time which can be achieved using a certain module clock.
Some numbers are rounded to 3 significant digits.
Table 16
Watchdog Time Ranges
Prescaler for fPCLK
Reload Value in
WDTREL
2 (WDTIN = 0)
128 (WDTIN = 1)
40 MHz
20 MHz
13.3 MHz
40 MHz
20 MHz
13.3 MHz
FFH
12.8 µs
25.6 µs
38.4 µs
0.82 ms
1.64 ms
2.46 ms
7FH
1.65 ms
3.30 ms
4.95 ms
106 ms
211 ms
317 ms
00H
3.28 ms
6.55 ms
9.83 ms
210 ms
419 ms
629 ms
Notes
1. For safety reasons, the user is advised to rewrite WDTCON each time before the Watchdog Timer is serviced.
2. The Watchdog Timer can be suspended when OCDS enters Monitor Mode and has the Debug-Suspend signal
activated, provided the respective suspend bit, WDTSUSP in SFR SCU_MODSUSP, are set. See Section 4.7.
4.8.2
Register Description
The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT, which is a nonbit-addressable read-only register. The operation of the Watchdog Timer is controlled by its bit-addressable
Watchdog Timer Control Register WDTCON. WDTREL register specifies the reload value for the high byte of the
timer. WDTWINB specifies Watchdog Window-Boundary count value.
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WDTREL
Watchdog Timer Reload Register
7
6
5
Reset Value: 00H
4
3
2
1
0
WDTREL
rw
Field
Bits
Type
Description
WDTREL
[7:0]
rw
Watchdog Timer Reload Value
(for the high byte of WDT)
WDTCON
Watchdog Timer Control Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
WINBEN
WDTPR
0
WDTEN
WDTRS
WDTIN
r
rw
rh
r
rw
rwh
rw
Field
Bits
Type
Description
WDTIN
0
rw
Watchdog Timer Input Frequency Selection
0B
Input frequency is fPCLK/2
1B
Input frequency is fPCLK/128
WDTRS
1
rwh
WDT Refresh Start
Active high. Set to start refresh operation on the watchdog timer.
Cleared automatically by hardware after it is set by software.
WDTEN
2
rw
WDT Enable
0B
WDT is disabled
1B
WDT is enabled
WDTEN is a protected bit. If the Protection Scheme is activated then
this bit cannot be written directly. For more information on Protection
Scheme, see Section 4.11.
Note: Clearing WDTEN bit to 0 during Prewarning Mode
(WDTPR = 1) has no effect.
WDTPR
4
rh
Watchdog Prewarning Mode Flag
0B
Normal mode (default after reset)
1B
The Watchdog is operating in Prewarning Mode
This bit is set to 1 when a Watchdog error is detected. The Watchdog
Timer has issued an NMI trap and is in Prewarning Mode. A reset of
the chip occurs after the prewarning period has expired.
WINBEN
5
rw
Watchdog Window-Boundary Enable
0B
Watchdog Window-Boundary feature is disabled. (default)
1B
Watchdog Window-Boundary feature is enabled.
0
3, [7:6]
r
Reserved
Returns 0 if read.
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WDTL
Watchdog Timer, Low Byte
7
6
Reset Value: 00H
5
4
3
2
1
0
WDT
rh
Field
Bits
Type
Description
WDT
[7:0]
rh
Watchdog Timer Current Value
WDTH
Watchdog Timer, High Byte
7
6
Reset Value: 00H
5
4
3
2
1
0
WDT
rh
Field
Bits
Type
Description
WDT
[7:0]
rh
Watchdog Timer Current Value
WDTWINB
Watchdog Window-Boundary Count
7
6
5
Reset Value: 00H
4
3
2
1
0
WDTWINB
rw
Field
Bits
Type
Description
WDTWINB
[7:0]
rw
Watchdog Window-Boundary Count Value
This value is programmable. Within this Window-Boundary range
from 0000H to (WDTWINB, 00H), the WDT cannot do a Refresh, else
it will cause a WDTRST to be asserted.
WDTWINB is matched to WDTH.
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4.9
XRAM Addressing Modes
External Data Memory (XRAM) is accessed using MOVX instructions only. These use either 8-bit or 16-bit indirect
address. The DPTR register is used for 16-bit addressing and either register R0 or R1 is used to form the 8-bit
address.
Since the external SFRs (XSFR) are located in the XRAM space, the same XRAM addressing modes can be used
to access XSFR.
4.9.1
Access to XRAM Using the DPTR (16-bit addressing mode)
The external memory can be accessed by two read/write instructions, which use the 16-bit DPTR for indirect
addressing. These instructions are:
•
•
MOVX A, @DPTR (Read)
MOVX @DPTR, A (Write)
4.9.2
Access to XRAM Using the Register R0/R1 (8-bit addressing mode)
The TLE983x provides also instructions for accesses to XRAM using the 8-bit address (indirect addressing with
registers R0 or R1). These instructions are:
•
•
MOVX A, @Ri (Read)
MOVX @Ri, A (Write)
To access the XRAM properly, higher order address must be put in SFR XADDRH. And this write instruction must
be preceding the MOVX instructions.
XADDRH
On-Chip XRAM Address Higher Order
7
6
5
Reset Value: F0H
4
3
2
1
0
ADDRH
rw
Field
Bits
Type
Description
ADDRH
[7:0]
rw
Higher Order of On-chip XRAM Address
The range for TLE983x is from F0H to FBH for XRAM and 00H for
XSFR.
4.10
Error Detection and Correction Control for Memories
This section defines the registers used for error detection and correction control of memories – namely XRAM,
IRAM and NVM, which support this function.
The handling of XRAM and IRAM ECC is described in Chapter 7.3. NVM ECC handling is described in the
separate NVM specification.
4.10.1
Error Detection and Correction Control Register
The EDCCON register determines the generation of an NMI due to double bit ECC error when read these
memories.
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EDCCON
Error Detection and Correction Control Register
7
6
5
Reset Value: 00H
4
3
2
1
0
0
0
NVMIE
IRIE
XRIE
r
r
rw
rw
rw
Field
Bits
Type
Description
XRIE
0
rw
XRAM Double Bit ECC Error Interrupt Enable
0B
No NMI is generated when a double bit ECC error occurs
reading XRAM.
1B
An NMI is generated when a double bit ECC error occurs
reading XRAM.
IRIE
1
rw
IRAM Double Bit ECC Error Interrupt Enable
0B
No NMI is generated when a double bit ECC error occurs
reading IRAM.
1B
An NMI is generated when a double bit ECC error occurs
reading IRAM.
NVMIE
2
rw
NVM Double Bit ECC Error Interrupt Enable
0B
No NMI is generated when a double bit ECC error occurs
reading NVM.
1B
An NMI is generated when a double bit ECC error occurs
reading NVM.
0
[7:3]
r
Reserved
Returns 0 if read.
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System Control Unit
4.10.2
Error Detection and Correction Status Register
The EDCSTAT register contains the status flags of ECC errors when read these memories.
EDCSTAT
Error Detection and Correction Status Register
Reset Value: 00H
7
6
5
4
3
2
1
0
0
0
IRSBE
XRSBE0
0
NVMDBE
IRDBE
XRDBE
r
r
r
r
r
rwh
rwh
rwh
Field
Bits
Type
Description
XRDBE
0
rwh
XRAM Double Bit Error
This bit is set by hardware and can be cleared only by software.
0B
No double bit error on XRAM has occured.
1B
A double bit error on XRAM has occured.
IRDBE
1
rwh
IRAM Double Bit Error
This bit is set by hardware and can be cleared only by software.
0B
No double bit error on IRAM has occured.
1B
A double bit error on IRAM has occured.
NVMDBE
2
rwh
NVM Double Bit Error
This bit is set by hardware and can be cleared only by software.
0B
No double bit error on NVM has occured.
1B
A double bit error on NVM has occured.
XRSBE
4
rwh
XRAM Single Bit Error
This bit is set by hardware and can be cleared only by software.
0B
No single bit error on XRAM has occured.
1B
A single bit error on XRAM has occured.
IRSBE
5
rwh
IRAM Single Bit Error
This bit is set by hardware and can be cleared only by software.
0B
No single bit error on IRAM has occured.
1B
A single bit error on IRAM has occured.
0
3, 6, 7
r
Reserved
Returns 0 if read.
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System Control Unit
4.11
Miscellaneous Control
This module consists of the Bit-Protection Scheme and general system control SFRs.
4.11.1
Bit Protection Register
The Bit-Protection Scheme disallows direct software writing of selected bits (i.e. Protected bits) by the SFR
PASSWD. When the bit field MODE is 11B, writing 10011B to the bit field PASS opens access to writing of all
protected bits and writing 10101B to the bit field PASS closes access to writing of all protected bits. Note that
access is opened for maximum 32 CCLKs if the “close access” password is not written. If “open access” password
is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles.
PASSWD
Password Register
7
Reset Value: 07H
6
5
4
3
2
1
0
PASS
PROTECT_S
MODE
wh
rh
rw
Field
Bits
Type
Description
MODE
[1:0]
rw
Bit-Protection Scheme Control Bit
00B Scheme Disabled
11B Scheme Enabled (default)
Others: Scheme Enabled
These two bits cannot be written directly. To change the value
between 11B and 00B, the bit field PASS must be written with 11000B,
only then the MODE[1:0] will be registered.
PROTECT_S
2
rh
Bit-Protection Signal Status Bit
This bit shows the status of the protection.
0B
Software is able to write to all protected bits.
1B
Software is unable to write to any protected bits.
PASS
[7:3]
wh
Password Bits
The Bit-Protection Scheme only recognizes three patterns.
11000B Enables writing of the bit field MODE.
10011B Opens access to writing of all protected bits.
10101B Closes access to writing of all protected bits.
The PASSWD register and the registers which contain protected bits are located in page 2 of the SCU SFR
address map. The list of protected bits is shown in Table 17.
Table 17
List of Protected Bits
Register
Bit Field
SYSCON0
IMODE
NVMCLKFAC
SYSCLKSEL
OSC_CON
OSCSS
XPD
OSCTRIM8
PLL_CON
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System Control Unit
Table 17
List of Protected Bits (cont’d)
Register
Bit Field
CMCON
K1DIV
K2DIV
PMCON0
SL
PD
SD
WDTCON
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4.11.2
System Control Registers
The system control registers provide some clock control functionality. These clock control bits are not affected in
case of WDT and soft resets, whereby the clock configuration is maintained across these resets.
SYSCON0 contains the main system control and status bits.
SYSCON0
System control Register 0
7
6
Reset Value: See Table 12
5
4
3
2
1
0
SYSCLKSEL
NVMCLKFAC
IMODE
0
0
RMAP
rwh
rw
rw
r
r
rw
Field
Bits
Type
Description
RMAP
0
rw
Special Function Register Map Control
0B
Accessed to non-mapped (standard) special function register
area.
1B
Accessed to mapped special function register area.
IMODE
3
rw
Interrupt Structure 2 Mode Select
0B
Interrupt Mode 1 is selected.
1B
Interrupt Mode 0 is selected.
The IMODE bit is a protected bit. When the Protection Scheme is
activated, this bit cannot be written directly. For more information on
Protection Scheme, see Section 4.11.
0
1, 2
r
Reserved
Returns 0 if read.
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The Identity Register identifies the product and versioning.
ID
Identity Register
7
Reset Value: 82H
6
5
4
3
2
PRODID
VERID
r
r
Field
Bits
Type
Description
VERID
[2:0]
r
Version ID
Defines the stepping code of the device.
001B A-Step silicon
010B B-Step silicon
PRODID
[7:3]
r
Product ID
10000B
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The Memory Status Register can be used in two ways. Upon the completion of the Boot ROM startup following a
reset, the register stores the NVM initialization status. Subsequently, the register can be used by the user code to
store the status of the NVM program and emergency program operation status.
For Boot ROM to indicate NVM initialization status upon completion of startup:
MEMSTAT
Memory Status Register
7
6
Reset Value: 00H
5
4
3
2
SASTATUS
SECTORINFO
rw
rw
1
0
Field
Bits
Type
Description
SECTORINFO
[5:0]
rw
Sector Information
01H to 10H, which represent the different sector addresses.
For values not within this range, the data will be considered invalid.
Once the SA has been executed, regardless of the execution status,
the last accessed sector information will be stored here.
SASTATUS
[7:6]
rw
Service Algorithm Status
00B Depending on SECTORINFO, there are two possible
outcomes: For SECTORINFO = 00H, NVM initialization is
successful and no SA is executed. For SECTORINFO = values
other than 00H, SA execution is successful and only one map
error is fixed.
01B SA execution is successful. More than one mapping error is
fixed.
10B SA execution is not successful. Map error exists in one sector.
11B SA execution is not successful. At least one sector failed (this
includes also the case where a sector is repaired but another
sector is still failing).
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For user code to indicate the NVM program and emergency program operation status:
MEMSTAT
Memory Status Register
7
6
Reset Value: 00H
5
4
3
2
1
0
RESERVED
EMPROP
NVMPROP
rw
rw
rw
Field
Bits
Type
Description
NVMPROP
0
rw
NVM Program Operation Status Bit
This bit is used to store the status of the NVM program operation.
0B
No NVM program operation is started.
1B
An NVM program operation is started.
EMPROP
1
rw
Emergency Program Operation Status Bit
This bit is used to store the status of the emergency program
operation.
0B
No emergency program operation is requested.
1B
An emergency program operation is requested.
RESERVED
[7:2]
rw
Reserved Bits
Should be written with 0.
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4.12
Register Mapping
The BPI of the SCU supports the local address extension mechanism and the SFRs of the SCU kernel are
organized into 3 pages.
SFR SCU_PAGE, at address F1H, contains the page value and the page control information.
SCU_PAGE
Page Register for SCU
7
Reset Value: 00H
6
5
4
3
2
1
OP
STNR
PAGE
w
w
rwh
0
Field
Bits
Type
Description
PAGE
[3:0]
rwh
Page Bits
When written, the value indicates the new page address. When read, the
value indicates the currently active page = addr [y:x+1]
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the target of the operation
defined by bit OP.
If OP = 10,
the contents of PAGE are saved in STx before being overwritten with the
new value.
If OP = 11,
the contents of PAGE are overwritten by the contents of STx. The value
written to the bit positions of PAGE is ignored.
00B ST0 is selected.
01B ST1 is selected.
10B ST2 is selected.
11B ST3 is selected.
OP
[7:6]
w
Operation
0XB Manual page mode. The value of STNR is ignored and PAGE is
directly written.
10B New page programming with automatic page saving. The value
written to the bit positions of PAGE is stored. In parallel, the former
contents of PAGE are saved in the storage bit field STx indicated by
STNR.
11B Automatic restore page action. The value written to the bit positions
PAGE is ignored and instead, PAGE is overwritten by the contents
of the storage bit field STx indicated by STNR.
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The addresses of the kernel SFRs are listed in Table 18. Not listed in the tables is the SFR SYSCON0, which can
be accessed in both standard (non-mapped) and mapped address of 8FH.
Table 18
SFR Address List for Pages 1-2
Address
Page 0
Page 1
Page 2
Page 3
F2H
IRCON0
NMICON
PASSWD
XADDRH
F3H
IRCON1
EXICON0
PMCON0
PMCON1
F4H
PLL_CON
F5H
IRCON3
CMCON
F6H
IRCON4
WDTCON
F7H
NMISR
Address
Page 4
F2H
MODIEN
Page 5
Page 6
Page 7
BCON
ID
MODPISEL
F3H
WDTREL
BGL
F4H
WDTWINB
BGH
OSC_CON
F5H
WDTL
LINST
COCON
F6H
WDTH
MODPISEL1
MODPISEL2
MODSUSP
F7H
Address
Page 8
Page 9
Page 10
F2H
EDCCON
P0_POCON0
F3H
EDCSTAT
P0_POCON1
F4H
Page 11
P0_POCON2
F5H
F6H
F7H
MEMSTAT
Address
Page 12
F2H
P1_POCON0
F3H
P1_POCON1
F4H
P1_POCON2
TCCR
Page 13
Page 14
Page 15
F5H
F6H
F7H
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5
System Control Unit - Power Modules
5.1
Structure of the power modules system control unit
The System Control Unit of the power modules consists of the following sub-modules:
•
•
•
•
•
•
•
Reset Control Unit (RCU): generation of all required system resets
Clock Generation Unit (CGU): providing all required clocks to the system
Supplement Unit (SPU): manages shared functiones of analogue modules
Interrupt Control Unit (ICU): includes all system relevant interrupt flags and status flags
System Status Unit (SSU): controls mode changes due to system failures
Power Control Unit (PCU): takes over control when device enters and exits sleep and Stop Mode
External Watchdog (WDT1): independent system watchdog to monitor system activity
On signals to analog
peripherals ; status
signals from analog
peripherals
XSFR-BPI
Reset_Type_0
Reset_Type_1
PCU
RCU
Reset_Type_2
Reset_Type_3
Reset_Type_4
fsys
mi_clk
CGU
clk_2mhz
all STS bits from
analog peripherals
I
N
T
E
R
N
A
L
ICU
PREWARN_SUP_NMI
XINT
B
U
S
SSU
WDT1
lp_clk
System Control Unit-Power Modules
Figure 14
Block diagram of System Control Unit - Power Modules
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5.2
Reset Control Unit (RCU)
A reset type represents a reset domain inside the device and can be triggered by various reset sources. An
overview of the reset types and the corresponding reset sources is shown in Figure 3-14. The RCU takes care of
the reset priorisation. The priorities are as follows:
•
•
•
•
•
•
•
•
•
Power-On-Reset: priority 1 reset, which overrules all other resets
Sleep Wake-up Reset (software) priority 2 reset
Sleep Wake-up Reset (safety fallback, supply or WDT1): priority 2 reset
Hardware-Reset: priority 3 reset, which is the pin reset
External Watchdog Reset (WDT1): priority 3 reset
Stop Wake-up Reset: priority 4 reset and can be optionally configured with wake-up from stop
Software Reset: priority 5 reset which is generated by software
Internal Watchdog Reset: priority 4 reset which is generated by the internal MCU watchdog
5.3
Clock Generation Unit (CGU)
The clock generation unit is responsible for the generation of all required clocks for the analog sub-system. The
system integration of the CGU inside the TLE983x is shown in Figure 15. The CGU uses the fsys as input clock.
The generated clocks are:
•
•
MI_CLK: clock root for all analog modules. This clock can be configured by the AMCLK1_CTRL_STS register.
This clock is monitored by a clock watchdog. The clock watchdog is configured to monitor frequencies between
12 - 32 MHz.
CLK_2MHz: mainly used for digital modules as filter time reference clock. The required accuracy here is ±
20%. This frequency has always to be fine tuned when the system frequency is changed. The register for
adjusting this clock is AMCLK2_CTRL_STS. This clock is as well monitored by a clock watchdog.
•
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CGU-PCM
HW_CLK
{1,2,3,... }
TLE 983x Clock system
MU
HW_CLK
LIN
MI_CLK
CLK_2MHz
AMCLK2_DIv
Measurement Core
MI_CLK
CLK_2MHz
QRE L2
HW_CLK
HW_CLK
CLK_2MHz
AMCLK1_DIV
LP_CLK
HW_CLK
1
2 x HSS
CLK_2MHz
MI_CLK
QRE L1
CGU-System Control Unit
TIMER3
MI_CLK
{1,2,3, 4}
LP_CLK
MI_CLK
MI_CLK
0
2 x LSS
HW_CLK
SCU_PM
HW_CLK
HW_CLK
PWM_GEN
CLK_2MHz
CLKSEL
MI_CLK
1
XSFR_CLK
MI_CLK
HW_CLK
WDT1
0
MI_CLK
PLLCON
OSC_CON
LP_CLK
CMCON
CLKSEL
XTAL1
OSC_
HP
PLL
PCLK
Peripherals
fpll = 24 / 40
XTAL2
fOSC
f LP_CLK (20 MHz)
SYSCLKSEL
{1,2,3,4}
NVMCLKFAC
{1,2,3, ...}
CLKREL
MCU
SCLK
PCLK
Core
M
U
X
fSYS
fSYS
/M
/N
EN
TE
SCU
CCLK
CP
CGT
= 20 / 24 / 40 / N MHz
NVMCLK
active, stop , sleep
PCLK2
PCLK
PCLK
Peripherals
NVM
LP_CLK
CP
/N
PMU
EN
NVMACCCLK
CGT
TE
COREL
TLEN
/R
Toggle
Latch
CLKOUT
COUTS1
PLLOUTEN
(internal
mode)
COUTS0
Figure 15
Block diagram of the TLE983x clock system
There are two clock watchdogs available. One main purpose of them, is to monitor the derived switched capacitor
clocks, which are used for analog module operation. If the clocks are not in the required range, a proper
functionality of those modules cannot be guaranteed.
The following chapter describes the functionality and the configuration possibilities of these clock watchdogs.
5.3.1
Fail Safe Functionality of Clock Generation Unit (Clock Watchdog)
The Clock Generation Unit provides also fail safe functionalities, which are related to the input clock, the generated
clocks and the clock settings. Those are:
•
•
MI_CLK and CLK_2MHz are out of Range: MI Clock settings for fsys, MI_CLK and CLK_2MHz Clock settings
are out of required range and as a result the analog functionalities cannot be guaranteed. This failure triggers
the clock watchdog NMI. The current status can be seen in the corresponding registers AMCLK1_STS for the
MI_CLK and AMCLK2_STS for the CLK_2MHz.
Loss of clock: When there is a loss of clock in the system, there is no possibility for the software to react upon
this situation, like to enter a fail safe mode or switch to another backup clock source. For this purpose there is
a clock watchdog implemented in the system which monitors the fsys and in case of this emergency situation,
disables all critical system functions, which are:
– Low Side 1 and Low Side 2
– High Side 1 and High Side 2
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– LIN
As shown in Figure 15 all analog clocks are derived from MI_CLK. This clock structure requires to place a monitor
on this clock, because fsys and therefore MI_CLK are adjustable in a wide range (see also Chapter System
Control Unit - CGU). As an important clock, also the CLK_2MHz is monitored by a clock watchdog. This clock
watchdogs have an adjustable lower and upper limits including hysteresis. The placement of the clock watchdogs
in the clock structure is sketched below:
CCU (SCU_PM)
{1,2,3,...}
AMCLK2_DIV
CLK_2MHz
QRE L1
{1,2, 3,4}
CLK WDT2
AMCLK1_DIV
1
LP_CLK
MI_CLK
QRE L2
fsys
0
CLK WDT3
CLK WDT1
AMCLK_SEL
1
fsys
XSFR_CLK
pclk2
0
AMCLK_SEL
Figure 16
Block diagram of CGU including Clock Watchdogs
5.3.1.1
Functional Description of Clock Watchdog Module
The clock watchdog module consists of a counter. This counter monitors the number of system clocks within a
defined time window. The duration of the time window is defined by a clock (LP_CLK), which is independent from
the monitored system clock (MI_CLK). If the required number of clock cycles is not reached within this time
window a clock watchdog NMI will be issued. The working principle of the clock watchdog is shown in Figure 17.
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mi_clk_o
mi_clk_i
mi_clk_i
/2/ 3/4
lp_clk_i
lp_clk_i
clock _sel_i
clock _sel_i
00
Inv
01
mi_clk
mi_clk_2m_en_i
1x
ref_toogle _i
mi_clk_inv_o
warn_o
freq_o
mi_2m_wd
glitchfree_mux
clk_2m_en_o
/qrel
qrel _i
ref_clk_i
clkwdt_nmi_o
/ 256
mi_clk
/ 32
ref_toogle _i
clkwdt_nmi_clr_ack_o
warn_o
clkwdt_nmi_clr_req_i
freq_o
mi_wd
clk_gen
out
modules _dis_o
mi_freq_o
mi_2m_freq_o
lp_sel _o_o
Figure 17
Block diagram of Clock Generation Unit including Clock Watchdog
In case the clock watchdog NMI will be issued, indicating that the clock is not within the required frequency range,
then the user has different options to overcome this situation:
•
•
•
stay on MI_CLK but reconfigure PLL to regain the required clock frequency. This would be the most time
consuming measure to avoid emergency shutdown of the modules which are supplied with a clock generated
by the CGU.
switch to divider factors 2, 3 and 4 to try to come back to specified frequency range.
switch to LP_CLK, which also can be divided by factor 2, 3 and 4. This is the fastest option which allows the
user to operate with a well defined backup clock rate. After this has been done the user can start investigating
the rootcause of the issued clock watchdog NMI, while operating on LP_CLK.
The register chapter below includes all necessary flags for setting up the analog module clock and monitoring its
status during operation.
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5.3.2
Clock Generation Unit Register
The analog module clock generation unit is fully controllable by the register described in this chapter.
Table 19
Registers Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Clock Generation Unit Register,
AMCLK1_CTRL_STS
Analog Module Clock 1 Control Status Register
19H
0000 0000B
AMCLK2_CTRL_STS
Analog Module Clock 2 Control Status Register
1AH
0000 1011B
AMCLK3_CTRL_STS
Analog Module Clock 3 Control Status Register
B4H
0000 0x00B
AMCLK1_FREQ_STS
Analog Module Clock 1 Frequency Status Register E9H
00xx xxxxB
AMCLK2_FREQ_STS
Analog Module Clock 2 Frequency Status Register EAH
00xx xxxxB
AMCLK_CTRL
Analog Clock Control Status Register
ECH
0000 010xB
AMCLK1_LOW_TH_HY Analog Module Clock 1 Lower Limit Register
S
EDH
1001 0100B
AMCLK1_UP_TH_HYS
Analog Module Clock 1 Upper Limit Register
EEH
1011 0011B
AMCLK2_LOW_TH_HY Analog Module Clock 2 Lower Limit Register
S
EFH
1101 0100B
AMCLK2_UP_TH_HYS
F0H
1110 0001B
Analog Module Clock 2 Upper Limit Register
The register is addressed bytewise.
Analog Clock Control Status Register
The register is reset by RESET_TYPE_4.
AMCLK_CTRL
Analog Clock Control Status Register
7
Offset
Reset Value
ECH
0000 010xB
6
2
1
0
AMCLK_S
EL
Res
AMCLK_S
ET_VAL*
PLL_LOC
K
rw
r
rw
r
Field
Bits
Type
Description
AMCLK_SEL
7
rw
Analog Module Clock Input Select
fsys is selected
0B
1B
LP_CLK is selected
Res
6:2
r
Reserved
Always read as 0
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Field
Bits
Type
Description
AMCLK_SET_VALID
1
rw
QREL & AMCLK1 Validate Bit
0B
DISABLE QREL setting will be ignored
1B
ENABLE QREL setting is used
PLL_LOCK
0
r
PLL_LOCK
0B
NO PLL LOCK PLL not locked
1B
PLL LOCK PLL locked
Analog Module Clock 1 Control Status Register
The register is reset by RESET_TYPE_4.
AMCLK1_CTRL_STS
Analog Module Clock 1 Control Status
Register
7
6
5
Offset
Reset Value
19H
0000 0000B
4
3
2
1
0
Res
AMCLK1_STS
Res
AMCLK1_DIV
r
rwh
r
rw
Field
Bits
Type
Description
Res
7:6
r
Reserved
Always read as 0
AMCLK1_STS
5:4
rwh
Analog Module Clock 1 Status
00B
Clock OK Analog Module Clock 1 is in the
required range
01B
High Clock PREWARN Analog Module Clock 1 is
too high
10B
Low Clock PREWARN Analog Module Clock 1 is
too low
11B
Low Clock Error Analog Module Clock 1 is too
low and because of this it will switch to LP_CLK
Res
3:2
r
Reserved
Always read as 0
AMCLK1_DIV
1:0
rw
Analog Module Clock 1 (MI_CLK) Divider
00B
divide by 1 Analog Module Clock is fsys
01B
divide by 2 Analog Module Clock is fsys/2
10B
divide by 3 Analog Module Clock is fsys/3
11B
divide by 4 Analog Module Clock is fsys/4
Analog Module Clock 2 Control Status Register
The register is reset by RESET_TYPE_4.
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AMCLK2_CTRL_STS
Analog Module Clock 2 Control Status
Register
7
6
5
Offset
Reset Value
1AH
0000 1011B
4
0
AMCLK2_STS
Res
AMCLK2_DIV
rwh
r
rw
Field
Bits
Type
Description
AMCLK2_STS
7:6
rwh
Analog Module Clock 2 Status
00B
Clock OK Analog Module Clock 2 is in the
required range
01B
High Clock PREWARN Analog Module Clock 2 is
too high
10B
Low Clock PREWARN Analog Module Clock 2 is
too low
11B
Low Clock Error Analog Module Clock 2 is too
low and because of this it will switch to LP_CLK
Res
5
r
Reserved
Always read as 0
AMCLK2_DIV
4:0
rw
Analog Module Clock 2 (QREL2) Divider
00000B divide by 1 Analog Module Clock is MI_CLK
00001B divide by 2 Analog Module Clock is MI_CLK/2
00010B divide by 3 Analog Module Clock is MI_CLK/3
00011B divide by 4 Analog Module Clock is MI_CLK/4
.
.
.
11110B divide by 31 Analog Module Clock is MI_CLK/31
11111B divide by 32 Analog Module Clock is MI_CLK/32
Analog Module Clock 1 Frequency Status Register
The register is reset by RESET_TYPE_4.
AMCLK1_FREQ_STS
Analog Module Clock 1 Frequency Status
Register
7
6
Offset
Reset Value
E9H
00xx xxxxB
5
0
Res
AMCLK1_FREQ
r
r
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Field
Bits
Type
Description
Res
7:6
r
Reserved
Always read as 0
AMCLK1_FREQ
5:0
r
Current frequency of Analog Module Clock System
Clock (MI_CLK)
0.75 Mhz * AMCLK1_FREQ
Analog Module Clock 2 Frequency Status Register
The register is reset by RESET_TYPE_4.
AMCLK2_FREQ_STS
Analog Module Clock 2 Frequency Status
Register
7
6
Offset
Reset Value
EAH
00xx xxxxB
5
0
Res
AMCLK2_FREQ
r
r
Field
Bits
Type
Description
Res
7:6
r
Reserved
Always read as 0
AMCLK2_FREQ
5:0
r
Current frequency of Analog Module Clock 2
(CLK_2MHz)
0.09375 Mhz * AMCLK2_FREQ
Analog Module Clock 1 Upper Limit Register
The register is reset by RESET_TYPE_4.
AMCLK1_UP_TH_HYS
Analog Module Clock 1 Upper Limit Register
7
6
Offset
Reset Value
EEH
1011 0011B
5
0
AMCLK1_UP_HYS
AMCLK1_UP_TH
rw
rw
Field
Bits
Type
Description
AMCLK1_UP_HYS
7:6
rw
Analog Module Clock 1 Upper Hysteresis
AMCLK1_UP_TH
5:0
rw
Analog Module Clock 1 (MI_CLK) Upper Limit Threshold
0.75 Mhz * AMCLK1_UP_TH
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Analog Module Clock 1 Lower Limit Register
The register is reset by RESET_TYPE_4.
AMCLK1_LOW_TH_HYS
Analog Module Clock 1 Lower Limit Register
7
6
Offset
Reset Value
EDH
1001 0100B
5
0
AMCLK1_LOW_HY
S
AMCLK1_LOW_TH
rw
rw
Field
Bits
Type
Description
AMCLK1_LOW_HYS
7:6
rw
Analog Module Clock 1 Lower Hysteresis
AMCLK1_LOW_TH
5:0
rw
Analog Module Clock 1 (MI_CLK) Lower Limit Threshold
0.75 Mhz * AMCLK1_LOW_TH
Analog Module Clock 2 Upper Limit Register
The register is reset by RESET_TYPE_4.
AMCLK2_UP_TH_HYS
Analog Module Clock 2 Upper Limit Register
7
6
Offset
Reset Value
F0H
1110 0001B
5
0
AMCLK2_UP_HYS
AMCLK2_UP_TH
rw
rw
Field
Bits
Type
Description
AMCLK2_UP_HYS
7:6
rw
Analog Module Clock 2 Upper Hysteresis
AMCLK2_UP_TH
5:0
rw
Analog Module Clock 2 (CLK_2MHz) Upper Limit
Threshold
0.09375 Mhz * AMCLK2_UP_TH
Analog Module Clock 2 Lower Limit Register
The register is reset by RESET_TYPE_4.
AMCLK2_LOW_TH_HYS
Offset
Reset Value
Analog Module Clock 2 Lower Limit Register
EFH
1101 0100B
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7
6
5
0
AMCLK2_LOW_HY
S
AMCLK2_LOW_TH
rw
rw
Field
Bits
Type
Description
AMCLK2_LOW_HYS
7:6
rw
Analog Module Clock 2 Lower Hysteresis
AMCLK2_LOW_TH
5:0
rw
Analog Module Clock 2 (CLK_2MHz) Lower Limit
Threshold
0.09375 Mhz * AMCLK2_LOW_TH
Analog Module Clock 3 Control Status Register
The register is reset by RESET_TYPE_4.
AMCLK3_CTRL_STS
Analog Module Clock 3 Control Status
Register
7
Offset
Reset Value
B4H
0000 0x00B
4
3
2
1
0
Res
AMCLK3_
MEAS_D*
AMCLK3_
LOCLK
AMCLK3_CNT_VA
L
r
rw
rwh
rw
Field
Bits
Type
Description
Res
7:4
r
Reserved
Always read as 0.
AMCLK3_MEAS_DIS
3
rw
Fsys Clock Loss of Clock Measurement Disable Bit
0B
Enabled loss of clock measurement enabled
1B
Disabled loss of clock measurement disabled
AMCLK3_LOCLK
2
rwh
Loss of Clock Status Bit
0B
no Loss of Clock
1B
Loss of Clock
AMCLK3_CNT_VAL
1:0
rw
Timer 3 Master Clock Divider
0H
2 Periods Timer Clock is fsys
1H
4 Periods Timer Clock is fsys/2
2H
8 Periods Timer Clock is fsys/4
3H
16 Periods Timer Clock is fsys/8
5.4
Supplement Unit (SPU)
The purpose of the Supplement Control Unit is the management of all remaining blocks which are shared by all
analog peripherals grouped inside the SCU. Those are:
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•
•
•
Status of Timer3: As Timer 3 can be used for building a measurement chain composed of PWM Unit, Timer3
and ADC2, its status flags are grouped together in the SPU. The overflow flags and interrupt enable on
overflow can be found in the SUPPLEMENT_CTRL register.
System Status: During reading a 100TP page a checksum test will be executed. If the checksum is wrong the
measurement customer values will not be taken from this page. Instead default values from the bootrom are
used. This can be checked within the SYS_STRTUP_STS Register. If this flag is set operation of the device
is still possible but the parameters can be out of spec.
System Status: If the trimming of analog modules is inconsistent, it will be indicated to the system. This can
be checked within the SYS_STRTUP_STS Register. If this flag is set operation of the device is still possible
but the parameters can be out of spec.
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5.4.1
Supplement Control Unit Register
The registers below are indicating the Timer 3 status and the analog module trimming status.
Table 20
Registers Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
2CH
0000 0000B
Supplement Control Unit Register,
SYS_STRTUP_STS
System Startup Status Register
The register is addressed bytewise.
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System Startup Status Register
The register is reset by RESET_TYPE_4.
SYS_STRTUP_STS
System Startup Status Register
Offset
Reset Value
2CH
0000 0000B
7
3
2
1
0
Res
100TP_C
HECKS_*
100TP_U
NUSED
INIT_FA
IL
r
r
r
r
Field
Bits
Type
Description
Res
7:3
r
Reserved
Always read as 0
100TP_CHECKS_ERR 2
r
Checksum Error in 100TP Page
Initialization of trimming parameters from NVM failed, default
values out of Boot-ROM are used.
100TP_UNUSED
1
r
Initialization of trimming parameters failed
Initialization of trimming parameters from NVM failed, default
values out of Boot-ROM are used.
INIT_FAIL
0
r
Initialization of trimming parameters failed
Initialization of trimming parameters from NVM failed, default
values out of Boot-ROM are used.
5.5
Interrupt Control Unit (ICU)
The Subblock Interrupt Control Unit (ICU) of the System Control Unit - Power Modules (SCU_PM) is responsible
for controlling and generating all analog peripheral relevant interrupts. Those analog interrupts are mainly
combined in two main interrupt nodes of the microcontroller core. Those are:
•
•
PREWARN_SUP_NMI: combines all supply relevant interrupts to a NMI.
XINT: combines all analog module related interrupts.
The following two chapters describe the structure of both interrupt nodes.
5.5.1
Structure of PREWARN_SUP_NMI
This NMI groups all system supply relevant interrupts. They can be divided into two groups:
•
•
voltages monitored by the Measurement Unit. The supply voltages VS, VBAT_SENSE, VDDP and VDDC
are monitored by the Measurement Unit. The Measurement Unit can be seen as an independent monitoring
instance of the PMU, with independent reference voltage and supply voltage.
voltages monitored by measurement functions of the PMU: The PMU itself is checking its output voltages.
Failures due to undervoltage (overload), overvoltage and overcurrent can be detected.
The Figure 18 shows the structure of the PREWARN_SUP_NMI:
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VBAT_SENSE_ UV_IS
0
VBAT_SENSE_O V_IS
0
VS_UV_IS
0
VS_OV_IS
0
> =1
0
> =1
0
0
0
MI-Voltage-Monitoring
PMU-Voltage-Monitoring
Figure 18
>= 1
0
0
0
VDDP_UV_IS
0
VDDP_OV_IS
0
VDDC_UV_IS
0
VDDC_OV_IS
0
VDDP_OVERVOLT
0
VDDP_OVERLOAD
0
VDDC_OVERVOLT
0
VDDC_OVERLOAD
0
VDDC_OVERVOLT
0
VDDC_OVERLOAD
0
>= 1
0
> =1
0
0
>= 1
0
0
PREWARN_SUP_NMI
> =1
0
> =1
0
0
0
>= 1
0
0
> =1
0
Structure of PREWARN_SUP_NMI
All PREWARN_SUP_NMI related flags are grouped in register SYS_SUPPLY_IRQ_STS. All measurement
interface related flags are edge triggered. Therefore each IRQ_STS register has also an STS register where the
current supply status can be monitored.
5.5.2
Structure of XINT
This XINT collects all analog peripheral related interrupts. They can be divided into several categories which can
also be found in the register structure:
•
•
•
Low Side related Interrupt Flags. All Low Side driver related interrupts are grouped in SYS_IS_2 register:
– Low Side Overcurrent / Overtemperature Prewarning
– Low Side Overcurrent / Overtemperature Shutdown
– Low Side Clamping Activation
High Side and LIN related Interrupt Flags: This interrupt flags can be found in the SYS_IS_1 register. There
are:
– High Side Overcurrent / Overtemperature Shutdown
– High Side Open Load Detection
– LIN Overcurrent / Overtemperature Shutdown
System related Interrupt Flags: This interrupt flags can be found in the SYS_IS_3 register. There are:
– System Overtemperature Prewarning
– System Overtemperature Shutdown
– Operational Amplifier lower threshold warning
– Operational Amplifier upper threshold warning
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–
–
–
–
Bandgap Reference lower threshold warning
Bandgap Reference upper threshold warning
10 Bit ADC Reference overload indication (VREF5V)
Loss of Ground indication
The Figure 19 shows the described structure of the XINT:
LS1_OC/OT_WARN_IS
LS1_OC/OT_IS
0
> =1
0
0
0
LS1_VCL_IS
SYS_IS_2 Register
LS2_OC/OT_WARN _IS
LS2_OC/OT_IS
0
>= 1
0
0
0
LS2_VCL_IS
0
0
>= 1
0
0
0
SYS_IS_1 Register
HS1_OL_IS
0
HS1_OC/OT_IS
0
HS2_OL_IS
0
HS2_OC/OT_IS
0
LIN _OT_IS
0
LIN_OC_IS
0
SYS_OT_WARN_IS
0
SYS_OT_IS
0
OPA_LOTHWARN_IS
0
OPA_UPTHWARN_IS
0
>= 1
0
> =1
0
> =1
0
0
Figure 19
XINT
> =1
0
> =1
0
0
0
0
0
0
0
SYS_IS_3 Register
Supplement Control
Register
>= 1
0
0
REFBG_LOTHWARN_IS
0
REFBG_UPTHWARN_IS
0
VREF 5V_OVL__IS
0
LOG_IS
0
T3L_OVL_IS
0
T3H_OVL_IS
0
>=1
0
> =1
0
> =1
0
> =1
0
Structure of XINT
All XINT related flags are grouped in the register shown in Figure 19. All *WARN_IS flags are edge triggered.
Therefore each *WARN_IS register has also an *_STS register where the current supply status can be monitored.
All module shutdown related flags are level triggered Chapter 5.5.3. If the interrupt is not activated the current
status can still be monitored by polling the *_IS flag. Chapter groups all relevant registers described before.
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5.5.3
Interrupt Behavior of Analog Peripherals
The analog peripherals generate mainly two sorts of interrupts:
Edge triggered interrupts
•
•
•
Set Behavior: Only when there is a change in the status, like upper or lower threshold is exceeded, the
corresponding interrupt status flag will be set. An interrupt will be issued in case the measured value crosses
the threshold. This applies for both directions of crossing the threshold. The status bits are indicating whether
the measured value is above or below the threshold.
Set Behavior in case of disabled interrupt while edge is detected: If the interrupt is disabled and an edge
event occurs, the corresponding interrupt flag will be set, but does not generate an interrupt. Subsequent
enabling will lead to the interrupt as long as the interrupt flag remains set.
Clear Behavior: The clearing of the edge triggered interrupt status and the corresponding status is
independent from each other. The interrupt status flag will be cleared by writing a zero into the corresponding
register. The assigned status flag will be cleared by reading implicitly.
Level Sensitive interrupts
•
•
•
Set Behavior: The corresponding status bit is set to 1, in case upper or lower threshold is exceeded. It remains
set as long as the corresponding measurement value is outside the specified or programmed threshold.
Set Behavior in case of disabled interrupt while status is active: In case the interrupt flag is disabled, the
interrupt status flag will be set, if one of the above described conditions will occur, but will not generate an
interrupt. Therefore the interrupt status flag can also be used as a status flag.
Clear Behavior: The interrupt status flag and the assigned status flag will be cleared by writing a zero into the
corresponding registers. Clearing one of the two bits will clear the assigned other bit as well.
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5.5.4
Interrupt Control Unit Register
All analog modules interrupt registers are described in this chapter.
Table 21
Registers Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Interrupt Control Unit Register, Interrupt Control Unit Status Register
INTERRUPT_STATUS
Interrupt Status Module Overview Register
06H
xxxx xxxxB
SYS_IS_1
System Interrupt Status 1 Register
09H
0000 0000B
SYS_SUPPLY_IRQ_ST System Supply Interrupt Status Register
S
68H
0000 0000B
SYS_IS_2
System Interrupt Status 2 Register
ACH
0000 0000B
SYS_IS_3
System Interrupt Status 3 Register
ADH
0000 0000B
Interrupt Control Unit Register, Interrupt Control Unit - Interrupt Enable Register
SYS_SUPPLY_IRQ_CT System Supply Interrupt Control Register
RL
66H
1111 1111B
SYS_IRQ_CTRL_1
System Interrupt Control 1 Register
67H
0000 0000B
SYS_IRQ_CTRL_2
System Interrupt Control 2 Register
AAH
0000 0000B
SYS_IRQ_CTRL_3
System Interrupt Control 3 Register
ABH
0000 0000B
The register is addressed bytewise.
5.5.4.1
Interrupt Control Unit Status Register
Due to the large variety of diagnosis possibilities of TLE983x, the system offers several overview registers, to help
in finding the right source of interrupt. Those registers are described in this subchapter.
Interrupt Control Unit Status Register, Interrupt Control Unit Status Overview Register
•
•
•
•
SYS_SUPPLY_IRQ_STS: Flags for Under- and Overvoltage detection for all system relevant supplies. These
Interrupts are edge triggered Interrupts to reduce interrupt load of the µC.
SYS_IS_1: Interrupts for LIN (Overcurrent, Overtemperature) and High Side (Overcurrent, Open Load). These
Interrupts are Level Sensitive Interrupts.
SYS_IS_2: Interrupts for Low Side Switches (Overcurrent and Overtemperature). These Interrupts are Level
Sensitive Interrupts.
SYS_IS_3: Interrupts for several grouped analog peripherals. These Interrupts are Level Sensitive Interrupts.
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Interrupt Status Module Overview Register
The register is reset by RESET_TYPE_4.
INTERRUPT_STATUS
Interrupt Status Module Overview Register
Offset
Reset Value
06H
xxxx xxxxB
7
6
5
4
3
2
1
0
CLKWDT_
IS
HALL_SU
P_IS
Res
PREWARN
_SUP_NM
I
TSENS_I
S
LIN_IS
HS_IS
LS_IS
r
r
r
r
r
r
r
r
Field
Bits
Type
Description
CLKWDT_IS
7
r
Clock Watchdog interrupt status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
HALL_SUP_IS
6
r
Hall Supply interrupt status (OR’ed)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
Res
5
r
Reserved
Always read as 0
PREWARN_SUP_NMI 4
r
Prewarning NMI for supply voltages
As enabled by WARN_VBAT/VS/VDDP/VDDC_EN. This bit is
an OR of all supply prewarnings
0B
SUPPLY_OK all monitored supplies are in the defined
range
1B
SUPPLY_FAIL at least one supply is not in the defined
range
TSENS_IS
3
r
Temperature (MU, Channel 8) interrupt status (OR’ed)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LIN_IS
2
r
LIN interrupt status (OR’ed)
0B
INACTIVE no interrupt status set
ACTIVE at least one interrupt status set
1B
HS_IS
1
r
HS interrupt status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS_IS
0
r
LS (MU, Channel 6 or Channel 7) interrupt status (OR’ed)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
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System Interrupt Status 1 Register
The register is reset by RESET_TYPE_4.
SYS_IS_1
Offset
Reset Value
09H
0000 0000B
System Interrupt Status 1 Register
7
6
5
4
3
2
1
0
HS2_OT_
IS
HS1_OT_
IS
LIN_OT_
IS
LIN_OC_
IS
HS2_OL_
IS
HS2_OC_
IS
HS1_OL_
IS
HS1_OC_
IS
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type
Description
HS2_OT_IS
7
rwh
HS2 Overtemperature interrupt status (Bit is set by
hardware and can be cleared by software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
HS1_OT_IS
6
rwh
HS1 Overtemperature interrupt status (Bit is set by
hardware and can be cleared by software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LIN_OT_IS
5
rwh
LIN Overtemperature interrupt status (Bit is set by hardware
and can be cleared by software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE LIN Overtemperature occurred
LIN_OC_IS
4
rwh
LIN Overcurrent interrupt status (Bit is set by hardware and
can be cleared by software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
HS2_OL_IS
3
rwh
HS2 Open Load interrupt status (Bit is set by hardware and
can be cleared by software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
HS2_OC_IS
2
rwh
HS2 Overcurrent interrupt status (Bit is set by hardware and
can be cleared by software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
HS1_OL_IS
1
rwh
HS1 Open Load interrupt status (Bit is set by hardware and
can be cleared by software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
HS1_OC_IS
0
rwh
HS1 Overcurrent interrupt status (Bit is set by hardware and
can be cleared by software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
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System Interrupt Status 2 Register
The register is reset by RESET_TYPE_4.
SYS_IS_2
System Interrupt Status 2 Register
Offset
Reset Value
ACH
0000 0000B
7
6
5
4
3
2
1
0
LS_OT_I
S
LS_OTWA
RN_IS
LS2_VCL
_IS
LS2_OC_
IS
LS2_OCW
ARN_IS
LS1_VCL
_IS
LS1_OC_
IS
LS1_OCW
ARN_IS
rwh
rwhe
rwh
rwh
rwhe
rwh
rwh
rwhe
Field
Bits
Type
Description
LS_OT_IS
7
rwh
LS1 or LS2 Overtemperature Shutdown (MU, Channel 9)
interrupt status (Bit is set by hardware and can be cleared
by software)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS_OTWARN_IS
6
rwhe
LS1 or LS2 Overtemperature Warning (MU, Channel 9)
interrupt status (Bit is set by hardware and can be cleared
by software)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS2_VCL_IS
5
rwh
LS2 Voltage Clamp interrupt status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS2_OC_IS
4
rwh
LS2 Overcurrent Shutdown (MU, Channel 7) interrupt status
(Bit is set by hardware and can be cleared by software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS2_OCWARN_IS
3
rwhe
LS2 Overcurrent Warning (MU, Channel 7) interrupt status
(Bit is set by hardware and can be cleared by software!)
0B
INACTIVE no interrupt status set
ACTIVE at least one interrupt status set
1B
LS1_VCL_IS
2
rwh
LS1 Voltage Clamp interrupt status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS1_OC_IS
1
rwh
LS1 Overcurrent Shutdown (MU, Channel 6) interrupt status
(Bit is set by hardware and can be cleared by software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS1_OCWARN_IS
0
rwhe
LS1 Overcurrent Warning (MU, Channel 6) interrupt status
(Bit is set by hardware and can be cleared by software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
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System Interrupt Status 3 Register
The register is reset by RESET_TYPE_4.
SYS_IS_3
System Interrupt Status 3 Register
7
6
5
LOG_IS
VREF5V_
OVL_IS
rwh
rwh
Offset
Reset Value
ADH
0000 0000B
4
3
2
1
0
Res
REFBG_U
PTHWAR*
REFBG_L
OTHWAR*
SYS_OT_
IS
SYS_OTW
ARN_IS
r
rwh
rwh
rwhe
rwhe
Field
Bits
Type
Description
LOG_IS
7
rwh
Loss of Ground Interrupt Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
VREF5V_OVL_IS
6
rwh
VREF5V Overload Interrupt Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
Res
5:4
r
Reserved
Always read as 0
REFBG_UPTHWARN
_IS
3
rwh
8 Bit ADC Reference Overvoltage (MU, Channel 5) interrupt
status (Bit is set by hardware and can be cleared by
software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
REFBG_LOTHWARN
_IS
2
rwh
8 Bit ADC Reference Undervoltage (MU, Channel 5) interrupt
status (Bit is set by hardware and can be cleared by
software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
SYS_OT_IS
1
rwhe
System Overtemperature Shutdown (MU, Channel 8)
interrupt status (Bit is set by hardware and can be cleared
by software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
SYS_OTWARN_IS
0
rwhe
System Overtemperature Warning (MU, Channel 8) interrupt
status (Bit is set by hardware and can be cleared by
software!)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
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System Supply Interrupt Status Register
The register is reset by RESET_TYPE_4.
SYS_SUPPLY_IRQ_STS
System Supply Interrupt Status Register
Offset
Reset Value
68H
0000 0000B
7
6
5
4
3
2
1
0
VDD1V5_
OV_IS
VDD5V_O
V_IS
VS_OV_I
S
VBAT_OV
_IS
VDD1V5_
UV_IS
VDD5V_U
V_IS
VS_UV_I
S
VBAT_UV
_IS
rwhe
rwhe
rwhe
rwhe
rwhe
rwhe
rwhe
rwhe
Field
Bits
Type
Description
VDD1V5_OV_IS
7
rwhe
VDDC Overvoltage Interrupt Status
0B
No Overvoltage Interrupt occurred
1B
Overvoltage Interrupt occurred
VDD5V_OV_IS
6
rwhe
VDDP Overvoltage Interrupt Status
0B
No Overvoltage Interrupt occurred
1B
Overvoltage Interrupt occurred
VS_OV_IS
5
rwhe
VS Overvoltage Interrupt Status
0B
No Overvoltage Interrupt occurred
1B
Overvoltage Interrupt occurred
VBAT_OV_IS
4
rwhe
VBAT Overvoltage Interrupt Status
0B
No Overvoltage Interrupt occurred
1B
Overvoltage Interrupt occurred
VDD1V5_UV_IS
3
rwhe
VDDC Undervoltage Interrupt Status
0B
No Undervoltage Interrupt occurred
1B
Undervoltage Interrupt occurred
VDD5V_UV_IS
2
rwhe
VDDP Undervoltage Interrupt Status
0B
No Undervoltage Interrupt occurred
1B
Undervoltage Interrupt occurred
VS_UV_IS
1
rwhe
VS Undervoltage Interrupt Status
0B
No Undervoltage Interrupt occurred
1B
Undervoltage Interrupt occurred
VBAT_UV_IS
0
rwhe
VBAT Undervoltage Interrupt Status
0B
No Undervoltage Interrupt occurred
1B
Undervoltage Interrupt occurred
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5.5.4.2
Interrupt Control Unit - Interrupt Enable Register
The XINT Interrupts and all other power modules interrupts can be enabled or disabled by their corresponding
enable bits which are located in the registers:
•
•
•
•
SYS_SUPPLY_IRQ_CTRL: Enabling or disabling of Interrupts for Under- and Overvoltage detection for all
system relevant supplies. These interrupts are edge triggered interrupts to reduce interrupt load of the µC.
SYS_IRQ_CTRL_1: Enabling or disabling of interrupts for LIN (Overcurrent, Overtemperature) and High Side
(Overcurrent, Open Load). These interrupts are level sensitive Interrupts.
SYS_IRQ_CTRL_2: Enabling or disabling of interrupts for Low Side Switches (Overcurrent and
Overtemperature). These Interrupts are level sensitive Interrupts.
SYS_IRQ_CTRL_3: Enabling or disabling of interrupts for several grouped analog peripherals. These
interrupts are level sensitive Interrupts.
System Interrupt Control 1 Register
The register is reset by RESET_TYPE_4.
SYS_IRQ_CTRL_1
Offset
Reset Value
67H
0000 0000B
System Interrupt Control 1 Register
7
6
5
4
3
2
1
0
HS2_OT_
IE
HS1_OT_
IE
LIN_OT_
IE
LIN_OC_
IE
HS2_OL_
IE
HS2_OC_
IE
HS1_OL_
IE
HS1_OC_
IE
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
HS2_OT_IE
7
rw
High Side 2 Overtemperature Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
HS1_OT_IE
6
rw
High Side 1 Overtemperature Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
LIN_OT_IE
5
rw
LIN Overtemperature Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
LIN_OC_IE
4
rw
LIN Overcurrent Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
HS2_OL_IE
3
rw
High Side 2 Open Load Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
HS2_OC_IE
2
rw
High Side 2 Overcurrent Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
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Field
Bits
Type
Description
HS1_OL_IE
1
rw
High Side 1 Open Load Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
HS1_OC_IE
0
rw
High Side 1 Overcurrent Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
System Interrupt Control 2 Register
The register is reset by RESET_TYPE_4.
SYS_IRQ_CTRL_2
System Interrupt Control 2 Register
Offset
Reset Value
AAH
0000 0000B
7
6
5
4
3
2
1
0
LS_OT_I
E
LS_OTWA
RN_IE
LS2_VCL
_IE
LS2_OC_
IE
LS2_OCW
ARN_IE
LS1_VCL
_IE
LS1_OC_
IE
LS1_OCW
ARN_IE
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
LS_OT_IE
7
rw
LS1 or LS2 Overtemperature Shutdown Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
LS_OTWARN_IE
6
rw
LS1 or LS2 Overtemperature Warning Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
LS2_VCL_IE
5
rw
Low Side 2 Voltage Clamp Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
LS2_OC_IE
4
rw
Low Side 2 Overcurrent Shutdown Interrupt Enable
0B
Interrupt is disabled
Interrupt is enabled
1B
LS2_OCWARN_IE
3
rw
Low Side 2 Overcurrent Warning Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
LS1_VCL_IE
2
rw
Low Side 1 Voltage Clamp Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
LS1_OC_IE
1
rw
Low Side 1 Overcurrent Shutdown Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
LS1_OCWARN_IE
0
rw
Low Side 1 Overcurrent Warning Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
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System Interrupt Control 3 Register
The register is reset by RESET_TYPE_3.
SYS_IRQ_CTRL_3
System Interrupt Control 3 Register
7
6
5
LOG_IE
VREF5V_
OVL_IE
rw
rw
Offset
Reset Value
ABH
0000 0000B
4
3
2
1
0
Res
REFBG_U
PTHWAR*
REFBG_L
OTHWAR*
SYS_OT_
IE
SYS_OTW
ARN_IE
r
rw
rw
rw
rw
Field
Bits
Type
Description
LOG_IE
7
rw
Loss of Ground Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
VREF5V_OVL_IE
6
rw
VREF5V Overload Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
Res
5:4
r
Reserved
Always read as 0
REFBG_UPTHWARN
_IE
3
rw
Reference Voltage Overvoltage Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
REFBG_LOTHWARN
_IE
2
rw
Reference Voltage Undervoltage Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
SYS_OT_IE
1
rw
System Overtemperature Shutdown Interrupt Enable (leads
to shutdown of System)
0B
Interrupt is disabled
1B
Interrupt is enabled
SYS_OTWARN_IE
0
rw
System Overtemperature Warning Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
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System Supply Interrupt Control Register
The register is reset by RESET_TYPE_4.
SYS_SUPPLY_IRQ_CTRL
System Supply Interrupt Control Register
Offset
Reset Value
66H
1111 1111B
7
6
5
4
3
2
1
0
VDD1V5_
OV_IE
VDD5V_O
V_IE
VS_OV_I
E
VBAT_OV
_IE
VDD1V5_
UV_IE
VDD5V_U
V_IE
VS_UV_I
E
VBAT_UV
_IE
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
VDD1V5_OV_IE
7
rw
VDDC Overvoltage Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
VDD5V_OV_IE
6
rw
VDDP Overvoltage Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
VS_OV_IE
5
rw
VS Overvoltage Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
VBAT_OV_IE
4
rw
VBAT Overvoltage Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
VDD1V5_UV_IE
3
rw
VDDC Undervoltage Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
VDD5V_UV_IE
2
rw
VDDP Undervoltage Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
VS_UV_IE
1
rw
VS Undervoltage Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
VBAT_UV_IE
0
rw
VBAT Undervoltage Interrupt Enable
0B
Interrupt is disabled
1B
Interrupt is enabled
5.6
System Status Unit (SSU)
The analog peripheral status is grouped in the System Status Unit. The concept of the system status bits is to
distribute them in the analog modules. To give the user a better overview about the system status, all of them are
grouped together inside the System Status Unit. The register structure is similar to the one of the ICU:
•
•
SYS_SUPPLY_STS: shows the current state of all system supplies. All flags in this register are clear-on-read.
SYS_STS_1: is an overview register, where all relevant analog status flags are grouped.
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•
•
•
SYS_STS_2: contains all status flags of the High Side drivers and the LIN driver. All flags in this register are
read only, because the corresponding *IS flags are already indicating the status.
SYS_STS_3: reflects the status of all Low Side switch related flags. The *WARN_STS flags in this register are
clear-on-read. The reason is, that their linked *IS flags are edge triggered.
SYS_STS_4: includes all system relevant flags. The *WARN_STS flags in this register are clear-on-read. The
reason is, that their linked *IS flags are edge triggered.
SCU_PM
RCU
IR
XSF
RBPI
PCU
MON1
MON5
PMU/ CLK_G
PCU
EN
Attenuator
VMON 1..5
Attenuator
VS_SENSE
VBAT_SENSE
VDDP_SENSE
VDDC_SENSE
WDT(external)
XSFR
- BPI
Timer 3
XSF
RBPI
VBAT
PWM-Unit
XSFR - BPI
BG
CTRL
CFU
High Side 1
HS 1
High Side 2
HS 2
CTRL
TSENSE
XSFR - BPI
VS_SENSE
VBAT_SENSE
VDDP_SENSE
VDDC_SENSE
LS1_SENSE
LS2_SENSE
T_SENSE
TS_LS_SENSE
REF_SENSE
OA_IN
XSF
RBPI
8-Bit ADC
DSP
CTRL
XSFR - BPI
Low Side 1
CTRL
LS1
GND_LS
XSFR - BPI
Measurement Unit
Low Side 2
LS2
CTRL
LIN
XSFR - BPI
LIN Transceiver
CTRL
Figure 20
Wake
LIN_GND
Block diagram of Peripherals monitored by the System Status Unit
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5.6.1
System Status Register
These registers are dedicated for a system status overview. The particular status of a module is located inside the
corresponding module register and must be cleared there. Those overview registers are mainly read only and are
mirroring the module status.
Table 22
Registers Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
SYS_SUPPLY_STS
System Supply Status Register
69H
0000 0000B
SYS_STS_1
System Status 1 Register
6AH
xxxx xxxxB
SYS_STS_2
System Status 2 Register
6BH
xxxx xxxxB
SYS_STS_3
System Status 3 Register
AEH
x0xx 0xx0B
SYS_STS_4
System Status 4 Register
AFH
xxxx xxxxB
System Status Register,
The register is addressed bytewise.
System Status 1 Register
The register is reset by RESET_TYPE_4.
SYS_STS_1
System Status 1 Register
Offset
Reset Value
6AH
xxxx xxxxB
7
6
5
4
3
2
1
0
CLKWDT_
STS
HALL_SU
P_STS
Res
SUPPLY_
STS
TSENS_S
TS
LIN_STS
HS_STS
LS_STS
r
r
r
r
r
r
r
r
Field
Bits
Type
Description
CLKWDT_STS
7
r
Clock Watchdog status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
HALL_SUP_STS
6
r
Hall Supply status (OR’ed)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
Res
5
r
Reserved
Always read as 0
SUPPLY_STS
4
r
Supply Voltage (MU) status (OR’ed)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
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Field
Bits
Type
Description
TSENS_STS
3
r
Temperature (MU) status (OR’ed)
INACTIVE no interrupt status set
0B
1B
ACTIVE at least one interrupt status set
LIN_STS
2
r
LIN status (OR’ed)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
HS_STS
1
r
HS status (OR’ed)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS_STS
0
r
LS (MU) status (OR’ed)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
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System Status 2 Register
The register is reset by RESET_TYPE_4.
SYS_STS_2
Offset
Reset Value
6BH
xxxx xxxxB
System Status 2 Register
7
6
5
4
3
2
1
0
HS2_OT_
STS
HS1_OT_
STS
LIN_OT_
STS
LIN_OC_
STS
HS2_OL_
STS
HS2_OC_
STS
HS1_OL_
STS
HS1_OC_
STS
r
r
r
r
r
r
r
r
Field
Bits
Type
Description
HS2_OT_STS
7
r
HS2 Overtemperature Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
HS1_OT_STS
6
r
HS1 Overtemperature Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LIN_OT_STS
5
r
LIN Overtemperature Status
0B
INACTIVE no interrupt status set
1B
ACTIVE LIN Overtemperature occurred
LIN_OC_STS
4
r
LIN Overcurrent Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
HS2_OL_STS
3
r
HS2 Open Load Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
HS2_OC_STS
2
r
HS2 Overcurrent Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
HS1_OL_STS
1
r
HS1 Open Load Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
HS1_OC_STS
0
r
HS1 Overcurrent Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
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System Status 3 Register
The register is reset by RESET_TYPE_4.
SYS_STS_3
System Status 3 Register
Offset
Reset Value
AEH
x0xx 0xx0B
7
6
5
4
3
2
1
0
LS_OT_S
TS
LS_OTWA
RN_STS
LS2_VCL
_STS
LS2_OC_
STS
LS2_OCW
ARN_STS
LS1_VCL
_STS
LS1_OC_
STS
LS1_OCW
ARN_STS
r
rh
r
r
rh
r
r
rh
Field
Bits
Type
Description
LS_OT_STS
7
r
LS1 and LS2 Overtemperature (MU) Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS_OTWARN_STS
6
rh
LS1 and LS2 Overtemperature (MU) Warning Status (Bit is
set by hardware and can be cleared by software)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS2_VCL_STS
5
r
LS2 Overcurrent (MU) Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS2_OC_STS
4
r
LS2 Overcurrent (MU) Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS2_OCWARN_STS
3
rh
LS2 Overcurrent (MU) Status (Bit is set by hardware and can
be cleared by software)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS1_VCL_STS
2
r
LS1 Overcurrent (MU) Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS1_OC_STS
1
r
LS1 Overcurrent (MU) Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
LS1_OCWARN_STS
0
rh
LS1 Overcurrent (MU) Status (Bit is set by hardware and can
be cleared by software)
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
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System Status 4 Register
The register is reset by RESET_TYPE_4.
SYS_STS_4
System Status 4 Register
Offset
Reset Value
AFH
xxxx xxxxB
7
6
5
4
3
2
1
0
LOG_STS
VREF5V_
OVL_STS
OPA_UPT
HWARN_*
OPA_LOT
HWARN_*
REFBG_U
PTHWAR*
REFBG_L
OTHWAR*
SYS_OT_
STS
SYS_OTW
ARN_STS
r
r
r
r
r
r
rh
rh
Field
Bits
Type
Description
LOG_STS
7
r
OR’ed Loss of Ground Status
0B
INACTIVE no status set
1B
ACTIVE status set
VREF5V_OVL_STS
6
r
VAREF5V Overload Status
0B
INACTIVE no status set
1B
ACTIVE status set
OPA_UPTHWARN_S
TS
5
r
Operational Amplifier Upper Threshold Warning (MU) Status
0B
INACTIVE no status set
1B
ACTIVE status set
OPA_LOTHWARN_ST 4
S
r
Operational Amplifier Lower Threshold Warning (MU)
Status
0B
INACTIVE no status set
1B
ACTIVE status set
REFBG_UPTHWARN
_STS
3
r
System 8 Bit Reference Overvoltage Warning (MU) Status
0B
INACTIVE no interrupt status set
1B
ACTIVE at least one interrupt status set
REFBG_LOTHWARN
_STS
2
r
System 8 Bit Reference Undervoltage Warning (MU) Status
0B
INACTIVE no status set
ACTIVE status set
1B
SYS_OT_STS
1
rh
System Overtemperature (MU) Status
0B
INACTIVE no status set
1B
ACTIVE status set
SYS_OTWARN_STS
0
rh
System Overtemperature Warning (MU) Status
0B
INACTIVE no status set
1B
ACTIVE status set
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System Supply Status Register
The register is reset by RESET_TYPE_4.
SYS_SUPPLY_STS
System Supply Status Register
Offset
Reset Value
69H
0000 0000B
7
6
5
4
3
2
1
0
VDD1V5_
OV_STS
VDD5V_O
V_STS
VS_OV_S
TS
VBAT_OV
_STS
VDD1V5_
UV_STS
VDD5V_U
V_STS
VS_UV_S
TS
VBAT_UV
_STS
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type
Description
VDD1V5_OV_STS
7
rh
VDDC Overvoltage Interrupt Status
0B
No Overvoltage Interrupt occurred
1B
Overvoltage Interrupt occurred
VDD5V_OV_STS
6
rh
VDDP Overvoltage Interrupt Status
0B
No Overvoltage Interrupt occurred
1B
Overvoltage Interrupt occurred
VS_OV_STS
5
rh
VS Overvoltage Interrupt Status
0B
No Overvoltage Interrupt occurred
1B
Overvoltage Interrupt occurred
VBAT_OV_STS
4
rh
VBAT Overvoltage Interrupt Status
0B
No Overvoltage Interrupt occurred
1B
Overvoltage Interrupt occurred
VDD1V5_UV_STS
3
rh
VDDC Undervoltage Interrupt Status
0B
No Undervoltage Interrupt occurred
1B
Undervoltage Interrupt occurred
VDD5V_UV_STS
2
rh
VDDP Undervoltage Interrupt Status
0B
No Undervoltage Interrupt occurred
1B
Undervoltage Interrupt occurred
VS_UV_STS
1
rh
VS Undervoltage Interrupt Status
0B
No Undervoltage Interrupt occurred
1B
Undervoltage Interrupt occurred
VBAT_UV_STS
0
rh
VBAT Undervoltage Interrupt Status
0B
No Undervoltage Interrupt occurred
1B
Undervoltage Interrupt occurred
5.7
Power Control Unit for Power Modules (PCU)
The chapter describes the implementation of the power modules state machine. This state machine is responsible
for powering up and powering down the on-chip power modules. It takes care of the interaction between the
Measurement Unit and the modules which are evaluated by the PCU. The following modules are controlled by this
statemachine:
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Analog Modules controlled by the Power Control Unit:
•
•
•
•
•
•
•
•
Central Reference Voltage Generation
Central Bias Current Generation
8 Bit ADC Core
Supply Voltage Attenuators
Monitoring Inputs Voltage Attenuators
LIN Transceiver
High Side Switches
Low Side Switches
PCU
PD_N
to analog
module
to analog
module
&
ON
0
0
PD_N
0
&
0
0
ON
0
XSFR
Analog Peripheral Control
Working Principle of PCU
Figure 21
Function of Analog Module controlled by PCU
If the device will power up the analog modules statemachine will startup all analog modules. First of all, the
reference voltage will be enabled. After that the biasing module will be enabled. If this step is completed the analog
modules will be enabled step by step. After this is done the measurement interface will start-up.
When exiting Stop Mode, this sequence restores the XSFR register contents with the values written before
entering Stop Mode.
The Sleep and Stop Mode entry is controlled by this state machine as well. This ensures a well controlled
shutdown of the modules avoiding disturbances (like load jumps) on the supplies.
The power control unit also handles system failures indicated by the analog measurement interface. They are:
System failures handled by PCU:
•
•
•
automatic shutdown of system in case of VS Overvoltage
automatic shutdown of system in case of System Overtemperature
automatic shutdown of system in case of internal supply fail
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•
automatic shutdown of system in case of loss of clock
How to enable these actions of the above listed system failures, will be described in the following chapters.
5.7.1
VS-Overvoltage System Shutdown
The PCU provides the possibility of a system shutdown in case of VS Overvoltage. This feature can be used to
reduce power dissipation in case of an increased supply voltage VS. This feature can be enabled by the Bit
VS_OV_PMU_DIS. This bit is active low. When there is an overvoltage, the system will enter Sleep Mode after
1ms. During this time corrective actions can be done by software, e.g. reset of the Bit VS_OV_STS to avoid
entering Sleep Mode if the overvoltage condition is no more present. The figure below shows the principle of the
enable bit:
VS_OV_STS
0
&
0
0
VS_OV_STS_gated
D
D
QQ
SET
XSFRQ
CLR
SYS_VS_OV_SLM_DIS – XSFR Bit
Figure 22
Implementation of Module Shutdown because of VS Overvoltage
The Bit is gating the status flag VS_OV_STS of the SSU. If this bit is set, 1 ms after the faillure the system will be
set into Sleep Mode.
5.7.2
Overtemperature System Shutdown
In case of overtemperature (Tj > 150 °C) the system will shutdown certain power modules. This functionality is
used to protect the system from thermal overstress. One possibility of avoiding this thermal shutdown is to stick to
an emergency procedure, which helps to minimize the power dissipation in the system. This routine would require
to shutdown all modules which have big contribution to power dissipation (e.g. Low Side switch, High Side switch).
This procedure has to be implemented in user software. Another possibility is to use the implemented hardware
shutdown procedure. This procedure can be activated by the flag SYS_OT_PS_DIS. This flag is active low.
When this flag is set all power dissipation contributors will be automatically shutdown.
•
Main power dissipation contributors, which will be switched off are:
– Low Side switches
– High Side switches
– LIN Transceiver
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VS_OV_STS
0
&
0
0
VS_OV_STS_gated
D
D
QQ
SET
XSFRQ
CLR
VS_OV_PMU_DIS – XSFR Bit
Figure 23
Implementation of Power Module Shutdown in case of System Overtemperature
As it can be seen, the bit is gating the status flag VS_OT_STS of the SSU. If this bit is set, 1ms after the failure
the Power Modules will be shutdown.
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5.7.3
Power Control Unit Register
The PCU is fully controllable by the below listed XSFR Registers. These registers are located in the XSFR address
space and therefore need not to be paged.
Table 23
Registers Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Power Control Unit Register,
PCU_CTRL_STS_2
Power Control Unit Control Status 2 Register
63H
0111 1110B
PCU_CTRL_STS_1
Power Control Unit Control Status 1 Register
65H
1111 0011B
PCU_CTRL_STS_3
Power Control Unit Control Status 3 Register
FDH
1110 0011B
PCU_CTRL_STS_4
Power Control Unit Control Status 4 Register
FEH
0000 0000B
The register is addressed bytewise.
Power Control Unit Control Status 1 Register
The register is reset by RESET_TYPE_4.
PCU_CTRL_STS_1
Power Control Unit Control Status 1 Register
7
Offset
Reset Value
65H
1111 0011B
6
2
VS_OV_P
MU_DIS
Res
rwp
1
0
CLKWDT_
SD_DIS
Res
rw
r
Field
Bits
Type
Description
VS_OV_PMU_DIS
7
rwp
System Status Shutdown Disable
0B
Automatic Shutdown Enabled Sleep Mode entry in case
of VS Overvoltage
1B
Automatic Shutdown Disabled Sleep Mode will not be
entered in case of VS Overvoltage
Res
7:2
r
Reserved
Always read as 0
CLKWDT_SD_DIS
1
rw
Power Modules Clock Watchdog Shutdown Disable
0B
Shutdown Enable Power Devices will be shutdown when
Loss of clock occurs
1B
Shutdown Disable Power Devices will not be shutdown
when Loss of clock occurs
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Field
Bits
Type
Description
Res
0
r
Reserved
Always read as 0
Power Control Unit Control Status 2 Register
The register is reset by RESET_TYPE_4.
PCU_CTRL_STS_2
Power Control Unit Control Status 2 Register
Offset
Reset Value
63H
0111 1110B
7
1
0
LIN_VS_
UV_SD_D
IS
Res
rw
Field
Bits
Type
Description
LIN_VS_UV_SD_DIS
0
rw
LIN Module VS Undervoltage Transmitter Shutdown
0B
Automatic Shutdown Enabled LIN Transmitter will be
stutdown in case of VS Undervoltage occurs
1B
Automatic Shutdown Disable LIN Transmitter will not be
shutdown in case of VS Undervoltage occurs
Res
7:1
r
Reserved
Always read as 0
Power Control Unit Control Status 3 Register
The register is reset by RESET_TYPE_4.
PCU_CTRL_STS_3
Power Control Unit Control Status 3 Register
7
Offset
Reset Value
FDH
1110 0011B
6
0
FAIL_PS
_DIS
Res
rw
r
Field
Bits
Type
Description
FAIL_PS_DIS
7
rw
Disable Power Switches because of Overtemperature
0B
Switch off Enabled Power Switches will be turned off
when Overtemperature occurs
1B
Switch off Disabled Power Switches will be kept on
when Overtemperature occurs
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Field
Bits
Type
Description
Res
6:0
r
Reserved
Always read as 0
Power Control Unit Control Status 4 Register
The register is reset by RESET_TYPE_4.
PCU_CTRL_STS_4
Power Control Unit Control Status 4 Register
Offset
Reset Value
FEH
0000 0000B
7
1
0
Res
SYS_OT_
PS_DIS
r
rwp
Field
Bits
Type
Description
Res
7:1
r
Reserved
Always read as 0
SYS_OT_PS_DIS
0
rwp
System Overtemperature Power Switches Shutdown
Disable
0B
Enabled Power modules will be shutdown in case of
system overtemperature
1B
Disable Power modules will not be shutdown in case
of system overtemperature
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XC800 Core
6
XC800 Core
The XC800 Core is a complete, high performance CPU core that is functionally upward compatible to the 8051.
While the standard 8051 core is designed around a 12-clock machine cycle, the XC800 Core uses a two-clock
period machine cycle.
The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions. Each instruction
takes 1, 2 or 4 machine cycles to execute. In case of access to slower memory, the access time may be extended
by wait cycles (one wait cycle lasts one machine cycle, which is equivalent to two clock cycles).
Via the dedicated DAP interface the XC800 Core supports a range of debugging features including basic
stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory
and special function registers.
6.1
Overview
The key features of the XC800 Core implemented are listed below.
•
•
•
•
•
•
•
•
Two clocks per machine cycle
256 Byte of internal data memory
Program Memory Download option
15-source, 4-level interrupt controller
2 data pointers
Power saving modes
Dedicated debug mode via low-pin-count DAP interface (native JTAG mode)
Two 16-bit timers (Timer 0 and Timer 1)
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Figure 24 shows the functional blocks of the XC800 Core. The XC800 Core consists mainly of the instruction
decoder, the arithmetic section, the program control section, the access control section, and the interrupt
controller.
The instruction decoder decodes each instruction and accordingly generates the internal signals required to
control the functions of the individual units within the core. These internal signals have an effect on the source and
destination of data transfers and control the ALU processing.
Internal Data
Memory
Core SFRs
Register Interface
External SFRs
External Data
Memory
16-bit Registers &
Memory Interface
ALU
Opcode &
Immediate
Registers
Multiplier / Divider
Opcode Decoder
Timer 0 / Timer 1
Program Memory
Clocks
Memory Wait
Reset
State Machine &
Power Saving
Legacy External Interrupts (IEN0, IEN1)
External Interrupts
Non-Maskable Interrupt
Interrupt
Controller
Core Block Diagram
Figure 24
XC800 Core Block Diagram
The arithmetic section of the processor performs extensive data manipulation and consists of the arithmetic/logic
unit (ALU), A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources
and generates an 8-bit result under the control of the instruction decoder. The ALU performs both arithmetic and
logic operations. Arithmetic operations include add, subtract, multiply, divide, increment, decrement, BCDdecimal-add-adjust and compare. Logic operations include AND, OR, Exclusive OR, complement and rotate (right,
left or swap nibble (left four)). Also included is a Boolean unit performing the bit operations as set, clear,
complement, jump-if-set, jump-if-not-set, jump-if-set-and-clear and move to/from carry. The ALU can perform the
bit operations of logical AND or logical OR between any addressable bit (or its complement) and the carry flag,
and place the new result in the carry flag.
The program control section controls the sequence in which the instructions stored in program memory are
executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The
conditional branch logic enables internal and external events to the processor to cause a change in the program
execution sequence.
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The access control unit is responsible for the selection of the on-chip memory resources. The interrupt requests
from the peripheral units are handled by the interrupt controller unit.
6.2
SFRs of the CPU
The XC800 Core registers occupy direct Internal Data Memory space locations in the range 80H to FFH.
6.2.1
Stack Pointer (SP)
The SP register contains the Stack Pointer. The Stack Pointer is used to load the program counter into internal
data memory during LCALL and ACALL instructions and to retrieve the program counter from memory during RET
and RETI instructions. Data may also be saved on or retrieved from the stack using PUSH and POP instructions.
Instructions that use the stack automatically pre-increment or post-decrement the stack pointer so that the stack
pointer always points to the last byte written to the stack, i.e. the top of the stack. On reset, the Stack Pointer is
reset to 07H. This causes the stack to begin at a location = 08H above register bank zero. The SP can be read or
written under software control. The programmer must ensure that the location and size of the stack in internal data
memory do not overlap with other application data.
6.2.2
Data Pointer (DPTR)
The Data Pointer (DPTR) is stored in registers DPL (Data Pointer Low byte) and DPH (Data Pointer High byte) to
form 16-bit addresses for External Data Memory accesses (MOVX A,@DPTR and MOVX @DPTR,A), for program
byte moves (MOVC A,@A+DPTR) and for indirect program jumps (JMP @A+DPTR).
Two true 16-bit operations are allowed on the Data Pointer: load immediate (MOV DPTR,#data) and increment
(INC DPTR).
6.2.3
Accumulator (ACC)
This register provides one of the operands for most ALU operations. ACC is the symbol for the accumulator
register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as “A”.
6.2.4
B Register
The B register is used during multiply and divide operations to provide the second operand. For other instructions,
it can be treated as another scratch pad register.
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6.2.5
Program Status Word
The Program Status Word (PSW) contains several status bits that reflect the current state of the core.
PSW
Program Status Word Register
Reset Value: 00H
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
rwh
rwh
rw
rw
rw
rwh
rw
rh
Field
Bits
Type
Description
P
0
rh
Parity Flag
Set/cleared by hardware after each instruction to indicate an
odd/even number of “one” bits in the accumulator, i.e. even parity.
F1
1
rw
General Purpose Flag
OV
2
rwh
Overflow Flag
Used by arithmetic instructions.
RS0
RS1
3
4
rw
Register Bank Select
These bits are used to select one of the four register banks.
00B Bank 0 selected, data address 00H - 07H
01B Bank 1 selected, data address 08H - 0FH
10B Bank 2 selected, data address 10H - 17H
11B Bank 3 selected, data address 18H - 1FH
F0
5
rw
General Purpose Flag
AC
6
rwh
Auxiliary Carry Flag
Used by instructions which execute BCD operations.
CY
7
rwh
Carry Flag
Used by arithmetic instructions.
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6.2.6
Extended Operation Register (EO)
The instruction set includes an additional instruction MOVC @(DPTR++),A which writes to program memory
implemented as RAM. This instruction may be used both to download code into the program memory when the
CPU is initialized and subsequently, to provide software updates. The instruction copies the contents of the
accumulator to the code memory at the location pointed to by the current data pointer, then increments the data
pointer.
The instruction uses the opcode A5H, which is the same as the software break instruction TRAP (see Table 24).
Bit TRAP_EN in the Extended Operation (EO) register is used to select the instruction executed by the opcode
A5H. When bit TRAP_EN is 0 (default), the A5H opcode executes the MOVC instruction. When bit TRAP_EN is 1,
the A5H opcode executes the software break instruction TRAP, which switches the CPU to debug mode for
breakpoint processing.
Register EO is also used to select the current data pointer.
EO
Extended Operation Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
TRAP_EN
0
DPSEL2
DPSEL1
DPSEL0
r
rw
r
rw
rw
rw
Field
Bits
Type
Description
DPSEL0
DPSEL1
DPSEL2
0
1
2
rw
Data Pointer Select
These bits are used to select the current data pointer.
000B DPTR0 selected
001B DPTR1 selected
others: Reserved
TRAP_EN
3
rw
TRAP Enable
0B
Select MOVC @(DPTR++),A
1B
Select software TRAP instruction
0
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
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6.2.7
Power Control Register (PCON)
The XC800 Core has two power-saving modes: idle mode and Stop Mode. The idle mode can be entered via the
PCON register. In idle mode, the clock to the core is disabled while the timers, serial port and interrupt controller
continue to run. In Stop Mode, the clock to the entire core is stopped. Details of the Power Control registers are
described in Chapter 20.3.
6.2.8
Interrupt Registers
One non-mask able and fourteen mistakable interrupt nodes are available.
Details of the interrupt registers are described in Chapter 11.7.
6.3
SFRs of The Core Peripherals
6.3.1
Timer Registers
Two 16-bit timers are provided - Timer 0 (T0) and Timer 1 (T1).
Details of the timer registers are described in Chapter 14.7.
6.4
Memory Extension
The standard amount of addressable program or external data memory in a 8051 system is 64 kBytes. The XC800
Core supports expansion of up to 1 Mbyte and this is enabled by the availability of a Memory Management Unit
(MMU) and a Memory Extension Stack. The MMU adds a set of Memory Extension registers (MEX1, MEX2 and
MEX3) to control access to the extended memory space by different addressing modes. The Memory Extension
Stack is used by the hardware to ‘push’ and ‘pop’ values of MEX1.
Program Code is always fetched from the 64-kByte block pointed to by a 4-bit Current Bank (CB) register bit field.
It is updated from a 4-bit Next Bank (NB) bit field upon execution of long jump (LJMP) and call instructions. CB
and NB together constitute the MEX1 register. The programmer simply writes the new bank number to NB before
a jump or call instruction, that is intended to take the program counter into a new 64K block.
Interrupt service routines are always executed from code in the 64-Kbyte block pointed to by the Interrupt Bank
(IB) register bit field. Further, memory constant data reads and external data accesses may take place in banks
other than the current bank. These banks are pointed to by the Memory Constant Bank pointer (MCB) and XRAM
Bank pointer (MX). These bit fields are located in MEX2 and MEX3 registers.
6.4.1
Memory Extension Stack
Interrupts and Calls in Memory Extension mode make use of a Memory Extension Stack, which is updated at the
same time as the standard stack.
The Memory Extension Stack is addressed using the SFR Memory Extension Stack Pointer MEXSP. This
read/write register provides for a stack depth of up to 128 bytes (Bit 7 is always 0). The SFR is then preincremented by each call instruction executed, and post-decremented by return instructions. MEXSP is by default
reset to 7FH so that the first increment selects the bottom of the stack. No indication of stack overflow is provided.
6.4.2
Memory Extension Effects
The following instructions can change the 64K block pointed to: MOVC, MOVX, LJMP, LCALL, ACALL, RET and
RETI.
Relative jumps (SJMP etc.) and absolute jumps within 2-Kbyte regions (AJMPs), however, will in no way change
the current bank. In other words, these instructions do not deselect the active 64-Kbyte bank block.
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Move Constant Instructions (MOVC)
MOVC instructions access data bytes in either the Current bank (CB19 – CB16) or a ‘Memory Constant’ bank,
defined by the MCB19 – MCB16 bit field in MEX3 and MEX2. The bank selection is done by the MCM bit in MEX2
(MEX2.7).
Move External Data Instructions (MOVX)
MOVX instructions can either access data in the Current bank or a ‘Data Memory’ bank, defined by the MX19 –
MX16 bits in MEX3. The mode selected is done by the MXM bit in MEX3 (MEX3.3).
Long Jump Instructions (LJMP)
When a jump to another bank of the Memory Extension is required, the Next Bank bits NB19 – NB16 in MEX1
(MEX1.3 – MEX1.0) must be set to the appropriate bank address before the LJMP instruction is executed. When
the LJMP is encountered in the code, the Next Bank bits (NB19 – 16) are copied to the Current Bank bits CB19 –
CB16 in MEX1 (MEX1.7 – MEX1.4) and appear on address bus at the beginning of the next program fetch cycle.
Note: The Next Bank Bits (NB19 – 16) are not changed by the jump.
CALL Instructions (LCALL and ACALL)
Whenever an LCALL occurs, the MMU carries out the following sequence of actions:
1.
2.
3.
4.
5.
6.
The Memory Extension Stack Pointer is incremented.
The MEX1 register bits are made available on data bus.
The MEXSP register bits [6:0] are made available on address lines.
The Memory Extension Stack read and write signals are set for a write operation.
A write is performed to the Memory Extension Stack.
The Next Bank bits NB19 – NB16 (MEX1.3 – MEX1.0) are copied to the CB19 – CB16 bits (MEX1.7 – MEX.4).
Return Instructions (RET and RETI)
On leaving a subroutine, the MMU carries out the following sequence of actions:
1.
2.
3.
4.
5.
The MEXSP register bits [6:0] are made available on address.
The Memory Extension Stack read and write signals are set for a read operation.
A read is performed on the Memory Extension Stack.
Memory Extension Stack data is written to the MEX1 register.
The Memory Extension Stack Pointer is decremented.
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6.4.3
Memory Extension Registers
MEX1
Memory Extension Register 1
7
6
Reset Value: 00H
5
4
3
2
1
CB[19:16]
NB[19:16]
rh
rw
Field
Bits
Type
Description
NB[19:16]
[3:0]
rw
Next Bank Number
CB[19:16]
[7:4]
rh
Current Bank Number
MEX2
Memory Extension Register 2
7
6
0
Reset Value: 00H
5
4
3
2
1
MCM
MCB[18:16]
IB[19:16]
rw
rw
rw
0
Field
Bits
Type
Description
IB[19:16]
[3:0]
rw
Interrupt Bank Number
MCB[18:16]
[6:4]
rw
Memory Constant Bank Number (with MEX3.7)
MCM
7
rw
Memory Constant Mode
0
MOVC access data in the current bank defined by the bit field
CB in MEX1 register
1
MOVC access data in the Memory Constant bank MCB
MEX3
Memory Extension Register 3
7
6
Reset Value: 00H
5
4
3
2
1
MCB19
0
MXB19
MXM
MXB[18:16]
rw
rw
rw
rw
rw
Field
Bits
Type
0
Description
MXB[19:16]
4,[2:0]
rw
XRAM Bank Number
MXM
3
rw
XRAM Bank Selector
0
MOVX access data in the current bank defined by the bit field
CB in MEX1 register
1
MOVX access data in the Memory XRAM bank MXB
MCB19
7
rw
Memory Constant Bank Number MSB
0
[6:5]
rw
Reserved
Read returns ‘0’.
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MEXSP
Memory Extension Stack Pointer Register
7
6
5
Reset Value: 7FH
4
3
0
MXSP
r
rwh
2
1
0
Field
Bits
Type
Description
MXSP
[6:0]
rwh
Memory Extension Stack Pointer
It provides for a stack depth of up to 128 bytes. It is pre-incremented
by call instructions and post-decremented by return instructions.
0
7
r
Reserved
Read returns ‘0’.
6.5
Instruction Timing
A CPU machine cycle comprises two input clock periods, referred to as Phase 1 (P1) and Phase 2 (P2), that
correspond to two different CPU states. A CPU state within an instruction is referenced by the machine cycle and
state number, e.g., C2P1 means the first clock period within machine cycle 2. Memory access takes place during
one or both phases of the machine cycle. SFR writes occur only at the end of P2. Instructions are 1, 2, or 3 bytes
long and can take 1, 2 or 4 machine cycles to execute. Registers are generally updated and the next opcode prefetched at the end of P2 of the last machine cycle for the current instruction.
The XC800 core supports access to slow memory by using wait cycle(s). Each wait cycle lasts one machine cycle,
i.e. two clock periods. For example, in case of a memory requiring one/two wait state(s), the access time is
increased by one machine cycle for every byte of opcode/operand fetched.
Figure 25 shows the fetch/execute timing related to the internal states and phases. Execution of an instruction
occurs at C1P1. For a 2-byte instruction, the second reading starts at C1P1.
Figure 25 (a) shows two timing diagrams for a 1-byte, 1-cycle (1 x machine cycle) instruction. The first diagram
shows the instruction being executed within one machine cycle since the opcode (C1P2) is fetched from a memory
without wait state. The second diagram shows the corresponding states of the same instruction being executed
over two machine cycles (instruction time extended), with one wait cycle inserted for opcode fetching from the
NVM memory requiring one/two wait state(s).
Figure 25 (b) shows two timing diagrams for a 2-byte, 1-cycle (1 x machine cycle) instruction. The first diagram
shows the instruction being executed within one machine cycle since the second byte (C1P1) and the opcode
(C1P2) are fetched from a memory without wait state. The second diagram shows the corresponding states of the
same instruction being executed over three machine cycles (instruction time extended), with one wait cycle
inserted for each access to the NVM memory requiring one/two wait state(s). In this case, two wait cycles are
inserted in total.
Figure 25 (c) shows two timing diagrams of a 1-byte, 2-cycle (2 x machine cycle) instruction. The first diagram
shows the instruction being executed over two machine cycles with the opcode (C2P2) fetched from a memory
without wait state. The second diagram shows the corresponding states of the same instruction being executed
over three machine cycles (instruction time extended), with one wait cycle inserted for opcode fetching from the
slow memory requiring one/two wait state(s).
Note: For instructions that are executed over two or more machine cycles, execution cycle may or may not be
extended in case of access to slow memory with one/two wait states. The execution cycle is, nonetheless,
guaranteed consistent for each instruction when accessed from slow memory with defined wait state(s).
Reference: Table 24.
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Instruction Timing Examples
fCCLK
Read next opcode
(without wait state)
C1P1
C1P2
next instruction
Read next opcode
(one wait cycle)
C1P1
C1P2
WAIT
WAIT
next instruction
(a) 1-byte, 1-cycle instruction, e.g. INC A
Read 2nd byte
(without wait state)
C1P1
Read next opcode
(without wait state)
C1P2
next instruction
Read 2nd byte
(one wait cycle)
C1P1
WAIT
Read next opcode
(one wait cycle)
WAIT
C1P2
WAIT
WAIT
next instruction
(b) 2-byte, 1-cycle instruction, e.g. ADD A, #data
Read next opcode
(without wait state)
C1P1
C1P2
C2P1
C2P2
next instruction
Read next opcode
(one wait cycle)
C1P1
C1P2
C2P1
C2P2
WAIT
WAIT
next instruction
(c) 1-byte, 2-cycle instruction, e.g. MOVX
Figure 25
CPU Instruction Timing
The time taken for each instruction includes:
•
•
•
decoding/executing the fetched opcode
fetching the operand/s (for instructions > 1 byte)
fetching the first byte (opcode) of the next instruction (due to CPU pipeline)
Note: The XC800 Core fetches the opcode of the next instruction while executing the current instruction.
Table 24 lists all the instructions supported by the XC800 Core. Instructions are 1, 2 or 3 bytes long as indicted in
the ‘Bytes’ column. Each instruction takes 1, 2 or 4 machine cycles to execute (with no wait cycle). The table gives
two values for the number of machine cycles required by each instruction. The first value applies to fetching
operand/s and opcode from fast memory (e.g. Boot ROM and XRAM) without wait state. The second value applies
to fetching operand/s and opcode (and in some cases accessing data) from slow memory (e.g. NVM) with wait
cycles inserted due to memory requiring one/two wait state(s). One machine cycle comprises two CCLK clock
cycles.
Note: In TLE983x, the NVM access (number of wait states) can be optimized in case of slower CPU clock with
respect to NVM access clock. The CPU frequency is divided by the factor NVMCLKFAC.
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Table 24
Instruction Table
Mnemonic
Hex Code
Bytes
Machine Cycles
(no wait state)
Machine Cycles
(with max. two wait
states1))
28-2F
1
1
2
ADD A,dir
25
2
1
3
ADD A,@Ri
26-27
1
1
2
ADD A,#data
24
2
1
3
ADDC A,Rn
38-3F
1
1
2
ADDC A,dir
35
2
1
3
ADDC A,@Ri
36-37
1
1
2
ADDC A,#data
34
2
1
3
SUBB A,Rn
98-9F
1
1
2
SUBB A,dir
95
2
1
3
SUBB A,@Ri
96-97
1
1
2
SUBB A,#data
94
2
1
3
INC A
04
1
1
2
INC Rn
08-0F
1
1
2
INC dir
05
2
1
3
INC @Ri
06-07
1
1
2
DEC A
14
1
1
2
ARITHMETIC
ADD A,Rn
DEC Rn
18-1F
1
1
2
DEC dir
15
2
1
3
DEC @Ri
16-17
1
1
2
INC DPTR
A3
1
2
2
MUL AB
A4
1
4
4
DIV AB
84
1
4
4
DA A
D4
1
1
2
LOGICAL
ANL A,Rn
58-5F
1
1
2
ANL A,dir
55
2
1
3
ANL A,@Ri
56-57
1
1
2
ANL A,#data
54
2
1
3
ANL dir,A
52
2
1
3
ANL dir,#data
53
3
2
5
ORL A,Rn
48-4F
1
1
2
ORL A,dir
45
2
1
3
ORL A,@Ri
46-47
1
1
2
ORL A,#data
44
2
1
3
ORL dir,A
42
2
1
3
ORL dir,#data
43
3
2
5
XRL A,Rn
68-6F
1
1
2
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Table 24
Instruction Table (cont’d)
Mnemonic
Hex Code
Bytes
Machine Cycles
(no wait state)
Machine Cycles
(with max. two wait
states1))
XRL A,dir
65
2
1
3
XRL A,@Ri
66-67
1
1
2
XRL A,#data
64
2
1
3
XRL dir,A
62
2
1
3
XRL dir,#data
63
3
2
5
CLR A
E4
1
1
2
CPL A
F4
1
1
2
SWAP A
C4
1
1
2
RL A
23
1
1
2
RLC A
33
1
1
2
RR A
03
1
1
2
RRC A
13
1
1
2
MOV A,Rn
E8-EF
1
1
2
MOV A,dir
E5
2
1
3
MOV A,@Ri
E6-E7
1
1
2
MOV A,#data
74
2
1
3
MOV Rn,A
F8-FF
1
1
2
MOV Rn,dir
A8-AF
2
2
4
MOV Rn,#data
78-7F
2
1
3
MOV dir,A
F5
2
1
3
MOV dir,Rn
88-8F
2
2
4
MOV dir,dir
85
3
2
5
MOV dir,@Ri
86-87
2
2
4
DATA TRANSFER
MOV dir,#data
75
3
2
5
MOV @Ri,A
F6-F7
1
1
2
MOV @Ri,dir
A6-A7
2
2
4
MOV @Ri,#data
76-77
2
1
3
MOV DPTR,#data
90
3
2
5
MOVC A,@A+DPTR
93
1
2
3 or 42)
MOVC A,@A+PC
83
1
2
3 or 42)
MOVX A,@Ri
E2-E3
1
2
3
MOVX A,@DPTR
E0
1
2
3
MOVX @Ri,A
F2-F3
1
2
3
MOVX @DPTR,A
F0
1
2
3
PUSH dir
C0
2
2
4
POP dir
D0
2
2
4
XCH A,Rn
C8-CF
1
1
2
XCH A,dir
C5
2
1
3
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Table 24
Instruction Table (cont’d)
Mnemonic
Hex Code
Bytes
Machine Cycles
(no wait state)
Machine Cycles
(with max. two wait
states1))
XCH A,@Ri
C6-C7
1
1
2
XCHD A,@Ri
D6-D7
1
1
2
CLR C
C3
1
1
2
CLR bit
C2
2
1
3
SETB C
D3
1
1
2
SETB bit
D2
2
1
3
CPL C
B3
1
1
2
BOOLEAN
CPL bit
B2
2
1
3
ANL C,bit
82
2
2
4
ANL C,/bit
B0
2
2
4
ORL C,bit
72
2
2
4
ORL C,/bit
A0
2
2
4
MOV C,bit
A2
2
1
3
MOV bit,C
92
2
2
4
ACALL addr11
11->F1
2
2
4
LCALL addr16
12
3
2
5
RET
22
1
2
2 or 32)
RETI
32
1
2
2 or 32)
AJMP addr 11
01->E1
2
2
4
LJMP addr 16
02
3
2
5
SJMP rel
80
2
2
4
JC rel
40
2
2
4
JNC rel
50
2
2
4
JB bit,rel
20
3
2
5
JNB bit,rel
30
3
2
5
JBC bit,rel
10
3
2
5
JMP @A+DPTR
73
1
2
2 or 32)
JZ rel
60
2
2
4
JNZ rel
70
2
2
4
CJNE A,dir,rel
B5
3
2
5
CJNE A,#d,rel
B4
3
2
5
CJNE Rn,#d,rel
B8-BF
3
2
5
CJNE @Ri,#d,rel
B6-B7
3
2
5
DJNZ Rn,rel
D8-DF
2
2
4
DJNZ dir,rel
D5
3
2
5
00
1
1
2
BRANCHING
MISCELLANEOUS
NOP
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XC800 Core
Table 24
Instruction Table (cont’d)
Mnemonic
Hex Code
Bytes
Machine Cycles
(no wait state)
Machine Cycles
(with max. two wait
states1))
MOVC @(DPTR++),A
A5
1
2
2 or 32)
TRAP
A5
1
1
–
ADDITIONAL INSTRUCTIONS
1) In case of fetch from slow memory requiring more than 2 wait states, the number of wait cycles could be more resulting in
longer machine cycles per the instruction fetched (normally for opcodes requiring a subsequent operand fetch in the next
clock cycle).
2) Depending on whether the operation is accessing memory with zero or one/two wait state.
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7
Memory Architecture
The TLE983x CPU manipulates operands in the following memory spaces:
•
•
•
•
•
•
64 kByte of Flash memory in code space
BootROM memory in code space
256 Byte of internal RAM data memory in internal data space
3 kByte of XRAM memory in code space and external data space (XRAM can be read/written as program
memory or external data memory)
128 Byte of special function registers SFR in internal data space
256 Byte of special function registers XSFR in external data space.
Figure 26 illustrates the memory address spaces of the TLE983x.
F' FFFF H
Bank F
F' 0000H
Bank E
Bank D
E' 0000H
Reserved
1)
Bank C
C' 0000H
B ank A
Bank B
B' 0000H
Reserved
A' 0C00H
XRAM
3 kByte
A' 0000H
Bank 9
2)
8' 0000H
Bank 7
Reserved 1)
Bank 5
7' 0000H
Memory Extension
Stack Pointer
(MEXSP)
6' 0000H
5' 0000H
Bank 4
FFH
4' 0000H
Bank 3
Reserved
XRAM
3 kByte
B a nk 2
Reserved
9' 0000H
Bank 8
Bank 6
D' 0000H
3' 0000H
2' FC00H
2' F000H
Reserved
XRAM
3 kByte
80H
BootROM
2' 9000H
Reserved
Reserved
2' 8000H
Flash
Lower 32 kByte
2' 0100H
2' 0000H
Bank 1
Reserved
Indirect
Address
XSFR, 256 Byte
Direct
Address
FFH
1)
Internal RAM
1' 0000H
B a nk 0
Not user-accessible ;
HW access only
Extension Stack RAM
Flash
Upper 32 kByte
Special Function Registers
80H
Reserved 2)
0' 8000H
7FH
Flash
Lower 32 kByte
40H
00H
0' 0000H
Code Space
Internal RAM
External Data Space
Internal Data Space
Memory Map User Mode
1) The lower 32 kByte of the 64 kByte Flash is always mapped and can be accessed in the lower half (0000H to 7FFFH) of each bank in
the code space (except bank A, where the 3 kByte XRAM is mapped.)
2) XRAM is always mapped and can be accessed in the range (F000H to FBFFH) of each bank in the external data space;
XSFR is always mapped and can be accessed in the range (0000H to 00FFH) of each bank in the external data space.
Figure 26
TLE983x Memory Map
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Note: XRAM is always mapped and can be accessed in the range (F000H to FBFFH) of each bank in the external
data space;
XSFR is always mapped and can be accessed in the range (0000H to 00FFH) of each bank in the external
data space.
7.1
Program Memory
The program memory is theoretically expanded up to 1 MByte, but actually excluding some reserved
regions.These reserved regions are not occupied by internal memory. TLE983x does not support physical external
memory access.
The lower 32 KByte of the Flash is always mapped and can be accessed in the lower half (0000H to 7FFFH) of
each bank in the code space. For Derivatives with a Flash size greater than 32KByte like XC800, the user code
must be executed from Bank0.
For Derivatives with a Flash size equal to or less than 32KByte, the user code must be executed from Bank2. This
is necessary in order to ensure a proper operation with the Boot ROM routines.
7.2
Data Memory
The data memory space consists of an internal and external memory space. The data space can theoretically be
externally expanded up to 1 MByte.
7.2.1
Internal Data Memory
The internal data memory is divided into three physically separate and distinct blocks: the 256 Byte RAM, the 128
Byte special function register (SFR) area and the 128 Byte extension memory stack RAM. While the upper 128
Byte of RAM, the SFR area and the 128 Byte extension memory stack RAM share the same address locations,
they are accessed through different addressing modes. The lower 128 Byte of RAM can be accessed through
direct or register indirect addressing - the upper 128 Byte of RAM can be accessed through register indirect
addressing; the special function registers are accessible through direct addressing; the 128 Byte extension
memory stack RAM are not accessible directly. Its address is indicated via MEXSP register.
The 16 Byte of RAM that occupy addresses from 20H to 2FH are Bit addressable. RAM occupying direct addresses
from 30H to 7FH can be used as scratch pad registers or for the stack.
7.2.2
External Data Memory
The on-chip 3 kByte XRAM and the 256 Byte XSFR are located in the external data memory space, and are
accessible in the defined address range on bank 2. Access to physical external memory is not supported.
External data memory space is accessed using MOVX instructions only. These use either 8-Bit or 16-Bit indirect
address. The DPTR register is used for 16-Bit addressing and either register R0 or R1 is used to form the 8-Bit
address. To access the respective external data memory, the bank where the memory resides must be selected
in MEX3.MX (XRAM bank) or MEX1.CB (current bank), depending on Bit MXM.
Section 7.2.2.1 and Section 7.2.2.2 describes the two methods to access the on-chip XRAM. The same can be
used to access the XSFR.
7.2.2.1
Access to External Data Memory Using the DPTR (16-Bit addressing mode)
The external data memory can be accessed by the 16-Bit DPTR for indirect addressing. These instructions are:
•
•
MOVX A, @DPTR (Read)
MOVX @DPTR, A (Write)
If the address is pointing to the on-chip XRAM, the physically on-chip XRAM will be accessed.
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7.2.2.2
Access to External Data Memory using the Register R0/R1 (8-Bit addressing
mode)
The TLE983x provides also instructions for accesses to on-chip XRAM, which use the 8-Bit address (indirect
addressing with registers R0 or R1). These instructions are:
•
•
MOVX A, @Ri (Read)
MOVX @Ri, A (Write)
To access on-chip XRAM, register XADDRH must be initialized. If bank 2 is selected and the content of the register
points to the range F0H to FBH, on-chip XRAM (in the address range of 2’F000H to 2’FBFFH) is accessed with the
higher order address Byte taking the value of the register content on the MOVX instruction.
Otherwise outside of this range, the on-chip XRAM will not be accessed on MOVX instruction.
Note: The definition of XADDRH register please refer to Chapter 20.9 of SCU chapter.
7.3
Error Correction Code (ECC) in Data Memory
The XRAM and IRAM includes an ECC logic to support single Bit error correction and double Bit error detection.
Each Byte of data requires a 5-Bit ECC.
When an ECC error occurs, the corresponding status flag in register EDCSTAT will be set. A double Bit error can
be configured via the interrupt enable Bit in register EDCCON to trigger an NMI.
Note: The definition of error detection and correction registers please refer to Chapter 20.10 of SCU chapter.
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7.4
Special Function Registers
All registers, except the program counter, reside in the SFR area. The SFR area consists of two portions: the
standard (non-mapped) SFR area and the mapped SFR area. To access the mapped SFR area, the SCU SFRBit SYSCON0.RMAP must be set. Alternatively, the standard SFR area can be accessed by clearing Bit RMAP (0).
SYSCON0
System Control Register 0
7
Reset Value: See Table 12
6
5
4
3
2
1
0
SYSCLKSEL
NVMCLKFAC
IMODE
0
RMAP
rw
rw
rw
r
rw
Field
Bits
Type
Description
RMAP
0
rw
Special Function Register Map Control
0B
The access to the non-mapped (standard) SFR area is
enabled.
1B
The access to the mapped SFR area is enabled.
0
[2:1]
r
Reserved
Returns 0 if read.
As long as Bit RMAP is set, the mapped SFR area can be accessed. This Bit is not cleared automatically by
hardware. Thus, before non-mapped/mapped registers are accessed, the Bit RMAP must be cleared/set,
respectively, by software.
The special function registers include pointers and registers that provide an interface between the CPU and the
other on-chip peripherals. SFRs that have addresses of the form 1XXXX000B (e.g. 80H, 88H, 90H, …, F0H, F8H)
are Bit-addressable.
All SFRs are listed in Table 25 and Table 26.
In Table 25, they are organized into standard and mapped SFRs.
Table 25
SFR Address Map
Standard (non-mapped) SFRs
Mapped SFRs
80H
PORT0
C0H
MOD
80H
81H
SP
C1H
MOD
81H
SP
C1H
82H
DPL
C2H
MOD
82H
DPL
C2H
83H
DPH
C3H
MOD
83H
DPH
C3H
84H
(reserved)
C4H
MOD
84H
(reserved)
C4H
85H
(reserved)
C5H
MOD
85H
(reserved)
C5H
86H
PORT0
C6H
MOD
86H
87H
PCON
C7H
PERIPHERAL_PAG
E
87H
PCON
C7H
88H
TCON
C8H
PORT2
88H
TCON
C8H
89H
TMOD
C9H
PORT2
89H
TMOD
C9H
8AH
TL0
CAH
ADC1
8AH
TL0
CAH
8BH
TL1
CBH
ADC1
8BH
TL1
CBH
8CH
TH0
CCH
ADC1
8CH
TH0
CCH
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TLE983x
Memory Architecture
Table 25
SFR Address Map (cont’d)
Standard (non-mapped) SFRs
Mapped SFRs
8DH
TH1
CDH
ADC1
8DH
TH1
CDH
8EH
PORT_PAGE
CEH
ADC1
8EH
8FH
SYSCON0
CFH
ADC1
8FH
90H
PORT1
D0H
PSW
90H
D0H
91H
PORT1
CEH
SYSCON0
CFH
D1H
ADC_PAGE
91H
D1H
92H
D2H
ADC1
92H
D2H
93H
D3H
ADC1
93H
D3H
94H
MEX1
D4H
94H
MEX1
D4H
95H
MEX2
D5H
95H
MEX2
D5H
96H
MEX3
D6H
96H
MEX3
D6H
97H
MEXSP
D7H
97H
MEXSP
D7H
98H
SCON
D8H
98H
SCON
D8H
99H
SBUF
D9H
99H
SBUF
9AH
CCU6
DAH
9AH
DAH
9BH
CCU6
DBH
9BH
DBH
9CH
CCU6
DCH
9CH
DCH
9DH
CCU6
DDH
9DH
DDH
9EH
CCU6
DEH
9EH
DEH
9FH
CCU6
DFH
9FH
DFH
E0H
A0H
A1H
E0H
A
A0H
PSW
D9H
E1H
FLASH
A1H
A2H
EO
E2H
FLASH
A2H
A3H
CCU6_PAGE
E3H
FLASH
A3H
E3H
A4H
CCU6
E4H
FLASH
A4H
E4H
A5H
CCU6
E5H
FLASH
A5H
E5H
A6H
CCU6
E6H
FLASH
A6H
E6H
A7H
CCU6
E7H
FLASH
A7H
E7H
A8H
IEN0
E8H
IEN1
A8H
A9H
SSC_PISEL
E9H
FLASH
AAH
SSC_CONL
EAH
FLASH
ABH
SSC_CONH
EBH
ACH
SSC_TBL
ADH
A
E1H
EO
E8H
IEN1
A9H
E9H
MMCR2
AAH
EAH
MEXTCR
FLASH
ABH
EBH
MMWR1
ECH
FLASH
ACH
ECH
MMWR2
SSC_RBL
EDH
FLASH
ADH
EDH
AEH
SSC_BRL
EEH
AEH
EEH
AFH
SSC_BRH
EFH
AFH
EFH
B0H
MDU_MDUSTAT
F0H
B
B0H
F0H
B
B1H
MDU_MDUCON
F1H
SCU_PAGE
B1H
F1H
MMCR
B2H
MDU_MD0/MR0
F2H
SCU
B2H
F2H
MMSR
B3H
MDU_MD1/MR1
F3H
SCU
B3H
F3H
MMBPCR
B4H
MDU_MD2/MR2
F4H
SCU
B4H
F4H
MMICR
B5H
MDU_MD3/MR3
F5H
SCU
B5H
F5H
MMDR
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Memory Architecture
Table 25
SFR Address Map (cont’d)
Standard (non-mapped) SFRs
Mapped SFRs
B6H
MDU_MD4/MR4
F6H
SCU
B6H
F6H
HWBPSR
B7H
MDU_MD5/MR5
F7H
SCU
B7H
F7H
HWBPDR
B8H
IP
F8H
IP1
B8H
IP
F8H
IP1
B9H
IPH
F9H
IPH1
B9H
IPH
F9H
IPH1
BAH
FAH
CCU6
BAH
FAH
BBH
FBH
CCU6
BBH
FBH
BCH
FCH
CCU6
BCH
FCH
BDH
FDH
CCU6
BDH
FDH
BEH
FEH
CCU6
BEH
FEH
BFH
FFH
CCU6
BFH
FFH
Note: The FLASH SFRs can only be accessed by the user via the Boot ROM FLASH routines. The user can obtain
the FLASH status, program or erase the FLASH by calling these routines. It is not supported for the user to
directly access the FLASH SFRs.
7.4.1
Address Extension by Paging
The TLE983x has a 256-SFR address range. This is less than the total number of SFRs needed by the on-chip
peripherals. To meet this demand, some of these peripherals have a built-in local address extension mechanism,
where additional address lines are added to decode the SFRs of the peripheral kernel. The additional address
lines are not directly controlled by the CPU instruction itself, but they are derived from register Bits that must be
programmed before accessing the target module. In this way, these new address Bits, defined in the Bus
Peripheral Interface (BPI), select a page inside the extended address range; see Figure 27.
local address
range extension
limited address
range
page
system bus
CPU
addr[y:x+1]
addr[x:0]
data
extended
address range
addr[x:0]
BPI
module
kernel
data
Page_BPI
Figure 27
Paging in the BPI
In order to access a register located in a page different to the actual one, the current page must be left. This is
done by reprogramming the page Bits in the page register. Then only can the desired access be done.
This leads to an inconvenience, especially in interrupt routines. If an interrupt routine is initiated between the page
register access and the module register access, and the interrupt must access a register located in another page,
the current page setting must be saved, the new one programmed and finally, the old page setting restored.
Actions to be taken in an interrupt routine:
•
•
•
•
•
read current page setting
store value read before (or keep it in a dedicated register)
program new page value
interrupt task
get old page setting (if not kept in dedicated register)
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•
restore old page setting
If the interrupt routine is short, the effort to control the paging mechanism becomes important compared to the
interrupt task.
Therefore, the paging mechanism can be made intelligent (up to a certain degree), so that under specific
conditions, the read action of the current page setting and its storage are not necessary.
The paging mechanism thus contains a certain number of storage Bits (ST0..STn) for the save and the restore
action of the current page setting. By indicating which storage Bit field should be used in parallel to the new page
value, a single write operation can replace the first three operations of the list above.
STn
...
ST1
page
control bits
addr[y:x+1]
from system
bus
ST0
PAGE
addr[y:x+1]
to module
kernel
Page_storage
Figure 28
Storage Elements for Paging
The additional page control information on where to store the current PAGE register contents can be given in
several ways, e.g. as additional data Bits, as address value, etc.
With this mechanism, a certain number of interrupt routines (or other routines) can do page changes without
reading and storing the formerly used page information. The use of only write operations makes the system
simpler and faster (the CPU waits for each read access, whereas write operations flow directly through the
pipeline). As a result, this mechanism significantly improves the performance for short interrupt routines.
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The page register has the following definition:
MOD_PAGE
Page Register for Module MOD
7
6
Reset Value: 00H
5
4
3
2
1
OP
STNR
PAGE
w
w
rwh
0
Field
Bits
Type
Description
PAGE
[3:0]
rwh
Page Bits
When written, the value indicates the new page address.
When read, the value indicates the currently active page = addr
[y:x+1] in Figure 27.
STNR
[5:4]
w
Storage Number
This number indicates which storage Bit field is the target of the
operation defined by Bit OP.
If OP = 10B,
the contents of PAGE are saved in STx before being overwritten with
the new value.
If OP = 11B,
the contents of PAGE are overwritten by the contents of STx. The
value written to the Bit positions of PAGE is ignored.
00B ST0 is selected.
01B ST1 is selected.
10B ST2 is selected.
11B ST3 is selected.
OP
[7:6]
w
Operation
0XB Manual page mode. The value of STNR is ignored and PAGE
is directly written.
10B New page programming with automatic page saving. The
value written to the Bit positions of PAGE is stored. In parallel,
the former contents of PAGE are saved in the storage Bit field
STx indicated by STNR.
11B Automatic restore page action. The value written to the Bit
positions PAGE is ignored and instead, PAGE is overwritten by
the contents of the storage Bit field STx indicated by STNR.
Note: The Bit positions marked ‘w’ are virtual and do not contain any flip-flops. They always read 0. They are used
as additional information to control the page mechanism.
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The on-chip peripherals of the TLE983x which support the local address extension are:
•
•
•
•
•
General Purpose I/O Ports
Analog Digital Converter
System Control Unit
Capture/Compare Unit 6
T2/T21
The SFRs of the peripherals are organized into pages shown in Table 26.
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Memory Architecture
Table 26
SFR Page List
PORTS x - PAGE (8EH): SFR starts with Px_xxxx
Addr.
Page 0
Page 1
Page 2
Page 3
80H
P0_DATA
P0_PUDSEL
P0_ALTSEL0
P0_OD
86H
P0_DIR
P0_PUDEN
P0_ALTSEL1
90H
P1_DATA
P1_PUDSEL
P1_ALTSEL0
91H
P1_DIR
P1_PUDEN
P1_ALTSEL1
C8H
P2_DATA
P2_PUDSEL
C9H
P2_DIR
P2_PUDEN
P1_OD
ADC1 - PAGE (D1H) NOTE: SFR starts with ADC_xxxx
Addr.
Page 0
Page 1
Page 2
Page 3
CAH
GLOBCTR
CHCTR0
RESR0L
RESRA0L
CBH
GLOBSTR
CHCTR1
RESR0H
RESRA0H
CCH
PRAR
CHCTR2
RESR1L
RESRA1L
CDH
LCBR
CHCTR3
RESR1H
RESRA1H
CEH
INPCR0
CHCTR4
RESR2L
RESRA2L
CFH
ETRCR
CHCTR5
RESR2H
RESRA2H
D2H
ETRSR
CHCTR6
RESR3L
RESRA3L
CHCTR7
RESR3H
RESRA3H
D3H
Addr.
Page 4
Page 5
Page 6
Page 7
CAH
RCR0
CHINFR
CRCR1
LCBR0
CBH
RCR1
CHINCR
CRPR1
LCBR1
CCH
RCR2
CHINSR
CRMR1
LCBR2
CDH
RCR3
CHINPR
QMR0
LCBR3
CEH
VFCR
EVINFR
QSR0
LCBR4
CFH
EMENR
EVINCR
Q0R0
LCBR5
D2H
EMCTR
EVINSR
QBUR0 / QINR0
LCBR6
D3H
EMSTR
EVINPR
LCBR7
PERIPHERAL - PAGE (C7H) NOTE: SFR starts with MOD_xxxx
Addr.
Page 0
C0H
T2_T2CON
C1H
T2_T2MOD
C2H
T2_RC2L
C3H
T2_RC2H
C4H
T2_T2L
C5H
T2_T2H
C6H
T2_T2CON1
Addr.
Page 4
Page 1
Page 2
Page 3
Page 5
Page 6
Page 7
C0H
C1H
C2H
C3H
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Table 26
SFR Page List (cont’d)
C4H
C5H
C6H
Addr.
Page 8
C0H
T21_T2CON
C1H
T21_T2MOD
C2H
T21_RC2L
C3H
T21_RC2H
C4H
T21_T2L
C5H
T21_T2H
C6H
T21_T2CON1
Page 9
Page 10
Page 11
SCU - PAGE (F1H), SYSCON0 (8FH mapped & non-mapped)
Addr.
Page 0
Page 1
Page 2
Page 3
F2H
IRCON0
NMICON
PASSWD
XADDRH
F3H
IRCON1
EXICON0
PMCON0
PMCON1
F4H
PLL_CON
F5H
IRCON3
CMCON
F6H
IRCON4
WDTCON
F7H
NMISR
MODIEN
Addr.
Page 4
Page 5
Page 6
Page 7
BCON
ID
MODPISEL
F2H
F3H
WDTREL
BGL
F4H
WDTWINB
BGH
OSC_CON
MODPISEL1
F5H
WDTL
LINST
COCON
F6H
WDTH
MODPISEL2
MODSUSP
F7H
Addr.
Page 8
Page 9
Page 10
F2H
EDCCON
P0_POCON0
F3H
EDCSTAT
P0_POCON1
F4H
Page 11
P0_POCON2
F5H
F6H
F7H
MEMSTAT
Addr.
Page 12
F2H
P1_POCON0
F3H
P1_POCON1
F4H
P1_POCON2
TCCR
Page 13
F5H
F6H
F7H
CCU6 - PAGE (A3H) NOTE: SFR starts with CCU6_xxxx
Addr.
Page 0
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Memory Architecture
Table 26
SFR Page List (cont’d)
9AH
CC63SRL
CC63RL
T12MSELL
MCMOUTL
9BH
CC63SRH
CC63RH
T12MSELH
MCMOUTH
9CH
TCTR4L
T12PRL
IENL
ISL
9DH
TCTR4H
T12PRH
IENH
ISH
9EH
MCMOUTSL
T13PRL
INPL
PISEL0L
9FH
MCMOUTSH
T13PRH
INPH
PISEL0H
A4H
ISRL
T12DTCL
ISSL
PISEL2
A5H
ISRH
T12DTCH
ISSH
A6H
CMPMODIFL
TCTR0L
PSLR
A7H
CMPMODIFH
TCTR0H
MCMCTRL
MCMCTRH
FAH
CC60SRL
CC60RL
TCTR2L
T12L
FBH
CC60SRH
CC60RH
TCTR2H
T12H
FCH
CC61SRL
CC61RL
MODCTRL
T13L
FDH
CC61SRH
CC61RH
MODCTRH
T13H
FEH
CC62SRL
CC62RL
TRPCTRL
CMPSTATL
FFH
CC62SRH
CC62RH
TRPCTRH
CMPSTATH
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7.5
Memory Control Unit
The Memory Control Unit (MCU) is the interface between the CPU and the memories, providing three functions to
the TLE983x:
Active memory map selection
Allows one physical memory (i.e. XRAM) to be accessed as both program and data memory at the same time
Memory protection
F' FFFF H
F' 0000H
E' FFFF H
E' 0000H
D' FFFF H
D' 0000H
C' FFFF H
C' 0000H
B' FFFF H
B' 0000H
A' FFFF H
A' 0000H
9' FFFF H
9' 0000H
8' FFFF H
8' 0000H
7' FFFF H
7' 0000H
6' FFFF H
6' 0000H
5' FFFF H
5' 0000H
4' FFFF H
4' 0000H
3' FFFF H
3' 0000H
2' FFFF H
Bank E
Bank D
Bank C
Bank B
Bank A
Bank 9
Bank 8
Bank 7
Bank 6
Bank 5
Bank 4
Bank 2
Bank 3
Jump to
Bank 2,
A80XH
1
CPU starts
execution
2' 9C00H
Select
active
memory
map 1
2' 0000H
1' FFFF H
Bank 1
1' 0000H
0' FFFF H
0' 5400H
Boot ROM
21 KByte
Bank E
Bank D
Bank C
Bank B
Bank A
Reserved
1)
Bank 9
Bank 8
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
2' F000H
3
Bank 0
2
Boot ROM
21 KByte
Bank F
Bank 2
Bank F
Reserved
XRAM
3 KByte
Boot ROM
21 KByte
Reserved
Bank 1
Reserved
1)
NVM
Upper 32 KByte
2' F000H
2' 9C00H
2' 8000H
2' 0000H
1' FFFF H
1' 0000H
0' FFFF H
0' 8000H
NVM
Lower 32 KByte
0' 0000H
Active Memory Map 1
F' FFFF H
F' 0000H
E' FFFF H
E' 0000H
D' FFFF H
D' 0000H
C' FFFF H
C' 0000H
B' FFFF H
B' 0000H
A' FFFF H
A' 0000H
9' FFFF H
9' 0000H
8' FFFF H
8' 0000H
7' FFFF H
7' 0000H
6' FFFF H
6' 0000H
5' FFFF H
5' 0000H
4' FFFF H
4' 0000H
3' FFFF H
3' 0000H
2' FFFF H
2' FC00H
NVM
Lower 32 KByte
Bank 0
•
•
•
0' 0000H
Active Memory Map 0
1) The lower 32 Kbyte of the 64 Kbyte NVM is always mapped
and can be accessed in the lower half (0000H to 7FFFH) of each
bank in the code space.
(After reset)
2) The 3 Kbyte XRAM is also mapped to Bank A at 0000H to
0BFFH (not shown in the above address map).
Figure 29
Active Memory Map Select
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7.6
Program and XRAM Data Bus Control
The MCU allows one physical memory or memories (non-overlapping) residing in the address range from 2’F000H
– 2’FBFFH and A’0000H – A’0BFFH, to be accessed as both program memory and external data memory at the
same time. Currently, the TLE983x has a 3-Kbyte XRAM residing in this address range.
The ‘MOVC @(DPTR++),A’ instruction is used to download software into the program memory where this is
implemented as RAM. This instruction can also be used subsequently to modify contents of the program memory.
The ‘MOVX’ instructions are used to access the XRAM and the XSFR as external data memory.
Note: A ‘MOVX’ instruction may cause a dummy program fetch if the targeted data memory address is also a valid
address in the program address space. The dummy program fetch will trigger an ECC error in the event the
data in the program memory space contains a real ECC error.
7.6.1
Memory Protection Unit
The TLE983x consists of the following memory blocks:
•
•
•
Boot ROM
NVM
XRAM
The target of the memory protection scheme is to prevent unauthorized read out of critical data and user IP from
the Boot ROM and NVM. Two memory protection schemes are offered in TLE983x.
The first memory protection scheme involves the blocking of all external access to the device by firmware.
Firmware will block the boot options such that it is not possible to load and execute external code, but only to
execute the user code starting from address 0000H. To enable this memory protection scheme, a valid password
must be programmed via the BootROM password routine.
The second memory protection scheme is hardware-based; MOVC read instructions executed out of the “unsafe”
program memory address range (e.g. XRAM) that target the Boot ROM or NVM are blocked when the respective
protection mode is enabled.
7.6.2
Hardware Protection Modes
Regardless of the protection modes, the following MOVC accesses are always possible:
•
•
•
•
MOVC read instructions that are executed from the Boot ROM can target itself or the XRAM
MOVC read instructions that are executed from the NVM linear range can target itself, the NVM non-linear
range or the XRAM
MOVC read instructions that are executed from the NVM non-linear range can target itself or the XRAM
MOVC read instructions that are executed from the XRAM can target itself
Unauthorized MOVC read access to the Boot ROM and/or NVM can be detected and consequently blocked by
the different memory protection modes: Boot ROM protection mode and NVM protection modes.
7.6.2.1
Boot ROM Protection Mode
The Boot ROM protection is enabled by default, and the following accesses are restricted:
•
MOVC read instructions that are executed from the NVM or the XRAM will be blocked if the Boot ROM
addresses are targeted
Figure 30 shows the possible MOVC execution paths (fetch + execute) when only the Boot ROM protection is
enabled (NVM protection modes disabled).
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XRAM
Non-linearly
Mapped NVM
Boot ROM
Linearly Mapped
NVM
Legend
Source address space from which MOVC read instruction is fetched
Target address space from which data is read
MOVC read instruction unblocked (read from target memory location allowed)
Boot ROM protection
Figure 30
Boot ROM Protection Mode Enabled
If the Boot ROM protection mode is enabled without enabling any NVM protection mode:
•
•
MOVC instructions that are executed from the NVM or the XRAM can target itself or one another
MOVC instructions that are executed from the Boot ROM can target itself, the NVM or the XRAM
7.6.2.2
NVM Protection Modes
Each NVM may be flexibly assigned on its linear and non-linear range based on sector addresses. The linear
range is used for program code while the non-linear range is used for data.
Protection for Linearly Mapped NVM
The linearly mapped NVM is read and program protected by default when NVM protection is enabled from the Boot
ROM password routine. The read and/or program protection can be dynamically enabled or disabled in user code
by calling the appropriate user routines in the Boot ROM.
With program protection enabled, no program or erase of the protected NVM range is possible. This prevents
inadvertent destruction of NVM contents.
With read protection enabled, the following restriction applies:
•
MOVC read instructions that are executed from the Boot ROM, non-linearly mapped NVM or the XRAM will be
blocked if the linearly mapped NVM addresses are targeted
Figure 31 shows the possible MOVC execution paths (fetch + execute) when both the Boot ROM protection mode
and linearly mapped NVM read protection are enabled.
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XRAM
Non-linearly
Mapped NVM
Boot ROM
Linearly Mapped
NVM
Legend
Source address space from which MOVC read instruction is fetched
Target address space from which data is read
MOVC read instruction unblocked (read from target memory location allowed)
Boot ROM and linearly mapped NVM read protectio
Figure 31
Boot ROM and Linearly Mapped NVM Read Protection Enabled
If both the Boot ROM protection mode and linearly mapped NVM read protection are enabled:
•
•
•
MOVC instructions that are executed from the non-linearly mapped NVM and the XRAM can target itself or
one another
MOVC instructions that are executed from the Boot ROM can target itself, non-linearly mapped NVM or the
XRAM
MOVC instructions that are executed from the linearly mapped NVM can target itself, non-linearly mapped
NVM or the XRAM
Protection for Non-linearly Mapped NVM
Similar to the linearly mapped NVM, the non-linearly mapped NVM is read and program protected by default when
NVM protection is enabled from the Boot ROM password routine. The read and/or program protection can also be
dynamically enabled or disabled in user code by calling the appropriate user routines in the Boot ROM.
With program protection enabled, no program or erase of the protected NVM range is possible. This prevents
inadvertent destruction of NVM contents.
With read protection enabled, the following restriction applies:
•
MOVC read instructions that are executed from the Boot ROM, non-linearly mapped NVM or the XRAM will be
blocked if the non-linearly mapped NVM addresses are targeted
Figure 32 shows the possible MOVC execution paths (fetch + execute) when the Boot ROM protection mode and
both linearly and non-linearly mapped NVM read protection are enabled.
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XRAM
Non-linearly
Mapped NVM
Boot ROM
Linearly Mapped
NVM
Legend
Source address space from which MOVC read instruction is fetched
Target address space from which data is read
MOVC read instruction unblocked (read from target memory location allowed)
Boot ROM and linearly mapped NVM read protectio
Figure 32
Boot ROM, Linear and Non-linear NVM Read Protection Enabled
If the Boot ROM protection mode and both linearly and non-linearly mapped NVM read protection are enabled:
•
•
•
•
MOVC instructions that are executed from the non-linearly mapped NVM can target the XRAM
MOVC instructions that are executed from the XRAM can target itself
MOVC instructions that are executed from the Boot ROM can target itself or the XRAM
MOVC instructions that are executed from the linearly mapped NVM can target itself, non-linearly mapped
NVM or the XRAM
Boot ROM Password Routine
After the complete code has been programmed into the linearly mapped NVM, the protection scheme can be
enabled by calling the Boot ROM password routine from BSL mode 6. The Boot ROM password routine programs
the user-defined password into the configuration sector and sets the protection mode.
Upon the next reset, the Boot ROM start-up routine will read out the user-defined password in the configuration
sector. If the value is valid (not zero nor the erased value of FFH), a user password is taken to exist and hence
NVM protection is enabled (both linear and non-linear NVM are read and program protected by default).
To allow external access to the device or to reprogram the password in the configuration sector, the same Boot
ROM password routine must be called. The Boot ROM password routine compares the password entered by the
user (e.g. in the XRAM) against the password in the configuration sector. A match activates the unprotected
TLE983x
sequence that will first erase the linearly mapped NVM, but not the configuration sectors. This ensures that even
if the password has been cracked, the user code is destroyed to safe guard against subsequent unauthorized read
out from the device. Non-linearly mapped NVM will also be erased if MSB of user-defined password is one.
Next, the Boot ROM password routine will proceed to erase the password in the configuration sector. To complete
the unprotected sequence, a reset must be performed.
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Embedded Flash Memory
8
Embedded Flash Memory
This chapter describes the embedded flash memory of the TLE983x:
8.1
Definitions
This section defines the nomenclature and some abbreviations. The used flash memory is a non-volatile memory
(“NVM”) based on a floating gate one-transistor cell. It is called “non-volatile” because the memory content is kept
when the memory power supply is shut off.
Logical and Physical States
Flash memory content can not be changed directly as in SRAMs. Changing data is a complicated process with a
typically much longer duration than reading.
•
•
Erasing: The erased state of a cell is logical 1. Forcing an flash cell to this state is called “erasing”. Erasing is
possible with a minimum granularity of one page (see below). A device is delivered with completely erased
flash memory.
Programming: The programmed state of a cell is logical 0. Changing an erased cell to this state is called
“programming”. A page must only be programmed once and has to be erased before it can be programmed
again.
The above listed processes have certain limitations:
•
•
•
Retention: This is the time during which the data of a flash cell can be read reliably. The retention time is a
statistical figure that depends on the operating conditions of the flash array (temperature profile) and the
accesses to the flash array. With an increasing number of program/erase cycles (see endurance) the retention
is lowered. Drain and gate disturbs decrease data retention as well.
Endurance: As described above the data retention is reduced with an increasing number of program/erase
cycles. A flash cell incurs one cycle whenever its page or sector is erased. This number is called “endurance”.
As said for the retention it is a statistical figure that depends on operating conditions and the use of the flash
cells and not to forget on the required quality level.
Drain Disturb: Because of using a so called “one-transistor” flash cell each program access disturbs all pages
of the same sector slightly. Over long these “drain disturbs” make 0 and 1 values indistinguishable and thus
provoke read errors. This effect is again interrelated with the retention. A cell that incurred a high number of
drain disturbs will have a lower retention. The physical sectors of the flash array are isolated from each other.
So pages of a different sector do not incur a drain disturb. This effect must be therefore considered when the
page erase feature is used.
The durations of programming and erasing as well as the limits for endurance, retention and drain disturbs are
documented in the data sheet.
Attention: No means exist in the device that prevent the application from violating these limitation.
Array Structure
The flash memory is hierarchically structured:
•
•
•
Block: A block consists of one doubleword and its associated ECC data (32 Bit data and 7 Bit ECC). A block
represents the smallest data portion that can be changed in the assembly buffer. Since the ECC protects 32
Bits, when a Byte is written to the assembly buffer automatically an Flash internal read of the complete block
is triggered, the Byte and the ECC are updated, and the complete block is written back to the assembly buffer.
One read access delivers one block.
Map Block: A map block consists of a module specific number of ECC-protected Bits that hold the necessary
information to map a physical page to a logical page.
Page: Each page consists of 32 data blocks of 32 bits each and one map block. The map block stores the
mapping information of the page in the sector. All blocks of a page are ECC-protected.
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Embedded Flash Memory
•
•
•
•
Spare Page: A spare page is an additional page in a sector used in each programming routine to allow tearingsafe programming.
Sector: A sector consists of 32 logical and 33 physical pages (i.e. 4096 bytes). The pages of one sector are
affected by drain disturb as described above. The pages of different sectors are isolated from each other.
Array: Each 64 kByte array has 16 sectors1), a 48 kByte array has 12, a 36 kByte array has 9 and a 24 kByte
array has 6 sectors. Usually when referring to an “array” this contains as well all accompanying logic as
assembly buffer, high voltage logic and the digital logic that allows to operate them in parallel.
Memory: The complete flash memory of the TLE983x consists of 1 flash array.
This structure of the is shown in Figure 33.
Sector
Number
24 … 64 kByte
Array
16
Page
Number
Sector
Block
Number
31
Page
31
2
2
2
1
1
1
Sector
0
0
Page
0
Block
41 Bits
7 Bits ECC
32 Bit Data
flas h_array_us erv iew_diagram .v s d
Figure 33
Flash Structure
8.2
Functional Description
The main tasks of the NVM module are reading from the memory array, writing to the assembly buffer, and
enabling (tearing-safe) programming of a single page.
1) For all Flash array sizes, one additional sector is reserved for device internal purposes. It is not accessible by software.
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8.2.1
Basic Block Functions
Figure 233 shows a schematic block diagram of the NVM module.
Page
Analog
Sector
:
:
Sector Address
Page
Sector
map-RAM
:
:
Physical Page
Address
Logical Page
Address
:
:
Page
Sector
:
:
Cell Array
FSM
+
SFRs
ECC
Assembly Buffer
Oscillator
ECC
BPI and NVMI
Bus Interface
BPI and NVMI busses
Figure 34
Schematic view of the NVM module
8.2.1.1
Memory Cell Array
WL NVM SCHEMATIC OVERVIEW
The non-volatile memory cells are organized in sectors, which consist of pages, which on their part are structured
in blocks and a map block.
Page
A page is the smallest granularity of data that can be changed (erased or written) within the cell array. One data
block is the minimum granularity of data that can be read from the NVM module within a memory read access.
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Employing the integrated EEPROM emulation using the map-RAM, the minimum granularity of data that can be
changed in the NVM is one byte, while all other bytes in the page do not change.
Sector
A sector consists of 33 physical pages. 32 pages can be logically addressed during a memory access. One page
is internally used as a spare page.
8.2.1.2
Assembly Buffer
The assembly buffer is a RAM that can hold the contents of one page including the map block.
page
map block
data blocks
memory access
Figure 35
Structure of assembly buffer
8.2.1.3
Map-RAM
The map-RAM is a static RAM that holds the mapping of logical page addresses to physical page addresses for
each sector. It is completely handled by the NVM programming related ROM routines. The map-RAM currently is
sized to support a maximum of 16 sectors map-RAM mapped sectors.
8.2.1.4
FSM and SFR block
This block contains the special function registers (SFRs) of the NVM module. Beside memory reads and writes to
the assembly buffer all interactions of the ROM software with the module take place through register accesses.
The finite state machine (FSM) controls the actions (e.g. read, erase, write) of the NVM module.
8.2.1.5
Analog Components
The module contains analog components to provide all the voltages necessary for erasing, writing and reading the
non-volatile memory cells.
8.2.2
SFR Accesses
All SFRs can only be accessed through the NVM related ROM routines, that is, the customer software cannot
access the SFRs directly but has to use the ROM routines.
8.2.3
Memory Read
The NVM memory internally can be read with a minimum granularity of one block (32 bits).
If the block is not within the memory address range of the NVM module, the module does not react at all and a
different memory module may handle the access.
If the page accessed during a read is not mapped, an NVM_TRAP is triggered (e.g. when accessing an erased
data sector).
Memory read accesses are only possible while no FSM procedure (program, init, sleep or copy) is in progress. A
memory read access while the FSM is busy is stalled as long as the FSM is busy and the access is carried out
when the FSM is in idle mode again.
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Since a read to the memory field takes a fixed time mostly independent of the system frequency, an optimized
number of waitstates (3, 1 or, 0) is generated for different system frequencies selected by
SYSCON0.NVMCLKFAC.
Furthermore, a module internal read buffer holds the block read last. An access to an address within this block
does not trigger a new reading from the memory field but is directly served from the read buffer: For execution of
linear code three out of four byte accesses are served without any waitstates.
8.2.4
Memory Write
Data is not written to the memory array directly, but to the assembly buffer and then copied to the cell array by the
write sequence.
Memory writes are handled through the ROM software, which at first copies the existing content of a page to the
assembly buffer, allows the user to modify the content of the assembly buffer, and afterwards executes the
programming of the data to the memory field followed by a verification step.
8.2.5
Verify
The data programmed by the ROM function is verified by the ROM routine itself. The programmed data in the cell
array is compared with the data still available in the assembly buffer. This is done using suitable hard-read levels.
These hard-read levels provide a margin compared to the normal read level to ensure that the data is actually
programmed with suitably distinct levels for written and erased bits.
8.2.6
Tearing-Safe Programming
The mapping mechanism of the NVM module is used like a log-structured file system: When a page is
programmed in the sector the old values are not physically overwritten, but a different physical page (spare page)
in the same sector is programmed in fact. If the programming fails (e.g. because of power loss during the erase
or write procedure), the old values are still present in the sector. The ROM routines therefore can program a single
page in a tearing-safe way.
The mapping mechanism of the NVM module is used like a log-structured file system: When a page is
programmed in the sector the old values are not physically overwritten, but a different physical page (spare page)
in the same sector is programmed in fact. If the programming fails (e.g. because of power loss during the erase
or write procedure), the old values are still present in the sector. The ROM routines therefore can program a single
page in a tearing-safe way.
When an erase or write procedure to the memory field was interrupted by a power-down, this fact is identified
during the reconstruction of the map-RAM content after the next reset. In this case a special routine in the ROM
(called Service Algorithm) is automatically started that identifies this tearing case of the respective logical page,
and repairs the NVM state, exploiting the fact that always either the old or the new data (or both) are fully valid.
8.2.7
Dynamic Address Scrambling
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system memory
sector and logical
page address
sector and
physical pages
..
.
..
.
sector
sector
NVM memory
address
space
map-RAM
Figure 36
Dynamic address scrambling through map-RAM
Starting from the system address space of the NVM, the NVM module supports mapping of pages within each
sector. This is useful for tearing-safe programming, but it also provides a dynamic address scrambling: After
programming a page the new information is physically stored in a different page in the same sector. The logical
page address and therefore the physical memory address stays the same. For this reason the mapping is fully
transparent for the customer software.
8.2.8
Linearly Mapped Sectors
A number of sectors can be configured not to use the map-RAM mapping mechanism, i.e. for these sectors logical
and physical page addresses are identical. The range of these linearly mapped sectors always starts at the lowest
NVM address of the NVM module, extending upwards to higher addresses. For these sectors (intended to mainly
store executable code without the need for tearing-save programming) no reconstruction of the map-RAM content
after reset is necessary, which saves time during the sleep-wake-up and power-up of the chip.
For memories with more than 16 sectors (the maximum number of sectors currently supported by the map-RAM),
the remaining lower sectors are always linearly mapped.
8.2.9
Disturb Handling
Due to the implementation of the cell array while writing a page into the cell array all other pages within the same
sector are slightly written (disturbed) too. If some pages of a sector are changed often and other pages of the same
sector accessed only rarely, these rarely programmed pages may be disturbed too often and loose their data.
If the disturbance of a page exceeds a specific value (this happens only when a different page in the same sector
is programmed), the page has to be reprogrammed (refreshed). The ROM programming routines make sure that
the pages are refreshed in time.
This refreshing of a page -when actually triggered- will double the overall programming time.
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8.2.10
Hot Spot Distribution
In the used UCP EEPROM technology always a whole page has to be programmed when any part of it (e.g. only
a byte or doubleword) is modified. This means that cycling multiple parts of one page separately physically means
cycling of the whole page every time one part is programmed.
In the following such a part (e.g. byte or doubleword) will be called a “hot spot”.
For H hot spots in a page where each hot spot is separately cycled c times, this results in a cycle stress of the
page of c*H.
As the EEPROM programming is always performed by copying the modified currently mapped page to the spare
page, the cycle stress is shared among two pages. Furthermore, as after some time the disturbance handling
described in Chapter 8.2.9 kicks in, the cycling stress eventually is shared among all 33 pages of the sector.
Therefore, the average cycle stress for a physical page in a sector is c*H/33, when H hot spots in a logical page
are separately cycled c times.
On the other hand, this means that with a cycle endurance of E for a page, the number of cycles which can be
performed before a page can become damaged by cycle stress can be calculated as c = 33*E/H per hot spot in
the sector.
Depending on the number of hot spots in a sector the maximum allowed number of cycles c per hot spot can
become unacceptably low.
If the hot spots are concentrated in one sector and other sectors have only a low number of hot spots, a hot spot
distribution over several sectors is advisable. This hot spot distribution is not supported in HW but has to be done
during the implementation of the software.
8.2.11
Properties of Error Correcting Code (ECC)
The error correcting code (ECC) for the data blocks implements a one-bit error correction and a double-bit error
detection for every data block of 32 bit. The correct ECC bits for every block are generated automatically when the
assembly buffer is written. During every read the ECC bits are read together with the data bits. The validity of the
code word is checked by hardware. Every one-bit error is corrected automatically.
The described ECC mechanism results in the limitation that a block of 32 bits is the smallest data unit that can be
read internally, since always a complete block has to be read to check for possible ECC errors and writing a byte
automatically triggers a read of the complete block as described in Chapter 8.2.4.
A data block with all bits fully erased is ECC-correct.
When a page is copied to the assembly buffer, the ECC correction of data blocks with a one-bit error is done
automatically, whereas data with an uncorrectable error is passed on unchanged. No ECC interrupt is generated
for ECC errors that are detected during the copying of a page to the assembly buffer.
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8.3
Operating Modes
The flash module have certain modes of operation. Some modes define clocking and power supply and the
operating state of the analog logic as oscillators and voltage pumps. Overall system modes (e.g. startup mode)
influence the behavior or the flash memory as well.
Other modes define the functional behavior. These will be discussed here.
8.3.1
Standard Read Mode
After reset and after performing a clean startup the flash memory with all its modules is in “standard read mode”.
In this mode it behaves as an on-chip ROM. This mode is entered:
•
•
•
•
After reset when the complete start-up has been performed.
After completion of a longer lasting command like “erase” or “program” which is acknowledged by clearing the
“busy” flag.
Immediately after each other command execution.
In case of detecting an execution error like attempting to write to a write protected range, sending a wrong
password, after all sequence errors.
For the long lasting commands the read mode stays active until the last command of the sequence is received and
the operation is started.
8.3.2
Command Mode
After receiving the last command of a command sequence the flash module placed into command mode. For most
commands this will not be noticed by the user as the command executes immediately and afterwards the flash
module is placed again into read mode. For the long lasting commands the flash module stays in command mode
for several milliseconds. This is reported by setting the corresponding “busy” flag. The data of a busy flash module
cannot be read. New command sequences are generally not accepted and cause a sequence error until the
running operation has finished. In certain cases however new command sequences are accepted in order to
enable concurrent programming and erase of independent flash modules.
Read accesses to busy flash modules stall the CPU until the read mode is entered again. Interrupts can be
handled only out of XRAM program execution.
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8.4
Operations
The flash memory supports the following operations:
•
•
•
Instruction fetch.
Data read.
Command sequences to change data and control the protection.
8.4.1
Instruction Fetch from Flash Memory
Instructions are fetched by the XC800 Core in groups of aligned 32 Bits. These code requests are forwarded to
the flash memory. It needs a varying number of cycles (depending on the system clock frequency) to perform the
read access.
One read access to the flash memory delivers 32 data Bit (i.e. 4 Byte) and a 7-Bit ECC value. The ECC value is
used to detect and possibly correct errors. The addressed 32-Bit part is sent to the XC800 Core. The complete 32
data Bits are stored in the read buffer. The XC800 Core reads 8-bit data from read buffer without wait states.
The stored data are a kind of instruction cache.
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8.4.2
Data Reads from Flash Memory
Data reads are issued by the XC800 Core. Data is always requested in 8-Bit words.
8.4.3
Data Writes to Flash Memory
Data is not written to the memory array directly, but to the assembly buffer and then copied to the cell array by the
write sequence.
Memory writes are handled through the ROM software, which at first copies the existing content of a page to the
assembly buffer, allows the user to modify the content of the assembly buffer, and afterwards executes the
programming of the data to the memory field followed by a verification step.
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8.4.4
Command Sequences
As described before changing data in the flash memory is performed with command sequences which are handled
through the ROM software.
All command sequences and user Flash routines of the ROM are described in the corresponding “TLE983x
BootROM User’s Manual”.
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Embedded Flash Memory
8.5
Data Integrity
This section describes means for detecting and preventing the inadvertent modification of data in the flash
memory.
8.5.1
Error Correcting Codes (ECC)
With very low probability a flash cell can become disturbed or lose its data value faster than specified. In order to
reach the defined overall device reliability each 32-Bit block of flash data is accompanied with a 7-Bit ECC value.
This redundancy supplies SEC-DED capability, meaning “single error correction and double error detection”. All
single Bit errors are corrected (and the incident is detected), all double Bit errors are detected and even most triple
Bit errors are detected but some of these escape as valid data or corrected data.
A detected double Bit error is reported in the flag NVMDBE of the EDCSTAT register. Software can select which
type of error should trigger a trap by the means of register.
8.5.2
Aborted Program/Erase Detection
Where the ECC should protect from intrinsic failures of the flash memory that affect usually only single Bits; an
interruption of a running program or erase process might cause massive data corruption:
•
•
The erase process programs first all cells to 1 before it erases them. So depending on the time when it is
interrupted the data might be in a different state. This can be the old data, all-one, a random value, a weak allzero or finally all-zero.
The program process programs all Bits concurrently from 0 to 1. If it is interrupted not all set Bits might read
as 1 or contain a weak 1.
One measure against aborted program/erase processes is to prevent resets by configuring the SCU appropriately.
If a program or erase process was aborted by a Power-On Reset (e.g. due to a power failure) there do not exist
reliable means to detect this by reading the affected flash range. Even with margin reads an early or late aborted
process might go unnoticed although it might in the long-term affect reliability.
Therefore the application must ensure that flash processes can perform uninterrupted and under the defined
operating conditions, e.g. by early brown-out warning that prevents the software from starting flash processes.
After a flash process aborted the affected address range must be erased and re-programmed.
8.5.3
Margin Reads
Margin reads can be used to verify that flash data is readable with a certain margin. This is typically used as
additional check directly after end-of-line programming. As explained above this is not a reliable method for
detecting interrupted program or erase processes but the probability of detecting such cases can be increased.
Reading with “using special read margin” is implemented for BootROM internal verifiys.
8.5.4
Protection Overview
An overview on the Flash protection modes is given in the chapter “NVM Protection Modes”.
8.6
Recommendations for Optimized Flash Usage
This section describes best practices for using the flash in certain application scenarios, e.g. how to use effectively
ECC and margin reads.
8.6.1
Programming Code and Constant Data
Code and constant data are programmed only few times during life-time of a device, e.g. end-of-line in ECU
production or when service updates are performed. As the readability of this data is decisive for the product quality
customers might want to implement the elaborate “best practice” advice.
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Basic Advice
Always ensure correct operating conditions and prevent power failures during flash operation.
As basic protection against handling errors all data should be verified after programming.
Best Practice
This approach offers best possible quality but risks that programming steps need to repeated even unnecessarily
(“false negatives”):
•
•
•
•
Use “Erase Sector” to erase complete sectors.
Program the sector with data. A common protection against software crashes is to fill the unused part of the
sector with trap code.
Verify the programmed data, note comparison errors and double-Bit ECC errors: Take care to evaluate the
ECC error flags only once per 32-Bit data block and clear them afterwards.
After programming all sectors:
– Erase and re-program all sectors with comparison or double-Bit ECC errors.
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Watchdog Timer (WDT1)
9
Watchdog Timer (WDT1)
9.1
Features
There are two watchdog timers in the system. The Watchdog Timer (WDT) within the microcontroller (see
Chapter 10) and the Watchdog Timer (WDT1), which is described in this section.
In Active Mode, the WDT1 acts as a windowed watchdog timer, which provides a highly reliable and safe way to
recover from software or hardware failures.
The WDT1 is always enabled in Active Mode. In Sleep Mode, Stop Mode and OCDS Mode the WDT1 is disabled.
Functional Features
•
•
•
•
•
Watchdog Timer is operating with a from the system clock (fPLL) independent clock source (fLP_CLK)
Windowed Watchdog Timer with programmable timing in Active Mode
Long open window (80 ms) after power-up, reset, wake-up
Short open window (30 ms) to facilitate Flash programming
System safety shutdown to Sleep Mode after 5 missed WDT1 services (see Chapter 3.1.3.1.2)
9.2
Functional Description
9.2.1
Modes of Operation
The mode transition from the low power modes (WDT1 off) to active (WDT1 on) automatically initializes WDT1 to
start in long open window mode.
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9.2.2
Normal Operation
The behavior of the Watchdog Timer in Active Mode is depicted in Figure 37.
Power-up
Reset
RESET
timeout always
RESET
RESET
Timeout
or
Trigger in closed window
timeout
Trigger SOW
Maximum number
of SOW triggers
exceeded
Long
Open Window
Trigger
Normal
„windowed“
operation
Trigger SOW
Short
open window
Trigger
Trigger
Figure 37
Trigger SOW
Watchdog Timer Behavior
The software has to trigger the watchdog by writing to the WDT1_TRIG register. By triggering the watchdog also
the length of the next watchdog period is selected inherently. The next period starts immediately with the trigger.
After Reset the WDT1 is starting with a long open window. The WDT1 has to be triggered within this long open
window otherwise a reset will be generated at the end of the long open window. If the watchdog is not served
properly consecutively 5 times, the system will enter sleep mode. After an initial successful trigger the WDT1
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operates in a window watchdog mode. Configuring of a short open window inside the long open window is not
allowed and will also cause a WDT1 reset.
Watchdog Period
Figure 38
50% of Watchdog Period
50% of Watchdog Period
closed window
open window
Windowed Watchdog
The first half of the watchdog period is the closed window and the second half is the open window. A trigger of the
watchdog has to be done in the open window only. Any trigger in the closed window or failing to trigger the
watchdog within the watchdog period will cause a reset. The reset will be indicated by the bit PMU_ExtWDT inside
PMU_RST_STS register located inside PMU.
Effective open window (safe trigger point)
Due to the variations in the clock source of the WDT1 the effective usable open window, and therefore a safe
trigger point, is shorter than 50% of the watchdog period as shown in Figure 39.
TWD
Nominal Watchdog Period
Minimum Watchdog Period
50% of Watchdog Period
50% of Watchdog Period
closed window
open window
closed window
open window
Maximum Watchdog Period
closed window
Safe Trigger Area
(Effective Open Window)
closed window
open window
open window
TOWmin
TOWmax
Figure 39
Effective open window
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E.g. for a variation of 20% and a nominal watchdog period of TWD the start of the effective open window TOWmin is
shifted back by 10%, and the end of the effective open window TOWmax is shifted forward by 20%.
Short Open Window (SOW)
Under certain programming conditions, e.g. NVM programming, it might be desired to interrupt the normal
windowed watchdog operation. For this purpose a special trigger of a short open window (see Figure 40) allows
to discard the current window period (also within the closed window) and immediately starts a short open window.
The short open window has a fixed length of TSOW independent of the settings of the WDP_SEL bits.
Watchdog operation:
closed window
open window
Short Open Short Open
window
window
closed window
closed window
open window
Software tasks:
Software Routine
Legende:
Figure 40
T
T Software Routine
Trigger within
open window
T
S
NVM
routine
T
S
NVM
routine
T
Software Routine
T Trigger of
S Short Open Window
Short Open Window
Example:
WDT_TRIG.SOWCONF = 10B „two successive
Short Open Windows allowed“
Watchdog operation:
closed window
open window closed window
Short Open Short Open
window
window
1
Software tasks:
Task
T
Task
T
S
closed window
Trigger in normal open
window will reset
SOW counter
2
Task
T
S
open window closed window
Task
T
Task
Short Open
window
1
T
Task
T
S
Task
Watchdog operation:
closed window
open window
1
Software tasks:
Task
Legende:
Figure 41
Short Open Short Open
window
window
closed window
T
Trigger within
open window
T
Task
T
S
3 Trigger will cause a reset
2
Task
T
S
Task
T
S
T Trigger of
S Short Open Window
SOW Counter
The mechanism of inserting Short Open Windows has to be enabled/configured with the bits SOWCONF. The
configuration allows to insert a maximum of three consecutive Short Open Windows. Each Trigger of the Short
Open Window will increase a SOW counter, if the SOW counter exceeds the maximum configured value a reset
will be generated. The SOW counter value is reset to 0 by a normal Trigger.
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9.2.2.1
Watchdog Register Overview
Table 27
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
07H
0000 0000B
Watchdog Register Overview,
WDT1_TRIG
WDT1 Watchdog Control
The registers are addressed bytewise.
WDT1 Watchdog Control
The register is reset by RESET_TYPE_3.
WDT1_TRIG
Offset
Reset Value
07H
0000 0000B
WDT1 Watchdog Control
7
6
5
0
SOWCONF
WDP_SEL
rw
rw
Field
Bits
Type
Description
SOWCONF
7:6
rw
Short Open Window Configuration
0H
DIS Short Open Windows disabled1)
1H
SOW1 one successive Short Open Window allowed
2H
SOW2 two successive Short Open Windows allowed
3H
SOW3 three successive Short Open Windows allowed
WDP_SEL
5:0
rw
Watchdog Period Selection and trigger
Selects the time for the next Watchdog period and allows to trigger the
short open window.
00H SOW_TRIG trigger short open window
01H watchdog peroid 16 ms
02H watchdog peroid 32 ms
03H watchdog peroid 48 msB
...H ...
3FH watchdog peroid 1008 ms
1) Writing 00H to the WDT_TRIG register will cause a reset
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Watchdog Timer (WDT)
10
Watchdog Timer (WDT)
There are two watchdog timers in the system: The SCU Watchdog Timer (WDT) within TLE983x, and the external
Watchdog Timer (WDT1). The description in this section refers to the SCU WDT.
The Watchdog Timer is a sub-module in the System Control Unit (SCU). The Watchdog Timer (WDT) provides a
highly reliable and secure way to detect and recover from software or hardware failures. The WDT helps to abort
an accidental malfunction of the TLE983x in a user-specified time period. When enabled, the WDT will cause the
TLE983x system to be reset if the WDT is not serviced within a user-programmable time period. The CPU must
service the WDT within this time interval to prevent the WDT from causing an TLE983x system reset. Hence,
routine service of the WDT confirms that the system is functioning properly.
The WDT is disabled by default.
In debug mode, the WDT is suspended by default and stops counting (its debug suspend bit is set i.e.,
MODSUSP.WDTSUSP = 1 by default). Therefore during debugging, there is no need to refresh the WDT.
Features
•
•
•
•
16-bit Watchdog Timer
Programmable reload value for upper 8 bits of timer
Programmable window boundary
Selectable input frequency of fPCLK/2 or fPCLK/128
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Watchdog Timer (WDT)
10.0.1
Functional Description
The Watchdog Timer is a 16-bit timer, which is incremented by a count rate of fPCLK/2 or fPCLK/128. This 16-bit timer
is realized as two concatenated 8-bit timers. The upper 8 bits of the Watchdog Timer can be preset to a userprogrammable value via a watchdog service access in order to vary the watchdog expire time. The lower 8 bits
are reset on each service access. Figure 42 shows the block diagram of the Watchdog Timer unit.
WDT
Control
Clear
1:2
MUX
f PCLK
WDTREL
WDT Low Byte
WDT High Byte
1:128
Overflow/Time-out Control &
Window-boundary control
WDTIN
ENWDT
WDTTO
WDTRST
Logic
ENWDT_P
Figure 42
WINBCNT
WDT Block Diagram
If the Watchdog Timer is enabled by setting bit WDTEN to 1, the timer is set to a user-defined start value and
begins to count up. It must be serviced before the counter overflows. Servicing is performed through refresh. This
reloads the timer with the start value, and normal operation continues.
If the WDT is not serviced before the timer overflows, a system malfunction is assumed and normal mode is
terminated. A Watchdog Timer NMI request (WDTTO) is asserted and Prewarning is entered. The Prewarning
lasts for 30H count. During the Prewarning period, refreshing of the Watchdog Timer is ignored and the Watchdog
Timer cannot be disabled. A reset (WDTRST) of the TLE983x is imminent and can no longer be stopped. If refresh
happens at the same time an overflow occurs, Watchdog Timer will not go into Prewarning period.
The Watchdog Timer must be serviced periodically so that its count value will not overflow. Servicing the
Watchdog Timer clears the low byte and reloads the high byte with the preset value in bit field WDTREL. Servicing
the Watchdog Timer also clears the bit WDTRS.
The Watchdog Timer has a ‘programmable window boundary’, it disallows a refresh during the Watchdog Timer’s
count-up. A Refresh during this window-boundary will cause the Watchdog Timer to activate WDTRST. The
window boundary is from 0000H to (WDTWINB,00H). This feature can be enabled by WINBEN.
After being serviced, the Watchdog Timer continues counting up from the value (<WDTREL> * 28). The time period
for an overflow of the Watchdog Timer is programmable in two ways:
•
•
the input frequency to the Watchdog Timer can be selected via bit WDTIN in register WDTCON to be either
fPCLK/2 or fPCLK/128.
the reload value WDTREL for the high byte of WDT can be programmed in register WDTREL.
The period PWDT between servicing the Watchdog Timer and the next overflow can be determined by the
following formula:
2 ( 1 + WDTIN × 6 ) × ( 2 16 – WDTREL × 2 8 )
P WDT = --------------------------------------------------------------------------------------------------
(6)
f PCLK
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Watchdog Timer (WDT)
If the Window-Boundary Refresh feature of the Watchdog Timer is enabled, the period PWDT between servicing
the Watchdog Timer and the next overflow is shortened if WDTWINB is greater than WDTREL. See also
Figure 43. This period can be calculated by the same formula by replacing WDTREL with WDTWINB. In order for
this feature to be useful, WDTWINB cannot be smaller than WDTREL.
Count
FFFF H
WDTWINB
WDTREL
time
No refresh
allowed
Figure 43
Refresh allowed
Watchdog Timer Timing Diagram
Table 28 lists the possible ranges for the watchdog time which can be achieved using a certain module clock.
Some numbers are rounded to 3 significant digits.
Table 28
Watchdog Time Ranges
Prescaler for fPCLK
Reload Value in
WDTREL
2 (WDTIN = 0)
128 (WDTIN = 1)
40 MHz
20 MHz
13.3 MHz
40 MHz
20 MHz
13.3 MHz
FFH
12.8 µs
25.6 µs
38.4 µs
0.82 ms
1.64 ms
2.46 ms
7FH
1.65 ms
3.30 ms
4.95 ms
106 ms
211 ms
317 ms
00H
3.28 ms
6.55 ms
9.83 ms
210 ms
419 ms
629 ms
Notes:
1. For safety reasons, the user is advised to rewrite WDTCON each time before the Watchdog Timer is serviced.
2. The Watchdog Timer can be suspended when OCDS enters Monitor Mode and has the Debug-Suspend signal
activated, provided the respective suspend bit, WDTSUSP in SFR SCU_MODSUSP, are set. See
Section 20.7.
10.0.2
Register Description
The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT, which is a nonbit-addressable read-only register. The operation of the Watchdog Timer is controlled by its bit-addressable
Watchdog Timer Control Register WDTCON. WDTREL register specifies the reload value for the high byte of the
timer. WDTWINB specifies Watchdog Window-Boundary count value.
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Watchdog Timer (WDT)
WDTREL
Watchdog Timer Reload Register
7
6
5
Reset Value: 00H
4
3
2
1
0
WDTREL
rw
Field
Bits
Type
Description
WDTREL
[7:0]
rw
Watchdog Timer Reload Value
(for the high byte of WDT)
WDTCON
Watchdog Timer Control Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
WINBEN
WDTPR
0
WDTEN
WDTRS
WDTIN
r
rw
rh
r
rw
rwh
rw
Field
Bits
Type
Description
WDTIN
0
rw
Watchdog Timer Input Frequency Selection
0B
Input frequency is fPCLK/2
1B
Input frequency is fPCLK/128
WDTRS
1
rwh
WDT Refresh Start
Active high. Set to start refresh operation on the watchdog timer.
Cleared automatically by hardware after it is set by software.
WDTEN
2
rw
WDT Enable
0B
WDT is disabled
1B
WDT is enabled
WDTEN is a protected bit. If the Protection Scheme is activated then
this bit cannot be written directly. For more information on Protection
Scheme, see Section 20.11.
Note: Clearing WDTEN bit to 0 during Prewarning Mode
(WDTPR = 1) has no effect.
WDTPR
4
rh
Watchdog Prewarning Mode Flag
0B
Normal mode (default after reset)
1B
The Watchdog is operating in Prewarning Mode
This bit is set to 1 when a Watchdog error is detected. The Watchdog
Timer has issued an NMI trap and is in Prewarning Mode. A reset of
the chip occurs after the prewarning period has expired.
WINBEN
5
rw
Watchdog Window-Boundary Enable
0B
Watchdog Window-Boundary feature is disabled (default).
1B
Watchdog Window-Boundary feature is enabled.
0
3, [7:6]
r
Reserved
Returns 0 if read
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Watchdog Timer (WDT)
WDTL
Watchdog Timer, Low Byte
7
6
Reset Value: 00H
5
4
3
2
1
0
WDT
rh
Field
Bits
Type
Description
WDT
[7:0]
rh
Watchdog Timer Current Value
WDTH
Watchdog Timer, High Byte
7
6
Reset Value: 00H
5
4
3
2
1
0
WDT
rh
Field
Bits
Type
Description
WDT
[7:0]
rh
Watchdog Timer Current Value
WDTWINB
Watchdog Window-Boundary Count
7
6
5
Reset Value: 00H
4
3
2
1
0
WDTWINB
rw
Field
Bits
Type
Description
WDTWINB
[7:0]
rw
Watchdog Window-Boundary Count Value
This value is programmable. Within this Window-Boundary range
from 0000H to (WDTWINB, 00H), the WDT cannot do a Refresh, else
it will cause a WDTRST to be asserted.
WDTWINB is matched to WDTH.
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Interrupt System
11
Interrupt System
11.1
Overview
The TLE983x supports 14 interrupt vectors with four priority levels. Eleven of these interrupt vectors are assigned
to the on-chip peripherals: Timer 0, Timer 1, UART, SSC and A/D Converter are each assigned to one dedicated
interrupt vector; while Timer 2, Timer 21, MDU, LIN and the Capture/Compare Unit share six interrupt vectors.
Two interrupt vectors are assigned to the external interrupts. External interrupts 0 to 1 are each assigned to one
dedicated interrupt vector, external interrupt 2 shares one interrupt vector with Timer 21 and the MDU.
One interrupt vector is dedicated to the XINT interrupt events whose interrupt flags are also located in registers in
XSFR area.
A Non-Maskable Interrupt (NMI) with the highest priority is shared by the following:
•
•
•
•
•
•
•
•
•
Watchdog Timer, warning before overflow
MI_CLK Watchdog Timer overflow event
PLL, loss of lock
Flash, on operation complete e.g. erase.
OCDS, on user IRAM event
Oscillator watchdog detection for too low oscillation of fOSC
Flash map error
Uncorrectable ECC error on Flash, XRAM and IRAM
VSUP supply prewarning when any supply voltage drops below or exceeds any threshold.
Figure 44, Figure 45, Figure 46, Figure 47 and Figure 48 give a general overview of the interrupt sources and
nodes, and their corresponding control and status flags. Figure 1 gives the corresponding overview for the NMI
sources.
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Interrupt System
Highest
Timer 0
Overflow
TF0
TCON.5
ET0
000B
H
IEN0.1
Timer 1
Overflow
ET1
001B
H
IEN0.3
IP.3/
IPH.3
RI
SCON.0
RIEN
SCON1.0
UART
Transmit
IP.1/
IPH.1
TF1
TCON.7
UART
Receive
Lowest
Priority Level
>=1
ES
TI
0023
H
IEN0.4
SCON.1
TIEN
IP.4/
IPH.4
SCON1.1
IE0
EINT0
TCON.1
IT0
EX0
0003
H
IEN0.0
TCON.0
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
IP.0/
IPH.0
EXINT0
EXICON0.0/1
IE1
EINT1
TCON.3
IT1
EX1
0013
H
IEN0.2
TCON.2
IP.2/
IPH.2
EXINT1
EA
EXICON0.2/3
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 44
Interrupt Request Sources (Part 1)
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Interrupt System
Highest
Timer 2
Overflow
TF2
T2_T2CON.7
T2EX
Lowest
Priority Level
TF2EN
T2_T2CON1.1
>=1
EXF2
EXEN2 T2_T2CON.6
T2_T2CON.3
EDGES
EL
T2_T2MOD.5
EXF2EN
T2_T2CON1.0
>=1
ET2
002B
H
IEN0.5
End of
Synch Byte
IP.5/
IPH.5
EOFSYN
LINST.4
Synch Byte
Error
>=1
ERRSYN
SYNEN
LINST.5
P
o
l
l
i
n
g
LINST.6
ADC Service
Request 0
ADCSR0
ADC Service
Request 1
ADCSR1
EADC
IRCON1.4
IEN1.0
IRCON1.3
>=1
0033
H
IP1.0/
IPH1.0
S
e
q
u
e
n
c
e
EA
IEN0.7
Bitaddressable
Request flag is cleared by hardware
Figure 45
Interrupt Request Sources (Part 2)
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Interrupt System
Highest
SSC_EIR
EIR
IRCON1.0
Lowest
Priority Level
EIREN
MODIEN.0
SSC_TIR
>=1
TIR
IRCON1.1
TIREN
MODIEN.1
ESSC
RIR
SSC_RIR
IRCON1.2
003B
H
IEN1.1
IP1.1/
IPH1.1
RIREN
MODIEN.2
P
o
l
l
i
n
g
EXINT2
EINT2
IRCON0.2
EXINT2
EXICON0.4/5
Timer 21
Overflow
TF2
T21_T2CON.7
TF2EN
T21_T2CON1.1
T21EX
>=1
EXF2
>=1
T21_T2CON.3
MDU_0
0043
H
IEN1.2
EXEN2 T21_T2CON.6 EXF2EN
EDGES
EL
T21_T2MOD.5
EX2
IP1.2/
IPH1.2
S
e
q
u
e
n
c
e
T21_T2CON1.0
IRDY
MDUSTAT.0
IE
MDUCON.7
MDU_1
IERR
MDUSTAT.1
IE
MDUCON.7
EA
IEN0.7
Bitaddressable
Request flag is cleared by hardware
Figure 46
Interrupt Request Sources (Part 3)
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Highest
Lowest
Priority Level
XINTx
P
o
l
l
i
n
g
XINTxF
.
.
.
XINTxEN
XSFRc.d
XSFRa.b
>=1
XINTyF
XINTy
XINTyEN
XSFRu.v
XSFRs.t
XINTw
XINTz
.
.
.
004B
EXM
H
IEN1.3
S
e
q
u
e
n
c
e
IP1.3/
IPH1.3
XINTwF
XSFRe.f
>=1
XINTzEN
XINTzF
XSFRi.j
XSFRg.h
EA
IEN0.7
Bit-addressable
Figure 47
Interrupt Request Sources (Part 4)
Highest
Lowest
Priority Level
CCU6 Node 0
CCU6SR0
IRCON3.0
ECCIP0
0053
H
IEN1.4
CCU6 Node 1
CCU6SR1
IRCON3.4
CCU6 Node 2
ECCIP1
IEN1.5
005B
H
IP1.5/
IPH1.5
CCU6SR2
IRCON4.0
ECCIP2
0063
H
IEN1.6
CCU6 Node 3
IP1.4/
IPH1.4
IP1.6/
IPH1.6
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
CCU6SRC3
IRCON4.4
ECCIP3
IEN1.7
006B
H
IP1.7/
IPH1.7
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 48
Interrupt Request Sources (Part 5)
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Watchdog Timer
Overflow
>=1
MI_CLK Watchdog
Timer Overflow
FNMIWDT
NMISR.0
(Type interrupt structure 1)
NMIWDT
NMICON.0
PLL Loss -of-Lock
FNMIPLL
NMISR.1
NMIPLL
NMICON.1
Flash Operation
Complete
FNMINVM
NMISR.2
IRAM read
event*
NMICON.2
FNMIRR
MMICR.2
NMIRRE
MMICR.0
IRAM write
event*
>=1
FNMIOCDS
NMISR.3
FNMIRW
MMICR.3
NMINVM
NMIOCDS
NMICON.3
NMIRWE
Non
Maskable
Interrupt
MMICR.1
Oscillator
Watchdog
>=1
FNMIOWD
NMISR.4
0073
H
NMIOWD
NMICON.4
Flash Map Error
FNMIMAP
NMISR.5
XRAM
Uncorrectable
ECC Error
XRDBE
NMIMAP
NMICON.5
EDCSTAT.0
XRIE
EDCCON.0
IRAM
Uncorrectable
ECC Error
IRDBE
>=1
EDCSTAT.1
Flash
Uncorrectable
ECC Error
IRIE
FNMIECC
NMISR.6
EDCCON.1
NMIECC
NMICON.6
NVMDBE
EDCSTAT.2
NVMIE
EDCCON.2
Supply Prewarning
(Type interrupt structure 1)
FNMISUP
NMISR.7
NMISUP
NMICON.7
* Includes other pre-condition
Figure 49
Non-Maskable Interrupt Request Source
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11.2
Interrupt Structure
An interrupt event source may be generated from the on-chip peripherals or from external. Detection of interrupt
events is controlled by the respective on-chip peripherals. Interrupt status flags are available for determining which
interrupt event has occured, especially useful for an interrupt node which is shared by several event sources. Each
interrupt node (except NMI) has a global enable/disable bit. In most cases, additional enable bits are provided for
enabling/disabling particular interrupt events (provided for NMI events). No interrupt will be requested for any
occured event that has its interrupt enable bit disabled.
The TLE983x has, in general, two interrupt structures distinguished mainly by the manner in which the pending
interrupt request (one per interrupt vector/node going directly to the core) is generated (due to the events) and
cleared.
Common among these two interrupt structures is the interrupt masking bit, EA, which is used to globally enable or
disable all interrupt requests (except NMI) to the core. Resetting bit EA to 0 only masks the pending interrupt
requests from the core, but does not block the capture of incoming interrupt requests.
Note: The NMI node is similar to the other interrupt nodes, except for 1) the exclusion of EA bit; 2) in case of
IMODE = 0, ‘interrupt node enable bit’ is replaced by OR of all NMICON bits. Effectively, NMI node is nonmaskable when IMODE = 1; whereas NMI pending interrupt request may be cleared by clearing all NMICON
bits when IMODE = 0.
11.2.1
Interrupt Structure 1
For interrupt structure 1 (see Figure 50), the interrupt event will set the interrupt status flag which doubles as a
pending interrupt request to the core. An active pending interrupt request will interrupt the core only if its
corresponding interrupt node is enabled. Once an interrupt node is serviced (interrupt acknowledged), its pending
interrupt request (represented by the interrupt status flag) may be automatically cleared by hardware (the core).
interrupt
acknowledge
(from core)
software
clear
interrupt
event
set
pending
interrupt
request
clear
interrupt status
flag
interrupt node
enable bit
AND
to core
EA bit
Figure 50
Interrupt Structure 1
For the TLE983x, interrupt sources Timer 0, Timer 1, external interrupt 0 and external interrupt 1 (each have a
dedicated interrupt node) will have their respective interrupt status flags TF0, TF1, IE0 and IE1 in register TCON
cleared by the core once their corresponding pending interrupt request is serviced. In the case that an interrupt
node is disabled (e.g. software polling is used), its interrupt status flag must be cleared by software since the core
will not be interrupted (and therefore the interrupt acknowledge is not generated).
In addition, the XINT interrupts whose event flags are located in the XSFR of external data space are of Interrupt
Structure 1. These XINT event flags, if enabled, drive the interrupt request and are to be cleared by software.
Note: The supply prewarning NMI & MI_CLK WDT NMI events are of interrupt structure 1. However, only the
supply prewarning NMI request source is of interrupt structure 1. MI_CLK WDT shares with WDT Watchdog
Timer one NMI request source which is of interrupt structure 2.
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11.2.2
Interrupt Structure 2
This structure applies to the UART, Timer 2, Timer 21, LIN, external interrupt 2, ADC, SSC, CCU6 and MDU
interrupt sources. For interrupt structure 2 (see Figure 51), the interrupt status flag does not directly drive the
pending interrupt request. Further, an additional control bit IMODE is used to select one of two defined modes of
handling incoming interrupt events.
All qualified flags of the
interrupt node
Corresponding
event status
flag
NOR
Event interrupt request
Event
occurrence
clear
AND
IMODE
Corresponding
event interrupt
enable bit
interrupt node
enable bit
set/clear
FF*
pending
interrupt
request
OR
AND
* Implemented as latch, cannot set by software
Figure 51
interrupt
acknowledge
(from core)
OR
to core
EA bit
Interrupt Structure 2
If IMODE = 1, an event generated by its corresponding interrupt source will set the status flag and in parallel, if the
event is enabled for interrupt, activate the pending interrupt request. If IMODE = 0 an event will set the status flag,
but the pending interrupt request is activated only if the event is enabled for interrupt and the interrupt node is
enabled. Consider the case where an interrupt is requested while its interrupt node was disabled (assume global
interrupt enable EA is set). When the interrupt node is enabled later, for IMODE = 1, previously activated pending
interrupt request will now cause an active interrupt request to the core. On the contrary with IMODE = 0, there is
no active interrupt request to the core due to previous events. Note for the special case of NMI node, that it is
essentially non-maskable. In case of IMODE = 0, clearing of all NMICON bits can clear the pending interrupt
request.
A pending interrupt request interrupts the core and is automatically cleared by hardware (the core) once the
interrupt node is serviced (interrupt acknowledged). The status flag remains set and must be cleared by software.
A pending interrupt request can also be cleared by software; the method differs and depends on the IMODE bit
setting.
If IMODE = 1, only on clearing all interrupt-enabled status flags of the node will indirectly clear its pending interrupt
request. Note that this is not exactly like interrupt structure 1 where the pending interrupt request is cleared directly
by resetting the node’s interrupt status flags. If IMODE = 0, only on clearing the interrupt node enable bit will
indirectly clear its pending interrupt request.
Hence when IMODE = 0, the interrupt node enable bit additionally serves a dual function: to enable/disable the
activation of pending interrupt request, and to clear an already generated pending interrupt request (by resetting
enable bit to 0).
In summary, the following lists in descending order the priority handling of pending interrupt request for interrupt
nodes of structure 2: 1) CPU acknowledge of interrupt on vectoring to the service routine will clear the pending
interrupt request, 2) If IMODE = 0, clear of interrupt node enable will clear the pending interrupt request and gate
new request, 3) Any event occurring and enabled for interrupt will set the pending interrupt request, 4) If
IMODE = 1, on clearing of all interrupt-enabled status flags will clear the pending interrupt request.
Note: Some NMI request source have several NMI events associated. Most NMI events are of interrupt structure
2, except supply prewarning & WDT1 NMI. Except for supply prewarning NMI request source, all other
interrupt request sources are of interrupt structure 2.
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11.3
Interrupt Source and Vector
Each interrupt event source has an associated interrupt vector address for the interrupt node it belongs to. This
vector is accessed to service the corresponding interrupt node request. The interrupt service of each interrupt
node can be individually enabled or disabled via an enable bit. The assignment of the TLE983x interrupt sources
to the interrupt vector address and the corresponding interrupt node enable bits are summarized in Table 29.
Table 29
Interrupt Vector Address
Interrupt Node
Vector
Address
Assignment for TLE983x
Enable Bit
SFR
NMI
0073H
Watchdog Timer NMI
NMIWDT
NMICON
PLL NMI
NMIPLL
NVM Operation Complete NMI
NMINVM
OCDS NMI
NMIOCDS
OWD NMI
NMIOWD
NVM Map Error NMI
NMIMAP
ECC Error NMI
NMIECC
Supply Prewarning NMI
NMISUP
XINTR0
0003H
External Interrupt 0
EX0
XINTR1
000BH
Timer 0
ET0
XINTR2
0013H
External Interrupt 1
EX1
XINTR3
001BH
Timer 1
ET1
XINTR4
0023H
UART
ES
XINTR5
002BH
Timer 2
ET2
IEN0
LIN
XINTR6
0033H
ADC
XINTR7
003BH
SSC
ESSC
XINTR8
0043H
External Interrupt 2
EX2
EADC
IEN1
Timer 21
MDU
XINTR9
004BH
XINT
EXM
XINTR10
0053H
CCU6 INP0
ECCIP0
XINTR11
005BH
CCU6 INP1
ECCIP1
XINTR12
0063H
CCU6 INP2
ECCIP2
XINTR13
006BH
CCU6 INP3
ECCIP3
11.4
Interrupt Priority
An interrupt that is currently being serviced can only be interrupted by a higher-priority interrupt, but not by another
interrupt of the same or lower priority. Hence, an interrupt of the highest priority cannot be interrupted by any other
interrupt request.
If two or more requests of different priority levels are received simultaneously, the request with the highest priority
is serviced first. If requests of the same priority are received simultaneously, an internal polling sequence
determines which request is serviced first. Thus, within each priority level, there is a second priority structure
determined by the polling sequence as shown in Table 30.
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Table 30
Priority Structure within Interrupt Level
Source
Level
Non-maskable Interrupt (NMI)
(highest)
External Interrupt 0
1
Timer 0
2
External Interrupt 1
3
Timer 1
4
UART
5
Timer2 / LIN
6
A/D Converter
7
SSC
8
External Interrupt 2 / Timer21 / MDU
9
XINT
10
CCU6 Interrupt Node Pointer 0
11
CCU6 Interrupt Node Pointer 1
12
CCU6 Interrupt Node Pointer 2
13
CCU6 Interrupt Node Pointer 3
14
11.5
Interrupt Handling
The interrupt request signals are sampled at phase 2 in each machine cycle. The sampled requests are then polled
during the following machine cycle. If one interrupt node request was active at phase 2 of the preceding cycle, the
polling cycle will find it and the interrupt system will generate a LCALL to the node’s service routine, provided this
hardware-generated LCALL is not blocked by any of the following conditions:
1. An interrupt of equal or higher priority is already in progress.
2. The current (polling) cycle is not in the final cycle of the instruction in progress.
3. The instruction in progress is RETI or any write access to registers IEN0/IEN1 or IP/IPH or IP1/IPH1.
Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2
ensures that the instruction in progress is completed before vectoring to any service routine. Condition 3 ensures
that if the instruction in progress is RETI or any write access to registers IEN0/IEN1, IP/IPH or IP1/IPH1, then at
least one more instruction will be executed before any interrupt is vectored to. This delay guarantees that changes
of the interrupt status can be observed by the CPU.
The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at
phase 2 of the previous machine cycle. Note that if any interrupt flag is active but its node interrupt request was
not responded to for one of the conditions already mentioned, and if the flag is no longer active at a later time when
servicing the interrupt node, the corresponding interrupt source will not be serviced. In other words, the fact that
the interrupt flag was once active but not serviced is not remembered. Every polling cycle interrogates only the
pending interrupt requests.
The processor acknowledges an interrupt request by executing a hardware generated LCALL to the
corresponding service routine. In some cases, hardware also clears the flag that generated the interrupt, while in
other cases, the flag must be cleared by the user’s software. The hardware-generated LCALL pushes the contents
of the Program Counter (PC) onto the stack (but it does not save the PSW) and reloads the PC with an address
that depends on the interrupt node being vectored to, as shown in the Table 29.
Program execution returns to the next instruction after calling the interrupt when the RETI instruction is
encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, then
pops the two top bytes from the stack and reloads the PC. Execution of the interrupted program continues from
the point where it was stopped. Note that the RETI instruction is important because it informs the processor that
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the program has left the current interrupt priority level. A simple RET instruction would also have returned
execution to the interrupted program, but it would have left the interrupt control system on the assumption that an
interrupt was still in progress. In this case, no interrupt of the same or lower priority level would be acknowledged.
11.6
Interrupt Response Time
Due to an interrupt event of (the various sources of) an interrupt node, its corresponding request signal will be
sampled active at phase 2 in every machine cycle. The value is not polled by the circuitry until the next machine
cycle. If the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the
requested service routine will be the next instruction to be executed. The call itself takes two machine cycles. Thus,
a minimum of three complete machine cycles will elapse from activation of the interrupt request to the beginning
of execution of the first instruction of the service routine as shown in Figure 52.
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
fCCLK
Interrupt
request
active/sampled
Interrupt request
polled
(last cycle of
current
instruction)
1st instruction at
interrupt vector
LCALL
Interrupt response time = 3 x machine cycle
Figure 52
Minimum Interrupt Response Time
A longer response time would be obtained if the request is blocked by one of the three previously listed conditions:
1. If an interrupt of equal or higher priority is already in progress, the additional wait time will depend on the nature
of the other interrupt's service routine.
2. If the instruction in progress is not in its final cycle, the additional wait time cannot be more than three machine
cycles since the longest instructions (MUL and DIV) are only four machine cycles long. See Figure 53.
3. If the instruction in progress is RETI or a write access to registers IEN0, IEN1 or IP(H), IP1(H), the additional
wait time cannot be more than five cycles (a maximum of one more machine cycle to complete the instruction
in progress, plus four machine cycles to complete the next instruction, if the instruction is MUL or DIV). See
Figure 54.
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
fCCLK
Interrupt
request
sampled active
4-cycle current instruction
(MUL or DIV)
Interrupt
request
sampled
Interrupt
request
polled
(last cycle of
current
instruction)
LCALL
1st instruction at
interrupt vector
Interrupt response time = 6 x machine cycle
Figure 53
Interrupt Response Time for Condition 2
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P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
fCCLK
Interrupt
request
sampled active
2-cycle current instruction
Interrupt
request
sampled
Interrupt request
polled
(RETI or write
access to interrupt
registers)
4-cycle next instruction
(MUL or DIV)
Interrupt
request
sampled
Interrupt request
polled
(last cycle of
current
instruction)
LCALL
1st instruction at
interrupt vector
Interrupt response time = 8 x machine cycle
Figure 54
Interrupt Response Time for Condition 3
Thus in a single interrupt system, the response time is always more than three machine cycles and less than nine
machine cycles (wait states are not considered). When considering wait states, the interrupt response time will be
extended depending on the user instructions (also the hardware generated LCALL) being executed during the
interrupt response time (shaded region in Figure 53 and Figure 54).
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11.7
Interrupt Registers
Interrupt registers are used for interrupt node enable, external interrupt control, interrupt flags and interrupt priority
setting.
11.7.1
Interrupt Node Enable Registers
Each interrupt node can be individually enabled or disabled by setting or clearing the corresponding bit in the
interrupt enable registers IEN0 and IEN1. Register IEN0 also contains the global interrupt masking bit (EA), which
can be cleared to block all pending interrupt requests at once.
The NMI interrupt vector is shared by a number of sources, each of which can be enabled or disabled individually
via register NMICON.
After reset, the enable bits in IEN0, IEN1 and NMICON are cleared to 0. This implies that all interrupt nodes are
disabled by default.
IEN0
Interrupt Enable Register 0
Reset Value: 00H
7
6
5
4
3
2
1
0
EA
0
ET2
ES
ET1
EX1
ET0
EX0
rw
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
EX0
0
rw
Interrupt Node XINTR0 Enable
0B
XINTR0 is disabled
1B
XINTR0 is enabled
ET0
1
rw
Interrupt Node XINTR1 Enable
0B
XINTR1 is disabled
1B
XINTR1 is enabled
EX1
2
rw
Interrupt Node XINTR2 Enable
0B
XINTR2 is disabled
1B
XINTR2 is enabled
ET1
3
rw
Interrupt Node XINTR3 Enable
0B
XINTR3 is disabled
1B
XINTR3 is enabled
ES
4
rw
Interrupt Node XINTR4 Enable
0B
XINTR4 is disabled
1B
XINTR4 is enabled
ET2
5
rw
Interrupt Node XINTR5 Enable
0B
XINTR5 is disabled
1B
XINTR5 is enabled
EA
7
rw
Global Interrupt Mask
0B
All pending interrupt requests (except NMI) are blocked from
the core.
1B
Pending interrupt requests are not blocked from the core.
0
6
r
Reserved
Returns 0 if read.
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IEN1
Interrupt Enable Register 1
Reset Value: 00H
7
6
5
4
3
2
1
0
ECCIP3
ECCIP2
ECCIP1
ECCIP0
EXM
EX2
ESSC
EADC
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
EADC
0
rw
Interrupt Node XINTR6 Enable
0B
XINTR6 is disabled
1B
XINTR6 is enabled
ESSC
1
rw
Interrupt Node XINTR7 Enable
0B
XINTR7 is disabled
1B
XINTR7 is enabled
EX2
2
rw
Interrupt Node XINTR8 Enable
0B
XINTR8 is disabled
1B
XINTR8 is enabled
EXM
3
rw
Interrupt Node XINTR9 Enable
0B
XINTR9 is disabled
1B
XINTR9 is enabled
ECCIP0
4
rw
Interrupt Node XINTR10 Enable
0B
XINTR10 is disabled
1B
XINTR10 is enabled
ECCIP1
5
rw
Interrupt Node XINTR11 Enable
0B
XINTR11 is disabled
1B
XINTR11 is enabled
ECCIP2
6
rw
Interrupt Node XINTR12 Enable
0B
XINTR12 is disabled
1B
XINTR12 is enabled
ECCIP3
7
rw
Interrupt Node XINTR13 Enable
0B
XINTR13 is disabled
1B
XINTR13 is enabled
NMICON
NMI Control Register
Reset Value: 00H
7
6
5
4
3
2
1
0
NMISUP
NMIECC
NMIMAP
NMIOWD
NMIOCDS
NMINVM
NMIPLL
NMIWDT
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
NMIWDT
0
rw
Watchdog Timer NMI Enable
0B
WDT NMI is disabled.
1B
WDT NMI is enabled.
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Field
Bits
Type
Description
NMIPLL
1
rw
PLL Loss of Lock NMI Enable
0B
PLL Loss of Lock NMI is disabled.
1B
PLL Loss of Lock NMI is enabled.
NMINVM
2
rw
NVM Operation Complete NMI Enable
0B
NVM operation complete NMI is disabled.
1B
NVM operation complete NMI is enabled.
NMIOCDS
3
rw
OCDS NMI Enable
0B
OCDS NMI is disabled.
1B
OCDS NMI is enabled.
NMIOWD
4
rw
Oscillator Watchdog NMI Enable
0B
Oscillator watchdog NMI is disabled.
1B
Oscillator watchdog NMI is enabled.
NMIMAP
5
rw
NVM Map Error NMI Enable
0B
NVM Map Error NMI is disabled.
1B
NVM Map Error NMI is enabled.
NMIECC
6
rw
ECC Error NMI Enable
0B
ECC Error NMI is disabled.
1B
ECC Error NMI is enabled.
NMISUP
7
rw
Supply Prewarning NMI Enable
0B
Supply NMI is disabled.
1B
Supply NMI is enabled.
11.7.2
External Interrupt Control Registers
External interrupts EXT_INT[2:0] can be rising, falling or double edge triggered. Register EXICON0 specifies the
active edge for the external interrupt. Among the external interrupts, external interrupt 0 and external interrupt 1
can be selected to bypass edge detection in the SCU, for direct feed-through to the core. This signal to the core
can be further programmed to either low-level or negative transition activated, by the bits IT0 and IT1 in the TCON
register. However for edge detection in SCU, TCON.IT0/1 must be set to falling edge triggered. An active edge
event detected in the SCU will generate internally two CCLK cycle low pulse for detection by the core.
If the external interrupt is rising (falling) edge triggered, the external source must hold the request pin low (high)
for at least one CCLK cycle, and then hold it high (low) for at least one CCLK cycle to ensure that the transition is
recognized. If edge detection is bypassed for external interrupt 0 and external interrupt 1, the external source must
hold the request pin “high” or “low” for at least two CCLK cycles.
External interrupt 2 share the interrupt node with other interrupt sources. Therefore in addition to the
corresponding interrupt node enable, external interrupt 2 may be disabled individually, and is disabled by default
after reset.
Note: Several external interrupts support alternative input pin, selected via MODPISEL register in the SCU. When
switching inputs, the active edge/level trigger select and the level on the associated pins should be
considered to prevent unintentional interrupt generation.
EXICON0
External Interrupt Control Register 0
7
6
Reset Value: 30H
5
4
3
2
1
0
0
EXINT2
EXINT1
EXINT0
r
rw
rw
rw
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Field
Bits
Type
Description
EXINT0
1:0
rw
External Interrupt 0 Trigger Select
00B Interrupt on falling edge.
01B Interrupt on rising edge.
10B Interrupt on both rising and falling edge.
11B Bypass the edge detection in SCU. The input signal directly
feeds to the core.
EXINT1
3:2
rw
External Interrupt 1 Trigger Select
00B Interrupt on falling edge.
01B Interrupt on rising edge.
10B Interrupt on both rising and falling edge.
11B Bypass the edge detection in SCU. The input signal directly
feeds to the core.
EXINT2
5:4
rw
External Interrupt 2 Trigger Select
00B Interrupt on falling edge.
01B Interrupt on rising edge.
10B Interrupt on both rising and falling edge.
11B External interrupt 2 is disabled.
0
7:6
r
Reserved
Returns 0 if read.
TCON
Timer and Counter Control/Status Register
Reset Value: 00H
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
rwh
rw
rwh
rw
rwh
rw
rwh
rw
Field
Bits
Type
Description
IT0
0
rw
External Interrupt 0 Level/Edge Trigger Control
0B
Low level triggered external interrupt 0 is selected
1B
Falling edge triggered external interrupt 0 is selected
IT1
2
rw
External Interrupt 1 Level/Edge Trigger Control
0B
Low level triggered external interrupt 1 is selected
1B
Falling edge triggered external interrupt 1 is selected
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11.7.3
Interrupt Flag Registers
The interrupt flags for the different interrupt sources are located in several special function registers. This section
describes the interrupt flags located in system registers or external interrupts belonging to the system. Other
interrupt flags located in respective module registers are described in the specific module chapter. For a complete
listing of the interrupt flags and their assignment to SFRs, refer to Section 11.8.
In case of software and hardware access to a flag bit at the same time, hardware will have higher priority.
IRCON0
Interrupt Request Register 0
7
6
Reset Value: 00H
5
4
3
0
r
2
1
0
r
r
EXINT2
r
r
r
r
rwh
Field
Bits
Type
Description
EXINT2
2
rwh
Interrupt Flag for External Interrupt 2
This bit is set by hardware and can only be cleared by software.
0B
Interrupt event has not occured.
1B
Interrupt event has occured.
0
0, 1, 7:3
r
Reserved
Returns 0 if read; Should be written with 0.
IRCON1
Interrupt Request Register 1
7
6
Reset Value: 00H
5
0
r
r
r
4
3
2
1
0
ADCSR1
ADCSR0
RIR
TIR
EIR
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type
Description
EIR
0
rwh
Error Interrupt Flag for SSC
This bit is set by hardware and can only be cleared by software.
0B
Interrupt event has not occured.
1B
Interrupt event has occured.
TIR
1
rwh
Transmit Interrupt Flag for SSC
This bit is set by hardware and can only be cleared by software.
0B
Interrupt event has not occured.
1B
Interrupt event has occured.
RIR
2
rwh
Receive Interrupt Flag for SSC
This bit is set by hardware and can only be cleared by software.
0B
Interrupt event has not occured.
1B
Interrupt event has occured.
ADCSR0
3
rwh
Interrupt Flag 0 for ADC
This bit is set by hardware and can only be cleared by software.
0B
Interrupt event has not occured.
1B
Interrupt event has occured.
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Field
Bits
Type
Description
ADCSR1
4
rwh
Interrupt Flag 1 for ADC
This bit is set by hardware and can only be cleared by software.
Interrupt event has not occured.
0B
1B
Interrupt event has occured.
0
5, 6, 7
r
Reserved
Returns 0 if read.
IRCON3
Interrupt Request Register 3
7
6
Reset Value: 00H
5
0
r
r
4
3
2
CCU6SR1
0
rwh
r
1
0
CCU6SR0
r
rwh
Field
Bits
Type
Description
CCU6SR0
0
rwh
Interrupt Flag 0 for CCU6
This bit is set by hardware and can only be cleared by software.
0B
Interrupt event has not occured.
1B
Interrupt event has occured.
CCU6SR1
4
rwh
Interrupt Flag 1 for CCU6
This bit is set by hardware and can only be cleared by software.
0B
Interrupt event has not occured.
1B
Interrupt event has occured.
0
1, 2, 3, 5,
6, 7
r
Reserved
Returns 0 if read.
IRCON4
Interrupt Request Register 4
7
6
Reset Value: 00H
5
0
r
r
4
3
2
CCU6SR3
0
rwh
r
1
0
CCU6SR2
r
rwh
Field
Bits
Type
Description
CCU6SR2
0
rwh
Interrupt Flag 2 for CCU6
This bit is set by hardware and can only be cleared by software.
0B
Interrupt event has not occured.
1B
Interrupt event has occured.
CCU6SR3
4
rwh
Interrupt Flag 3 for CCU6
This bit is set by hardware and can only be cleared by software.
0B
Interrupt event has not occured.
1B
Interrupt event has occured.
0
1, 2, 3, 5,
6, 7
r
Reserved
Returns 0 if read.
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TCON
Timer and Counter Control/Status Register
Reset Value: 00H
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
rwh
rw
rwh
rw
rwh
rw
rwh
rw
Field
Bits
Type
Description
IE0
1
rwh
External Interrupt 0 Flag
Set by hardware when external interrupt 0 event is detected.
Cleared by hardware when the processor vectors to interrupt routine.
Can also be cleared by software.
IE1
3
rwh
External Interrupt 1 Flag
Set by hardware when external interrupt 1 event is detected.
Cleared by hardware when the processor vectors to interrupt routine.
Can also be cleared by software.
Note: Bits TF0 and TF1 are the overflow flags of Timer 0 and Timer 1 respectively, and described in the Timer 0
and Timer 1 chapter.
Each NMI event and status flag is retained across these resets: 1) WDT reset, 2) soft reset. These include all the
flags of NMISR register: FNMIWDT, FNMIPLL, FNMINVM, FNMIOCDS, FNMIOWD, FNMIMAP, and indirectly,
FNMIECC and FNMISUP. In the case of NMIs with shared source i.e. watchdog, ECC or supply prewarning NMI,
the respective indicator or event flags not located in NMISR are also retained. Refer to Chapter 20.4.4 for
identifying the NMI event.
NMISR
NMI Status Register
Reset Value: 00H
7
6
5
4
3
2
1
0
FNMISUP
FNMIECC
FNMI
MAP
FNMIOWD
FNMI
OCDS
FNMINVM
FNMIPLL
FNMIWDT
rh
rh
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type
Description
FNMIWDT
0
rwh
Watchdog Timer NMI Flag
This bit is set by hardware and can only be cleared by software.
As this is a shared NMI source, this flag should be cleared after
checking and clearing the corresponding event flags.
0B
No watchdog NMI has occured.
1B
WDT prewarning has occured.
FNMIPLL
1
rwh
PLL NMI Flag
This bit is set by hardware and can only be cleared by software.
0B
No PLL NMI has occured.
1B
PLL loss-of-lock to the external crystal has occured.
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Field
Bits
Type
Description
FNMINVM
2
rwh
NVM Operation Complete NMI Flag
This bit is set by hardware and can only be cleared by software.
0B
No NVM NMI has occured.
1B
NVM operation complete event has occured.
FNMIOCDS
3
rwh
OCDS NMI Flag
This bit is set by hardware and can only be cleared by software.
As this is a shared NMI source, this flag should be cleared after
checking and clearing the corresponding event flags.
0B
No OCDS NMI has occured.
1B
OCDS NMI event has occured.
FNMIOWD
4
rwh
Oscillator Watchdog NMI Flag
This bit is set by hardware and can only be cleared by software.
0B
No oscillator watchdog NMI has occured.
1B
Oscillator watchdog event has occured.
FNMIMAP
5
rwh
NVM Map Error NMI Flag
This bit is set by hardware and can only be cleared by software.
0B
No NVM Map Error NMI has occured.
1B
NVM Map Error has occured.
FNMIECC
6
rh
ECC Error NMI Flag
This flag is cleared automatically by hardware when the
corresponding enabled event flags are cleared.
0B
No uncorrectable ECC error has occured on NVM, XRAM or
IRAM.
1B
Uncorrectable ECC error has occured on NVM, XRAM or
IRAM.
FNMISUP
7
rh
Supply Prewarning NMI Flag
This flag is cleared automatically by hardware when the
corresponding event flags are cleared.
0B
No supply prewarning NMI has occured.
1B
Supply prewarning has occured.
11.7.4
Interrupt Priority Registers
Each interrupt node can be individually programmed to one of the four priority levels available. Two pairs of
Interrupt Priority Registers are available to program the priority level of the each interrupt vector. The first pair of
Interrupt Priority Registers are SFRs IP and IPH. The second pair of Interrupt Priority Registers are SFRs IP1 and
IPH1.
The corresponding bits in each pair of Interrupt Priority Registers select one of the four priority levels as shown in
Table 31.
Table 31
Interrupt Priority Level Selection
IPH.x / IPH1.x
IP.x / IP1.x
Priority Level
0
0
Level 0 (lowest)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest)
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Note: NMI always has the highest priority (above Level 3); it does not use the priority level selection shown in
Table 31.
IP
Interrupt Priority Register
7
Reset Value: 00H
6
5
4
3
2
1
0
0
PT2
PS
PT1
PX1
PT0
PX0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
PX0
0
rw
Priority Level Low Bit for Interrupt Node XINTR0
PT0
1
rw
Priority Level Low Bit for Interrupt Node XINTR1
PX1
2
rw
Priority Level Low Bit for Interrupt Node XINTR2
PT1
3
rw
Priority Level Low Bit for Interrupt Node XINTR3
PS
4
rw
Priority Level Low Bit for Interrupt Node XINTR4
PT2
5
rw
Priority Level Low Bit for Interrupt Node XINTR5
0
7:6
r
Reserved
Returns 0 if read.
IPH
Interrupt Priority High Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
PX0H
0
rw
Priority Level High Bit for Interrupt Node XINTR0
PT0H
1
rw
Priority Level High Bit for Interrupt Node XINTR1
PX1H
2
rw
Priority Level High Bit for Interrupt Node XINTR2
PT1H
3
rw
Priority Level High Bit for Interrupt Node XINTR3
PSH
4
rw
Priority Level High Bit for Interrupt Node XINTR4
PT2H
5
rw
Priority Level High Bit for Interrupt Node XINTR5
0
7:6
r
Reserved
Returns 0 if read.
IP1
Interrupt Priority 1 Register
Reset Value: 00H
7
6
5
4
3
2
1
0
PCCIP3
PCCIP2
PCCIP1
PCCIP0
PXM
PX2
PSSC
PADC
rw
rw
rw
rw
rw
rw
rw
rw
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Field
Bits
Type
Description
PADC
0
rw
Priority Level Low Bit for Interrupt Node XINTR6
PSSC
1
rw
Priority Level Low Bit for Interrupt Node XINTR7
PX2
2
rw
Priority Level Low Bit for Interrupt Node XINTR8
PXM
3
rw
Priority Level Low Bit for Interrupt Node XINTR9
PCCIP0
4
rw
Priority Level Low Bit for Interrupt Node XINTR10
PCCIP1
5
rw
Priority Level Low Bit for Interrupt Node XINTR11
PCCIP2
6
rw
Priority Level Low Bit for Interrupt Node XINTR12
PCCIP3
7
rw
Priority Level Low Bit for Interrupt Node XINTR13
IPH1
Interrupt Priority 1 High Register
Reset Value: 00H
7
6
5
4
3
2
1
0
PCCIP3H
PCCIP2H
PCCIP1H
PCCIP0H
PXMH
PX2H
PSSCH
PADCH
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
PADCH
0
rw
Priority Level High Bit for Interrupt Node XINTR6
PSSCH
1
rw
Priority Level High Bit for Interrupt Node XINTR7
PX2H
2
rw
Priority Level High Bit for Interrupt Node XINTR8
PXMH
3
rw
Priority Level High Bit for Interrupt Node XINTR9
PCCIP0H
4
rw
Priority Level High Bit for Interrupt Node XINTR10
PCCIP1H
5
rw
Priority Level High Bit for Interrupt Node XINTR11
PCCIP2H
6
rw
Priority Level High Bit for Interrupt Node XINTR12
PCCIP3H
7
rw
Priority Level High Bit for Interrupt Node XINTR13
11.8
Interrupt Flag Overview
The interrupt events have interrupt flags that are located in different SFRs. Table 32 shows the corresponding
SFR to which each interrupt flag belongs. Detailed information on the interrupt flags is given in the respective
module chapters.
In case of software and hardware access to a flag bit at the same time, hardware will have higher priority.
Table 32
Location of the Interrupt Flags
Interrupt Event
Interrupt Flag
SFR
Timer 0 Overflow
TF0
TCON
Timer 1 Overflow
TF1
TCON
Timer2 Overflow
TF2
T2_T2CON
Timer2 External Event
EXF2
T2_T2CON
Timer21 Overflow
TF2
T21_T2CON
Timer21 External Event
EXF2
T21_T2CON
UART Receive
RI
SCON
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Table 32
Location of the Interrupt Flags (cont’d)
Interrupt Event
Interrupt Flag
SFR
UART Transmit
TI
SCON
LIN End of Synch Byte
EOFSYN
LINST
LIN Synch Byte Error
ERRSYN
LINST
External Interrupt 0
IE0
TCON
External Interrupt 1
IE1
TCON
External Interrupt 2
EXINT2
IRCON0
A/D Converter Service Request 0
ADCSR0
IRCON1
A/D Converter Service Request 1
ADCSR1
IRCON1
MDU Result Ready
IRDY
MDUSTAT
MDU Error
IERR
MDUSTAT
SSC Error
EIR
IRCON1
SSC Transmit
TIR
IRCON1
SSC Receive
RIR
IRCON1
CCU6 Node 0 Interrupt
CCU6SR01)
IRCON3
CCU6 Node 1 Interrupt
CCU6SR1
1)
IRCON3
CCU6SR2
1)
IRCON4
CCU6SR3
1)
IRCON4
CCU6 Node 2 Interrupt
CCU6 Node 3 Interrupt
2)
Watchdog Timer NMI
WDTPR
WDTCON
PLL NMI
FNMIPLL
NMISR
NVM Operation Complete NMI
FNMINVM
NMISR
OCDS NMI
FNMIOCDS
NMISR
OWD NMI
FNMIOWD
NMISR
NVM Map Error NMI
FNMIMAP
NMISR
3)
XRAM Double Bit Error NMI
XRDBE
IRAM Double Bit Error NMI
IRDBE
EDCSTAT
3)
EDCSTAT
3)
NVM Double Bit Error NMI
NVMDBE
EDCSTAT
1) Each CCU6 interrupt can be assigned to any of the CCU6 interrupt nodes [3:0] via CCU6 registers INPL/INPH.
2) Sets also bit FNMIWDT of SFR NMISR.
3) Sets also bit FNMIECC of SFR NMISR.
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12
Multiplication/Division Unit
12.1
Introduction
The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and 32-bit division as well as shift
and normalize features. It has been integrated to support the TLE983x Core in real-time control applications, which
require fast mathematical computations.
Features
•
•
•
•
Fast signed/unsigned 16-bit multiplication
Fast signed/unsigned 32-bit divide by 16-bit and 16-bit divide by 16-bit operations
32-bit unsigned normalize operation
32-bit arithmetic/logical shift operations
Table 33 specifies the number of clock cycles used for calculation in various operations.
Table 33
MDU Operation Characteristics
Operation
Result
Remainder
No. of Clock Cycles used for
Calculation
Signed 32-bit/16-bit
32-bit
16-bit
33
Signed 16-bit/16bit
16-bit
16-bit
17
Signed 16-bit x 16-bit
32-bit
–
16
Unsigned 32-bit/16-bit
32-bit
16-bit
32
Unsigned 16-bit/16-bit
16-bit
16-bit
16
Unsigned 16-bit x 16-bit
32-bit
–
16
32-bit normalize
–
–
No. of shifts + 1 (Max. 32)
32-bit shift L/R
–
–
No. of shifts + 1 (Max. 32)
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12.2
Functional Description
The MDU can be regarded as a special coprocessor for multiplication, division, normalization and shift. Its
operation can be divided into three phases (see Figure 55).
Phase One: Load MDx Registers
In this phase, the operands are loaded into the MDU Operand (MDx) registers by the CPU.
The type of calculation the MDU must perform is selected by writing a 4-bit opcode that represents the required
operation into the bit field MDUCON.OPCODE.
Phase Two: Execute Calculation
This phase commences only when the start bit MDUCON.START is set, which in return sets the busy flag. The
start bit is automatically cleared in the next cycle.
During this phase, the MDU works on its own, in parallel with the CPU. The result of the calculation is made
available in the MDU Result (MRx) registers at the end of this phase.
Phase Three: Read Result from the MRx Registers
In this final phase, the result is fetched from the MRx registers by the CPU. The MRx registers will be overwritten
at the start of the next calculation phase.
First Write
Start bit is
set
First Read
Phase 1
Load Registers
Phase 2
Calculate
Last Read
Phase 3
Read Registers
Time
Figure 55
Operating Phases of the MDU
12.2.1
Division Operation
The MDU supports the truncated division operation, which is also the ISO C99 standard and the popular choice
among modern processors. The division and modulus functions of the truncated division are related in the
following way:
If q = D div d
and r = D mod d
then D = q * d + r
and | r | < | d |
where “D” is the dividend, “d” is the divisor, “q” is the quotient and “r” is the remainder.
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The truncated division rounds the quotient towards zero and the sign of its remainder is always the same as that
of its dividend, i.e., sign (r) = sign (D).
12.2.2
Normalize
The MDU supports up to 32-bit unsigned normalize.
Normalizing is done on an unsigned integer variable stored in MD0 (least significant byte) to MD3 (most significant
byte). This feature is mainly meant to support applications where floating point arithmetic is used. During
normalization, all leading zeros of an unsigned integer variable in registers MD0 to MD3 are removed by shift left
operations. The whole operation is completed when the MSB (most significant bit) contains a 1.
After normalizing, the bit field MR4.SCTR contains the number of shift left operations that were done. This number
may be used later as an exponent. The maximum number of shifts in a normalize operation is 31.
12.2.3
Shift
The MDU implements both logical and arithmetic shifts to support up to 32-bit unsigned and signed shift
operations.
During logical shift, zeros are shifted in from the left end of register MD3 or right end of register MD0. An arithmetic
left shift is identical to a logical left shift, but during arithmetic right shifts, signed bits are shifted in from the left end
of register MD3. For example, if the data 0101B and 1010B are to undergo an arithmetic shift right, the results
obtained will be 0010B and 1101B, respectively.
For any shift operation, register bit MD4.SLR specifies the shift direction, and MD4.SCTR the shift count.
Note: The MDU does not detect overflows due to an arithmetic shift left operation. User must always ensure that
the result of an arithmetic shift left is within the boundaries of MDU.
12.2.4
Busy Flag
A busy flag is provided to indicate the MDU is still performing a calculation. The flag MDUSTAT.BSY is set at the
start of a calculation and cleared after the calculation is completed at the end of phase two. It is also cleared when
the error flag is set.
If a second operation needs to be executed, the status of the busy flag will be polled first and only when it is not
set, can the start bit be written and the second operation begin. Any unauthorized write to the start bit while the
busy flag is still set will be ignored.
12.2.5
Error Detection
The error flag MDUSTAT.IERR is provided to indicate that an error has occured while performing a calculation.
The flag is set by hardware when one of these occurs:
•
•
Division by zero
Writing of reserved opcodes to MDUCON register
The setting of the error flag causes the current operation to be aborted and triggers an interrupt (see Section 12.3
below). A division by zero error does not set the error flag immediately but rather, at the end of calculation phase
for a division operation. An opcode error is detected upon setting MDUCON.START to 1. Errors due to division by
zero lead to the loading of a saturated value into the MRx registers.
Note: The accuracy of any result obtained when the error flag is set is not guaranteed by MDU and hence the result
should not be used.
12.3
Interrupt Generation
The interrupt structure of the MDU is shown in Figure 56. There are two possible interrupt events in the MDU, and
each event sets one of the two interrupt flags. The interrupt flags are reset by software by writing 0.
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At the end of phase two, the interrupt flag MDUSTAT.IRDY is set by hardware to indicate the successful
completion of a calculation. The results can then be obtained from the MRx registers. The interrupt line INT_O0 is
mapped directly to this interrupt source.
An interrupt can also be triggered when an error occurs during calculation. This is indicated by the setting of the
interrupt flag MDUSTAT.IERR. In the event of a division by zero error, MDUSTAT.IERR is set only at the end of
the calculation phase. Once the MDUSTAT.IERR is set, any ongoing calculation will be aborted. For division by
zero, a saturated value is then loaded into the MRx registers. The bit MDUCON.IR determines the interrupt line to
be mapped to this interrupt source.
An interrupt is only generated when the interrupt enable bit MDUCON.IE is 1 and the corresponding interrupt event
occurs. An interrupt request signal is always asserted positively for 2 CCLK clocks.
int_reset_SW
reset
IRDY
set
Completion of
Calculation
&
to INT_O0
IE
int_reset_SW
to INT_O1
&
Occurrence
of Error
set
reset
Figure 56
Interrupt Generation
12.4
Register Mapping
IR
IERR
Table 34 lists the MDU registers with their addresses in the standard SFR area.
Table 34
SFR Address List
SFR
Address
Name
MDUCON
B1H
MDU Control Register
MDUSTAT
B0H
MDU Status Register
MD0/MR0
B2H
MDU Data/Result Register 0
MD1/MR1
B3H
MDU Data/Result Register 1
MD2/MR2
B4H
MDU Data/Result Register 2
MD3/MR3
B5H
MDU Data/Result Register 3
MD4/MR4
B6H
MDU Data/Result Register 4
MD5/MR5
B7H
MDU Data/Result Register 5
The MDx and MRx registers share the same address. However, since MRx registers should never be written to,
any write operation to one of these addresses will be interpreted as a write to an MDx register.
In the event of a read operation, an additional bit MDUCON.RSEL is needed to select which set of registers, MDx
or MRx, the read operation must be directed to. By default, the MRx registers are read.
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12.5
MDU Kernel Registers
The 14 SFRs of the MDU consist of a control register MDUCON, a status register MDUSTAT and 2 sets of data
registers, MD0 to MD5 (which contain the operands) and MR0 to MR5 (which contain the results).
Depending on the type of operation, the individual MDx and MRx registers assume specific roles as summarized
in Table 35 and Table 36. For example, in a multiplication operation, the low byte of the 16-bit multiplicator must
be written to register MD4 and the high byte to MD5.
Table 35
MDx Registers
Register
Roles of Registers in Operations
16-bit Multiplication 32/16-bit Division
16/16-bit Division
Normalize and Shift
MD0
M’andL
D’endL
D’endL
OperandL
MD1
M’andH
D’end
D’endH
Operand
MD2
–
D’end
–
Operand
MD3
–
D’endH
–
OperandH
MD4
M’orL
D’orL
D’orL
Control
MD5
M’orH
D’orH
D’orH
–
Table 36
MRx Registers
Register
MR0
Roles of Registers in Operations
16-bit Multiplication 32/16-bit Division
16/16-bit Division
Normalize and Shift
PrL
QuoL
ResultL
QuoL
MR1
Pr
Quo
QuoH
Result
MR2
Pr
Quo
–
Result
MR3
PrH
QuoH
–
ResultH
MR4
M’orL
RemL
RemL
Control
MR5
M’orH
RemH
RemH
–
Abbreviations:
•
•
•
•
•
•
•
•
•
D’end: Dividend, 1st operand of division
D’or: Divisor, 2nd operand of division
M’and: Multiplicand, 1st operand of multiplication
M’or: Multiplicator, 2nd operand of multiplication
Pr: Product, result of multiplication
Rem: Remainder
Quo: Quotient, result of division
...L: means that this byte is the least significant of the 16-bit or 32-bit operand
...H: means that this byte is the most significant of the 16-bit or 32-bit operand
The MDx registers are built with shadow registers, which are latched with data from the actual registers at the start
of a calculation. This frees up the MDx registers to be written with the next set of operands while the current
calculation is ongoing.
MDx and MRx registers not used in an operation are undefined to the user. For normalize and shift operations,
the registers MD4 and MR4 are used as shift input and output control registers to specify the shift direction and
store the number of shifts performed.
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12.5.1
Operand and Result Registers
The MDx and MRx registers are used to store the operands and results of a calculation. MD4 and MR4 are also
used as input and output control registers for shift and normalize operations.
MDx (x = 0 - 3, 5)
MDU Operand Register
7
6
Reset Value: 00H
5
4
3
2
1
0
DATA
rw
Field
Bits
Type
Description
DATA
7:0
rw
Operand Value
See Table 35.
MRx (x = 0 - 3, 5)
MDU Result Register
7
6
Reset Value: 00H
5
4
3
2
1
0
DATA
rh
Field
Bits
Type
Description
DATA
7:0
rh
Result Value
See Table 36.
MD4
Shift Input Control Register
7
6
Reset Value: 00H
5
4
3
2
0
SLR
SCTR
rw
rw
rw
1
0
Field
Bits
Type
Description
SCTR
4:0
rw
Shift Counter
The count written to SCTR determines the number of shifts to be
performed during a shift operation.
SLR
5
rw
Shift Direction
0B
Selects shift left operation.
Selects shift right operation.
1B
0
7:6
rw
Reserved
Should be written with 0. Returns undefined data if read.
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MR4
Shift Output Control Register
7
Reset Value: 00H
6
5
4
3
2
1
0
SCTR
rh
rh
0
Field
Bits
Type
Description
SCTR
4:0
rw
Shift Counter
After a normalize operation, SCTR contains the number of
normalizing shifts performed.
0
7:5
rh
Reserved
Returns undefined data if read.
12.5.2
Control Register
Register MDUCON contains control bits that select and start the type of operation to be performed.
MDUCON
MDU Control Register
Reset Value: 00H
7
6
5
4
3
2
1
IE
IR
RSEL
START
OPCODE
rw
rw
rw
rwh
rw
Field
Bits
Type
Description
OPCODE
3:0
rw
Operation Code
00H Unsigned 16-bit Multiplication
01H Unsigned 16-bit/16-bit Division
02H Unsigned 32-bit/16-bit Division
03H 32-bit Logical Shift L/R
04H Signed 16-bit Multiplication
05H Signed 16-bit/16-bit Division
06H Signed 32-bit/16-bit Division
07H 32-bit Arithmetic Shift L/R
08H 32-bit Normalize
Note: Others: Reserved
START
4
rwh
Start Bit
The bit START is set by software and reset by hardware.
0B
Operation is not started.
1B
Operation is started.
RSEL
5
rw
Read Select
0B
Read the MRx registers.
1B
Read the MDx registers.
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Field
Bits
Type
Description
IR
6
rw
Interrupt Routing
0B
The two interrupt sources have their own dedicated interrupt
lines.
1B
The two interrupt sources share one interrupt line INT_O0.
IE
7
rw
Interrupt Enable
0B
The interrupt is disabled.
1B
The interrupt is enabled.
Note: Write access to MDUCON is not allowed when the busy flag MDUSTAT.BSY is set during the calculation
phase.
Note: Writing reserved opcode values to MDUCON results in an error condition when MDUCON.START bit is set
to 1.
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12.5.3
Status Register
Register MDUSTAT contains the status flags of the MDU.
MDUSTAT
MDU Status Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
BSY
IERR
IRDY
r
rh
rwh
rwh
Field
Bits
Type
Description
IRDY
0
rwh
Interrupt on Result Ready
The bit IRDY is set by hardware and reset by software.
0B
No interrupt is triggered at the end of a successful operation.
1B
An interrupt is triggered at the end of a successful operation.
IERR
1
rwh
Interrupt on Error
The bit IERR is set by hardware and reset by software.
0B
No interrupt is triggered with the occurrence of an error.
1B
An interrupt is triggered with the occurrence of an error.
BSY
2
rh
Busy Bit
0B
The MDU is not running any calculation.
1B
The MDU is still running a calculation.
0
7:3
r
Reserved
Returns 0 if read.
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12.6
MDU Module Implementation Details
This section describes:
•
•
the MDU module related interfaces
all MDU module related registers with its addresses
12.6.1
Interfaces of the MDU Module
An overview of the MDU kernel I/O interface is shown Figure 57.
Interrupt
Controller
Clock
Control
INT_O
MDU
Kernel
fMDU
Address
Decoder
BPI
Figure 57
MDU Module I/O Interface
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GPIO Ports and Peripheral I/O
13
GPIO Ports and Peripheral I/O
This chapter describes the GPIO Ports of the TLE983x. It contains the following sections:
•
•
•
Functional description of the GPIO Ports (see Section 13.1)
GPIO Port register descriptions (see Section 13.2)
TLE983x implementation specific details and registers of the GPIO module (see Section 13.3)
13.1
General Description
Figure 58 shows the block diagram of an TLE983x bidirectional port pin. Each port pin is equipped with a number
of control and data bits, thus enabling very flexible usage of the pin. By defining the contents of the control register,
each individual pin can be configured as an input or an output. The user can also configure each pin as an open
drain pin with or without internal pull-up/pull-down device.
Each bidirectional port pin can be configured for input or output operation. Switching between input and output
mode is accomplished through the register Px_DIR (x = 0 or 1), which enables or disables the output and input
drivers. A port pin can only be configured as either input or output mode at any one time.
In input mode (default after reset), the output driver is switched off (high-impedance). The actual voltage level
present at the port pin is translated into a logic 0 or 1 via a Schmitt-Trigger device and can be read via the register
Px_DATA.
In output mode, the output driver is activated and drives the value supplied through the multiplexer to the port pin.
In the output driver, each port line can be switched to open drain mode or normal mode (push-pull mode) via the
register Px_OD.
The output multiplexer in front of the output driver enables the port output function to be used for different
purposes. If the pin is used for general purpose output, the multiplexer is switched by software to the data register
Px_DATA. Software can set or clear the bit in Px_DATA and therefore directly influence the state of the port pin.
If an on-chip peripheral uses the pin for output signals, alternate output lines (AltDataOut) can be switched via the
multiplexer to the output driver circuitry. Selection of the alternate function is defined in registers Px_ALTSEL0 and
Px_ALTSEL1. When a port pin is used as an alternate function, its direction must be set accordingly in the register
Px_DIR.
Each pin can also be programmed to activate an internal weak pull-up or pull-down device. Register Px_PUDSEL
selects whether a pull-up or the pull-down device is activated while register Px_PUDEN enables or disables the
pull device.
The port structure used in this device offers the possibility to select the output driver strength and the slew rate.
These selections are independent from the output port functionality, such as open-drain, push/pull or input only.
The driver strength for each pin can be adapted to the application requirements by registers Px_POCONy (y = 0,
1 or 2) in SCU.
The temperature compensation signals TC[1:0] of all output drivers are connected to all outputs and are controlled
by register TCCR in SCU.
Note: For the definition of Px_POCONy and TCCR registers, refer to Chapter 20.5.2 of SCU chapter.
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GPIO Ports and Peripheral I/O
PUDSEL
Internal
Bus
Pull -up/Pull -down
Select Register
Pull-up/Pull-down
Control Logic
PUDEN
Pull -up/Pull -down
Enable Register
TCCR
Temperature
Compensation
Control Register
Px_POCONy
Port Output
Driver Control
Registers
OD
Open Drain
Control Register
DIR
Direction Register
ALTSEL0
Alternate Select
Register 0
ALTSEL1
Pull
Device
Alternate Select
Register 1
AltDataOut 3
Output
Driver
11
AltDataOut 2
10
AltDataOut1
Pin
01
00
Data
Data Register
Out
Input
Driver
In
Schmitt
Trigger
AltDataIn
Pad
AnalogIn
Figure 58
General Structure of Bidirectional Port
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Figure 59 shows the structure of an input-only port pin. Each P2 pin can only function in input mode. Register
P2_DIR is provided to enable or disable the input driver. When the input driver is enabled, the actual voltage level
present at the port pin is translated into a logic 0 or 1 via a Schmitt-Trigger device and can be read via the register
P2_DATA. Each pin can also be programmed to activate an internal weak pull-up or pull-down device. Register
P2_PUDSEL selects whether a pull-up or the pull-down device is activated while register P2_PUDEN enables or
disables the pull device. The analog input (AnalogIn) bypasses the digital circuitry and Schmitt-Trigger device for
direct feed-through to the ADC input channel.
Internal Bus
PUDSEL
Pull-up/Pull-down
Select Register
Pull-up/Pull-down
Control Logic
PUDEN
Pull-up/Pull-down
Enable Register
Pull
Device
Data
In
Input
Driver
Pin
Data Register
Schmitt Trigger
Pad
AltDataIn
AnalogIn
Figure 59
General Structure of Input Port
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GPIO Ports and Peripheral I/O
13.2
Port Register Description
Each port consists of 8-bit control and data registers. The registers are defined in Table 37.
Control Registers
Data Registers
Px_DIR
Px_DATA
Px_OD
Px_PUDSEL
Px_PUDEN
Px_ALTSEL0
Px_ALTSEL1
Portx_Regs
Figure 60
Port Registers
Table 37
Port Registers
Register Short Name
Register Long Name
Description
Px_DATA
Port x Data Register
Page-260
Px_DIR
Port x Direction Register
Page-260
Px_OD
Port x Open Drain Control Register
Page-261
Px_PUDSEL
Port x Pull-Up/Pull-Down Select Register
Page-261
Px_PUDEN
Port x Pull-Up/Pull-Down Enable Register
Page-261
Px_ALTSEL0
Port x Alternate Select Register 0
Page-263
Px_ALTSEL1
Port x Alternate Select Register 1
Page-263
Note: Not all the registers are implemented for each port.
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13.2.1
Port Data Register
If a port pin is used as general purpose output, output data is written into register Px_DATA of port x. When the
port pin is used as general purpose input, the value at a port pin can be read through the register Px_DATA. The
data register Px_DATA always contains a latched value of the assigned port pin.
Px_DATA
Port x Data Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type
Description
Pn
(n = 0 - 7)
n
rwh
Portx Pin n Data Value
0B
Port x pin n data value = 0
1B
Port x pin n data value = 1
Bit Px_DATA.n can only be written if the corresponding pin is set to output, i.e. Px_DIR.n = 1. The contents of
Px_DATA.n are output on the assigned pin if the pin is assigned as GPIO pin and the direction is switched/set to
output. A read operation of Px_DATA returns the register value and not the state of the Px_DATA pins.
13.2.2
Direction Register
The direction of bidirectional port pins is controlled by the respective direction register Px_DIR. For input-only port
pins, register Px_DIR is used to enable or disable the input drivers.
Px_DIR
Port x Direction Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 - 7)
n
rw
Bidirectional: Port x Pin n Direction Control
0B
Direction is set to input (default)
1B
Direction is set to output
or
Input-only: Port x Pin n Driver Control
0B
Input driver is enabled (default)
1B
Input driver is disabled
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13.2.3
Open Drain Control Register
Each pin in output mode can be switched to Open Drain Mode. If driven with 1, no driver will be activated and the
pin output state depends on the internal pull-up/pull-down device setting; if driven with 0, the driver’s pull-down
transistor will be activated.
The open drain mode is controlled by the register Px_OD.
Px_OD
Port x Open Drain Control Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 - 7)
n
rw
Port x Pin n Open Drain Mode
0B
Normal Mode, output is actively driven for 0 and 1 state (default)
1B
Open Drain Mode, output is actively driven only for 0 state
13.2.4
Pull-Up/Pull-Down Device Register
Internal pull-up/pull-down devices can be optionally applied to a port pin. This offers the possibility to configure the
following input characteristics:
•
•
•
tristate
high-impedance with a weak pull-up device
high-impedance with a weak pull-down device
and the following output characteristics:
•
•
•
push/pull (optional pull-up/pull-down)
open drain with internal pull-up
open drain with external pull-up
The pull-up/pull-down device can be fixed or controlled via the registers Px_PUDSEL and Px_PUDEN. Register
Px_PUDSEL selects the type of pull-up/pull-down device, while register Px_PUDEN enables or disables it. The
pull-up/pull-down device can be selected pinwise.
Note: The selected pull-up/pull-down device is enabled by setting the respective bit in the Px_PUDEN register.
Px_PUDSEL
Port x Pull-Up/Pull-Down Select Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 - 7)
n
rw
Pull-Up/Pull-Down Select Port x Bit n
0B
Pull-down device is selected
1B
Pull-up device is selected
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Px_PUDEN
Port x Pull-Up/Pull-Down Enable Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 - 7)
n
rw
Pull-Up/Pull-Down Enable at Port x Bit n
0B
Pull-up or Pull-down device is disabled
1B
Pull-up or Pull-down device is enabled
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13.2.5
Alternate Input Functions
The number of alternate functions that uses a pin for input is not limited. Each port control logic of an I/O pin
provides several input paths:
•
•
Digital input value via register
Direct digital input value
13.2.6
Alternate Output Functions
Alternate functions are selected via an output multiplexer which can select up to four output lines. This multiplexer
can be controlled by the following signals:
•
•
Register Px_ALTSEL0
Register Px_ALTSEL1
Selection of alternate functions is defined in registers Px_ALTSEL0 and Px_ALTSEL1.
Px_ALTSELn (n = 0, 1)
Port x Alternate Select Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 - 7)
n
rw
See Table 38
Table 38
Function of Bits Px_ALTSEL0.Pn and Px_ALTSEL1.Pn
Px_ALTSEL0.Pn
Px_ALTSEL1.Pn
Function
0
0
Normal GPIO
1
0
Alternate Select 1
0
1
Alternate Select 2
1
1
Alternate Select 3
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13.3
TLE983x Port Implementation Details
13.3.1
Port 0
13.3.1.1
Overview
Port 0 is a general purpose bidirectional port. The port registers of Port 0 are shown in Table 61.
Control Registers
Data Register
P0_DIR
P0_DATA
P0_OD
P0_PUDSEL
P0_PUDEN
P0_ALTSEL0
P0_ALTSEL1
Port0_Regs
Figure 61
Port 0 Registers
Table 39
Port 0 Registers
Register Short Name
Register Long Name
P0_DATA
Port 0 Data Register
P0_DIR
Port 0 Direction Register
P0_OD
Port 0 Open Drain Control Register
P0_PUDSEL
Port 0 Pull-Up/Pull-Down Select Register
P0_PUDEN
Port 0 Pull-Up/Pull-Down Enable Register
P0_ALTSEL0
Port 0 Alternate Select Register 0
P0_ALTSEL1
Port 0 Alternate Select Register 1
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GPIO Ports and Peripheral I/O
13.3.1.2
Port 0 Functions
Table 40
Port 0 Input/Output Functions
Port Pin
Input/Output
Select
P0.0
Input
GPI
P0_DATA.P0
ALT1
TCK_0
JTAG
ALT2
T12HR_0
CCU6
ALT3
–
ALT4
T2_0
Timer 2
ALT5
DAP0
DAP
ALT6
EXINT2_3
SCU
GPO
P0_DATA.P0
ALT1
–
ALT2
EXF21_0
Timer 21
ALT3
RXDO_0
UART
GPI
P0_DATA.P1
ALT1
TDI_0
JTAG
ALT2
T13HR_0
CCU6
ALT3
RXD_1
UART
ALT4
T2EX_1
Timer 2
ALT5
T21_0
Timer 21
ALT6
EXINT0_3
SCU
GPO
P0_DATA.P1
ALT1
–
ALT2
–
ALT3
–
GPI
P0_DATA.P2
ALT1
–
Output
P0.1
Input
Output
P0.2
Input
Output
User’s Manual
Connected Signal(s)
From/to Module
ALT2
CTRAP#_0
ALT3
–
ALT4
–
ALT5
T21EX_0
Timer 21
ALT6
EXINT1_3
SCU
GPO
P0_DATA.P2
ALT1
–
ALT2
TXD_1
UART
ALT3
EXF2_0
Timer 2
265
CCU6
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GPIO Ports and Peripheral I/O
Table 40
Port 0 Input/Output Functions (cont’d)
Port Pin
Input/Output
Select
Connected Signal(s)
P0.3
Input
GPI
P0_DATA.P3
ALT1
SCK_0
ALT2
–
ALT3
–
Output
P0.4
Input
Output
P0.5
Input
Output
User’s Manual
From/to Module
SSC
ALT4
EXINT1_2
ALT5
T0_0
Timer 0
ALT6
CCPOS0_1
CCU6
GPO
P0_DATA.P3
ALT1
SCK_0
SSC
ALT2
EXF21_2
Timer 21
ALT3
–
GPI
P0_DATA.P4
ALT1
MTSR_0
SSC
ALT2
CC60_0
CCU6
ALT3
T21_2
Timer 21
ALT4
EXINT2_2
SCU
ALT5
–
ALT6
CCPOS1_1
GPO
P0_DATA.P4
ALT1
MTSR_0
SSC
ALT2
CC60_0
CCU6
ALT3
CLKOUT_0
SCU
GPI
P0_DATA.P5
ALT1
MRST_0
SSC
ALT2
EXINT0_0
SCU
ALT3
T21EX_2
Timer 21
ALT4
–
ALT5
T1_0
Timer 1
CCU6
CCU6
ALT6
CCPOS2_1
GPO
P0_DATA.P5
ALT1
MRST_0
SSC
ALT2
COUT60_0
CCU6
ALT3
–
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13.3.1.3
Port 0 Register Description
Data Register
P0_DATA
Port 0 Data Register
7
Reset Value: XXH
6
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type
Description
Pn
(n = 0 - 5)
n
rwh
Port 0 Pin n Data Value
0B
Port 0 pin n data value = 0
1B
Port 0 pin n data value = 1
0
[7:6]
r
Reserved
Returns 0 if read.
Direction Register
P0_DIR
Port 0 Direction Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0-5)
n
rw
Port 0 Pin n Direction Control
0B
Direction is set to input (default)
1B
Direction is set to output
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
Open Drain Control Register
P0_OD
Port 0 Open Drain Control Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 - 5)
n
rw
Port 0 Pin n Open Drain Mode
0B
Normal Mode, output is actively driven for 0 and 1 state (default)
1B
Open Drain Mode, output is actively driven only for 0 state
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Field
Bits
Type
Description
0
[7:6]
r
Reserved
Returns 0 if read.
Pull-Up/Pull-Down Device Register
P0_PUDSEL
Port 0 Pull-Up/Pull-Down Select Register
7
6
Reset Value: 3FH
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 - 5)
n
rw
Pull-Up/Pull-Down Select Port 0 Bit n
0B
Pull-down device is selected
1B
Pull-up device is selected (default)
0
[7:6]
r
Reserved
Returns 0 if read.
P0_PUDEN
Port 0 Pull-Up/Pull-Down Enable Register
7
6
Reset Value: 3FH
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 - 5)
n
rw
Pull-Up/Pull-Down Enable at Port 0 Bit n
0B
Pull-up or Pull-down device is disabled
1B
Pull-up or Pull-down device is enabled (default)
0
[7:6]
r
Reserved
Returns 0 if read.
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GPIO Ports and Peripheral I/O
Alternate Output Select Register
P0_ALTSELn (n = 0, 1)
Port 0 Alternate Select Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 - 5)
n
rw
See Table 41
Table 41
Function of Bits P0_ALTSEL0.Pn and P0_ALTSEL1.Pn
P0_ALTSEL0.Pn
P0_ALTSEL1.Pn
Function
0
0
Normal GPIO
1
0
Alternate Select 1
0
1
Alternate Select 2
1
1
Alternate Select 3
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13.3.2
Port 1
13.3.2.1
Overview
Port 1 is a general purpose bidirectional port. The port registers of Port 1 are shown in Table 62.
Control Registers
Data Register
P1_DIR
P1_DATA
P1_OD
P1_PUDSEL
P1_PUDEN
P1_ALTSEL0
P1_ALTSEL1
Port1_Regs
Figure 62
Port 1 Registers
Table 42
Port 1 Registers
Register Short Name
Register Long Name
P1_DATA
Port 1 Data Register
P1_DIR
Port 1 Direction Register
P1_OD
Port 1 Open Drain Control Register
P1_PUDSEL
Port 1 Pull-Up/Pull-Down Select Register
P1_PUDEN
Port 1 Pull-Up/Pull-Down Enable Register
P1_ALTSEL0
Port 1 Alternate Select Register 0
P1_ALTSEL1
Port 1 Alternate Select Register 1
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13.3.2.2
Port 1 Functions
Table 43
Port 1 Input / Output Functions
Port Pin
Input/Output
Select
Connected Signal(s)
P1.0
Input
GPI
P1_DATA.P0
ALT 1
–
ALT 2
T0_1
Timer 0
ALT 3
CC61_0
CCU6
ALT 4
SCK_1
SSC
GPO
P1_DATA.P0
ALT1
SCK_1
SSC
ALT2
CC61_0
CCU6
Timer 21
Output
P1.1
Input
Output
P1.2
Input
Output
User’s Manual
From/to Module
ALT3
EXF21_3
GPI
P1_DATA.P1
ALT 1
–
ALT 2
T1_1
Timer 1
ALT 3
–
Timer 0
ALT 4
MTSR_1
SSC
ALT 5
T21EX_3
Timer 2
GPO
P1_DATA.P1
ALT1
MTSR_1
SSC
ALT2
COUT61_0
CCU6
ALT3
–
GPI
P1_DATA.P2
ALT 1
EXINT0_1
SCU
ALT 2
T21_1
Timer 21
ALT 3
–
ALT 4
MRST_1
ALT 5
–
ALT 6
CCPOS2_2
GPO
P1_DATA.P2
ALT1
MRST_1
SSC
ALT2
COUT63_0
CCU6
ALT3
–
271
SSC
CCU6
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GPIO Ports and Peripheral I/O
Table 43
Port 1 Input / Output Functions (cont’d)
Port Pin
Input/Output
Select
Connected Signal(s)
P1.3
Input
GPI
P1_DATA.P3
ALT 1
EXINT1_1
ALT 2
–
ALT 3
CC62_0
ALT 4
–
ALT 5
–
ALT 6
CCPOS0_2
GPO
P1_DATA.P3
ALT1
EXF21_1
Timer 21
ALT2
CC62_0
CCU6
ALT3
–
GPI
P1_DATA.P4
ALT 1
EXINT2_1
SCU
ALT 2
T21EX_1
Timer 21
ALT 3
–
ALT 4
–
ALT 5
–
ALT6
CCPOS1_2
GPO
P1_DATA.P4
ALT1
CLKOUT_1
SCU
ALT2
COUT62_0
CCU6
ALT3
–
Output
P1.4
Input
Output
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From/to Module
SCU
CCU6
CCU6
CCU6
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GPIO Ports and Peripheral I/O
13.3.2.3
Port 1 Register Description
Data Register
P1_DATA
Port 1 Data Register
7
Reset Value: XXH
6
5
4
3
2
1
0
0
P4
P3
P2
P1
P0
r
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type
Description
Pn
(n = 0 - 4)
n
rwh
Port 1 Pin n Data Value
0B
Port 1 pin n data value = 0
1B
Port 1 pin n data value = 1
0
[7:5]
r
Reserved
Returns 0 if read.
Direction Register
P1_DIR
Port 1 Direction Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 - 4)
n
rw
Port 1 Pin n Direction Control
0B
Direction is set to input (default)
Direction is set to output
1B
0
[7:5]
r
Reserved
Returns 0 if read.
Open Drain Control Register
P1_OD
Port 1 Open Drain Control Register
7
User’s Manual
6
5
Reset Value: 00H
4
3
2
1
0
0
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
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Field
Bits
Type
Description
Pn
(n = 0 - 4)
n
rw
Port 1 Pin n Open Drain Mode
0B
Normal Mode, output is actively driven for 0 and 1 state (default)
1B
Open Drain Mode, output is actively driven only for 0 state
0
[7:5]
r
Reserved
Returns 0 if read.
Pull-Up/Pull-Down Device Register
P1_PUDSEL
Port 1 Pull-Up/Pull-Down Select Register
7
6
5
Reset Value: 1FH
4
3
2
1
0
0
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 - 4)
n
rw
Pull-Up/Pull-Down Select Port 1 Bit n
0B
Pull-down device is selected
1B
Pull-up device is selected (default)
0
[7:5]
r
Reserved
Returns 0 if read.
P1_PUDEN
Port 1 Pull-Up/Pull-Down Enable Register
7
6
5
Reset Value: 00H
4
3
2
1
0
0
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 - 4)
n
rw
Pull-Up/Pull-Down Enable at Port 1 Bit n
0B
Pull-up or Pull-down device is disabled (default)
1B
Pull-up or Pull-down device is enabled
0
[7:5]
r
Reserved
Returns 0 if read.
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GPIO Ports and Peripheral I/O
Alternate Output Select Register
P1_ALTSELn (n = 0, 1)
Port 1 Alternate Select Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 - 4)
n
rw
See Table 44
Table 44
Function of Bits P1_ALTSEL0.Pn and P1_ALTSEL1.Pn
P1_ALTSEL0.Pn
P1_ALTSEL1.Pn
Function
0
0
Normal GPIO
1
0
Alternate Select 1
0
1
Alternate Select 2
1
1
Alternate Select 3
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GPIO Ports and Peripheral I/O
13.3.3
Port 2
13.3.3.1
Overview
Port 2 is a general purpose input-only port. The port registers of Port 2 are shown in Table 63.
Control Registers
Data Register
P2_DIR
P2_DATA
P2_PUDSEL
P2_PUDEN
Port2_Regs
Figure 63
Port 2 Registers
Table 45
Port 2 Registers
Register Short Name
Register Long Name
P2_DATA
Port 2 Data Register
P2_DIR
Port 2 Direction Register
P2_PUDSEL
Port 2 Pull-Up/Pull-Down Select Register
P2_PUDEN
Port 2 Pull-Up/Pull-Down Enable Register
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13.3.3.2
Port 2 Functions
Table 46
Port 2 Input Functions
Port Pin
Input/Output
Select
P2.1
Input
GPI
P2_DATA.P1
ALT 1
CCPOS0_0
CCU6
ALT 2
EXINT1_0
SCU
ALT 3
T12HR_1
CCU6
ALT 4
–
ALT 5
CC61_1
CCU6
ANALOG
AN1
ADC
GPI
P2_DATA.P3
ALT 1
CCPOS1_0
CCU6
ALT 2
EXINT0_2
SCU
ALT 3
CTRAP#_1
CCU6
ALT 4
–
ALT 5
CC60_1
CCU6
ANALOG
AN3
ADC
GPI
P2_DATA.P4
ALT 1
–
P2.3
P2.4
P2.5
P2.7
User’s Manual
Input
Input
Input
Input
Connected Signal(s)
ALT 2
T0_2
ALT 3
–
ANALOG
AN4
GPI
P2_DATA.P5
ALT 1
–
ALT 2
T1_2
ALT 3
–
ANALOG
AN5
From/to Module
ADC
ADC
GPI
P2_DATA.P7
ALT 1
CCPOS2_0
CCU6
ALT 2
EXINT2_0
SCU
ALT 3
T13HR_1
CCU6
ALT 4
–
ALT 5
CC62_1
CCU6
ANALOG
AN7
ADC
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13.3.3.3
Port 2 Register Description
Data Register
P2_DATA
Port 2 Data Register
Reset Value: XXH
7
6
5
4
3
2
1
0
P7
0
P5
P4
P3
0
P1
0
rwh
r
rwh
rwh
rwh
r
rwh
r
Field
Bits
Type
Description
Pn
(n = 1, 3 - 5, 7)
n
rwh
Port 2 Pin n Data Value
0B
Port 2 pin n data value = 0
1B
Port 2 pin n data value = 1
0
2
r
Reserved
Returns 0 if read.
Direction Register
P2_DIR
Port 2 Direction Register
Reset Value: 00H
7
6
5
4
3
2
1
0
P7
0
P5
P4
P3
0
P1
0
rw
r
rw
rw
rw
r
rw
r
Field
Bits
Type
Description
Pn
(n = 1, 3 - 5, 7)
n
rw
Port 2 Pin n Driver Control
0B
Input driver is enabled
1B
Input driver is disabled (default)
0
2
r
Reserved
Returns 0 if read.
Pull-Up/Pull-Down Device Register
P2_PUDSEL
Port 2 Pull-Up/Pull-Down Select Register
Reset Value: BAH
7
6
5
4
3
2
1
0
P7
0
P5
P4
P3
0
P1
0
rw
r
rw
rw
rw
r
rw
r
Field
Bits
Type
Description
Pn
(n = 1, 3 - 5, 7)
n
rw
Pull-Up/Pull-Down Select Port 2 Bit n
0B
Pull-down device is selected
1B
Pull-up device is selected (default)
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Field
Bits
Type
Description
0
2
r
Reserved
Returns 0 if read.
P2_PUDEN
Port 2 Pull-Up/Pull-Down Enable Register
Reset Value: 00H
7
6
5
4
3
2
1
0
P7
0
P5
P4
P3
0
P1
0
rw
r
rw
rw
rw
r
rw
r
Field
Bits
Type
Description
Pn
(n = 1, 3 - 5, 7)
n
rw
Pull-Up/Pull-Down Enable at Port 2 Bit n
0B
Pull-up or Pull-down device is disabled (default)
1B
Pull-up or Pull-down device is enabled
0
2
r
Reserved
Returns 0 if read.
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13.3.4
Register Mapping
The BPI of the Ports supports the local address extension mechanism, such that the SFRs of the Ports kernel are
organized into 4 pages. Please refer to Chapter 7 for details on the local address extension.
SFR PORT_PAGE, at address 8EH, contains the page value and the page control information.
PORT_PAGE
Page Register for PORT
7
Reset Value: 00H
6
5
4
3
2
1
OP
STNR
PAGE
w
w
rwh
0
Field
Bits
Type
Description
PAGE
[3:0]
rwh
Page Bits
When written, the value indicates the new page address.
When read, the value indicates the currently active page = addr
[y:x+1]
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the target of the
operation defined by bit OP.
If OP = 10B,
the contents of PAGE are saved in STx before being overwritten with
the new value.
If OP = 11B,
the contents of PAGE are overwritten by the contents of STx. The
value written to the bit positions of PAGE is ignored.
00B ST0 is selected.
01B ST1 is selected.
10B ST2 is selected.
11B ST3 is selected.
OP
[7:6]
w
Operation
0XB Manual page mode. The value of STNR is ignored and PAGE
is directly written.
10B New page programming with automatic page saving. The
value written to the bit positions of PAGE is stored. In parallel,
the former contents of PAGE are saved in the storage bit field
STx indicated by STNR.
11B Automatic restore page action. The value written to the bit
positions PAGE is ignored and instead, PAGE is overwritten by
the contents of the storage bit field STx indicated by STNR.
The addresses of the Port SFRs are listed in Table 47.
Table 47
SFR Address List for Pages 0-5
Address
Page 0
Page 1
Page 2
Page 3
80H
P0_DATA
P0_PUDSEL
P0_ALTSEL0
P0_OD
86H
P0_DIR
P0_PUDEN
P0_ALTSEL1
90H
P1_DATA
P1_PUDSEL
P1_ALTSEL0
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P1_OD
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GPIO Ports and Peripheral I/O
Table 47
SFR Address List for Pages 0-5 (cont’d)
91H
P1_DIR
P1_PUDEN
C8H
P2_DATA
P2_PUDSEL
C9H
P2_DIR
P2_PUDEN
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TLE983x
Timer 0 and Timer 1
14
Timer 0 and Timer 1
Features
•
•
•
•
•
•
16bit-upcounting Timer/Counter
Counting frequency fPCLK/2
External counting frequency input
4 operation modes
Software/hardware run control
Interrupt upon overflow
14.1
Overview
The Timer/Counter is designed to count cycles on fPCLK/2 or an externally supplied clock input. Different modes of
operation provide functionality suited for various applications. Upon overflow of the Timer/Counter an interrupt
may be issued to trigger software operations.
14.2
Register Overview
Seven SFR registers are provided to control Timer 0 and Timer 1. The timer count register is split up into two 8Bit registers (TLx/THx) and are implemented for both timers, Timer 0 and Timer 1, individually. All other registers
are shared among both timers. All registers are accessible from the non-mapped SFR area as well as from the
mapped SFR area.
Table 48
SFR Address List
Address
Register
Description
88H
TCON
Timer Control Register
89H
TMOD
Timer Mode Register
8AH
TL0
Timer Value Low, Timer 0
8BH
TL1
Timer Value Low, Timer 1
8CH
TH0
Timer Value High, Timer 0
8DH
TH1
Timer Value High, Timer 1
A8H
IEN0
Interrupt Enable Register
14.3
Description
Four different modes of operation are provided to fulfill a various number of tasks with the timers. In every mode
the clocking source can be chosen from internal clock fPCLK/2 or the external source T0/T1 by setting the T0S/T1S
flag in TMOD accordingly. In every mode the run control of the timer is controlled either by software using the
TR0/TR1 flag in TCON, or by hardware. The timer counts upwards, starting with the timer count register (TLx/THx)
until the maximum count value depending on the selected operation mode. Upon an overflow of the timer count
register this register will be reset to 0x0000. The initialization of the timer count registers (TLx/THx) to a value other
than 0x0000 can be used as an initial preload of the timer counter register. A reload-functionality is not provided
for Timer 0 and Timer 1.
14.4
Hardware Run Control
The timer can be started by pulling the external input EXINT0/EXINT1 high, during the high phase of these inputs
the corresponding timer runs. As soon as the external input EXINT0/EXINT1 gets pulled to low the corresponding
timer stops. To enable the hardware run control the appropriate GATE0/GATE1 flag in TMOD has to be set. By
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Timer 0 and Timer 1
resetting GATE0/GATE1 the hardware control is switched back to software control. To ensure a proper operation
of the hardware run control the EXINT0/EXINT1 sources needs to be configured to bypass-mode in register
EXICON0.
14.5
Interrupt
The TLE983x implements two individual interrupt vectors, one for each timer. For each timer the corresponding
overflow interrupt has to be enabled in the register IEN0 individually. Upon an overflow of the timer the
corresponding TF0/TF1 flag gets set in the register TCON. An interrupt is raised when enabled. The corresponding
TF0/TF1 flag gets cleared as soon as the ISR is entered.
Table 49
Interrupt Routing
Interrupt Vector
Vector Name
Description
01H
T0INT
Timer 0 Interrupt
03H
T1INT
Timer 1 Interrupt
14.6
Modes of Operation
Timer 0 and Timer 1 are providing four different modes of operation, which are described in the following sections.
By setting T0M/T1M in the TMOD register the timer will be configured to operate in a certain mode.
Table 50
Timer 0, 1 Modes
Mode
Operation
0
13-bit timer
Compatibility with Intel 8048 devices.
1
16-bit timer
The timer registers, TLx and THx, are concatenated to form a 16-bit counter.
2
8-bit timer with auto-reload
The timer register TLx is reloaded with a user-defined 8-bit value in THx upon overflow.
3
Timer 0 Operates as two 8-bit timers
The timer registers, TL0 and TH0, operate as two separate 8-bit counters. Timer 1 is halted and
retains its count even if enabled.
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Timer 0 and Timer 1
14.6.1
Mode 0
Mode 0 implements a 13-bit-timer/counter compatible to the 8048 device. TH0/TH1 holds the upper 8 bits of the
13-bit timer value. TL0/TL1 holds the lower 5 bits of the 13-bit timer value. The bits TL0/TL1[7:5] are not defined
and should not be used in this mode of operation. An overflow will be generated by the transition of the timer value
from 0x1FFF to 0x0000.
fPCLK/2
T0S = 0
TL0
(5 Bits)
TH0
(8 Bits)
TF0
T0S = 1
T0
Control
TR0
&
=1
GATE0
>1
EXINT0
Timer0_Mode0
Figure 64
Timer 0, Mode 0: 13-Bit Timer
14.6.2
Mode 1
Mode 1 configures the timer to 16-bit mode. TH0/TH1 holds the upper 8 bits of the timer value, while TL0/TL1 is
holding the lower 8 bits of the timer value. An overflow will be generated by the transition of the timer value from
0xFFFF to 0x0000.
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Timer 0 and Timer 1
fPCLK/2
T0S = 0
TL0
(8 Bits)
TH0
(8 Bits)
TF0
Interrupt
T0S = 1
T0
Control
TR0
&
=1
GATE0
>1
EXINT0
Figure 65
Timer 0, Mode 1: 16-Bit Timer
14.6.3
Mode 2
Timer0_Mode1
In Mode 2 the timer is configured to an 8-bit-timer/counter with reload. The TL0/TL1 register is the counting register
and will be clocked by the defined clock source. The run of Mode 2 can be controlled with the above described run
control methods. Upon an overflow of TL0/TL1 by changing the register content from 0xFF to 0x00 the overflow
flag TF0/TF1 will be set as well as an interrupt will be raised if enabled. Furthermore the overflow issues a reload
of the TL0/TL1 register with the preloaded content of the register TH0/TH1. The content of TH0/TH1 stays
unchanged by the reload process.
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Timer 0 and Timer 1
fPCLK/2
T0S = 0
TL0
(8 Bits)
TF0
Interrupt
T0S = 1
T0
Control
TR0
Reload
&
=1
GATE0
TH0
(8 Bits)
>1
Timer0_Mode2
EXINT0
Figure 66
Timer 0, Mode 2: 8-Bit Timer with Auto-Reload
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Timer 0 and Timer 1
14.6.4
Mode 3
In Mode 3 the two Timer 0 registers, TL0 and TH0, function as two separate 8-bit counters. Timer 1 retains its
count and stops running even when it is enabled (TCON.TR1 = 1). The 8-bit counter, TL0, uses the Timer 0 control
bits: T0S, GATE0, TR0 and TF0, while the other 8-bit counter, TH0, is locked into a timer function (counting
machine cycles) and takes over the use of TR1 from Timer 1. Furthermore, TH0 now sets the Timer 1 flag bit TF1
upon overflow and generates an interrupt if IEN0.ET1 is set. Mode3 is provided for applications requiring an extra
8-bit timer. When Timer 0 operates in Mode 3 and TCON.TR1 is set, Timer 1 can be programmed to halt (by putting
it into Mode 3) or to run (by switching into Mode 0, 1 or 2). It can even be used by the UART as a baud rate
generator. Note, however, that Timer 1 is unable to indicate an overflow or generate an interrupt if Timer 0 is in
Mode 3.
Timer Clock
fPCLK/2
T0S = 0
TL0
(8 Bits)
TF0
TH0
(8 Bits)
TF1
Interrupt
T0S = 1
T0
Control
TR0
&
=1
GATE0
>1
EXINT0
TR1
Figure 67
Interrupt
Timer0_Mode3
Timer 0, Mode 3: Two 8-Bit Timers
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Timer 0 and Timer 1
14.7
Register Description
Seven Special Function Registers are available to control the operation of Timer 0 and Timer 1. TL0/TH0 and
TL1/TH1 are the low and high timer registers. TCON and IEN0 are the control and interrupt enable registers.
TMOD is the mode select registers.
Table 51
SFR Address List
Address
Register
Description
88H
TCON
Timer Control Register
89H
TMOD
Timer Mode Register
8AH
TL0
Timer Value Low, Timer 0
8BH
TL1
Timer Value Low, Timer 1
8CH
TH0
Timer Value High, Timer 0
8DH
TH1
Timer Value High, Timer 1
A8H
IEN0
Interrupt Enable Register
Timer 0 and Timer 1 SFRs can be accessed from both the standard (non-mapped) and mapped SFR area.
TLx (x = 0, 1)
Timer x, Low Byte
7
Reset Value: 00H
6
5
4
3
2
1
0
VAL
rwh
Field
Bits
Type
Description
TLx.VAL(x = 0, 1)
7:0
rwh
Timer 0/1 Low Register
Mode 0TLx holds lower the 5 bits of the timer value.
Mode 1TLx holds the lower 8-bit part of the 16-bit timer value.
Mode 2TLx holds the 8-bit timer value.
Mode 3TL0 holds the 8-bit timer value; TL1 is not used.
THx (x = 0, 1)
Timer x, High Byte
7
Reset Value: 00H
6
5
4
3
2
1
0
VAL
rwh
Field
Bits
Type
Description
THx.VAL(x = 0, 1)
7:0
rwh
Timer 0/1 High Register
Mode 0THx holds the 8-bit timer value.
Mode 1THx holds the higher 8-bit part of the 16-bit timer value.
Mode 2THx holds the 8-bit reload value.
Mode 3TH0 holds the 8-bit timer value; TH1 is not used.
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Timer 0 and Timer 1
TCON
Timer 0/1 Control Registers
7
6
TF1
TR1
rwh
r
rw
Reset Value: 00H
5
4
3
2
TF0
TR0
IE1
IT1
rwh
rw
rwh
rw
r
1
0
IE0
IT0
rwh
rw
Field
Bits
Type
Description
TR0
4
rw
Timer 0 Run Control
0B
Timer is halted
1B
Timer runs
TF0
5
rwh
Timer 0 Overflow Flag
Set by hardware when Timer 0 overflows. Cleared by hardware
when the processor calls the interrupt service routine.
TR1
6
rw
Timer 1 Run Control
Note: Timer 1 Run Control affects TH0 also if Timer 0 operates in
Mode 3
0B
1B
TF1
7
rwh
Timer is halted
Timer runs
Timer 1 Overflow Flag
Set by hardware when Timer 11) overflows. Cleared by hardware
when the processor calls the interrupt service routine.
1) TF1 is set by TH0 instead if Timer 0 operates in Mode 3.
TMOD
Timer Mode Register
7
6
GATE1
T1S
rw
rw
Reset Value: 00H
5
4
3
2
T1M
GATE0
T0S
T0M
rw
rw
rw
rw
r
1
0
Field
Bits
Type
Description
T0M[1:0]
1:0
rw
Mode Select Bits
00B 13-bit timer (M8048 compatible mode)
01B 16-bit timer
10B 8-bit auto-reload timer
11B Timer 0 is split into two halves. TL0 is an 8-bit timer
controlled by the standard Timer 0 control bits, and TH0 is
the other 8-bit timer controlled by the standard Timer 1
control bits. TH1 and TL1 of Timer 1 are held (Timer 1 is
stopped).
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Field
Bits
Type
Description
T1M[1:0]
5:4
rw
Mode Select Bits
00B 13-bit timer (M8048 compatible mode)
01B 16-bit timer
10B 8-bit auto-reload timer
11B Timer 0 is split into two halves. TL0 is an 8-bit timer
controlled by the standard Timer 0 control bits, and TH0 is
the other 8-bit timer controlled by the standard Timer 1
control bits. TH1 and TL1 of Timer 1 are held (Timer 1 is
stopped).
T0S
2
rw
Timer 0 Selector
0B
Input is from internal system clock
1B
Input is from T0 pin
GATE0
3
rw
Timer 0 Gate Flag
0B
Timer 0 will only run if TCON.TR0 = 1 (software control)
1B
Timer 0 will only run if NINT0 pin = 1 (hardware control) and
TCON.TR0 is set
T1S
6
rw
Timer 1 Selector
0B
Input is from internal system clock
1B
Input is from T1 pin
GATE1
7
rw
Timer 1 Gate Flag
0B
Timer 1 will only run if TCON.TR1 = 1 (software control)
1B
Timer 1 will only run if NINT1 pin = 1 (hardware control) and
TCON.TR1 is set
IEN0
Interrupt Enable Register
7
6
EA
0
rw
Reset Value: 00H
r
r
5
4
3
2
1
0
ET2
ES
ET1
EX1
ET0
EX0
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
ET0
1
rw
Timer 0 Overflow Interrupt Enable
0B
Timer 0 interrupt is disabled
1B
Timer 0 interrupt is enabled
ET1
3
rw
Timer 1 Overflow Interrupt Enable
Note: When Timer 0 operates in Mode 3, this interrupt indicates
an overflow in the Timer 0 register, TH0.
0B
1B
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Timer 1 interrupt is disabled
Timer 1 interrupt is enabled
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Timer 0 and Timer 1
14.8
Interfaces of the Timer 0 and Timer 1 Modules
An overview of the Timer 0 and Timer 1 module signal interface is shown in Figure 68. The System Control Unit
(SCU) edge detection circuitry for the external interrupts, EXINT0 and EXINT1, can be bypassed to allow a direct
feed-through to NINT0 and NINT1.
The timer and external interrupt inputs can be selected from several different sources. This selection is performed
by the SCU via the corresponding input select bits in SFRs MODPISEL and MODPISEL1.
EXINT0 _0
P 0.5/EXINT0_ 0
EXINT0_ 1
P 1.2/EXINT0_ 1
EXINT0 _2
P2 .3/EXINT0_2
NINT0
EXINT0 _3
P0.1/EXINT0_3
NINT1
EXINT1_ 0
P 2.1/EXINT1_ 0
EXINT1_1
P 1.3/EXINT1_ 1
EXINT1_ 2
P0 .3/EXINT1_2
Port
EXINT1_ 3 Control
P0.2/EXINT1_3
M8051 E -Warp
Timer 0
and
Timer 1
Module
(Kernel )
T0
System
Control
Unit
T0_0
T1
T0 _1
T0_2
T1_0
T1_1
T1_2
Figure 68
P 0.3/T0_ 0
P 1.0/T0_ 1
P2 .4/T0_2
P0 .5/T1_0
P1.1/T1_1
P2.5/T1_2
Timers 0 and 1 Modules Signal Interface
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Timer2 and Timer21
15
Timer2 and Timer21
This chapter describes the Timer2 and Timer21. Each timer is a 16-bit timer which additionally can function as a
counter. Each Timer 2 module also provides a single channel 16-bit capture.
Note: “Timer 2” is generally referred in the following description which is applicable to each of the Timer 2 and
Timer 21.
15.1
Functional Description
Timer 2 is a 16-bit general purpose timer which is functionally compatible with the Timer 2 from the C501 product
family. Timer 2 can function as a timer or counter in each of its modes. As a timer, it counts with an input clock of
fPCLK/12 (if prescaler is disabled). As a counter, Timer 2 counts 1-to-0 transitions on pin T2. In the counter mode,
the maximum resolution for the count is fPCLK/24 (if prescaler is disabled).
Features
•
•
16-bit auto-reload mode
– selectable up or down counting
One channel 16-bit capture mode
Timer 2 can be started by setting bit TR2 by software. If bit T2RHEN is set, Timer 2 can be started by hardware.
Bit T2REGS defines the event on pin T2EX: falling edge or rising edge, that can set the run bit TR2 by hardware.
Timer 2 can only be stopped by resetting bit TR2 by software.
15.1.1
Auto-Reload Mode
The auto-reload mode is selected when the bit CP_RL2 in register T2CON is zero. In the auto-reload mode, Timer
2 counts to an overflow value and then reloads its register contents with a 16-bit start value for a fresh counting
sequence. The overflow condition is indicated by setting bit TF2 in the T2CON register. This will then generate an
interrupt request to the core. The overflow flag TF2 must be cleared by software.
The auto-reload mode is further classified into two categories depending upon the DCEN control bit.
15.1.1.1
Up/Down Count Disabled
If DCEN = 0, the up-down count selection is disabled. The timer, therefore, functions as a pure up counter/timer
only. The operational block diagram is shown in Figure 69.
In this mode, if EXEN2 = 0, the timer starts to count up to a maximum of FFFFH, once TR2 is set. Upon overflow,
bit TF2 is set and the timer register is reloaded with the 16-bit reload value of the RC2 register. This reload value
is chosen by software, prior to the occurrence of an overflow condition. A fresh count sequence is started and the
timer counts up from this reload value as in the previous count sequence.
If EXEN2 = 1, the timer counts up to a maximum of FFFFH once TR2 is set. A 16-bit reload of the timer registers
from register RC2 is triggered either by an overflow condition or by a negative/positive edge (chosen by
T2MOD.EDGESEL) at input pin T2EX. If an overflow caused the reload, the overflow flag TF2 is set. If a
negative/positive transition at pin T2EX caused the reload, bit EXF2 is set. In either case, an interrupt is generated
to the core and the timer proceeds to its next count sequence. The EXF2 flag, similar to the TF2, must be cleared
by software.
If bit T2RHEN is set, Timer 2 is started by first falling/rising edge at pin T2EX, which is defined by bit T2REGS. If
bit EXEN2 is set, bit EXF2 is also set at the same point when Timer 2 is started with the same falling/rising edge
at pin T2EX, which is defined by bit EDGESEL. The reload will happen with the following negative/positive
transitions at pin T2EX, which is defined by bit EDGESEL.
Note: In counter mode, if the reload via T2EX and the count clock T2 are detected simultaneously, the reload takes
precedence over the count. The counter increments its value with the following T2 count clock.
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PREN
fPCLK
/12
0
T2PRE
1
C/T2=0
THL2
C/T2=1
TR2
T2
Overflow
OR
RC2
TF2
Timer 2
OR
Interrupt
EXF2
EXEN2
T2EX
Figure 69
Auto-Reload Mode (DCEN = 0)
15.1.1.2
Up/Down Count Enabled
If DCEN = 1, the up-down count selection is enabled. The direction of count is determined by the level at input pin
T2EX. The operational block diagram is shown in Figure 70.
A logic 1 at pin T2EX sets the Timer 2 to up counting mode. The timer, therefore, counts up to a maximum of
FFFFH. Upon overflow, bit TF2 is set and the timer register is reloaded with a 16-bit reload value of the RC2
register. A fresh count sequence is started and the timer counts up from this reload value as in the previous count
sequence. This reload value is chosen by software, prior to the occurrence of an overflow condition.
A logic 0 at pin T2EX sets the Timer 2 to down counting mode. The timer counts down and underflows when the
THL2 value reaches the value stored at register RC2. The underflow condition sets the TF2 flag and causes FFFFH
to be reloaded into the THL2 register. A fresh down counting sequence is started and the timer counts down as in
the previous counting sequence.
If bit T2RHEN is set, Timer 2 can only be started either by rising edge (T2REGS = 1) at pin T2EX and then does
the up counting, or can be started by falling edge (T2REGS = 0) at pin T2EX and then does the down counting.
In this mode, bit EXF2 toggles whenever an overflow or an underflow condition is detected. This flag, however,
does not generate an interrupt request.
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Timer2 and Timer21
FFFFH
(Down count reload)
EXF2
PREN
Underflow
fPCLK
/12
0
T2PRE
1
Timer 2
C/T2=0
THL2
C/T2=1
OR
TF2
Interrupt
TR2
T2
16-bit
Comparator
Overflow
RC2
T2EX
Figure 70
Auto-Reload Mode (DCEN = 1)
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Timer2 and Timer21
15.1.2
Capture Mode
In order to enter the 16-bit capture mode, bits CP_RL2 and EXEN2 in register T2CON must be set. In this mode,
the down count function must remain disabled. The timer functions as a 16-bit timer or counter and always counts
up to FFFFH and overflows. Upon an overflow condition, bit TF2 is set and the timer reloads its registers with
0000H. The setting of TF2 generates an interrupt request to the core.
Additionally, with a falling/rising edge on pin T2EX (chosen by T2MOD.EDGESEL) the contents of the timer
register (THL2) are captured into the RC2 register. The external input is sampled in every PCLK cycle. When a
sampled input shows a low (high) level in one PCLK cycle and a high (low) in the next PCLK cycle, a transition is
recognized. If the capture signal is detected while the counter is being incremented, the counter is first
incremented before the capture operation is performed. This ensures that the latest value of the timer register is
always captured.
If bit T2RHEN is set, Timer 2 is started by the first falling/rising edge at pin T2EX, which is defined by bit T2REGS.
If bit EXEN2 is set, bit EXF2 is also set at the same point when Timer2 is started with the same falling/rising edge
at pin T2EX, which is defined by bit EDGESEL. The capture will happen with the following negative/positive
transitions at pin T2EX, which is defined by bit EDGESEL.
When the capture operation is completed, bit EXF2 is set and can be used to generate an interrupt request. Figure
71 describes the capture function of Timer 2.
PREN
fPCLK
/12
0
T2PRE
1
C/T2=0
THL2
C/T2=1
TR2
T2
Overflow
RC2
TF 2
Timer 2
OR
Interrupt
EXF2
EXEN2
T2EX
Figure 71
Capture Mode
15.1.3
Count Clock
The count clock for the auto-reload mode is chosen by the bit C_T2 in register T2CON. If C_T2 = 0, a count clock
of fPCLK/12 (if prescaler is disabled) is used for the count operation.
If C_T2 = 1, Timer 2 behaves as a counter that counts 1-to-0 transitions of input pin T2. The counter samples pin
T2 over 2 PCLK cycles. If a 1 was detected during the first clock and a 0 was detected in the following clock, then
the counter increments by one. Therefore, the input levels should be stable for at least 1 clock.
If bit T2RHEN is set, Timer 2 can be started by the falling/rising edge on pin T2EX, which is defined by bit T2REGS.
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Note: If pin T2 is not connected, counting clock function on pin T2 cannot be used.
15.1.4
Interrupt Generation
When an interrupt event happened, the corresponding interrupt flag bit EXF2/TF2 is set. If enabled by the related
interrupt enable bit EXF2EN/TF2EN in register T2CON1, an interrupt for the interrupt event EXF2/TF2 will be
generated.
The interrupt output signal is a pulse, which is active high for 2 clock periods.
Note: When the timer/counter is stopped and while the module remains enabled, it is possible for an external event
at T2EX to generate an interrupt. For this to occur, bit EXEN2 in SFR T2CON must be set. In this case, a
dummy reload or capture happens depending on the CP_RL2 bit selection. The resulting interrupt could
therefore be used in the product as an external falling/rising edge triggered interrupt.
15.1.5
Timer 2 Registers
All Timer 2 and Timer 21 register names described in the following sections will be referenced in other chapters
with the module name prefix “T2_” and “T21_”, respectively.
15.1.5.1
Mode Register
The T2MOD is used to configure Timer 2 for various modes of operation.
T2MOD
Timer 2 Mode Register
Reset Value: 00H
7
6
5
4
3
2
1
0
T2REGS
T2RHEN
EDGESEL
PREN
T2PRE
DCEN
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
DCEN
0
rw
Up/Down Counter Enable
0B
Up/Down Counter function is disabled
1B
Up/Down Counter function is enabled and controlled by pin
T2EX (Up = 1, Down = 0)
T2PRE
3:1
rw
Timer 2 Prescaler Bit
Selects the input clock for Timer 2 which is derived from the
peripheral clock.
000B fT2 = fPCLK
001B fT2 = fPCLK / 2
010B fT2 = fPCLK / 4
011B fT2 = fPCLK / 8
100B fT2 = fPCLK / 16
101B fT2 = fPCLK / 32
110B fT2 = fPCLK / 64
111B fT2 = fPCLK / 128
PREN
4
rw
Prescaler Enable
0B
Prescaler is disabled and the 2 or 12 divider takes effect.
1B
Prescaler is enabled (see T2PRE bit) and the 2 or 12 divider is
bypassed.
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Field
Bits
Type
Description
EDGESEL
5
rw
Edge Select in Capture Mode/Reload Mode
0B
The falling edge at Pin T2EX is selected.
1B
The rising edge at Pin T2EX is selected.
T2RHEN
6
rw
Timer 2 External Start Enable
0B
Timer 2 External Start is disabled.
1B
Timer 2 External Start is enabled.
T2REGS
7
rw
Edge Select for Timer 2 External Start
0B
The falling edge at Pin T2EX is selected.
1B
The rising edge at Pin T2EX is selected.
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Timer2 and Timer21
15.1.5.2
Control Register
Control register is used to control the operating modes and interrupt of Timer 2.
T2CON
Timer 2 Control Register
7
6
TF2
EXF2
rwh
rwh
Reset Value: 00H
5
4
r
r
3
2
1
0
EXEN2
TR2
C_T2
CP_RL2
rw
rwh
rw
rw
Field
Bits
Type
Description
CP_RL2
0
rw
Capture/Reload Select
0B
Reload upon overflow or upon negative/positive transition at
pin T2EX (when EXEN2 = 1).
1B
Capture Timer 2 data register contents on the negative/positive
transition at pin T2EX, provided EXEN2 = 1.The negative or
positive transition at Pin T2EX is selected by bit EDGESEL.
C_T2
1
rw
Timer or Counter Select
0B
Timer function selected.
1B
Count upon negative edge at pin T2.
TR2
2
rwh
Timer 2 Start/Stop Control
0B
Stop Timer 2.
1B
Start Timer 2.
EXEN2
3
rw
Timer 2 External Enable Control
0B
External events are disabled.
1B
External events are enabled in Capture/Reload Mode.
EXF2
6
rwh
Timer 2 External Flag
In Capture/Reload Mode, this bit is set by hardware when a
negative/positive transition occurs at pin T2EX, if bit EXEN2 = 1.
This bit must be cleared by software.
Note: When bit DCEN = 1 in auto-reload mode, no interrupt request
to the core is generated.
TF2
7
rwh
Timer 2 Overflow/Underflow Flag
Set by a Timer 2 overflow/underflow. Must be cleared by software.
T2CON1
Timer 2 Control Register 1
7
6
Reset Value: 03H
5
4
3
2
1
0
0
TF2EN
EXF2EN
r
rw
rw
Field
Bits
Type
Description
EXF2EN
0
rw
External Interrupt Enable
0B
External interrupt is disabled.
1B
External interrupt is enabled.
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Timer2 and Timer21
Field
Bits
Type
Description
TF2EN
1
rw
Overflow/Underflow Interrupt Enable
0B
Overflow/underflow interrupt is disabled.
1B
Overflow/underflow interrupt is enabled.
0
7:2
r
Reserved
Returns 0 if read; should be written with 0.
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Timer2 and Timer21
15.1.5.3
Timer 2 Reload/Capture Register
The RC2 register is used for a 16-bit reload of the timer count upon an overflow or a capture of the current timer
count depending on the mode selected.
RC2L
Timer 2 Reload/Capture Register, Low Byte
7
6
5
Reset Value: 00H
4
3
2
1
0
RC2[7:0]
rwh
Field
Bits
Type
Description
RC2
[7:0] of
RC2L
rwh
Reload/Capture Value
These contents are loaded into the timer register upon an overflow
condition, if CP_RL2 = 0.
If CP_RL2 = 1, this register is loaded with the current timer count
upon a negative/positive transition at pin T2EX when EXEN2 = 1.
RC2H
Timer 2 Reload/Capture Register, High Byte
7
6
5
Reset Value: 00H
4
3
2
1
0
RC2[15:8]
rwh
Field
Bits
Type
Description
RC2
[7:0] of
RC2H
rwh
Reload/Capture Value
These contents are loaded into the timer register upon an overflow
condition, if CP_RL2 = 0.
If CP_RL2 = 1, this register is loaded with the current timer count
upon a negative/positive transition at pin T2EX when EXEN2 = 1.
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Timer2 and Timer21
15.1.5.4
Timer 2 Count Register
The THL2 register holds the current 16-bit value of the Timer 2 count.
T2L
Timer 2, Low Byte
7
Reset Value: 00H
6
5
4
3
2
1
0
THL2[7:0]
rwh
Field
Bits
Type
THL2[7:0]
[7:0] of T2L rwh
Description
Timer 2 Value
These bits indicate the current timer value.
T2H
Timer 2, High Byte
7
Reset Value: 00H
6
5
4
3
2
1
0
THL2[15:8]
rwh
Field
Bits
Type
Description
THL2[15:8]
[7:0] of
T2H
rwh
Timer 2 Value
These bits indicate the current timer value.
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Timer2 and Timer21
15.2
Timer2 and Timer21 Implementation Details
This section describes:
•
•
the TLE983x module related interfaces such as port connections and interrupt control
all TLE983x module related registers with their addresses
15.2.1
Interfaces of the Timer2 and Timer21
Overviews of the Timer2 and Timer21 kernel I/O interfaces and interrupt signals are shown in Figure 72 and
Figure 73.
The Bus Peripheral Interface (BPI) enables the Timer2 and Timer21 kernel to be attached to the 8-bit Bus. The
BPI consists of a clock control logic which gates the clock input to the kernel, and an address decoder for SFRs
in the Timer2 and Timer21 kernel.
Timer2 and Timer21 can be suspended when OCDS enters Monitor Mode and has the Debug Suspend signal
activated. The bits T2SUSP and T21SUSP (in SCU SFR MODSUSP) control the suspension of the timer. Refer
to SCU chapter and OCDS chapter.
The interrupt request of the Timer2 and Timer21 is not connected directly to the CPU’s Interrupt Controller, but via
the System Control Unit (SCU). The General Purpose IO (GPIO) Port provides the interface for the Timer2 and
Timer21 to the external world.
The external trigger and counter inputs of the two Timer 2 modules can be selected from several different sources.
This selection is performed by the SCU via the corresponding input control and select bits in SFR MODPISEL1
and MODPISEL2.
In the TLE983x Timer2 and Timer21 allow additional to trigger ADC conversions through the t2(1)_trigger signals.
These trigger signals are generated as a one PCLK cycle pulse whenever a timer overflow event occurs while the
timer is working in timer mode (C_T2 = 0).
t2_adc_ trigger
t2_ext_trigger
T2EX _0
Interrupt
Controller
T2 _IRQ
T2 EX
T2_ SUSPEND
Cloc
k
Control
f T2
Timer 2
Module
(Kernel )
Address
Decoder
SCU
Module
(kernel )
T2
EXF 2
T2EX _1
P0 .1/T2EX _1
Port
Control
P0 .0/T2
P0 .2 /EXF 2
BPI
Figure 72
Timer 2 Module I/O Interface
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Timer2 and Timer21
t21 _adc_trigger
t21_ext_trigger
T21_0
Interrupt
Controller
T21_ IRQ
P0.1/T 21_0
T21_1
P1.2/T 21_1
T21_2
T2
T21_ SUSPEND
Clock
Control
fT 21
Timer 21
Module
( Kernel)
SCU )
Module
( kernel
T21EX_0
P0.2/T21EX_0
T21EX_1
T21EX_2
T2EX
P0.4/T 21_2
T21EX_3
P1.4/T21EX_1
Port
Control
P0.5/T21EX_2
P1.1/T21EX_3
P0.0/EXF 21_0
Address
Decoder
EXF2
P1.3/EXF 21_1
P0.3/ EXF21_2
P1.0/ EXF21_3
BPI
Figure 73
Timer 21 Module I/O Interface
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Timer2 and Timer21
15.2.2
Register Mapping
15.2.2.1
Timer2 and Timer21 Register Mapping
Table 52 describes the mapping of the Timer2 and Timer21 registers (non-mapped).
Table 52
SFR Address List for Timer2 and Timer21
Address
Page 0
Page 8
C0H
T2_T2CON
T21_T2CON
C1H
T2_T2MOD
T21_T2MOD
C2H
T2_RC2L
T21_RC2L
C3H
T2_RC2H
T21_RC2H
C4H
T2_T2L
T21_T2L
C5H
T2_T2H
T21_T2H
C6H
T2_T2CON1
T21_T2CON1
SFR PERIPHERAL_PAGE, at address C7H, contains the page value and the page control information.
PERIPHERAL_PAGE
Page Register for Peripherals
7
6
Reset Value: 00H
5
4
3
2
1
OP
STNR
PAGE
w
w
rwh
0
Field
Bits
Type
Description
PAGE
3:0
rwh
Page Bits
When written, the value indicates the new page address.
When read, the value indicates the currently active page = addr
[y:x+1]
STNR
5:4
w
Storage Number
This number indicates which storage bit field is the target of the
operation defined by bit OP.
If OP = 10B,
the contents of PAGE are saved in STx before being overwritten with
the new value.
If OP = 11B,
the contents of PAGE are overwritten by the contents of STx. The
value written to the bit positions of PAGE is ignored.
00B ST0 is selected.
01B ST1 is selected.
10B ST2 is selected.
11B ST3 is selected.
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Timer2 and Timer21
Field
Bits
Type
Description
OP
7:6
w
Operation
0XB Manual page mode. The value of STNR is ignored and PAGE
is directly written.
10B New page programming with automatic page saving. The
value written to the bit positions of PAGE is stored. In parallel,
the former contents of PAGE are saved in the storage bit field
STx indicated by STNR.
11B Automatic restore page action. The value written to the bit
positions PAGE is ignored and instead, PAGE is overwritten by
the contents of the storage bit field STx indicated by STNR.
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Timer 3
16
Timer 3
Features
•
•
•
•
•
•
16-bit-upcounting Timer/Counter
Counting frequency up to fsys
Selectable clock prescaler
7 modes of operation
Interrupt upon overflow
Interrupt on compare
16.1
Overview
The Timer 3 is designed to count cycles on fPCLK2 or fLP_CLK. Various modes of operation are suitable for numerous
tasks, like:
•
•
•
•
simple time measurement between two events
triggering of the measuring unit upon PWM/CCU6 unit
measuring of the LIN SyncField - Baudrate
detection precise measurement of the 100kHz LP_CLK2
16.2
Register Overview
The Timer 3 provides nine XSFR registers to control its operation. An overview about the implemented registers
is provided by the table below. A detailed register description is given in the Chapter 16.6.
Table 53
Register Overview
Offset Address
Register Short Name
Register Long Name
64H
T3_TRIGG_CTRL
Timer 3 Trigger Control Register
A9H
SUPPLEMENT_CTRL
Interrupt Control Register for Timer 3
CAH
T3_CLK_CTRL
Timer 3 Clock Control Register
CBH
TIMER3_LOW
Timer 3 Low Byte
CCH
TIMER3_HIGH
Timer 3 High Byte
CDH
TIMER3_CTRL
Timer 3 Control Register
CEH
TIMER3_MODE_CONF
Timer 3 Mode Configuration Register
FAH
TIMER3_CMP_LO
Timer 3 Compare Value Low Byte
FBH
TIMER3_CMP_HI
Timer 3 Compare Value High Byte
16.3
Description
Seven modes of operation are provided to fulfill various tasks using this timer. In every mode the clocking source
can be selected between PCLK2 and LP_CLK. A prescaler provides in addtion capability to divide the selected
clock source by 2, 4 or 8. The clocking source and the prescaler can be set in the register T3_CLK_CTRL. The
timer counts upwards, starting with the value in the timer count registers, until the maximum count value which
depends on the selected mode of operation. The Timer 3 provides two individual interrupts upon counter overflow,
one for the counter register low byte and one for the counter register high byte. The run control of the Timer3 is
controlled by software by setting the bits TR3L/TR3H in the register TIMER3_CTRL. Some modes of operation
are providing in addition to the software run control a run control triggered by various hardware sources coming
from other modules within the device. Furthermore the Timer 3 provides a 16-bit compare register, which is split
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Timer 3
up into TIMER3_CMP_LO and TIMER3_CMP_HI registers. The compare register can be used by some operation
modes to issue an overflow interrupt upon matching of the timer counter register to the compare register. The
entire Timer 3 module will be enabled by setting bit T3_CLK_PD_N in the register T3_CLK_CTRL.
16.4
Interrupts
The Timer 3 issues an interrupt upon overflow of the timer counter register low, as well as counter register high if
enabled. One interrupt vector, which is shared among other resources of the device, is used to hook an interrupt
service routine to the Timer 3. The Timer 3 provides individual interrupt enable flags as well as individual flags to
indicate a timer overflow event. The timer overflow flags need to be cleared by software. The register
SUPPLEMENT_CTRL holds the interrupt enable bits for the Timer 3 for an overflow of the timer count registers,
separated for timer counter register low and timer counter register high. The register TIMER3_CTRL holds the
status bits for a timer overflow event, separated for timer counter register low and timer counter register high.
Table 54
Interrupt Routing
Interrupt Vector
Vector Name
Description
09H
XINTR9INT
Shared Interrupt
16.5
Modes of Operation
The Timer 3 provides seven modes of operation, which are described in the following chapters. The seven modes
of operations are divided into four main modes. Some of the four main modes are further separated into submodes. The bit field T3M in the register TIMER3_MODE_CONF selects one out of the four main modes. The bit
field T3_SUBM in the register TIMER3_MODE_CONF selects a sub-mode of the selected main mode, if
applicable. The following table provides an overview of the timer modes together with the reasonable configuration
options in Table 56.
Table 55
Timer 3, 1 Modes of Operation
Mode
SubMode
Operation
0
no SubMode
exists
13-bit Timer
The timer is a 13-bit counter. This mode is included solely for compatibility with Intel 8048
devices.
1
a
16-bit Timer
The timer registers, TLx and THx, are concatenated to form a 16-bit counter.
1
b
16-bit Timer
The timer registers, TLx and THx, are concatenated to form a 16-bit counter, which is
triggered by the PWM Unit or CCU6 unit to enable a single shot measurement on a preset
channel with the measurement unit.
1
c
16-bit Timer
The timer registers, TLx and THx, are concatenated to form a 16-bit counter, which is
triggered by the LIN input to measure the LIN baudrate.
2
no SubMode
exists
8-bit Timer with Auto-reload
The timer register TLx is reloaded with a user-defined 8-bit value in THx upon overflow.
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Timer 3
Table 55
Timer 3, 1 Modes of Operation (cont’d)
Mode
SubMode
Operation
3
a
Timer 3 Operates as Two 8-bit Timers
The timer registers, TL3 and TH3, operate as two separate 8-bit counters.
3
b
Timer 3 Operates as Two 8-bit Timers
The timer registers, TL3 and TH3, operate as two separate 8-bit counters. In this mode the
100 kHz Low Power Clock can be measured. TL3 acts as an edge counter for the clock
edges and TH3 as an counter which counts the time between the edges.
Table 56
Timer 3, 1 List of Options
Sub-Mode
0
1a
1b
1c
2
3a
3b
Mode
Config
T3M
0
1
1
1
2
3
3
T3_SUBM
0
0
1
3
0
0
2
Run
Control
TR3L
1
1
1
1
1
1
1
TR3H
n/a
n/a
n/a
1
n/a
1
1
CCU6_Ch1
n/a
n/a
1
1
n/a
n/a
n/a
CCU6_Ch2
n/a
n/a
1
1
n/a
n/a
n/a
PWM1
n/a
n/a
1
1
n/a
n/a
n/a
PWM2
n/a
n/a
1
1
n/a
n/a
n/a
LP_CLK2
n/a
n/a
n/a
n/a
n/a
n/a
1
LIN
n/a
n/a
1
1
n/a
n/a
n/a
Trigger
Source
Interrupt
Status
T3L_OVF_STS 1
1
1
1
1
1
1
T3H_OVF_STS 1
1
1
1
0
1
1
Compare
Compare
0
1
0
1
0
0
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Timer 3
16.5.1
Mode 0
Mode 0 implements a 13-bit timer/counter compatible to the 8048 microcontroller. TIMER3_HIGH holds the upper
8 bits of the 13-bit timer value. TIMER3_LOW holds the lower 5 bits of the 13-bit timer value. The bits
TIMER3_LOW [7:5] are not defined and should not be used in this mode of operation. An overflow will be
generated by the transition of the timer value from 0x1FFF to 0x0000.
T3_CLK_DIV
[1,2,4,8]
0
pclk2
TL3
(5 Bits)
1/2/4/8
lp_clk
TH3
(8 Bits)
T3H_OVF_STS
Interrupt
1
T3_CLK_SEL
SCU_PM
Control
TR3L
Timer3_Mode0
Figure 74
Timer 3, Mode 0: 13-Bit Timer
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Timer 3
16.5.2
Mode 1a
Mode 1a implements a 16-bit timer/counter. TIMER3_HIGH holds the upper 8 bits whileTIMER3_LOW holds the
lower 8 bits of the 16-bit timer value. An overflow will be generated by the transition of the timer value from 0xFFFF
to 0x0000.
T3_CLK_DIV
[1,2,4,8]
pclk2
0
TL3
(8 Bits)
1/2/4/8
lp_clk
T3_CLK_SEL
1
SCU_PM
TH3
(8 Bits)
T3H_O
VF_STS
Interrupt
located in
SCU_PM
Control
TR3L
Timer3_Mode1a
Figure 75
Timer 3, Mode 1a: 16-Bit Timer
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Timer 3
16.5.3
Mode 1b
Mode 1b is intended to delay certain actions based on a PWM trigger source. The timer operates as a 16-bit timer.
The timer starts counting upwards upon trigger by the selected trigger source. The trigger source has to be
selected in the register T3_TRIGG_CTRL, bit field T3_TRIGG_INP_SEL. As trigger sources the two PWM
generators or the channels 1 or 2 of the CCU6 module are available. To enable a repetitive operation a reset of
the timer counter can be defined on the rising edge, falling edge or on both edges of the selected trigger source.
The desired selection can be taken in the register T3_TRIGG_CTRL, bit field T3_RES_CONF. An interrupt will be
issued upon overflow, or if the compare value is reached. The compare value may be defined in the registers
TIMER3_CMP_LO and TIMER3_CMP_HI. In this mode the preload of the timer count registers TIMER3_HIGH
and TIMER3_LOW has no effect, the counting always starts with 0x0000 until the set compare value.
This mode can be used to trigger the measurement unit with a desired delay based on a PWM edge to perform
measurements synchronous to the selected PWM source. The working principle of this mode is shown in
Figure 76.
PWM
TIMER3
MU-DPP
clearing edge can be
configured to rising or
falling
pwm_1_o
HSS
timer3
00h
01h
02h
03h
xxh
ccu6_int – single shot
ccu6_int – continous
measurement
Figure 76
Timer 3, Mode 1b: 16-Bit Timer with triggering of PWM Input
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Timer 3
16.5.4
Mode 1c
The Mode 1c can be used to measure the time between a selected number of falling edges of a given trigger
source. Please refer to the options table about what trigger sources are available in this mode. The trigger source
has to be selected in the register T3_TRIGG_CTRL, bit field T3_TRIGG_INP_SEL. The number of falling edges
to be count from the selected trigger source can be chosen by the bit field T3_LIN_SYNCEDGE_CNT in the
register T3_TRIGG_CTRL. The timer operates in 16-bit mode. It starts counting upwards upon the detection of a
falling edge of the selected trigger source. Internally the desired edges of the trigger source get counted. Once the
selected number of edges has passed the timer stops counting. Additionally the bit CNT_RDY in the
TIMER3_CTRL register gets set and an interrupt will be triggered. In addition to that an interrupt might be issued
on an overflow as well. The CNT_RDY flag can be evaluated to determine where the interrupt was issued from.
The Mode 1c can be used to measure the bit time within the SyncField of a LIN message. Mode 1c operation for
Timer 3 is shown in Figure 77.
LIN-SyncField
Measurement
Transfer to TIMER3_LOW/
TIMER3_HIGH
00
01 02
03
04
xx
xx
xx
2
Figure 77
Transfer to TIMER3_LOW/
TIMER3_HIGH
Transfer to TIMER3_LOW/
TIMER3_HIGH
Transfer to TIMER3_LOW/
TIMER3_HIGH
xx
4
6
8
Timer 3, Mode 1c: 16-Bit Timer with triggering of lin_rxd Input
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Timer 3
16.5.5
Mode 2
In Mode 2 the timer operates as an 8-bit-timer with reload. The register TIMER3_LOW is the timer value count
register, while the register TIMER3_HIGH holds the reload value. Upon an overflow of the TIMER3_LOW register
from 0xFF to 0x00 an interrupt gets issued. Simultaneously the TIMER3_LOW register gets load with the value in
the TIMER3_HIGH register. Furthermore the TIMER3_CMP_LO register can be programmed with a compare
value. Once the TIMER3_LOW register hits the compare value an interrupt will be issued and a reload takes place.
In Mode 2 the clock divider T3_CLK_DIV, in the register T3_CLK_CTRL, needs to be programmed to 1 (fsys/2).
The working principle is shown in Figure 78.
T3_CLK_DIV
[1,2,4,8]
pclk2
0
TL3
(8 Bits)
1/2/4/8
lp_clk
T3_CLK_SEL
T3L_OV
F_STS
Interrupt
1
Control
SCU_PM
Reload
TR3L
TH3
(8 Bits)
Timer3_Mode2
Figure 78
Timer 3, Mode 2: 8-Bit Timer with Auto-Reload
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Timer 3
16.5.6
Mode 3a
In Mode 3a, the two Timer 3 registers, TL3 and TH3, function as two separate 8-bit counters. The 8-bit counter,
TL3, uses the Timer 3 control bits TR3 and TF3, while the other 8-bit counter, TH3, is locked into a timer function
(counting machine cycles). Furthermore, TH3 sets the Timer 3 flag bit T3H_OVF_STS, upon overflow and
generates an interrupt if is set. Mode 3a is provided for applications requiring an extra 8-bit timer.
T3_CLK_DIV
[1,2,4,8]
pclk2
0
1/2/4/8
lp_clk
Timer Clock
1
T3_CLK_SEL
SCU_PM
TL3
(8 Bits)
T3L_OV
F_STS
Interrupt
TH3
(8 Bits)
T3H_O
VF_STS
Interrupt
Control
TR3L
Timer3_Mode3
TR3H
Figure 79
Timer 3, Mode 3a: Two 8-Bit Timers
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Timer 3
16.5.7
Mode 3b
The Mode 3b is used to measure the period of the LP_CLK2. The Timer 3 is split up into an 8-bit counter
(TIMER3_LOW) and an 8-bit timer (TIMER3_HIGH). The TIMER3_LOW counts falling edges of the LP_CLK2,
which need to be selected as a trigger source. The register TIMER3_CMP_LO defines how many edges shall be
counted. The TIMER3_HIGH runs with the selected clocking source and starts counting with the next falling edge
on LP_CLK2. Once TIMER3_LOW has counted the desired number of edges of the LP_CLK2, by hitting the
TIMER3_CMP_LO value and interrupt will be issued and TIMER3_HIGH stops.
T3_CLK_DIV
[1,2,4,8]
pclk2
0
1/2/4/8
lp_clk
Timer Clock
1
T3_CLK_SEL
SCU_PM
TL3
(8 Bits)
T3L_OV
F_STS
TH3
(8 Bits)
T3H_O
VF_STS
Interrupt
Control
TR3L
&
0
1
2
3
4
5
lp_clk2
Interrupt
Timer3_Mode3
T3_TRIGG_INP_SEL
TR3H
Figure 80
&
Timer 3, Mode 3b: Two 8-Bit Timers
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Timer 3
16.6
Register Description
A total of seven XSFR Registers control the operation of Timer 3. TL3/TH3 are the low and high timer registers.
TIMER3_CTRL and TIMER3_MODE_CONF are the mode selection register.
Timer 3 XSFRs can be accessed from the standard XSFR address space.
Table 57
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Register Description, Timer 3 Control Register
T3_TRIGG_CTRL
Timer 3 Trigger Control Register
64H
0000 0000B
SUPPLEMENT_CTRL
Interrupt Control Register for Timer 3
A9H
0000 0001B
T3_CLK_CTRL
Timer 3 Clock Control Register
CAH
0000 1110B
TIMER3_LOW
Timer 3 Low Byte
CBH
0000 0000B
TIMER3_HIGH
Timer 3 High Byte
CCH
0000 0000B
TIMER3_CTRL
Timer 3 Control Register
CDH
0000 0001B
TIMER3_MODE_CONF
Timer 3 Mode Configuration Register
CEH
0001 0001B
TIMER3_CMP_LO
Timer 3 Compare Value Low Byte
FAH
0000 0000B
TIMER3_CMP_HI
Timer 3 Compare Value High Byte
FBH
0000 0000B
The registers are addressed bytewise.
16.6.1
Timer 3 Control Register
Timer 3 Trigger Control Register
The register is reset by RESET_TYPE_3.
T3_TRIGG_CTRL
Timer 3 Trigger Control Register
7
6
5
Offset
Reset Value
64H
0000 0000B
4
3
2
0
T3_LIN_SYNCED
GE_CNT
T3_RES_CONF
Res
T3_TRIGG_INP_SEL
rw
rw
r
rw
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Timer 3
Field
Bits
Type
Description
T3_LIN_SYNCEDGE_C 7:6
NT
rw
Timer 3 Trigger Reset Selection for Mode 1c
0H
2 Bit Times Timer should measure 2 Bit Times of Sync
Field (time between two falling edges).
1H
4 Bit Times Timer should measure 4 Bit Times of Sync
Field (time between three falling edges).
2H
6 Bit Times Timer should measure 6 Bit Times of Sync
Field (time between four falling edges).
3H
8 Bit Times Timer should measure 8 Bit Times of Sync
Field (time between five falling edges).
T3_RES_CONF
5:4
rw
Timer 3 Trigger Reset Selection for Mode 1b
0H
No Reset on PWM Edge Counter is not reset while
PWM Module is running.
1H
Reset On Rising Edge Counter is reset on rising edge
input
2H
Reset On Falling Edge Counter is reset on falling edge
input.
3H
Reset on both Edges Counter is reset on both edge
input.
Res
3
r
Reserved
Always read as 0
T3_TRIGG_INP_SEL
2:0
rw
Timer 3 Trigger Input Selection
0H
CCU6-CH1 Capture Compare Unit Channel 1.
1H
CCU6-CH2 Capture Compare Unit Channel 2.
2H
PWM1 PWM Unit 1.
3H
PWM2 PWM Unit 2.
4H
LP_CLK2 100 kHz Low Power Clock.
5H
LIN LIN Baudrate Measurement.
Timer 3 Compare Value Low Byte
The register is reset by RESET_TYPE_3.
TIMER3_CMP_LO
Timer 3 Compare Value Low Byte
Offset
Reset Value
FAH
0000 0000B
7
0
TIMER3_CMP_LO
rw
Field
Bits
Type
Description
TIMER3_CMP_LO
7:0
rw
Timer 3 Compare Value Low Byte
Timer 3 Compare Value High Byte
The register is reset by RESET_TYPE_3.
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Timer 3
TIMER3_CMP_HI
Timer 3 Compare Value High Byte
Offset
Reset Value
FBH
0000 0000B
7
0
TIMER3_CMP_HI
rw
Field
Bits
Type
Description
TIMER3_CMP_HI
7:0
rw
Timer 3 Compare Value High Byte
Timer 3 Low Byte
The register is reset by RESET_TYPE_3.
TIMER3_LOW
Timer 3 Low Byte
Offset
Reset Value
CBH
0000 0000B
7
0
TIMER3_LO
rw
Field
Bits
Type
Description
TIMER3_LO
7:0
rw
Timer 3 Low Register1)
Mode 0TIMER3_LO holds the 5-bit timer value.
Mode 1TIMER3_LO holds the lower 8-bit part of the 16-bit
timer value.
Mode 2TIMER3_LO holds the 8-bit timer value.
Mode 3TIMER3_LO holds the 8-bit timer value; T1 is not
used.
1) M is the selected timer mode which can be changed by writing TIMER3_MODE_CONF
Timer 3 High Byte
The register is reset by RESET_TYPE_3.
TIMER3_HIGH
Timer 3 High Byte
Offset
Reset Value
CCH
0000 0000B
7
0
TIMER3_HI
rw
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Timer 3
Field
Bits
Type
Description
TIMER3_HI
7:0
rw
Timer 3 High Register
Mode 0TIMER3_HI holds the 8-bit timer value.
Mode 1TIMER3_HI holds the higher 8-bit part of the 16-bit
timer value.
Mode 2TIMER3_HI holds the 8-bit reload value.
Mode 3TIMER3_HI holds the 8-bit timer value; TH1 is not
used.
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Timer 3
Timer 3 Control Register
The register is reset by RESET_TYPE_3.
TIMER3_CTRL
Timer 3 Control Register
Offset
Reset Value
CDH
0000 0001B
7
6
5
4
3
2
1
0
T3L_OVF
_STS
TR3L
T3H_OVF
_STS
TR3H
CNT_RDY
T3_RD_R
EQ_CONF
T3_RD_R
EQ
T3_PD_N
rwh
rw
rwh
rw
rw
rw
rwh1
rw
Field
Bits
Type
Description
T3L_OVF_STS
7
rwh
Timer 3 Overflow Flag (Low Byte Timer)
0B
T3L_OVF_STS No overflow occurred.
1B
T3L_OVF_STS Overflow occured. Set by hardware
when Low Byte of Timer 3 overflows.
Cleared by software.
TR3L
6
rw
Timer 3 Run Control (Low Byte Timer)
0B
TR3L Timer is halted
1B
TR3L Timer runs
T3H_OVF_STS
5
rwh
Timer 3 Overflow Flag (High Byte Timer)
0B
T3H_OVF_STS No Overflow occured.
1B
T3H_OVF_STS Overflow occured. Set by hardware
when High Byte of Timer 3 overflows.
Cleared by software.
TR3H
4
rw
Timer 3 Run Control
0B
TR3H Timer is halted
TR3H Timer runs
1B
CNT_RDY
3
rw
Timer 3 Count Ready
0B
CNT_RDY Timer hasn’t finished counting in Mode 1b,
1c, 3b
1B
CNT_RDY Timer has finished counting in Mode 1b, 1c,
3b
T3_RD_REQ_CONF
2
rw
Timer 3 Read Mode
0B
T3_RD_REQ_CONF Timer 3 Read Request can be
triggered by software
1B
T3_RD_REQ_CONF Timer 3 Read Request can be
triggered by hardware
T3_RD_REQ
1
rwh1
Timer 3 Value Read Request
0B
T3_RD_REQ Timer value is not read from Timer 3
1B
T3_RD_REQ Timer value is read from Timer 3
T3_PD_N
0
rw
Timer 3 Power Down
0B
Power Down Timer 3 is in Power Down
1B
no Power Down Timer 3 is not in Power Down
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Timer 3
Timer 3 Mode Configuration Register
The register is reset by RESET_TYPE_3.
TIMER3_MODE_CONF
Offset
Reset Value
CEH
0001 0001B
Timer 3 Mode Configuration Register
7
6
5
2
1
0
T3_SUBM
Res
T3M
rw
r
rw
Field
Bits
Type
Description
T3_SUBM
7:6
rw
Sub-Mode Select Bits
00B No Sub-Mode no Sub-Mode enabled
01B CCU6 Trigger Counting enables the Mode 1b for
Generation of CCU6 Trigger. This mode has only an
Effect with Mode 1 (16 Bit Mode)
10B LP_CLK2 Clock Counting enables the 100 kHz Clock
Measurement. This Mode has only an Effect with Mode
3.
11B LIN Baudrate Counting enables the measurement of
the LIN Baudrate (16 Bit Mode).
Res
5:2
r
Reserved
Always read as 0100B
T3M
1:0
rw
Mode Select Bits
00B T3M 13-bit timer (M8048 compatible mode)
01B T3M 16-bit timer
10B T3M 8-bit auto-reload timer
11B T3M Timer 3 is split into two halves. TL3 is an 8-bit timer
controlled by the standard Timer 3 control bits, and TH3
is the other 8-bit timer controlled by the standard Timer
3 high byte control bits.
Supplement Control Register
The register is reset by RESET_TYPE_3.
SUPPLEMENT_CTRL
Offset
Reset Value
A9H
0000 0001B
Supplement Control Register
7
6
5
4
3
2
T3H_OVF
_IS
T3L_OVF
_IS
T3H_OVF
_STS
T3L_OVF
_STS
T3H_OVF
_IE
T3L_OVF
_IE
Res
rwh
rwh
r
r
rw
rw
r
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Timer 3
Field
Bits
Type
Description
T3H_OVF_IS
7
rwh
Interrupt Status Timer 3 High Byte Overflow
0B
No Overflow write clears status
1B
Overflow trigger status set
T3L_OVF_IS
6
rwh
Interrupt Status Timer 3 Low Byte Overflow
0B
No Overflow write clears status
1B
Overflow trigger status set
T3H_OVF_STS
5
r
Status for Timer 3 High Byte Overflow
0B
No Overflow write clears status
1B
Overflow trigger status set
T3L_OVF_STS
4
r
Status for Timer 3 Low Byte Overflow
0B
No Overflow write clears status
1B
Overflow trigger status set
T3H_OVF_IE
3
rw
Interrupt Enable for Timer 3 High Byte Overflow
0B
Interrupt Disabled Interrupt for Timer 3 High Byte
Overflow
1B
Interrupt Enabled Interrupt for Timer 3 High Byte
Overflow
T3L_OVF_IE
2
rw
Interrupt Enable for Timer 3 Low Byte Overflow
0B
Interrupt Disabled Interrupt for Timer 3 Low Byte
Overflow
1B
Interrupt Enabled Interrupt for Timer 3 Low Byte
Overflow
Res
1:0
r
Reserved
Always read as 01B
Timer 3 Clock Control Register
The register is reset by RESET_TYPE_4.
T3_CLK_CTRL
Timer 3 Clock Control Register
7
Offset
Reset Value
CAH
0000 1110B
4
3
2
0
Res
T3_CLK_DIV
T3_CLK_
SEL
T3_CLK_
PD_N
r
rw
rw
rw
Field
Bits
Type
Description
Res
7:4
r
Reserved
Always read as 0
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Timer 3
Field
Bits
Type
Description
T3_CLK_DIV
3:2
rw
Timer 3 Master Clock Divider
Clock is not divided
0H
1H
Clock divided by 2
2H
Clock divided by 4
3H
Clock divided by 8
T3_CLK_SEL
1
rw
Timer 3 Master Clock Selection
0H
PCLK2 PCU Peripheral Clock is selected as Master
Clock.
1H
LP_CLK Low Power Clock is selected as Master
Clock.
T3_CLK_PD_N
0
rw
Power Down for Timer 3
0H
DISABLE Timer 3 is off
1H
ENABLE Timer 3 is on
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Capture/Compare Unit 6 (CCU6)
17
Capture/Compare Unit 6 (CCU6)
The CCU6 is a high-resolution 16-bit capture and compare unit with application specific modes, mainly for AC drive
control. Special operating modes support the control of Brushless DC-motors using Hall sensors or Back-EMF
detection. Furthermore, block commutation and control mechanisms for multi-phase machines are supported.
It also supports inputs to start several timers synchronously, an important feature in devices with several CCU6
modules.
This chapter is structured as follows:
•
•
•
Functional description of the CCU6 kernel (see Section 17.1)
– Introduction (see Section 17.1)
– Operating T12 (see Section 17.2)
– Operating T13 (see Section 17.3)
– Trap handling (see Section 17.4)
– Multi-Channel mode (see Section 17.5)
– Hall sensor mode (see Section 17.6)
– Interrupt handling (see Section 17.7)
– General module operation (see Section 17.8)
CCU6 kernel registers description (see Section 17.9)
TLE983x implementation specific details (see Section 17.10)
17.1
Introduction
The CCU6 unit is made up of a Timer T12 Block with three capture/compare channels and a Timer T13 Block with
one compare channel. The T12 channels can independently generate PWM signals or accept capture triggers, or
they can jointly generate control signal patterns to drive AC-motors or inverters.
A rich set of status bits, synchronized updating of parameter values via shadow registers, and flexible generation
of interrupt request signals provide means for efficient software-control.
Note: The capture/compare module itself is named CCU6 (capture/compare unit 6). A capture/compare channel
inside this module is named CC6x.
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17.1.1
Feature Set Overview
This section gives an overview over the different building blocks and their main features.
Timer 12 Block Features
•
•
•
•
•
•
•
•
•
•
•
Three capture/compare channels, each channel can be used either as capture or as compare channel
Generation of a three-phase PWM supported (six outputs, individual signals for High Side and low-side
switches)
16-bit resolution, maximum count frequency = peripheral clock
Dead-time control for each channel to avoid short-circuits in the power stage
Concurrent update of T12 registers
Center-aligned and edge-aligned PWM can be generated
Single-shot mode supported
Start can be controlled by external events
Capability of counting external events
Multiple interrupt request sources
Hysteresis-like control mode
Timer 13 Block Features
•
•
•
•
•
•
•
•
One independent compare channel with one output
16-bit resolution, maximum count frequency = peripheral clock
Concurrent update of T13 registers
Can be synchronized to T12
Interrupt generation at period-match and compare-match
Single-shot mode supported
Start can be controlled by external events
Capability of counting external events
Additional Specific Functions
•
•
•
•
•
•
•
•
Block commutation for Brushless DC-drives implemented
Position detection via Hall-sensor pattern
Noise filter supported for position input signals
Automatic rotational speed measurement and commutation control for block commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC-drives
Output levels can be selected and adapted to the power stage
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17.1.2
Block Diagram
The Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined
(e.g. a channel works in compare mode, whereas another channel works in capture mode). The Timer T13 can
work in compare mode only. The multi-channel control unit generates output patterns which can be modulated by
T12 and/or T13. The modulation sources can be selected and combined for the signal modulation.
CCU6 Module Kernel
Compare
T13
CC63
Compare
Interrupt
Control
1
SR[3:0]
3
2
2
2
Trap Input
Start
fCC 6
Trap
Control
Output Select
1
Multichannel
Control
Hall Input
CC62
DeadTime
Control
Output Select
1
Compare
CC61
Compare
Clock
Control
1
Compare
T13SUSP
T12
CC60
Capture
Debug T12 SUSP
Suspend
3
1
CTRAP
CCPOS2
CCPOS1
CCPOS0
CC62
COUT62
CC61
COUT61
CC60
COUT60
COUT63
T13HR
T12HR
Input / Output Control
Port Control
CCU6_MCB05506+
Figure 81
CCU6 Block Diagram
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17.2
Operating Timer T12
The timer T12 block is the main unit to generate the 3-phase PWM signals. A 16-bit counter is connected to 3
channel registers via comparators, which generate a signal when the counter contents match one of the channel
register contents. A variety of control functions facilitate the adaptation of the T12 structure to different application
needs.
Besides the 3-phase PWM generation, the T12 block offers options for individual compare and capture functions,
as well as dead-time control and hysteresis-like compare mode.
This section provides information about:
•
•
•
•
•
•
•
T12 overview (see Section 17.2.1)
Counting scheme (see Section 17.2.2)
Compare modes (see Section 17.2.3)
Compare mode output path (see Section 17.2.4)
Capture modes (see Section 17.2.5)
Shadow transfer (see Section 17.2.6)
T12 operating mode selection (see Section 17.2.7)
State Bits
Timer T12
Logic
Capture/Compare
Channel CC60
CC60ST
Capture/Compare
Channel CC61
CC61ST
Capture/Compare
Channel CC62
CC62ST
To
Dead-Time
Control
and
Output
Modulation
Input and Control/Status Logic
T12HR
Figure 82
CC6xIN
CCPOSx
CCU6_MCA05507
Overview Diagram of the Timer T12 Block
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17.2.1
T12 Overview
Figure 83 shows a detailed block diagram of Timer T12. The functions of the timer T12 block are controlled by
bits in registers TCTR0, TCTR2, and PISEL0.
Timer T12 receives its input clock (fT12) from the module clock fCC6 via a programmable prescaler and an optional
1/256 divider or from an input signal T12HR. These options are controlled via bit fields T12CLK and T12PRE (see
Table 58). T12 can count up or down, depending on the selected operation mode. A direction flag, CDIR, indicates
the current counting direction.
T12RSEL
T12RS
T12RR
T12R
CDIR
edge
detection
ISCNT12
T12STD
T12HR
STE12
edge
detection
Clock
Selection
T12CNT
fCC6
CTM
T12STR
n
T12CLK
fT12
T12
Control
& Status
Counter Register
T12
256
T12RES
= 0000 H
T12_ZM
= 0001 H
T12PRE
Read from
T12PR
T12SSC
T12_OM
Comp.
=?
T12_PM
Period Register
T12_ST
Write to
T12PR
Figure 83
Period Shadow
Register
CCU6_MCA05508
Timer T12 Logic and Period Comparators
Via a comparator, the T12 counter register T12 is connected to a Period Register T12PR. This register determines
the maximum count value for T12.
In Edge-Aligned mode, T12 is cleared to 0000H after it has reached the period value defined by T12PR. In CenterAligned mode, the count direction of T12 is set from ‘up’ to ‘down’ after it has reached the period value (please
note that in this mode, T12 exceeds the period value by one before counting down). In both cases, signal T12_PM
(T12 Period Match) is generated. The Period Register receives a new period value from its Shadow Period
Register.
A read access to T12PR delivers the current period value at the comparator, whereas a write access targets the
Shadow Period Register to prepare another period value. The transfer of a new period value from the Shadow
Period Register into the Period Register (see Section 17.2.6) is controlled via the ‘T12 Shadow Transfer’ control
signal, T12_ST. The generation of this signal depends on the operating mode and on the shadow transfer enable
bit STE12. Providing a shadow register for the period value as well as for other values related to the generation
of the PWM signal allows a concurrent update by software for all relevant parameters.
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Two further signals indicate whether the counter contents are equal to 0000H (T12_ZM = zero match) or 0001H
(T12_OM = one match). These signals control the counting and switching behavior of T12.
The basic operating mode of T12, either Edge-Aligned mode (Figure 84) or Center-Aligned mode (Figure 85), is
selected via bit CTM. A Single-Shot control bit, T12SSC, enables an automatic stop of the timer when the current
counting period is finished (see Figure 86 and Figure 87).
The start or stop of T12 is controlled by the Run bit T12R that can be modified by bits in register TCTR4. The run
bit can be set/cleared by software via the associated set/clear bits T12RS or T12RR, it can be set by a selectable
edge of the input signal T12HR (TCTR2.T12RSEL), or it is cleared by hardware according to preselected
conditions.
The timer T12 run bit T12R must not be set while the applied T12 period value is zero. Timer T12 can be cleared
via control bit T12RES. Setting this write-only bit does only clear the timer contents, but has no further effects, for
example, it does not stop the timer.
The generation of the T12 shadow transfer control signal, T12_ST, is enabled via bit STE12. This bit can be set
or reset by software indirectly through its associated set/clear control bits T12STR and T12STD.
While Timer T12 is running, write accesses to the count register T12 are not taken into account. If T12 is stopped
and the Dead-Time counters are 0, write actions to register T12 are immediately taken into account.
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17.2.2
T12 Counting Scheme
This section describes the clocking and counting capabilities of T12.
17.2.2.1
Clock Selection
In Timer Mode (PISEL2.ISCNT12 = 00B), the input clock fT12 of Timer T12 is derived from the internal module
clock fCC6 through a programmable prescaler and an optional 1/256 divider. The resulting prescaler factors are
listed in Table 58. The prescaler of T12 is cleared while T12 is not running (TCTR0.T12R = 0) to ensure
reproducible timings and delays.
Table 58
Timer T12 Input Frequency Options
T12CLK
Resulting Input Clock fT12
Prescaler Off (T12PRE = 0)
Resulting Input Clock fT12
Prescaler On (T12PRE = 1)
000B
fCC6
fCC6 / 256
001B
fCC6 / 2
fCC6 / 512
010B
fCC6 / 4
fCC6 / 1024
011B
fCC6 / 8
fCC6 / 2048
100B
fCC6 / 16
fCC6 / 4096
101B
fCC6 / 32
fCC6 / 8192
110B
fCC6 / 64
fCC6 / 16384
111B
fCC6 / 128
fCC6 / 32768
In Counter Mode, timer T12 counts one step:
•
•
•
If a 1 is written to TCTR4.T12CNT and PISEL2.ISCNT12 = 01B
If a rising edge of input signal T12HR is detected and PISEL2.ISCNT12 = 10B
If a falling edge of input signal T12HR is detected and PISEL2.ISCNT12 = 11B
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17.2.2.2
Edge-Aligned / Center-Aligned Mode
In Edge-Aligned Mode (CTM = 0), timer T12 is always counting upwards (CDIR = 0). When reaching the value
given by the period register (period-match T12_PM), the value of T12 is cleared with the next counting step (saw
tooth shape).
fT12
Period
Value
T12 Count
Period Zero
Match Match
Zero
Up
Up
Value n+1
Value n+2
CDIR
CC6x
Shadow Transfer
Figure 84
CCU6_MCT05509
T12 Operation in Edge-Aligned Mode
As a result, in Edge-Aligned mode, the timer period is given by:
T12PER = <Period-Value> + 1; in T12 clocks (fT12)
(7)
In Center-Aligned Mode (CTM = 1), timer T12 is counting upwards or downwards (triangular shape). When
reaching the value given by the period register (period-match T12_PM) while counting upwards (CDIR = 0), the
counting direction control bit CDIR is changed to downwards (CDIR = 1) with the next counting step.
When reaching the value 0001H (one-match T12_OM) while counting downwards, the counting direction control
bit CDIR is changed to upwards with the next counting step.
As a result, in Center.Aligned mode, the timer period is given by:
T12PER = (<Period-Value> + 1) x2; in T12 clocks (fT12)
•
•
•
(8)
With the next clock event of fT12 the count direction is set to counting up (CDIR = 0) when the counter reaches
0001H while counting down.
With the next clock event of fT12 the count direction is set to counting down (CDIR = 1) when the Period-Match
is detected while counting up.
With the next clock event of fT12 the counter counts up while CDIR = 0 and it counts down while CDIR = 1.
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fT12
<Period Value> + 1
Period
Value
Zero
Match
T12 Count
Period
Match
Period
Match
Zero
Down
Up
Up
Down
Value n
Value n+1
Value n+1
Value n+2
CDIR
CC6x
Shadow Transfer
Figure 85
Shadow Transfer
CCU6_MCT05510
T12 Operation in Center-Aligned Mode
Note: Bit CDIR changes with the next timer clock event after the one-match or the period-match. Therefore, the
timer continues counting in the previous direction for one cycle before actually changing its direction (see
Figure 85).
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17.2.2.3
Single-Shot Mode
In Single-Shot Mode, the timer run bit T12R is cleared by hardware. If bit T12SSC = 1, the timer T12 will stop when
the current timer period is finished.
In Edge-Aligned mode, T12R is cleared when the timer becomes zero after having reached the period value (see
Figure 86).
fT12
Period
Value
Compare
Value
T12 Count
0
T12R
CC6xST
T12SSC
Figure 86
CCU6_MCT05511
Single-Shot Operation in Edge-Aligned Mode
In Center-Aligned mode, the period is finished when the timer has counted down to zero (one clock cycle after the
one-match while counting down, see Figure 87).
fT12
Period
Value
Compare
Value
T12 Count
1
0
T12R
CC6xST
T12SSC
Figure 87
CCU6_MCT05512
Single-Shot Operation in Center-Aligned Mode
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17.2.3
T12 Compare Mode
Associated with Timer T12 are three individual capture/compare channels, that can perform compare or capture
operations with regard to the contents of the T12 counter. The capture functions are explained in Section 17.2.5.
17.2.3.1
Compare Channels
In Compare Mode (see Figure 88), the three individual compare channels CC60 CC61, and CC62 can generate
a three-phase PWM pattern.
Counter Register
T12
fT12
Compare
Match CM_60
Comp.
=?
Comp.
=?
Comp.
=?
Compare Register
CC60R
Compare Register
CC61R
Compare Register
CC62R
Compare
Match CM_61
Compare
Match CM_62
T12_ST
Compare Shadow
Register CC60SR
Compare Shadow
Register CC61SR
Compare Shadow
Register CC62SR
CCU6_MCA05513
Figure 88
T12 Channel Comparators
Each compare channel is connected to the T12 counter register via its individual equal-to comparator, generating
a match signal when the contents of the counter matches the contents of the associated compare register. Each
channel consists of the comparator and a double register structure - the actual compare register CC6xR, feeding
the comparator, and an associated shadow register CC6xSR, that is preloaded by software and transferred into
the compare register when signal T12 shadow transfer, T12_ST, gets active. Providing a shadow register for the
compare value as well as for other values related to the generation of the PWM signal facilitates a concurrent
update by software for all relevant parameters of a three-phase PWM.
17.2.3.2
Channel State Bits
Associated with each (compare) channel is a State Bit, CMPSTAT.CC6xST, holding the status of the compare (or
capture) operation (see Figure 89). In compare mode, the State Bits are modified according to a set of switching
rules, depending on the current status of timer T12.
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CC60_R
CCPOS0
Compare
Channel
CC60
CM_60
To Interrupt
CC60_F Control
Switching
Rule
Logic
State Bit
CC60ST
MSEL60
To Dead_Time
Counter 0
MCC60S/R
CC61_R
CCPOS1
Compare
Channel
CC61
CM_61
To Interrupt
CC61_F Control
Switching
Rule
Logic
State Bit
CC61ST
MSEL61
To Dead_Time
Counter 1
MCC61S/R
CC62_R
CCPOS2
Compare
Channel
CC62
T12 Counter
CM_62
To Interrupt
CC62_F Control
Switching
Rule
Logic
State Bit
CC62ST
MSEL62
MCC62S/R
CDIR
T12R
To Dead_Time
Counter 2
T12_ZM
CCU6_MCB05514
Figure 89
Compare State Bits for Compare Mode
The inputs to the switching rule logic for the CC6xST bits are the timer direction (CDIR), the timer run bit (T12R),
the timer T12 zero-match signal (T12_ZM), and the actual individual compare-match signals CM_6x as well as the
mode control bits, T12MSEL.MSEL6x.
In addition, each state bit can be set or cleared by software via the appropriate set and reset bits in register
CMPMODIF, MCC6xS and MCC6xR. The input signals CCPOSx are used in hysteresis-like compare mode,
whereas in normal compare mode, these inputs are ignored.
Note: In Hall Sensor, single shot or capture modes, additional/different rules are taken into account (see related
sections).
A compare interrupt event CC6x_R is signaled when a compare match is detected while counting upwards,
whereas the compare interrupt event CC6x_F is signaled when a compare match is detected while counting down.
The actual setting of a State Bit has no influence on the interrupt generation in compare mode.
A modification of a State Bit CC6xST by the switching rule logic due to a compare action is only possible while
Timer T12 is running (T12R = 1). If this is the case, the following switching rules apply for setting and clearing the
State Bits in Compare Mode (illustrated in Figure 90 and Figure 91):
A State Bit CC6xST is set to 1:
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•
•
with the next T12 clock (fT12) after a compare-match when T12 is counting up (i.e., when the counter is
incremented above the compare value);
with the next T12 clock (fT12) after a zero-match AND a parallel compare-match when T12 is counting up.
A State Bit CC6xST is cleared to 0:
•
•
with the next T12 clock (fT12) after a compare-match when T12 is counting down (i.e., when the counter is
decremented below the compare value in center-aligned mode);
with the next T12 clock (fT12) after a zero-match AND NO parallel compare-match when T12 is counting up.
fT12
Period
Value
Compare
Value
Zero
T12 Count
CC6xST
CCU6_MCT05515
Figure 90
Compare Operation, Edge-Aligned Mode
Figure 92 illustrates some more examples for compare waveforms. It is important to note that in these examples,
it is assumed that some of the compare values are changed while the timer is running. This change is performed
via a software preload of the Shadow Register, CC6xSR. The value is transferred to the actual Compare Register
CC6xR with the T12 Shadow Transfer signal, T12_ST, that is assumed to be enabled.
fT12
Compare-Match
Compare-Match
T12 Count
Compare
Value
Zero
CC6xST
Figure 91
Period
Value
CCU6_MCT05516
Compare Operation, Center-Aligned Mode
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fT12
Period
Value = 5
T12 Count
Zero
Down
Up
Down
Up
Value n
Value n+1
Value n+2
Value n+3
CC6x = 2
CC6x = 2
CC6x = 1
CC6x = 1
CC6x = 1
CC6x = 0
CC6x = 0
CC6x = 0
CC6x = 3
CC6x = 3
CC6x = 3
CC6x = 3
CC6x = 4
CC6x = 4
CC6x = 4
CC6x = 4
CC6x = 5
CC6x = 5
CC6x = 5
CC6x = 5
CC6x = 3
CC6x = 6
CC6x = 6
CC6x = 6
CDIR
CC6x
a)
b)
c)
d)
e)
f)
CCU6_MCT05517
Figure 92
Compare Waveform Examples
Example b) illustrates the transition to a duty cycle of 100%. First, a compare value of 0001H is used, then changed
to 0000H. Please note that a low pulse with the length of one T12 clock is still produced in the cycle where the new
value 0000H is in effect; this pulse originates from the previous value 0001H. In the following timer cycles, the State
Bit CC6xST remains at 1, producing a 100% duty cycle signal. In this case, the compare rule ‘zero-match AND
compare-match’ is in effect.
Example f) shows the transition to a duty cycle of 0%. The new compare value is set to <Period-Value> + 1, and
the State Bit CC6ST remains cleared.
Figure 93 illustrates an example for the waveforms of all three channels. With the appropriate dead-time control
and output modulation, a very efficient 3-phase PWM signal can be generated.
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Period
Value
CC61R
CC62R
T12 Count
Down
Up
Down
Up
CC60R
Zero
Down
CDIR
Shadow
Transfer
CC60ST
CC61ST
CC62ST
Figure 93
CCU6_MCT05518
Three-Channel Compare Waveforms
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17.2.3.3
Hysteresis-Like Control Mode
The hysteresis-like control mode (T12MSEL.MSEL6x = 1001B) offers the possibility to switch off the PWM output
if the input CCPOSx becomes 0 by clearing the State Bit CC6xST. This can be used as a simple motor control
feature by using a comparator indicating, e.g., overcurrent. While CCPOSx = 0, the PWM outputs of the
corresponding channel are driving their passive levels, because the setting of bit CC6xST is only possible while
CCPOSx = 1.
As long as input CCPOSx is 0, the corresponding State Bit is held 0. When CCPOSx is at high level, the outputs
can be in active state and are determined by bit CC6xST (see Figure 89 for the state bit logic and Figure 94 for
the output paths). The CCPOSx inputs are evaluated with fCC6.
This mode can be used to introduce a timing-related behavior to a hysteresis controller. A standard hysteresis
controller detects if a value exceeds a limit and switches its output according to the compare result. Depending on
the operating conditions, the switching frequency and the duty cycle are not fixed, but change permanently.
If (outer) time-related control loops based on a hysteresis controller in an inner loop should be implemented, the
outer loops show a better behavior if they are synchronized to the inner loops. Therefore, the hysteresis-like mode
can be used, that combines timer-related switching with a hysteresis controller behavior. For example, in this
mode, an output can be switched on according to a fixed time base, but it is switched off as soon as a falling edge
is detected at input CCPOSx.
This mode can also be used for standard PWM with overcurrent protection. As long as there is no low level signal
at pin CCPOSx, the output signals are generated in the normal manner as described in the previous sections. Only
if input CCPOSx shows a low level, e.g. due to the detection of overcurrent, the outputs are shut off to avoid
harmful stress to the system.
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17.2.4
Compare Mode Output Path
Figure 94 gives an overview on the signal path from a channel State Bit to its output pin in its simplest form. As
illustrated, a user has a variety of controls to determine the desired output signal switching behavior in relation to
the current state of the State Bit, CC6xST. Please refer to Section 17.2.4.3 for details on the output modulation.
T12
State Bits
Dead-Time
Generation
CC60ST
CC61ST
CC62ST
T12
State Selection
Output Level
Selection
CC6xPS
PSLy
CC6xST
CC6x_O
Dead-Time
Counters
T12 Output
Modulation
CC6xST
CC6x
Level
Select
Level
Select
COUT6x
COUT6x_O
COUT6xPS
PSLy+1
CCU6_MCA05519
Figure 94
Compare Mode Simplified Output Path Diagram
The output path is based on signals that are defined as active or passive. The terms active and passive are not
related to output levels, but to internal actions. This mainly applies for the modulation, where T12 and T13 signals
are combined with the multi-channel signals and the trap function. The Output level Selection allows the user to
define the output level at the output pin for the passive state (inverted level for the active state). It is recommended
to configure this block in a way that an external power switch is switched off while the CCU6 delivers an output
signal in the passive state.
17.2.4.1
Dead-Time Generation
The generation of (complementary) signals for the High Side and the low-side switches of one power inverter
phase is based on the same compare channel. For example, if the High Side switch should be active while the
T12 counter value is above the compare value (State Bit = 1), then the low-side switch should be active while the
counter value is below the compare value (State Bit = 0).
In most cases, the switching behavior of the connected power switches is not symmetrical concerning the switchon and switch-off times. A general problem arises if the time for switch-on is smaller than the time for switch-off of
the power device. In this case, a short-circuit can occur in the inverter bridge leg, which may damage the complete
system. In order to solve this problem by HW, this capture/compare unit contains a programmable Dead-Time
Generation Block, that delays the passive to active edge of the switching signals by a programmable time (the
active to passive edge is not delayed).
The Dead-Time Generation Block, illustrated in Figure 95, is built in a similar way for all three channels of T12. It
is controlled by bits in register T12DTC. Any change of a CC6xST State Bit activates the corresponding DeadTime Counter, that is clocked with the same input clock as T12 (fT12). The length of the dead-time can be
programmed by bit field DTM. This value is identical for all three channels. Writing TCTR4.DTRES = 1 sets all
dead-times to passive.
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Dead-Time Value
DTM
fT12
DTRES
Dead-Time
Counter 0
DTE0
CC60ST
Dead-Time 0
active / passive
CC60ST
CC60ST
Dead-Time
Counter 1
DTE1
CC61ST
Dead-Time 1
active / passive
CC61ST
CC61ST
Dead-Time
Counter 2
DTE2
CC62ST
Dead-Time 2
active / passive
CC62ST
CC62ST
CCU6_MCB05520
Figure 95
Dead-Time Generation Block Diagram
Each of the three dead-time counters has its individual dead-time enable bit, DTEx. An enabled dead-time counter
generates a dead-time delaying the passive-to-active edge of the channel output signal. The change in a State Bit
CC6xST is not taken into account while the dead-time generation of this channel is currently in progress (active).
This avoids an unintentional additional dead-time if a State Bit CC6xST changes too early.
A disabled dead-time counter is always considered as passive and does not delay any edge of CC6xST.
Based on the State Bits CC6xST, the Dead-Time Generation Block outputs a direct signal CC6xST and an
inverted signal CC6xST for each compare channel, each masked with the effect of the related Dead-Time
Counters (waveforms illustrated in Figure 96).
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T12 Counter
Value
Compare
Value
active
State Bit
CC6xST
DeadTime
passive
active
CC6xST
with DeadTime
CC6xST
with DeadTime
active
passive
passive
active
passive
active
Figure 96
Dead-Time Generation Waveforms
17.2.4.2
State Selection
passive
CCU6_MCT05521
To support a wide range of power switches and drivers, the state selection offers the flexibility to define when an
output can be active and can be modulated, especially useful for complementary or multi-phase PWM signals.
The state selection is based on the signals CC6xST and CC6xST delivered by the dead-time generator (see
Figure 94). Both signals are never active at the same time, but can be passive at the same time. This happens
during the dead-time of each compare channel after a change of the corresponding State Bit CC6xST.
The user can select independently for each output signal CC6xO and COUT6xO if it should be active before or
after the compare value has been reached (see register CMPSTAT). With this selection, the active (conducting)
phases of complementary power switches in a power inverter bridge leg can be positioned with respect to the
compare value (e.g. signal CC6xO can be active before, whereas COUT6xO can be active after the compare value
is reached). Like this, the output modulation, the trap logic and the output level selection can be programmed
independently for each output signal, although two output signals are referring to the same compare channel.
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17.2.4.3
Output Modulation and Level Selection
The last block of the data path is the Output Modulation block. Here, all the modulation sources and the trap
functionality are combined and control the actual level of the output pins (controlled by the modulation enable bits
T1xMODENy and MCMEN in register MODCTR). The following signal sources can be combined here for each
T12 output signal (see Figure 97 for compare channel CC60):
•
•
•
•
A T12 related compare signal CC6x_O (for outputs CC6x) or COUT6x_O (for outputs COUT6x) delivered by
the T12 block (state selection with dead-time) with an individual enable bit T12MODENy per output signal
(y = 0, 2, 4 for outputs CC6x and y = 1, 3, 5 for outputs COUT6x)
The T13 related compare signal CC63_O delivered by the T13 state selection with an individual enable bit
T13MODENy per output signal (y = 0, 2, 4 for outputs CC6x and y = 1, 3, 5 for outputs COUT6x)
A multi-channel output signal MCMPy (y = 0, 2, 4 for outputs CC6x and y = 1, 3, 5 for outputs COUT6x) with
a common enable bit MCMEN
The trap state TRPS with an individual enable bit TRPENy per output signal (y = 0, 2, 4 for outputs CC6x and
y = 1, 3, 5 for outputs COUT6x)
If one of the modulation input signals CC6x_O/COUT6x_O, CC63_O, or MCMPy of an output modulation block is
enabled and is at passive state, the modulated is also in passive state, regardless of the state of the other signals
that are enabled. Only if all enabled signals are in active state the modulated output shows an active state. If no
modulation input is enabled, the output is in passive state.
If the Trap State is active (TRPS = 1), then the outputs that are enabled for the trap signal (by TRPENy = 1) are
set to the passive state.
The output of each of the modulation control blocks is connected to a level select block that is configured by
register PSLR. It offers the option to determine the actual output level of a pin, depending on the state of the output
line (decoupling of active/passive state and output polarity) as specified by the Passive State Select bit PSLy. If
the modulated output signal is in the passive state, the level specified directly by PSLy is output. If it is in the active
state, the inverted level of PSLy is output. This allows the user to adapt the polarity of an active output signal to
the connected circuitry.
The PSLy bits have shadow registers to allow for updates without undesired pulses on the output lines. The bits
related to CC6x and COUT6x (x = 0, 1, 2) are updated with the T12 shadow transfer signal (T12_ST). A read
action returns the actually used values, whereas a write action targets the shadow bits. Providing a shadow
register for the PSL value as well as for other values related to the generation of the PWM signal facilitates a
concurrent update by software for all relevant parameters.
Figure 97 shows the output modulation structure for compare channel CC60 (output signals CC60 and COUT60).
A similar structure is implemented for the other two compare channels CC61 and CC62.
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Trap Handling
Block
TRPS
TRPEN0
T13 Block
CC63_O
T13MODEN0
Output
Modulation
CC60
active
passive
Level
Selection
CC60
CC60_O
T12 Block +
Dead-Time
PSL0
COUT60_O
T12MODEN0
MCMP0
Multi-Channel
Mode
MCMEN
MCMP1
TRPEN1
T13MODEN1
Output
Modulation
COUT60
active
passive
Level
Selection
COUT60
PSL1
T12MODEN1
CCU6_MCA05543
Figure 97
Output Modulation for Compare Channel CC60
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17.2.5
T12 Capture Modes
Each of the three channels of the T12 Block can also be used to capture T12 time information in response to an
external signal CC6xIN.
In capture mode, the interrupt event CC6x_R is detected when a rising edge is detected at the input CC6xIN,
whereas the interrupt event CC6x_F is detected when a falling edge is detected.
There are a number of different modes for capture operation. In all modes, both of the registers of a channel are
used. The selection of the capture modes is done via the T12MSEL.MSEL6x bit fields and can be selected
individually for each of the channels.
Table 59
Capture Modes Overview
MSEL6x
Mode
0100B
1
Signal
Active Edge
CC6nSR Stored in
T12 Stored in
CC6xIN
Rising
–
CC6xR
CC6xIN
Falling
–
CC6xSR
0101B
2
CC6xIN
Rising
CC6xR
CC6xSR
0110B
3
CC6xIN
Falling
CC6xR
CC6xSR
0111B
4
CC6xIN
Any
CC6xR
CC6xSR
Figure 98 illustrates Capture Mode 1. When a rising edge (0-to-1 transition) is detected at the corresponding input
signal CC6xIN, the current contents of Timer T12 are captured into register CC6xR. When a falling edge (1-to-0
transition) is detected at the input signal CC6xIN, the contents of Timer T12 are captured into register CC6xSR.
fT12
Counter Register
T12
MSEL6x
CC6xIN
Edge
Detect
fCC6
Capture
Mode
Selection
Rising
Falling
Set
State Bit
CC6xST
Register CC6xR
Shadow Register
CC6xSR
CC6x_R
CC6x_F
To Interrupt Logic
CCU6_MCB05522
Figure 98
Capture Mode 1 Block Diagram
Capture Modes 2, 3 and 4 are shown in Figure 99. They differ only in the active edge causing the capture
operation. In each of the three modes, when the selected edge is detected at the corresponding input signal
CC6xIN, the current contents of the shadow register CC6xSR are transferred into register CC6xR, and the current
Timer T12 contents are captured in register CC6xSR (simultaneous transfer). The active edge is a rising edge of
CC6xIN for Capture Mode 2, a falling edge for Mode 3, and both, a rising or a falling edge for Capture Mode 4, as
shown in Table 59. These capture modes are very useful in cases where there is little time between two
consecutive edges of the input signal.
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Counter Register
T12
fT12
MSEL6x
CC6xIN
Edge
Detect
Capture
Mode
Selection
Shadow Register
CC6xSR
Set
fCC6
State Bit
CC6xST
Register CC6xR
CC6x_R
CC6x_F
To Interrupt Logic
CCU6_MCB05523
Figure 99
Capture Modes 2, 3 and 4 Block Diagram
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Five further capture modes are called Multi-Input Capture Modes, as they use two different external inputs,
signal CC6xIN and signal CCPOSx.
Counter Register
T12
fT12
MSEL6x
CC6xIN
Edge
Detect
fCC6
Capture
Mode
Selection
Set
State Bit
CC6xST
Register CC6xR
Set
CC6x_R
CC6x_F
Edge
CCPOSx
Detect
Shadow Register
CC6xSR
To Interrupt Logic
Capture
Mode
Selection
MSEL6x
CCU6_MCB05524
Figure 100 Multi-Input Capture Modes Block Diagram
In each of these modes, the current T12 contents are captured in register CC6xR in response to a selected event
at signal CC6xIN, and in register CC6xSR in response to a selected event at signal CCPOSx. The possible events
can be opposite input transitions, or the same transitions, or any transition at the two inputs. The different options
are detailed in Table 60.
In each of the various capture modes, the Channel State Bit, CC6xST, is set to 1 when the selected capture trigger
event at signal CC6xIN or CCPOSx has occured. The State Bit is not cleared by hardware, but can be cleared by
software.
In addition, appropriate signal lines to the interrupt logic are activated, that can generate an interrupt request to
the CPU. Regardless of the selected active edge, all edges detected at signal CC6xIN can lead to the activation
of the appropriate interrupt request line (see also Section 17.7).
Table 60
Multi-Input Capture Modes Overview
MSEL6x
Mode
1010B
5
1011B
1100B
User’s Manual
6
7
Signal
Active Edge
T12 Stored in
CC6xIN
Rising
CC6xR
CCPOSx
Falling
CC6xSR
CC6xIN
Falling
CC6xR
CCPOSx
Rising
CC6xSR
CC6xIN
Rising
CC6xR
CCPOSx
Rising
CC6xSR
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Table 60
Multi-Input Capture Modes Overview (cont’d)
MSEL6x
Mode
Signal
Active Edge
T12 Stored in
1101B
8
CC6xIN
Falling
CC6xR
CCPOSx
Falling
CC6xSR
CC6xIN
Any
CC6xR
CCPOSx
Any
CC6xSR
1110B
1111B
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–
reserved (no capture or compare action)
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17.2.6
T12 Shadow Register Transfer
A special shadow transfer signal (T12_ST) can be generated to facilitate updating the period and compare values
of the compare channels CC60, CC61, and CC62 synchronously to the operation of T12. Providing a shadow
register for values defining one PWM period facilitates a concurrent update by software for all relevant parameters.
The next PWM period can run with a new set of parameters. The generation of this signal is requested by software
via bit TCTR0.STE12 (set by writing 1 to the write-only bit TCTR4.T12STR, cleared by writing 1 to the write-only
bit TCTR4.T12STD).
Figure 101 shows the shadow register structure and the shadow transfer signals, as well as on the read/write
accessibility of the various registers.
Read
Read
Read
Read
Period Register
T12PR
(T12)
PSLy
CC6xPS
COUT6xPS
Period Shadow
Register T12PR
(T12) PSLy
Shadow
CC6xPS
Shadow
COUT6xPS
Shadow
Write
Write
Write
Write
Read
Compare Register
CC6xR
_
>1
T12_ST
Other Modes
(Hall, Capture, etc.)
Compare Shadow
Register CC6xSR
Write
Read
CCU6_MCA05546
Figure 101 T12 Shadow Register Overview
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A T12 shadow register transfer takes place (T12_ST active):
•
•
•
while timer T12 is not running (T12R = 0), or
STE12 = 1 and a Period-Match is detected while counting up, or
STE12 = 1 and a One-Match is detected while counting down
When signal T12_ST is active, a shadow register transfer is triggered with the next cycle of the T12 clock. Bit
STE12 is automatically cleared with the shadow register transfer.
17.2.7
Timer T12 Operating Mode Selection
The operating mode for the T12 channels are defined by the bit fields T12MSEL.MSEL6x.
Table 61
T12 Capture/Compare Modes Overview
MSEL6x
Selected operating mode
0000B,
1111B
Capture/Compare modes switched off
0001B,
0010B,
0011B
Compare mode, see Section 17.2.3
same behavior for all three codings
01XXB
Double-Register Capture modes, see Section 17.2.5
1000B
Hall Sensor Mode, see Section 17.6
In order to properly enable this mode, all three MSEL6x fields have to be programmed to Hall
Sensor mode.
1001B
Hysteresis-like compare mode, see Section 17.2.3.3
1010B,
1011B,
1100B,
1101B,
1110B
Multi-Input Capture modes, see Section 17.2.5
The clocking and counting scheme of the timers are controlled by the timer control registers TCTR0 and TCTR2.
Specific actions are triggered by write operations to register TCTR4.
17.3
Operating Timer T13
Timer T13 is implemented similarly to Timer T12, but only with one channel in compare mode. A 16-bit up-counter
is connected to a channel register via a comparator, that generates a signal when the counter contents match the
contents of the channel register. A variety of control functions facilitate the adaptation of the T13 structure to
different application needs. In addition, T13 can be started synchronously to timer T12 events.
This section provides information about:
•
•
•
•
•
T13 overview (see Section 17.3.1)
Counting scheme (see Section 17.3.2)
Compare mode (see Section 17.3.3)
Compare output path (see Section 17.3.4)
Shadow register transfer (see Section 17.3.5)
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State Bit
Timer T13
Logic
Capture/Compare
Channel CC63
CC63ST
To Output
Modulation
Input and Control/Status Logic
T13HR
Synchronization to T12
CCU6_MCA05526
Figure 102 Overview Diagram of the Timer T13 Block
17.3.1
T13 Overview
Figure 103 shows a detailed block diagram of Timer T13. The functions of the timer T12 block are controlled by
bits in registers TCTR0, TCTR2, and PISEL2.
Timer T13 receives its input clock, fT13, from the module clock fCC6 via a programmable prescaler and an optional
1/256 divider or from an input signal T13HR. T13 can only count up (similar to the Edge-Aligned mode of T12).
Via a comparator, the timer T13 Counter Register T13 is connected to the Period Register T13PR. This register
determines the maximum count value for T13. When T13 reaches the period value, signal T13_PM (T13 Period
Match) is generated and T13 is cleared to 0000H with the next T13 clock edge. The Period Register receives a
new period value from its Shadow Period Register, T13PS, that is loaded via software. The transfer of a new
period value from the shadow register into T13PR is controlled via the ‘T13 Shadow Transfer’ control signal,
T13_ST. The generation of this signal depends on the associated control bit STE13. Providing a shadow register
for the period value as well as for other values related to the generation of the PWM signal facilitates a concurrent
update by software for all relevant parameters (refer to Table 17.3.5). Another signal indicates whether the
counter contents are equal to 0000H (T13_ZM).
A Single-Shot control bit, T13SSC, enables an automatic stop of the timer when the current counting period is
finished (see Figure 105).
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T13RSEL
Sync. to T12
T13RS
T13RR
T13R
edge
detection
ISCNT13
T13STD
T13HR
STE13
edge
detection
T13CNT
fCC6
T13STR
Clock
Selection
n
T13CLK
fT13
T13
Control
& Status
Counter Register
T13
256
T13RES
= 0000 H
T13PRE
Read from
T13PR
T13SSC
T13_ZM
Comp.
=?
T13_PM
Period Register
T13_ST
Write to
T13PR
Period Shadow
Register
CCU6_MCA05527
Figure 103 T13 Counter Logic and Period Comparators
The start or stop of T13 is controlled by the Run bit, T13R. This control bit can be set by software via the associated
set/clear bits T13RS or T13RR in register TCTR4, or it is cleared by hardware according to preselected conditions
(single-shot mode).
The timer T13 run bit T13R must not be set while the applied T13 period value is zero. Bit T13R can be set
automatically if an event of T12 is detected to synchronize T13 timings to T12 events, e.g. to generate a
programmable delay via T13 after an edge of a T12 compare channel before triggering an AD conversion (T13
can trigger ADC conversions).
Timer T13 can be cleared to 0000H via control bit T13RES. Setting this write-only bit only clears the timer contents,
but has no further effects, e.g., it does not stop the timer.
The generation of the T13 shadow transfer control signal, T13_ST, is enabled via bit STE13. This bit can be set
or cleared by software indirectly through its associated set/reset control bits T13STR and T13STD.
Two bit fields, T13TEC and T13TED, control the synchronization of T13 to Timer T12 events. T13TEC selects the
trigger event, while T13TED determines for which T12 count direction the trigger should be active.
While Timer T13 is running, write accesses to the count register T13 are not taken into account. If T13 is stopped,
write actions to register T13 are immediately taken into account.
Note: The T13 Period Register and its associated shadow register are located at the same physical address. A
write access to this address targets the Shadow Register, while a read access reads from the actual period
register.
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17.3.2
T13 Counting Scheme
This section describes the clocking and the counting capabilities of T13.
17.3.2.1
Clock Selection
In Timer Mode (PISEL2. ISCNT13 = 00B), the input clock fT13 of Timer T13 is derived from the internal module
clock fCC6 through a programmable prescaler and an optional 1/256 divider. The resulting prescaler factors are
listed in Table 62. The prescaler of T13 is cleared while T13 is not running (TCTR0.T13R = 0) to ensure
reproducible timings and delays.
Table 62
Timer T13 Input Clock Options
T13CLK
Resulting Input Clock fT13
Prescaler Off (T13PRE = 0)
Resulting Input Clock fT13
Prescaler On (T13PRE = 1)
000B
fCC6
fCC6 / 256
001B
fCC6 / 2
fCC6 / 512
010B
fCC6 / 4
fCC6 / 1024
011B
fCC6 / 8
fCC6 / 2048
100B
fCC6 / 16
fCC6 / 4096
101B
fCC6 / 32
fCC6 / 8192
110B
fCC6 / 64
fCC6 / 16384
111B
fCC6 / 128
fCC6 / 32768
In Counter Mode, timer T13 counts one step:
•
•
•
If a 1 is written to TCTR4.T13CNT and PISEL2.ISCNT13 = 01B
If a rising edge of input signal T13HR is detected and PISEL2.ISCNT13 = 10B
If a falling edge of input signal T13HR is detected and PISEL2.ISCNT13 = 11B
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17.3.2.2
T13 Counting
The period of the timer is determined by the value in the period Register T13PR according to the following formula:
T13PER = <Period-Value> + 1; in T13 clocks (fT13)
(9)
Timer T13 can only count up, comparable to the Edge-Aligned mode of T12. This leads to very simple ‘counting
rule’ for the T13 counter:
•
The counter is cleared with the next T13 clock edge if a Period-Match is detected. The counting direction is
always upwards.
The behavior of T13 is illustrated in Figure 104.
fT13
Period
Value
T13 Count
Period Zero
Match Match
Zero
CC63
Value n+1
Value n+2
Shadow Transfer
CCU6_MCT05528
Figure 104 T13 Counting Sequence
17.3.2.3
Single-Shot Mode
In Single-Shot Mode, the timer run bit T13R is cleared by hardware. If bit T13SSC = 1, the timer T13 will stop when
the current timer period is finished.
fT13
Period
Value
Compare
Value
T13 Count
0
T13R
CC63ST
T13SSC
CCU6_MCT05529
Figure 105 Single-Shot Operation of Timer T13
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17.3.2.4
Synchronization to T12
Timer T13 can be synchronized to a T12 event. Bit fields T13TEC and T13TED select the event that is used to
start Timer T13. The selected event sets bit T13R via HW, and T13 starts counting. Combined with the SingleShot mode, this feature can be used to generate a programmable delay after a T12 event.
Figure 106 shows an example for the synchronization of T13 to a T12 event. Here, the selected event is a
compare-match (compare value = 2) while counting up. The clocks of T12 and T13 can be different (other
prescaler factor); the figure shows an example in which T13 is clocked with half the frequency of T12.
fT12
Compare-Match
Period
Value
T12 Count
Compare
Value
Zero
T13R
T13 Count
fT13
CCU6_MCT05530
Figure 106 Synchronization of T13 to T12 Compare Match
Bit field T13TEC selects the trigger event to start T13 (automatic set of T13R for synchronization to T12 compare
signals) according to the combinations shown in Table 63. Bit field T13TED additionally specifies for which count
direction of T12 the selected trigger event should be regarded (see Table 64).
Table 63
T12 Trigger Event Selection
T13TEC
Selected Event
000B
None
001B
T12 Compare Event on Channel 0 (CM_CC60)
010B
T12 Compare Event on Channel 1 (CM_CC61)
011B
T12 Compare Event on Channel 2 (CM_CC62)
100B
T12 Compare Event on any Channel (0, 1, 2)
101B
T12 Period-Match (T12_PM)
110B
T12 Zero-Match while counting up (T12_ZM and CDIR = 0)
111B
Any Hall State Change
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Table 64
T12 Trigger Event Additional Specifier
T13TED
Selected Event Specifier
00B
Reserved, no action
01B
Selected event is active while T12 is counting up (CDIR = 0)
10B
Selected event is active while T12 is counting down (CDIR = 1)
11B
Selected event is active independently of the count direction of T12
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17.3.3
T13 Compare Mode
Associated with Timer T13 is one compare channel, that can perform compare operations with regard to the
contents of the T13 counter.
Figure 102 gives an overview on the T13 channel in Compare Mode. The channel is connected to the T13 counter
register via an equal-to comparator, generating a compare match signal when the contents of the counter matches
the contents of the compare register.
The channel consists of the comparator and a double register structure - the actual compare register, CC63R,
feeding the comparator, and an associated shadow register, CC63SR, that is preloaded by software and
transferred into the compare register when signal T13 shadow transfer, T13_ST, gets active. Providing a shadow
register for the compare value as well as for other values related to the generation of the PWM signal facilitates a
concurrent update by software for all relevant parameters.
Associated with the channel is a State Bit, CMPSTAT.CC63ST, holding the status of the compare operation.
Figure 107 gives an overview on the logic for the State Bit.
fT13
Counter Register
T13
T13_ZM
Comp.
=?
CM_63
Compare Register
CC63R
Switching
Rule
Logic
State Bit
CC63ST
T13R
MCC63S/R
To State
Selection and
Output
Modulation
To Interrupt
Control
T13_ST
Compare Shadow
Register CC63SR
CCU6_MCB05532
Figure 107 T13 State Bit Block Diagram
A compare interrupt event CM_63 is signaled when a compare match is detected. The actual setting of a State Bit
has no influence on the interrupt generation.
The inputs to the switching rule logic for the CC63ST bit are the timer run bit (T13R), the timer zero-match signal
(T13_ZM), and the actual individual compare-match signal CM_63. In addition, the state bit can be set or cleared
by software via bits MCC63S and MCC63R in register CMPMODIF.
A modification of the State Bit CC63ST by hardware is only possible while Timer T13 is running (T13R = 1). If this
is the case, the following switching rules apply for setting and resetting the State Bit in Compare Mode:
State Bit CC63ST is set to 1
•
•
with the next T13 clock (fT13) after a compare-match (T13 is always counting up) (i.e., when the counter is
incremented above the compare value);
with the next T13 clock (fT13) after a zero-match AND a parallel compare-match.
State Bit CC63ST is cleared to 0
•
with the next T13 clock (fT13) after a zero-match AND NO parallel compare-match.
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fT13
Compare-Match
Compare-Match
Period
Value
Compare
Value
T13 Count
Zero
CC63ST
CCU6_MCT05533
Figure 108 T13 Compare Operation
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17.3.4
Compare Mode Output Path
Figure 109 gives an overview on the signal path from the channel State Bit CC63ST to its output pin COUT63. As
illustrated, a user can determine the desired output behavior in relation to the current state of CC63ST. Please
refer to Section 17.2.4.3 for detailed information on the output modulation for T12 signals.
T13
State Selection
Output
Modulation
Output Level
Selection
T13IM
CC63ST
CC63_O
T13
State Bit
CC63ST
T12 Output
Modulation
T13 Output
Modulation
CC63ST
Level
Select
COUT63
COUT63_O
COUT63PS
ECT13O
PSL63
CCU6_MCA05534
Figure 109 Channel 63 Output Path
The output line COUT63_O can generate a T13 PWM at the output pin COUT63. The signal CC63_O can be used
to modulate the T12-related output signals with a T13 PWM. In order to decouple COUT63 from the internal
modulation, the compare state leading to an active signal can be selected independently by bits T13IM and
COUT63PS.
The last block of the data path is the Output Modulation block. Here, the modulation source T13 and the trap
functionality are combined and control the actual level of the output pin COUT63 (see Figure 110):
•
•
The T13 related compare signal COUT63_O delivered by the T13 state selection with the enable bit
MODCTR.ECT13O
The trap state TRPS with an individual enable bit TRPCTR.TRPEN13
If the modulation input signal COUT63_O is enabled (ECT13O = 1) and is at passive state, the modulated is also
in passive state. If the modulation input is not enabled, the output is in passive state.
If the Trap State is active (TRPS = 1), then the output enabled for the trap signal (by TRPEN13 = 1) is set to the
passive state.
The output of the modulation control block is connected to a level select block. It offers the option to determine the
actual output level of a pin, depending on the state of the output line (decoupling of active/passive state and output
polarity) as specified by the Passive State Select bit PSLR.PSL63. If the modulated output signal is in the passive
state, the level specified directly by PSL63 is output. If it is in the active state, the inverted level of PSL63 is output.
This allows the user to adapt the polarity of an active output signal to the connected circuitry.
The PSL63 bit has a shadow register to allow for updates with the T13 shadow transfer signal (T13_ST) without
undesired pulses on the output lines. A read action returns the actually used value, whereas a write action targets
the shadow bit. Providing a shadow register for the PSL value as well as for other values related to the generation
of the PWM signal facilitates a concurrent update by software for all relevant parameters.
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Trap Handling
Block
TRPS
TRPEN13
T13 Block
COUT63_O
Output
Modulation
COUT63
ECT13O
active
passive
Level
Selection
COUT63
PSL63
CCU6_MCA05545
Figure 110 T13 Output Modulation
17.3.5
T13 Shadow Register Transfer
A special shadow transfer signal (T13_ST) can be generated to facilitate updating the period and compare values
of the compare channel CC63 synchronously to the operation of T13. Providing a shadow register for values
defining one PWM period facilitates a concurrent update by software for all relevant parameters. The next PWM
period can run with a new set of parameters. The generation of this signal is requested by software via bit
TCTR0.STE13 (set by writing 1 to the write-only bit TCTR4.T13STR, cleared by writing 1 to the write-only bit
TCTR4.T13STD).
When signal T13_ST is active, a shadow register transfer is triggered with the next cycle of the T13 clock. Bit
STE13 is automatically cleared with the shadow register transfer. A T13 shadow register transfer takes place
(T13_ST active):
•
•
while timer T13 is not running (T13R = 0), or
STE13 = 1 and a Period-Match is detected while T13R = 1
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Read
Read
Read
Read
Period Register
T13PR
PSL63
CC63PS
T13IM
Period Shadow
Register T13PR
PSL63
Shadow
CC63PS
Shadow
T13IM
Shadow
Write
Write
Write
Write
Read
Compare Register
CC63R
T13_ST
Compare Shadow
Register CC63SR
Write
Read
CCU6_MCA05547
Figure 111 T13 Shadow Register Overview
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17.4
Trap Handling
The trap functionality permits the PWM outputs to react on the state of the input signal CTRAP. This functionality
can be used to switch off the power devices if the trap input becomes active (e.g. to perform an emergency stop).
The trap handling and the effect on the output modulation are controlled by the bits in the trap control register
TRPCTR. The trap flags TRPF and TRPS are located in register IS and can be set/cleared by SW by writing to
registers ISS and ISR.
Figure 112 gives an overview on the trap function.
The Trap Flag TRPF monitors the trap input and initiates the entry into the Trap State. The Trap State Bit TRPS
determines the effect on the outputs and controls the exit of the Trap State.
When a trap condition is detected (CTRAP = 0) and the input is enabled (TRPPEN = 1), both, the Trap Flag TRPF
and the Trap State Bit TRPS, are set to 1 (trap state active). The output of the Trap State Bit TRPS leads to the
Output Modulation Blocks (for T12 and for T13) and can there deactivate the outputs (set them to the passive
state). Individual enable control bits for each of the six T12-related outputs and the T13-related output facilitate a
flexible adaptation to the application needs.
There are a number of different ways to exit the Trap State. This offers SW the option to select the best operation
for the application. Exiting the Trap State can be done either immediately when the trap condition is removed
(CTRAP = 1 or TRPPEN = 0), or under software control, or synchronously to the PWM generated by either Timer
T12 or Timer T13.
RTRPF
Trap
Entry / Exit
Control
CTRAP
TRPPEN
STRPF
TRM2
TRPF
T12_ZM
T13_ZM
Trap Exit
Synchronization
TRPS
To T12,
T13 Output
Modulation
TRM0/1
CCU6_MCB05541
Figure 112 Trap Logic Block Diagram
Clearing of TRPF is controlled by the mode control bit TRPM2. If TRPM2 = 0, TRPF is automatically cleared by
HW when CTRAP returns to the inactive level (CTRAP = 1) or if the trap input is disabled (TRPPEN = 0). When
TRPM2 = 1, TRPF must be reset by SW after CTRAP has become inactive.
Clearing of TRPS is controlled by the mode control bits TRPM1 and TRPM0 (located in the Trap Control Register
TRPCTR). A reset of TRPS terminates the Trap State and returns to normal operation. There are three options
selected by TRPM1 and TRPM0. One is that the Trap State is left immediately when the Trap Flag TRPF is
cleared, without any synchronization to timers T12 or T13. The other two options facilitate the synchronization of
the termination of the Trap State to the count periods of either Timer T12 or Timer T13. Figure 113 gives an
overview on the associated operation.
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T12 Count
T13 Count
TRPF
CTRAP active
TRPS
Sync. to T12
TRPS
Sync. to T13
TRPS
No sync.
CCU6_MCT05542
Figure 113 Trap State Synchronization (with TRM2 = 0)
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17.5
Multi-Channel Mode
The Multi-Channel mode offers the possibility to modulate all six T12-related output signals with one instruction.
The bits in bit field MCMOUT.MCMP are used to specify the outputs that may become active. If Multi-Channel
mode is enabled (bit MODCTR.MCMEN = 1), only those outputs may become active, that have a 1 at the
corresponding bit position in bit field MCMP.
This bit field has its own shadow bit field MCMOUTS.MCMPS, that can be written by software. The transfer of the
new value in MCMPS to the bit field MCMP can be triggered by, and synchronized to, T12 or T13 events. This
structure permits the software to write the new value, that is then taken into account by the hardware at a welldefined moment and synchronized to a PWM signal. This avoids unintended pulses due to unsynchronized
modulation sources.
SWSYN
SWSEL
STRMCM
CM_CHE
CM_61
T12_PM
T12_OM
Switching
Synchronization
T12_ZM
T13_ZM
Switching
Event
Detection
Shadow Register
MCMOUTS.MCMPS
Shadow Transfer
MCM_ST
IDLE
set
T13_PM
CDIR
R
clear
STR
set
clear
Register
MCMOUT.MCMP
To Interrupt Control
T13_ST
T12_ST
T12/T13
Shadow
Transfer
Control
T12 Output Modulation
STE12U
STE12D
Outputs CC6x/COUT6x
STE13U
CCU6_MCB05535+
Figure 114 Multi-Channel Mode Block Diagram
Figure 114 shows the functional blocks for the Multi-Channel operation, controlled by bit fields in register
MCMCTR. The event that triggers the update of bit field MCMP is chosen by SWSEL. In order to synchronize the
update of MCMP to a PWM generated by T12 or T13, bit field SWSYN allows the selection of the synchronization
event leading to the transfer from MCMPS to MCMP. Due to this structure, an update takes place with a new PWM
period. A reminder flag R is set when the selected switching event occurs (the event is not necessarily
synchronous to the modulating PWM), and is cleared when the transfer takes place. This flag can be monitored
by software to check for the status of this logic block. If the shadow transfer from MCMPS to MCMP takes place,
bit IS.STR becomes set and an interrupt can be generated.
In addition to the Multi-Channel shadow transfer event MCM_ST, the shadow transfers for T12 (T12_ST) and T13
(T13_ST) can be generated to allow concurrent updates of applied duty cycles for T12 and/or T13 modulation and
Multi-Channel patterns.
If it is explicitly desired, the update takes place immediately with the occurrence of the selected event when the
direct synchronization mode is selected. The update can also be requested by software by writing to bit field
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MCMPS with the shadow transfer request bit STRMCM = 1. The option to trigger an update by SW is possible for
all settings of SWSEL.
By using the direct mode and bit STRMCM = 1, the update takes place completely under software control.
Table 65
Multi-Channel Mode Switching Event Selection
SWSEL
Selected Event (see register MCMCTR)
000B
No automatic event detection
001B
Correct Hall Event (CM_CHE) detected at input signals CCPOSx without additional delay
010B
T13 Period-Match (T13_PM)
011B
T12 One-Match while counting down (T12_OM and CDIR = 1)
100B
T12 Compare Channel 1 Event while counting up (CM_61 and CDIR = 0) to support the phase
delay function by CC61 for block commutation mode.
101B
T12 Period-Match while counting up (T12_PM and CDIR = 0)
110B, 111B
Reserved, no action
Table 66
Multi-Channel Mode Switching Synchronization
SWSYN
Synchronization Event (see register MCMCTR)
00B
Direct Mode: the trigger event directly causes the shadow transfer
01B
T13 Zero-Match (T13_ZM),
the MCM shadow transfer is synchronized to a T13 PWM
10B
T12 Zero-Match (T12_ZM),
the MCM shadow transfer is synchronized to a T12 PWM
11B
Reserved, no action
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17.6
Hall Sensor Mode
For Brushless DC-Motors in block commutation mode, the Multi-Channel Mode has been introduced to provide
efficient means for switching pattern generation. These patterns need to be output in relation to the angular
position of the motor. For this, usually Hall sensors or Back-EMF sensing are used to determine the angular rotor
position. The CCU6 provides three inputs, CCPOS0, CCPOS1, and CCPOS2, that can be used as inputs for the
Hall sensors or the Back-EMF detection signals.
There is a strong correlation between the motor position and the output modulation pattern. When a certain
position of the motor has been reached, indicated by the sampled Hall sensor inputs (the Hall pattern), the next,
pre-determined Multi-Channel Modulation pattern has to be output. Because of different machine types, the
modulation pattern for driving the motor can vary. Therefore, it is wishful to have a wide flexibility in defining the
correlation between the Hall pattern and the corresponding Modulation pattern. Furthermore, a hardware
mechanism significantly reduces the CPU for block-commutation.
The CCU6 offers the flexibility by having a register containing the currently assumed Hall pattern (CURH), the next
expected Hall pattern (EXPH) and the corresponding output pattern (MCMP). A new Modulation pattern is output
when the sampled Hall inputs match the expected ones (EXPH). To detect the next rotation phase (segment for
block commutation), the CCU6 monitors the Hall inputs for changes. When the next expected Hall pattern is
detected, the next corresponding Modulation pattern is output.
To increase for noise immunity (to a certain extend), the CCU6 offers the possibility to introduce a sampling delay
for the Hall inputs. Some changes of the Hall inputs are not leading to the expected Hall pattern, because they are
only short spikes due to noise. The Hall pattern compare logic compares the Hall inputs to the next expected
pattern and also to the currently assumed pattern to filter out spikes.
For the Hall and Modulation output patterns, a double-register structure is implemented. While register MCMOUT
holds the actually used values, its shadow register MCMOUTS can be loaded by software from a pre-defined table,
holding the appropriate Hall and Modulation patterns for the given motor control.
A transfer from the shadow register into register MCMOUT can take place when a correct Hall pattern change is
detected. Software can then load the next values into register MCMOUTS. It is also possible by software to force
a transfer from MCMOUTS into MCMOUT.
Note: The Hall input signals CCPOSx and the CURH and EXPH bit fields are arranged in the following order:
CCPOS0 corresponds to CURH.0 (LSB) and EXPH.0 (LSB)
CCPOS1 corresponds to CURH.1 and EXPH.1
CCPOS2 corresponds to CURH.2 (MSB) and EXPH.2 (MSB)
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17.6.1
Hall Pattern Evaluation
The Hall sensor inputs CCPOSx can be permanently monitored via an edge detection block (with the module clock
fCC6). In order to suppress spikes on the Hall inputs due to noise in rugged inverter environment, two optional noise
filtering methods are supported by the Hall logic (both methods can be combined).
•
•
Noise filtering with delay:
For this function, the mode control bit fields MSEL6x for all T12 compare channels must be programmed to
1000B and DBYP = 0. The selected event triggers Dead-Time Counter 0 to generate a programmable delay
(defined by bit field DTM). When the delay has elapsed, the evaluation signal HCRDY becomes activated.
Output modulation with T12 PWM signals is not possible in this mode.
Noise filtering by synchronization to PWM:
The Hall inputs are not permanently monitored by the edge detection block, but samples are taken only at
defined points in time during a PWM period. This can be used to sample the Hall inputs when the switching
noise (due to PWM) does not disturb the Hall input signals.
CCPOS 0..2
If neither the delay function of Dead-Time Counter 0 is not used for the Hall pattern evaluation nor the Hall mode
for Brushless DC-Drive control is enabled, the timer T12 block is available for PWM generation and output
modulation.
Hall
Compare
Logic
Hall
Inputs
HCRDY
Hall Pattern Evaluation
Edge
Detect
fCC6
Dead-Time
Counter 0
CM_63
T13_PM
T12_PM
Event
Selection
Delay
Bypass
CDIR
T12_OM
CM_61
HSYNC
DBYP
CCU6_MCB05553
Figure 115 Hall Pattern Evaluation
If the evaluation signal HCRDY (Hall Compare Ready, see Figure 116) becomes activated, the Hall inputs are
sampled and the Hall compare logic starts the evaluation of the Hall inputs.
Figure 115 illustrates the events for Hall pattern evaluation and the noise filter logic, Table 67 summarizes the
selectable trigger input signals.
Table 67
Hall Sensor Mode Trigger Event Selection
HSYNC
Selected Event (see register T12MSEL)
000B
Any edge at any of the inputs CCPOSx, independent from any PWM signal (permanent
check).
001B
A T13 Compare-Match (CM_63).
010B
A T13 Period-Match (T13_PM).
011B
Hall sampling triggered by HW sources is switched off.
100B
A T12 Period-Match while counting up (T12_PM and CDIR = 0).
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Table 67
Hall Sensor Mode Trigger Event Selection (cont’d)
HSYNC
Selected Event (see register T12MSEL)
101B
A T12 One-Match while counting down (T12_OM and CDIR = 1).
110B
A T12 Compare-Match of compare channel CC61 while counting up (CM_61 and CDIR = 0).
111B
A T12 Compare-Match of compare channel CC61 while counting down (CM_61 and
CDIR = 1).
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17.6.2
Hall Pattern Compare Logic
Figure 116 gives an overview on the double-register structure and the pattern compare logic. Software writes the
next modulation pattern (MCMPS) and the corresponding current (CURHS) and expected (EXPHS) Hall patterns
into the shadow register MCMOUTS. Register MCMOUT holds the actually used values CURH and EXPH. The
modulation pattern MCMP is provided to the T12 Output Modulation block. The current (CURH) and expected
(EXPH) Hall patterns are compared to the sampled Hall sensor inputs (visible in register CMPSTAT). Sampling of
the inputs and the evaluation of the comparator outputs is triggered by the evaluation signal HCRDY (Hall
Compare Ready), that is detailed in the next section.
Multi-Channel Mode Logic
SW Write
SW Write
CURHS
EXPHS
HP_ST
CURH
Hall Pattern
Evaluation
SW Write
MCMPS
MCM_ST
EXPH
HCRDY
MCMP
clear
T12 Output
Modulation
CM_CHE
Sample
CCPOS0..2
Hall
Inputs
Pattern Compare
CM_WHE
IDLE
Hall Compare Logic
CCU6_MCA05536
Figure 116 Hall Pattern Compare Logic
•
•
•
If the sampled Hall pattern matches the value programmed in CURH, the detected transition was a spike (no
Hall event) and no further actions are necessary.
If the sampled Hall pattern matches the value programmed in EXPH, the detected transition was the expected
event (correct Hall event CM_CHE) and the MCMP value has to change.
If the sampled Hall pattern matches neither CURH nor EXPH, the transition was due to a major error (wrong
Hall event CM_CWE) and can lead to an emergency shut down (IDLE).
At every correct Hall event (CM_CHE), the next Hall patterns are transferred from the shadow register MCMOUTS
into MCMOUT (Hall pattern shadow transfer HP_ST), and a new Hall pattern with its corresponding output pattern
can be loaded (e.g. from a predefined table in memory) by software into MCMOUTS. For the Modulation patterns,
signal MCM_ST is used to trigger the transfer.
Loading this shadow register can also be done by writing MCMOUTS.STRHP = 1 (for EXPH and CURH) or
MCMOUTS.STRMCMP = 1 (for MCMP).
17.6.3
Hall Mode Flags
Depending on the Hall pattern compare operation, a number of flags are set in order to indicate the status of the
module and to trigger further actions and interrupt requests.
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Flag IS.CHE (Correct Hall Event) is set by signal CM_CHE when the sampled Hall pattern matches the expected
one (EXPH). This flag can also be set by SW by setting bit ISS.SCHE = 1. If enabled by bit IEN.ENCHE = 1, the
set signal for CHE can also generate an interrupt request to the CPU. Bit field INP.INPCHE defines which service
request output becomes activated in case of an interrupt request.To clear flag CHE, SW needs to write
ISR.RCHE = 1.
Flag IS.WHE indicates a Wrong Hall Event. Its handling for flag setting and resetting as well as interrupt request
generation are similar to the mechanism for flag CHE.
The implementation of flag STR is done in the same way as for CHE and WHE. This flag is set by HW by the
shadow transfer signal MCM_ST (see also Figure 114).
Please note that for flags CHE, WHE, and STR, the interrupt request generation is triggered by the set signal for
the flag. That means, a request can be generated even if the flag is already set. There is no need to clear the flag
in order to enable further interrupt requests.
The implementation for the IDLE flag is different. It is set by HW through signal CM_WHE if enabled by bit ENIDLE.
Software can also set the flag via bit SIDLE. As long as bit IDLE is set, the modulation pattern field MCMP is
cleared to force the outputs to the passive state. Flag IDLE must be cleared by software by writing RIDLE = 1 in
order to return to normal operation. To fully restart from IDLE mode, the transfer requests for the bit fields in
register MCMOUTS to register MCMOUT have to be initiated by software via bits STRMCM and STRHP in register
MCMOUTS. In this way, the release from IDLE mode is under software control, but can be performed
synchronously to the PWM signal.
Clear
RCHE
SCHE
CHE
INPCHE
To SR0
Set
_
>1
To SR1
To SR2
CM_CHE
To SR3
ENCHE
Hall Compare
Logic
CM_WHE
Clear
RWHE
SWHE
WHE
INPERR
To SR0
Set
_
>1
To SR1
To SR2
To SR3
ENWHE
ENIDLE
SIDLE
_
>1
Set
IDLE
Clear
MCMP
Clear
RIDLE
CCU6_MCA05540
Figure 117 Hall Mode Flags
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17.6.4
Hall Mode for Brushless DC-Motor Control
The CCU6 provides a mode for the Timer T12 Block especially targeted for convenient control of block
commutation patterns for Brushless DC-Motors. This mode is selected by setting all T12MSEL.MSEL6x bit fields
of the three T12 Channels to 1000B.
In this mode, illustrated in Figure 118, channel CC60 is placed in capture mode to measure the time elapsed
between the last two correct Hall events, channel CC61 in compare mode to provide a programmable phase delay
between the Hall event and the application of a new PWM output pattern, and channel CC62 also in compare
mode as first time-out criterion. A second time-out criterion can be built by the T12 period match event.
fT12
Counter Register
T12
Clear
Hall Compare
Logic
CM_CHE
CM_61
Capture Register
CC60R
Comp.
=?
Comp.
=?
Compare Register
CC61R
Compare Register
CC62R
Compare Shadow
Register CC61SR
Compare Shadow
Register CC62SR
CM_62
CCU6_MCA05538
Figure 118 T12 Block in Hall Sensor Mode
The signal CM_CHE from the Hall compare logic is used to transfer the new compare values from the shadow
registers CC6xSR into the actual compare registers CC6xR, performs the shadow transfer for the T12 period
register, to capture the current T12 contents into register CC60R, and to clear T12.
Note: In this mode, the shadow transfer signal T12_ST is not generated. Not all shadow bits, such as the PSLy
bits, will be transferred to their main registers. To program the main registers, SW needs to write to these
registers while Timer T12 is stopped. In this case, a SW write actualizes both registers.
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CC62 Compare
for Time-Out
Hall Event captures
and resets T12
CC62 Comp.
T12 Count
CC61 Compare
for Phase Delay
CC61 Comp.
0000 H
CCPOS0
1
1
1
0
0
CCPOS1
0
0
1
1
1
CCPOS2
1
0
0
0
1
CURH
= 101
= 001
= 011
= 010
= 110
EXPH
= 001
= 011
= 010
= 110
= 100
MCMP
Phase Delay
CC6x
COUT6y
CCU6_MCT05539
Figure 119 Brushless DC-Motor Control Example (all MSEL6x = 1000B)
After the detection of an expected Hall pattern (CM_CHE active), the T12 count value is captured into channel
CC60 (representing the actual rotor speed by measuring the elapsed time between the last two correct Hall
events), and T12 is reset. When the timer reaches the compare value in channel CC61, the next multi-channel
state is switched by triggering the shadow transfer of bit field MCMP (if enabled in bit field SWEN). This trigger
event can be combined with the synchronization of the next multi-channel state to the PWM source (to avoid
spikes on the output lines, see Section 17.5). This compare function of channel CC61 can be used as a phase
delay from the position sensor input signals to the switching of the output signals, that is necessary if a sensorless
back-EMF technique or Hall sensors are used. The compare value in channel CC62 can be used as a time-out
trigger (interrupt), indicating that the actual motor speed is far below the desired destination value. An abnormal
load change can be detected with this feature and PWM generation can be disabled.
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17.7
Interrupt Handling
This section describes the interrupt handling of the CCU6 module.
17.7.1
Interrupt Structure
The HW interrupt event or the SW setting of the corresponding interrupt set bit (in register ISS) sets the event
indication flags (in register IS) and can trigger the interrupt generation. The interrupt pulse is generated
independently from the interrupt status flag in register IS (it is not necessary to clear the related status bit to be
able to generate another interrupt). The interrupt flag can be cleared by SW by writing to the corresponding bit in
register ISR.
If enabled by the related interrupt enable bit in register IEN, an interrupt pulse can be generated on one of the four
service request outputs (SR0 to SR3) of the module. If more than one interrupt source is connected to the same
interrupt node pointer (in register INP), the requests are logically OR-combined to one common service request
output (see Figure 120).
SW Requests
Clear
Interrupt
Clear
Interrupt
Status
Set
Interrupt
Enable
Set Interrupt
Interrupt
Node Pointer
To SR0
_
>1
To SR1
To SR2
To SR3
HW Interrupt
Event
CCU6_MCA05549
Figure 120 General Interrupt Structure
The available interrupt events in the CCU6 are shown in Figure 121.
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T12_PM
T12 Counter
T12_OM
CDIR
T12 Capture
Compare
Channels CC6x
T13 Counter
T13 Compare
Channel CC63
SR0
Interrupt Request
Reg. CC6x_0IC
SR1
Interrupt Request
Reg. CC6x_1IC
SR2
Interrupt Request
Reg. CC6x_2IC
SR3
Interrupt Request
Reg. CC6x_3IC
CC6x_R
CC6x_F
T13_PM
CM_63
Interrupt
Control Logic
Interrupt Set
Register ISS
Interrupt Status
Register IS
Multi-Channel
Mode Logic
STR
Interrupt Reset
Register ISR
CM_CHE
Hall Compare
Logic
CM_WHE
Interrupt Enable
Register IEN
TRPF
Trap Handling
Node Pointer
Register INP
TRPS
CCU6_MCA05548
Figure 121 Interrupt Sources and Events
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Capture/Compare Unit 6 (CCU6)
17.8
General Module Operation
This section provides information about the:
•
Input selection (see Section 17.8.1)
17.8.1
Input Selection
Each CCU6 input signal can be selected from a vector of four or eight possible inputs by programming the port
input select registers PISEL0 and PISEL2. This permits to adapt the pin functionality of the device to the
application requirements.
The output pins for the module output signals are chosen in the ports.
Note: All functional inputs of the CCU6 are synchronized to fCC6 before they affect the module internal logic. The
resulting delay of 2/fCC6 and for asynchronous signals an additional uncertainty of 1/fCC6 have to be taken
into account for precise timing calculation. An edge of an input signal can only be correctly detected if the
high phase and the low phase of the input signal are both longer than 1/fCC6.
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17.9
CCU6 Register Description
All CCU6 kernel register names described in this section will be referenced in other parts of this specification with
the module name prefix “CCU6_”.
Table 68 lists the CCU6 registers.
Note: If a hardware and a software request to modify a bit occur simultaneously, the software wins.
Table 68
Registers Overview
Register Short
Name
Register Long Name
Description see
PISEL0L
Port Input Select Register 0 Low
Page 21-379
PISEL0H
Port Input Select Register 0 High
Page 21-380
PISEL2
Port Input Select Register 2
Page 21-381
T12L
Timer T12 Counter Register Low
Page 21-385
T12H
Timer T12 Counter Register High
Page 21-385
T12PRL
Timer T12 Period Register Low
Page 21-386
T12PRH
Timer T12 Period Register High
Page 21-386
CC6xRL
Capture/Compare Register for Channel CC6x Low
Page 21-386
CC6xRH
Capture/Compare Register for Channel CC6x High
Page 21-387
CC6xSRL
Compare Shadow Register for Channel CC6x Low
Page 21-387
CC6xSRH
Compare Shadow Register for Channel CC6x High
Page 21-387
T12DTCL
Timer T12 Dead-Time Control Register Low
Page 21-388
T12DTCH
Timer T12 Dead-Time Control Register High
Page 21-388
T13L
Timer T13 Counter Register Low
Page 21-389
T13H
Timer T13 Counter Register High
Page 21-390
T13PRL
Timer T13 Period Register Low
Page 21-390
T13PRH
Timer T13 Period Register High
Page 21-390
CC63RL
Compare Register T13 Low
Page 21-391
CC63RH
Compare Register T13 High
Page 21-392
CC63SRL
Compare Shadow Register T13 Low
Page 21-391
CC63SRH
Compare Shadow Register T13 High
Page 21-392
System Registers
Timer T12 Registers
Timer T13 Registers
CCU6 Control Registers
CMPSTATL
Compare State Register High
Page 21-392
CMPSTATH
Compare State Register High
Page 21-393
CMPMODIFL
Compare State Modification Register Low
Page 21-393
CMPMODIFH
Compare State Modification Register High
Page 21-394
T12MSELL
T12 Mode Select Register Low
Page 21-383
T12MSELH
T12 Mode Select Register High
Page 21-383
TCTR0L
Timer Control Register 0 Low
Page 21-395
TCTR0H
Timer Control Register 0 High
Page 21-396
TCTR2L
Timer Control Register 2 Low
Page 21-397
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Capture/Compare Unit 6 (CCU6)
Table 68
Registers Overview (cont’d)
Register Short
Name
Register Long Name
Description see
TCTR2H
Timer Control Register 2 High
Page 21-398
TCTR4L
Timer Control Register 4 Low
Page 21-399
TCTR4H
Timer Control Register 4 High
Page 21-400
Modulation Control Registers
MODCTRL
Modulation Control Register Low
Page 21-401
MODCTRH
Modulation Control Register High
Page 21-401
TRPCTRL
Trap Control Register Low
Page 21-402
TRPCTRH
Trap Control Register High
Page 21-403
PSLR
Passive State Level Register
Page 21-404
MCMOUTSL
Multi_Channel Mode Output Shadow Register Low
Page 21-405
MCMOUTSH
Multi_Channel Mode Output Shadow Register High
Page 21-406
MCMOUTL
Multi_Channel Mode Output Register Low
Page 21-407
MCMOUTH
Multi_Channel Mode Output Register High
Page 21-407
MCMCTRL
Multi_Channel Mode Control Register Low
Page 21-408
MCMCTRH
Multi_Channel Mode Control Register High
Page 21-409
Interrupt Control Registers
ISL
Interrupt Status Register Low
Page 21-410
ISH
Interrupt Status Register High
Page 21-411
ISSL
Interrupt Status Set Register Low
Page 21-412
ISSH
Interrupt Status Set Register High
Page 21-413
ISRL
Interrupt Status Reset Register Low
Page 21-414
ISRH
Interrupt Status Reset Register High
Page 21-415
IENL
Interrupt Enable Register Low
Page 21-416
IENH
Interrupt Enable Register High
Page 21-417
INPL
Interrupt Node Pointer Register Low
Page 21-418
INPH
Interrupt Node Pointer Register High
Page 21-419
17.9.1
Register Mapping
The BPI of the CCU6 supports the local address extension mechanism. The SFRs of the CCU6 kernel are
organized into four pages. Please refer to Chapter 7 for details on the local address extension.
The addresses (non-mapped) of the kernel SFRs are listed in Table 69.
Table 69
SFR Address List for Pages 0-3
Address
Page 0
Page 1
Page 2
Page 3
9AH
CC63SRL
CC63RL
T12MSELL
MCMOUTL
9BH
CC63SRH
CC63RH
T12MSELH
MCMOUTH
9CH
TCTR4L
T12PRL
IENL
ISL
9DH
TCTR4H
T12PRH
IENH
ISH
9EH
MCMOUTSL
T13PRL
INPL
PISEL0L
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Table 69
SFR Address List for Pages 0-3 (cont’d)
Address
Page 0
Page 1
Page 2
Page 3
9FH
MCMOUTSH
T13PRH
INPH
PISEL0H
A4H
ISRL
T12DTCL
ISSL
PISEL2
A5H
ISRH
T12DTCH
ISSH
A6H
CMPMODIFL
TCTR0L
PSLR
A7H
CMPMODIFH
TCTR0H
MCMCTRL
MCMCTRH
FAH
CC60SRL
CC60RL
TCTR2L
T12L
FBH
CC60SRH
CC60RH
TCTR2H
T12H
FCH
CC61SRL
CC61RL
MODCTRL
T13L
FDH
CC61SRH
CC61RH
MODCTRH
T13H
FEH
CC62SRL
CC62RL
TRPCTRL
CMPSTATL
FFH
CC62SRH
CC62RH
TRPCTRH
CMPSTATH
SFR CCU_PAGE, at address A3H, contains the page value and the page control information.
CCU6_PAGE
Page Register for CCU6
7
6
Reset Value: 00H
5
4
3
2
1
OP
STNR
PAGE
w
w
rwh
0
Field
Bits
Type
Description
PAGE
3:0
rwh
Page Bits
When written, the value indicates the new page address.
When read, the value indicates the currently active page = addr [y:x+1]
STNR
5:4
w
Storage Number
This number indicates which storage bit field is the target of the
operation defined by bit OP.
If OP = 10B,
the contents of PAGE are saved in STx before being overwritten with
the new value.
If OP = 11B,
the contents of PAGE are overwritten by the contents of STx. The
value written to the bit positions of PAGE is ignored.
00B ST0 is selected.
01B ST1 is selected.
10B ST2 is selected.
11B ST3 is selected.
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Field
Bits
Type
Description
OP
7:6
w
Operation
0XB Manual page mode. The value of STNR is ignored and PAGE is
directly written.
10B New page programming with automatic page saving. The value
written to the bit positions of PAGE is stored. In parallel, the
former contents of PAGE are saved in the storage bit field STx
indicated by STNR.
11B Automatic restore page action. The value written to the bit
positions PAGE is ignored and instead, PAGE is overwritten by
the contents of the storage bit field STx indicated by STNR.
17.9.2
System Registers
Registers PISEL0 and PISEL2 contain bit fields that select the actual input port/signal for the module inputs. This
permits the adaptation of the pin functionality of the device to the application’s requirements. The output pins are
chosen according to the registers in the ports.
PISEL0L
Port Input Select Register 0 Low
7
6
Reset Value: 00H
5
4
3
2
1
0
ISTRP
ISCC62
ISCC61
ISCC60
rw
rw
rw
rw
Field
Bits
Type
Description
ISCC60
1:0
rw
Input Select for CC60
This bit field defines the port pin that is used for the CC60 capture input
signal.
00B The input pin for CC60_0.
01B The input pin for CC60_1.
10B Reserved
11B Reserved
ISCC61
3:2
rw
Input Select for CC61
This bit field defines the port pin that is used for the CC61 capture input
signal.
00B The input pin for CC61_0.
01B The input pin for CC61_1.
10B Reserved
11B Reserved
ISCC62
5:4
rw
Input Select for CC62
This bit field defines the port pin that is used for the CC62 capture input
signal.
00B The input pin for CC62_0.
01B The input pin for CC62_0.
10B Reserved
11B Reserved
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Field
Bits
Type
Description
ISTRP
7:6
rw
Input Select for CTRAP
This bit field defines the port pin that is used for the CTRAP input
signal.
00B The input pin for CTRAP_0.
01B The input pin for CTRAP_1.
10B Reserved
11B Reserved
PISEL0H
Port Input Select Register 0 High
7
6
Reset Value: 00H
5
4
3
2
1
0
IST12HR
ISPOS2
ISPOS1
ISPOS0
rw
rw
rw
rw
Field
Bits
Type
Description
ISPOS0
1:0
rw
Input Select for CCPOS0
This bit field defines the port pin that is used for the CCPOS0 input
signal.
00B The input pin for CCPOS0_0.
01B The input pin for CCPOS0_1.
10B The input pin for CCPOS0_2.
11B Reserved
ISPOS1
3:2
rw
Input Select for CCPOS1
This bit field defines the port pin that is used for the CCPOS1 input
signal.
00B The input pin for CCPOS1_0.
01B The input pin for CCPOS1_1.
10B The input pin for CCPOS1_2.
11B Reserved
ISPOS2
5:4
rw
Input Select for CCPOS2
This bit field defines the port pin that is used for the CCPOS2 input
signal.
00B The input pin for CCPOS2_0.
01B The input pin for CCPOS2_1.
10B The input pin for CCPOS2_2.
11B Reserved
IST12HR
7:6
rw
Input Select for T12HR
This bit field defines the input signal used as T12HR input.
00B Either signal T12HRA (if T12EXT = 0) or T12HRE (if
T12EXT = 1) is selected.
01B Either signal T12HRB (if T12EXT = 0) or T12HRF (if
T12EXT = 1) is selected.
10B Either signal T12HRC (if T12EXT = 0) or T12HRG (if
T12EXT = 1) is selected.
11B Either signal T12HRD (if T12EXT = 0) or T12HRH (if
T12EXT = 1) is selected.
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PISEL2
Port Input Select Register 2
Reset Value: 00H
7
6
5
4
3
2
1
0
T13EXT
T12EXT
ISCNT13
ISCNT12
IST13HR
rw
rw
rw
rw
rw
Field
Bits
Type
Description
IST13HR
1:0
rw
Input Select for T13HR
This bit field defines the input signal used as T13HR input.
00B Either signal T13HRA (if T13EXT = 0) or T13HRE (if
T13EXT = 1) is selected.
01B Either signal T13HRB (if T13EXT = 0) or T13HRF (if T13EXT = 1)
is selected.
10B Either signal T13HRC (if T13EXT = 0) or T13HRG (if
T13EXT = 1) is selected.
11B Either signal T13HRD (if T13EXT = 0) or T13HRH (if
T13EXT = 1) is selected.
ISCNT12
3:2
rw
Input Select for T12 Counting Input
This bit field defines the input event leading to a counting action of T12.
00B The T12 prescaler generates the counting events. Bit
TCTR4.T12CNT is not taken into account.
01B Bit TCTR4.T12CNT written with 1 is a counting event. The T12
prescaler is not taken into account.
10B The timer T12 is counting each rising edge detected in the
selected T12HR signal.
11B The timer T12 is counting each falling edge detected in the
selected T12HR signal.
ISCNT13
5:4
rw
Input Select for T13 Counting Input
This bit field defines the input event leading to a counting action of T13.
00B The T13 prescaler generates the counting events. Bit
TCTR4.T13CNT is not taken into account.
01B Bit TCTR4.T13CNT written with 1 is a counting event. The T13
prescaler is not taken into account.
10B The timer T13 is counting each rising edge detected in the
selected T13HR signal.
11B The timer T13 is counting each falling edge detected in the
selected T13HR signal.
T12EXT
6
rw
Extension for T12HR Inputs
This bit extends the 2-bit field IST12HR.
One of the signals T12HR[D:A] is selected.
0B
One of the signals T12HR[H:E] is selected.
1B
T13EXT
7
rw
Extension for T13HR Inputs
This bit extends the 2-bit field IST13HR.
One of the signals T13HR[D:A] is selected.
0B
One of the signals T13HR[H:E] is selected.
1B
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Capture/Compare Unit 6 (CCU6)
17.9.3
Timer 12 – Related Registers
The generation of the patterns for a 3-channel PWM is based on timer T12. The registers related to timer T12 can
be concurrently updated (with well-defined conditions) in order to ensure consistency of the three PWM channels.
Timer T12 supports capture and compare modes, which can be independently selected for the three channels
CC60, CC61, and CC62.
Register T12MSEL contains control bits to select the capture/compare functionality of the three channels of timer
T12. Table 70, Table 71 and Table 72 define and elaborate some of the capture/compare modes selectable.
Refer to the following register description for the selection.
Table 70
Double-Register Capture Modes
Description
0100B
The contents of T12 are stored in CC6nR after a rising edge and in CC6nSR after a falling edge on
the input pin CC6n.
0101B
The value stored in CC6nSR is copied to CC6nR after a rising edge on the input pin CC6n. The actual
timer value of T12 is simultaneously stored in the shadow register CC6nSR. This feature is useful for
time measurements between consecutive rising edges on pins CC6n. COUT6n is I/O.
0110B
The value stored in CC6nSR is copied to CC6nR after a falling edge on the input pin CC6n. The actual
timer value of T12 is simultaneously stored in the shadow register CC6nSR. This feature is useful for
time measurements between consecutive falling edges on pins CC6n. COUT6n is I/O.
0111B
The value stored in CC6nSR is copied to CC6nR after any edge on the input pin CC6n. The actual
timer value of T12 is simultaneously stored in the shadow register CC6nSR. This feature is useful for
time measurements between consecutive edges on pins CC6n. COUT6n is I/O.
Table 71
Combined T12 Modes
Description
1000B
Hall Sensor mode:
Capture mode for channel 0, compare mode for channels 1 and 2. The contents of T12 are captured
into CC60 at a valid hall event (which is a reference to the actual speed). CC61 can be used for a
phase delay function between hall event and output switching. CC62 can act as a time-out trigger if
the expected hall event comes too late. The value 1000B must be programmed to MSEL0, MSEL1 and
MSEL2 if the hall signals are used. In this mode, the contents of timer T12 are captured in CC60 and
T12 is reset after the detection of a valid hall event. In order to avoid noise effects, the dead-time
counter channel 0 is started after an edge has been detected at the hall inputs. On reaching the value
of 000001B, the hall inputs are sampled and the pattern comparison is done.
1001B
Hysteresis-like control mode with dead-time generation:
The negative edge of the CCPOSx input signal is used to reset bit CC6nST. As a result, the output
signals can be switched to passive state immediately and switch back to active state (with dead-time)
if the CCPOSx is high and the bit CC6nST is set by a compare event.
Table 72
Multi-Input Capture Modes
Description
1010B
The timer value of T12 is stored in CC6nR after a rising edge at the input pin CC6n. The timer value
of T12 is stored in CC6nSR after a falling edge at the input pin CCPOSx.
1011B
The timer value of T12 is stored in CC6nR after a falling edge at the input pin CC6n. The timer value
of T12 is stored in CC6nSR after a rising edge at the input pin CCPOSx.
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Capture/Compare Unit 6 (CCU6)
Table 72
Multi-Input Capture Modes
Description
1100B
The timer value of T12 is stored in CC6nR after a rising edge at the input pin CC6n. The timer value
of T12 is stored in CC6nSR after a rising edge at the input pin CCPOSx.
1101B
The timer value of T12 is stored in CC6nR after a falling edge at the input pin CC6n. The timer value
of T12 is stored in CC6nSR after a falling edge at the input pin CCPOSx.
1110B
The timer value of T12 is stored in CC6nR after any edge at the input pin CC6n. The timer value of
T12 is stored in CC6nSR after any edge at the input pin CCPOSx.
1111B
reserved (no capture or compare action)
T12MSELL
T12 Capture/Compare Mode Select Register Low
7
6
5
Reset Value: 00H
4
3
2
1
MSEL61
MSEL60
rw
rw
Field
Bits
Type
MSEL60, MSEL61
3:0, 7:4 rw
Description
Capture/Compare Mode Selection
These bit fields select the operating mode of the three timer T12
capture/compare channels. Each channel (n = 0, 1, 2) can be
programmed individually either for compare or capture operation
according to:
0000BCompare outputs disabled, pins CC6n and COUT6n can be used
for I/O. No capture action.
0001BCompare output on pin CC6n, pin COUT6n can be used for I/O. No
capture action.
0010BCompare output on pin COUT6n, pin CC6n can be used for I/O. No
capture action.
0011BCompare output on pins COUT6n and CC6n.
01XXBDouble-Register Capture modes, see Table 70.
1000BHall Sensor mode, see Table 71. In order to enable the hall edge
detection, all three MSEL6x must be programmed to Hall Sensor
mode.
1001BHysteresis-like mode, see Table 71.
101XBMulti-Input Capture modes, see Table 72.
11XXBMulti-Input Capture modes, see Table 72.
T12MSELH
T12 Capture/Compare Mode Select Register High
7
6
5
Reset Value: 00H
4
3
2
1
D
BYP
HSYNC
MSEL62
rw
rw
rw
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
MSEL62
3:0
rw
Capture/Compare Mode Selection
These bit fields select the operating mode of the three timer T12
capture/compare channels. Each channel (n = 0, 1, 2) can be
programmed individually either for compare or capture operation
according to:
0000BCompare outputs disabled, pins CC6n and COUT6n can be
used for I/O. No capture action.
0001BCompare output on pin CC6n, pin COUT6n can be used for I/O.
No capture action.
0010BCompare output on pin COUT6n, pin CC6n can be used for I/O.
No capture action.
0011BCompare output on pins COUT6n and CC6n.
01XXBDouble-Register Capture modes, see Table 70.
1000BHall Sensor mode, see Table 71. In order to enable the hall
edge detection, all three MSEL6x must be programmed to Hall
Sensor mode.
1001BHysteresis-like mode, see Table 71.
101XBMulti-Input Capture modes, see Table 72.
11XXBMulti-Input Capture modes, see Table 72.
HSYNC
6:4
rw
Hall Synchronization
Bit field HSYNC defines the source for the sampling of the Hall input
pattern and the comparison to the current and the expected Hall
pattern bit fields. In all modes, a trigger by software by writing a 1 to bit
SWHC is possible.
000B Any edge at one of the inputs CCPOSx (x = 0, 1, 2) triggers the
sampling.
001B A T13 compare-match triggers the sampling.
010B A T13 period-match triggers the sampling.
011B The Hall sampling triggered by hardware sources is switched off.
100B A T12 period-match (while counting up) triggers the sampling.
101B A T12 one-match (while counting down) triggers the sampling.
110B A T12 compare-match of channel 0 (while counting up) triggers
the sampling.
111B A T12 compare-match of channel 0 (while counting down)
triggers the sampling.
DBYP
7
rw
Delay Bypass
Bit DBYP defines if the source signal for the sampling of the Hall input
pattern (selected by HSYNC) uses the dead-time counter DTC0 of
timer T12 as additional delay or if the delay is bypassed.
The delay bypass is not active. The dead-time counter DTC0 is
0B
generating a delay after the source signal becomes active.
The delay bypass is active. The dead-time counter DTC0 is not
1B
used by the sampling of the Hall pattern.
Note: In the capture modes, all edges at the CC6x inputs lead to the setting of the corresponding interrupt status
flags in register IS. In order to monitor the selected capture events at the CCPOSx inputs in the multi-input
capture modes, the CC6xST bits of the corresponding channel are set when detecting the selected event.
The interrupt status bits and the CC6xST bits must be reset by software.
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Register T12 represents the counting value of timer T12. It can only be written while the timer T12 is stopped. Write
actions while T12 is running are not taken into account. Register T12 can always be read by software.
In edge-aligned mode, T12 only counts up, whereas in center-aligned mode, T12 can count up and down.
T12L
Timer T12 Counter Register Low
7
6
5
Reset Value: 00H
4
3
2
1
0
T12CVL
rwh
Field
Bits
Type
Description
T12CVL
7:0
rwh
Timer T12 Counter Value Low Byte
This register represents the lower 8-bit counter value of timer T12.
T12H
Timer T12 Counter Register High
7
6
5
Reset Value: 00H
4
3
2
1
0
T12CVH
rwh
Field
Bits
Type
Description
T12CVH
7:0
rwh
Timer T12 Counter Value High Byte
This register represents the upper 8-bit counter value of timer T12.
Note: While timer T12 is stopped, the internal clock divider is reset in order to ensure reproducible timings and
delays.
Note: The timer period, compare values, passive state selects bits and passive levels bits for both timers are
written to shadow registers and not directly to the actual registers. Thus, the values for a new output signal
can be programmed without disturbing the currently generated signal(s). The transfer from the shadow
registers to the actual registers is enabled by setting the respective shadow transfer enable bit STEx.
If the transfer is enabled, the shadow registers are copied to the respective registers as soon as the
associated timer reaches the value zero the next time (being cleared in edge-aligned mode or counting down
from 1 in center-aligned mode). When timer T12 is operating in center-aligned mode, it will also copy the
registers (if enabled by STE12) if it reaches the currently programmed period value (counting up).
When a timer is stopped (TxR = 0), the shadow transfer takes place immediately if the corresponding bit
STEx is set.
After the transfer, the respective bit STEx is cleared automatically.
Register T12PR contains the period value for timer T12. The period value is compared to the actual counter value
of T12 and the resulting counter actions depend on the defined counting rules. This register has a shadow register
and the shadow transfer is controlled by bit STE12. A read action by software delivers the value which is currently
used for the compare action, whereas the write action targets a shadow register. The shadow register structure
allows a concurrent update of all T12-related values.
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Capture/Compare Unit 6 (CCU6)
T12PRL
Timer T12 Period Register Low
7
Reset Value: 00H
6
5
4
3
2
1
0
T12PVL
rwh
Field
Bits
Type
Description
T12PVL
7:0
rwh
T12 Period Value Low Byte
The value T12PV defines the counter value for T12, which leads to a
period-match. On reaching this value, the timer T12 is set to zero
(edge-aligned mode) or changes its count direction to down counting
(center-aligned mode).
T12PRH
Timer T12 Period Register High
7
6
Reset Value: 00H
5
4
3
2
1
0
T12PVH
rwh
Field
Bits
Type
Description
T12PVH
7:0
rwh
T12 Period Value High Byte
The value T12PV defines the counter value for T12, which leads to a
period-match. On reaching this value, the timer T12 is set to zero
(edge-aligned mode) or changes its count direction to down counting
(center-aligned mode).
In compare mode, the registers CC6xR (x = 0, 1, 2) are the actual compare registers for T12. The values stored
in CC6xR are compared (all three channels in parallel) to the counter value of T12. In capture mode, the current
value of the T12 counter register is captured by registers CC6xR if the corresponding capture event is detected.
CC6xRL (x = 0, 1, 2)
Capture/Compare Register for Channel CC6x Low
7
6
5
Reset Value: 00H
4
3
2
1
0
CCVL
rh
Field
Bits
Type
Description
CCVL
7:0
rh
Channel x Capture/Compare Value Low Byte
In compare mode, the bit fields CCV contain the values that are
compared to the T12 counter value. In capture mode, the captured
value of T12 can be read from these registers.
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Capture/Compare Unit 6 (CCU6)
CC6xRH (x = 0, 1, 2)
Capture/Compare Register for Channel CC6x High
7
6
5
Reset Value: 00H
4
3
2
1
0
CCVH
rh
Field
Bits
Type
Description
CCVH
7:0
rh
Channel x Capture/Compare Value High Byte
In compare mode, the bit fields CCV contain the values that are
compared to the T12 counter value. In capture mode, the captured
value of T12 can be read from these registers.
The registers CC6xR can only be read by software, the modification of the value is done by a shadow register
transfer from register CC6xSR. The corresponding shadow registers CC6xSR can be read and written by
software. In capture mode, the value of the T12 counter register can also be captured by registers CC6xSR if the
selected capture event is detected (depending on the selected mode).
CC6xSRL (x = 0, 1, 2)
Capture/Compare Shadow Register for Channel CC6x Low
7
6
5
4
3
Reset Value: 00H
2
1
0
CCSL
rwh
Field
Bits
Type
Description
CCSL
7:0
rwh
Shadow Register for Channel x Capture/Compare Value Low
Byte
In compare mode, the contents of bit field CCS are transferred to
the bit field CCV for the corresponding channel during a shadow
transfer. In capture mode, the captured value of T12 can be read
from these registers.
CC6xSRH (x = 0, 1, 2)
Capture/Compare Shadow Register for Channel CC6x High
7
6
5
4
3
Reset Value: 00H
2
1
0
CCSH
rwh
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TLE983x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
CCSH
7:0
rwh
Shadow Register for Channel x Capture/Compare Value High
Byte
In compare mode, the contents of bit field CC6xS are transferred
to the bit field CC6xV for the corresponding channel during a
shadow transfer. In capture mode, the captured value of T12 can
be read from these registers.
Note: The shadow registers can also be written by SW in capture mode. In this case, the HW capture event wins
over the SW write if both happen in the same cycle (the SW write is discarded).
Register T12DTC controls the dead-time generation for the timer T12 compare channels. Each channel can be
independently enabled/disabled for dead-time generation. If enabled, the transition from passive state to active
state is delayed by the value defined by bit field DTM. The dead-time counter can only be reloaded while it is zero.
The dead time counters are clocked with the same frequency as T12. This structure allows symmetrical dead-time
generation in center-aligned and in edge-aligned PWM mode. A duty cycle of 50% leads to CC6x, COUT6x
switched on for: 0.5 * period - dead time.
Note: The dead-time counters are not reset by bit T12RES, but by bit DTRES.
T12DTCL
Dead-Time Control Register for Timer T12 Low
7
6
5
Reset Value: 00H
4
3
2
1
0
DTM
rw
Field
Bits
Type
Description
DTM
7:0
rw
Dead-Time
Bit field DTM determines the programmable delay between switching
from the passive state to the active state of the selected outputs. The
switching from the active state to the passive state is not delayed.
T12DTCH
Dead-Time Control Register for Timer T12 High
Reset Value: 00H
7
6
5
4
3
2
1
0
0
DTR2
DTR1
DTR0
0
DTE2
DTE1
DTE0
r
rh
rh
rh
r
rw
rw
rw
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TLE983x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
DTEx (x = 0, 1, 2)
2:0
rw
Dead-Time Enable Bits
Bits DTE0..DTE2 enable and disable the dead-time generation for
each compare channel (0, 1, 2) of timer T12.
Dead-time generation is disabled. The corresponding outputs
0B
switch from the passive state to the active state (according to the
actual compare status) without any delay.
Dead-time generation is enabled. The corresponding outputs
1B
switch from the passive state to the active state (according to the
compare status) with the delay programmed in bit field DTM.
DTRx (x = 0, 1, 2)
6:4
rh
Dead-Time Run Indication Bits
Bits DTR0..DTR2 indicate the status of the dead-time generation for
each compare channel (0, 1, 2) of timer T12.
The value of the corresponding dead-time counter channel is 0.
0B
The value of the corresponding dead-time counter channel is not
1B
0.
0
3, 7
r
Reserved
Returns 0 if read; should be written with 0.
Note: The dead-time counters are clocked with the same frequency as T12.
This structure allows symmetrical dead-time generation in center-aligned and in edge-aligned PWM mode.
A duty cycle of 50% leads to CC6x, COUT6x switched on for: 0.5 * period - dead-time.
Note: The dead-time counters are not reset by bit T12RES, but by bit DTRES.
17.9.4
Timer 13 – Related Registers
The generation of the patterns for a single channel pulse width modulation (PWM) is based on timer T13. The
registers related to timer T13 can be concurrently updated (with well-defined conditions) in order to ensure
consistency of the PWM signal. T13 can be synchronized to several timer T12 events.
Timer T13 supports only compare mode on its compare channel CC63.
Register T13 represents the counting value of timer T13. It can only be written while the timer T13 is stopped. Write
actions while T13 is running are not taken into account. Register T13 can always be read by software.
Timer T13 supports only edge-aligned mode (counting up).
T13L
Timer T13 Counter Register Low
7
6
Reset Value: 00H
5
4
3
2
1
0
T13CVL
rwh
Field
Bits
Type
Description
T13CVL
7:0
rwh
Timer T13 Counter Value Low Byte
This register represents the lower 8-bit counter value of timer T13.
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TLE983x
Capture/Compare Unit 6 (CCU6)
T13H
Timer T13 Counter Register High
7
6
Reset Value: 00H
5
4
3
2
1
0
T13CVH
rwh
Field
Bits
Type
Description
T13CVH
7:0
rwh
Timer T13 Counter Value High Byte
This register represents the upper 8-bit counter value of timer T13.
Note: While timer T13 is stopped, the internal clock divider is reset in order to ensure reproducible timings and
delays.
Register T13PR contains the period value for timer T13. The period value is compared to the actual counter value
of T13 and the resulting counter actions depend on the defined counting rules. This register has a shadow register
and the shadow transfer is controlled by bit STE13. A read action by software delivers the value which is currently
used for the compare action, whereas the write action targets a shadow register. The shadow register structure
allows a concurrent update of all T13-related values.
T13PRL
Timer T13 Period Register Low
7
6
Reset Value: 00H
5
4
3
2
1
0
T13PVL
rwh
Field
Bits
Type
Description
T13PVL
7:0
rwh
T13 Period Value Low Byte
The value T13PV defines the counter value for T13, which leads to a
period-match. On reaching this value, the timer T13 is set to zero.
T13PRH
Timer T13 Period Register High
7
6
Reset Value: 00H
5
4
3
2
1
0
T13PVH
rwh
Field
Bits
Type
Description
T13PVH
7:0
rwh
T13 Period Value High Byte
The value T13PV defines the counter value for T13, which leads to a
period-match. On reaching this value, the timer T13 is set to zero.
Register CC63R is the actual compare register for T13. The value stored in CC63R is compared to the counter
value of T13. The State Bit CC63ST is located in register CMPSTAT.
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TLE983x
Capture/Compare Unit 6 (CCU6)
CC63RL
Capture/Compare Register for Channel CC63 Low
7
6
5
Reset Value: 00H
4
3
2
1
0
CCVL
rh
Field
Bits
Type
Description
CCVL
7:0
rh
Channel CC63 Compare Value Low Byte
The bit field CCV contains the value that is compared to the T13
counter value.
CC63RH
Capture/Compare Register for Channel CC63 High
7
6
5
Reset Value: 00H
4
3
2
1
0
CCVH
rh
Field
Bits
Type
Description
CCVH
7:0
rh
Channel CC63 Compare Value High Byte
The bit field CCV contains the value that is compared to the T13
counter value.
The register CC63R can only be read by software and the modification of the value is done by a shadow register
transfer from register CC63SR. The corresponding shadow register CC63SR can be read and written by software.
CC63SRL
Capture/Compare Shadow Register for Channel CC63 Low
7
6
5
4
3
Reset Value: 00H
2
1
0
CCSL
rw
Field
Bits
Type
Description
CCSL
7:0
rw
Shadow Register for Channel CC63 Compare Value Low Byte
The contents of bit field CCS are transferred to the bit field CCV
during a shadow transfer.
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TLE983x
Capture/Compare Unit 6 (CCU6)
CC63SRH
Capture/Compare Shadow Register for Channel CC63 High
7
6
5
4
3
Reset Value: 00H
2
1
0
CCSH
rw
Field
Bits
Type
Description
CCSH
7:0
rw
Shadow Register for Channel CC63 Compare Value High Byte
The contents of bit field CCS are transferred to the bit field CCV
during a shadow transfer.
17.9.5
Capture/Compare Control Registers
The Compare State Register CMPSTAT contains status bits monitoring the current capture and compare state,
and control bits defining the active/passive state of the compare channels.
CMPSTATL
Compare State Register Low
Reset Value: 00H
7
6
5
4
3
2
1
0
0
CC
63ST
CC
POS
2
CC
POS
1
CC
POS
0
CC
62ST
CC
61ST
CC
60ST
r
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type
Description
CC6xST (x = 0, 1, 2,
3)
0, 1, 2,
6
rh
Capture/Compare State Bits
Bits CC6xST monitor the state of the capture/compare channels. Bits
CC6xST are related to T12; bit CC63ST is related to T13.
These bits are set and reset according to the T12 and T13 switching
rules.
In compare mode, the timer count is less than the compare value.
0B
In capture mode, the selected edge has not yet been detected
since the bit has been reset by software the last time.
In compare mode, the counter value is greater than or equal to
1B
the compare value. In capture mode, the selected edge has been
detected.
CCPOSx (x = 0, 1, 2) 3, 4, 5
rh
Sampled Hall Pattern Bits
Bits CCPSOx indicate the value of the input Hall pattern that has been
compared to the current and expected value. The value is sampled
when the event hcrdy (Hall compare ready) occurs.
The input CCPOSx has been sampled as 0.
0B
The input CCPOSx has been sampled as 1.
1B
r
Reserved
Returns 0 if read.
0
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TLE983x
Capture/Compare Unit 6 (CCU6)
CMPSTATH
Compare State Register High
Reset Value: 00H
7
6
5
4
3
2
1
0
T13
IM
C
OUT63PS
C
OUT62PS
CC
62PS
C
OUT61PS
CC
61PS
C
OUT60PS
CC
60PS
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
CC6xPS (x = 0, 1, 2) 0, 2, 4
COUT6xPS (x = 0, 1, 1, 3, 5,
2, 3)
6
7
T13IM
Type
Description
rwh
Passive State Select for Compare Outputs
Bits CC6xPS, COUT6xPS select the state of the corresponding
compare channel, which is considered to be the passive state. During
the passive state, the passive level (defined in register PSLR) is driven
by the output pin. Bits CC6xPS, COUT6xPS (x = 0, 1, 2) are related to
T12, bit COUT63PS is related to T13.
These bits have shadow bits and are updated in parallel to the
capture/compare registers of T12 and T13, respectively. A read action
targets the actually used values, whereas a write action targets the
shadow bits.
In capture mode, these bits are not used.
The corresponding compare output drives passive level while
0B
CC6xST is 0.
The corresponding compare output drives passive level while
1B
CC6xST is 1.
rwh
T13 Inverted Modulation
Bit T13IM inverts the T13 signal for the modulation of the CC6x and
COUT6x (x = 0, 1, 2) signals.
This bit has a shadow bit and is updated in parallel to the compare and
period registers of T13. A read action targets the actually used values,
whereas a write action targets the shadow bit.
T13 output is not inverted.
0B
T13 output is inverted for further modulation.
1B
The Compare Status Modification Register CMPMODIF provides software-control (independent set and clear
conditions) for the channel state bits CC6xST. This feature enables the user to individually change the status of
the output lines by software, for example when the corresponding compare timer is stopped.
CMPMODIFL
Compare State Modification Register Low
7
6
0
MCC
63S
r
w
User’s Manual
5
Reset Value: 00H
4
3
2
1
0
0
MCC
62S
MCC
61S
MCC
60S
r
w
w
w
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Capture/Compare Unit 6 (CCU6)
Field
Bits
MCC6xS (x = 0, 1, 2, 0, 1, 2,
3)
6
5:3, 7
0
Type
Description
w
Capture/Compare Status Modification Bits (Set)
These bits are used to set the corresponding CC6xST bits by software.
This feature allows the user to individually change the status of the
output lines by software, e.g. when the corresponding compare timer is
stopped. This allows a bit manipulation of CC6xST-bits by a single data
write action.
The following functionality of a write access to bits concerning the same
capture/compare state bit is provided:
MCC6xR, MCC6xS =
0B,0B Bit CC6xST is not changed.
0B,1B Bit CC6xST is set.
1B,0B Bit CC6xST is reset.
1B,1B Reserved (toggle)
r
Reserved
Returns 0 if read.
CMPMODIFH
Compare State Modification Register High
7
6
0
MCC
63R
r
w
Field
5
Bits
MCC6xR (x = 0, 1, 2, 0, 1, 2,
3)
6
0
5:3, 7
Reset Value: 00H
4
3
2
1
0
0
MCC
62R
MCC
61R
MCC
60R
r
w
w
w
Type
Description
w
Capture/Compare Status Modification Bits (Reset)
These bits are used to reset the corresponding CC6xST bits by
software.
This feature allows the user to individually change the status of the
output lines by software, e.g. when the corresponding compare timer is
stopped. This allows a bit manipulation of CC6xST-bits by a single data
write action.
The following functionality of a write access to bits concerning the same
capture/compare state bit is provided:
MCC6xR, MCC6xS =
0B,0B Bit CC6xST is not changed.
0B,1B Bit CC6xST is set.
1B,0B Bit CC6xST is reset.
1B,1B Reserved (toggle)
r
Reserved
Returns 0 if read.
Register TCTR0 controls the basic functionality of both timers T12 and T13.
Note: A write action to the bit fields T12CLK or T12PRE is only taken into account while the timer T12 is not running
(T12R = 0). A write action to the bit fields T13CLK or T13PRE is only taken into account while the timer T13
is not running (T13R = 0).
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Capture/Compare Unit 6 (CCU6)
TCTR0L
Timer Control Register 0 Low
Reset Value: 00H
7
6
5
4
3
2
1
CTM
CDIR
STE12
T12R
T12
PRE
T12CLK
rw
rh
rh
rh
rw
rw
0
Field
Bits
Type
Description
T12CLK
2:0
rw
Timer T12 Input Clock Select
Selects the input clock for timer T12 which is derived from the
peripheral clock according to the equation fT12 = fCCU / 2<T12CLK>.
000B fT12 = fCCU
001B fT12 = fCCU / 2
010B fT12 = fCCU / 4
011B fT12 = fCCU / 8
100B fT12 = fCCU / 16
101B fT12 = fCCU / 32
110B fT12 = fCCU / 64
111B fT12 = fCCU / 128
T12PRE
3
rw
Timer T12 Prescaler Bit
In order to support higher clock frequencies, an additional prescaler
factor of 1/256 can be enabled for the prescaler for T12.
The additional prescaler for T12 is disabled.
0B
The additional prescaler for T12 is enabled.
1B
T12R
4
rh
Timer T12 Run Bit
T12R starts and stops timer T12. It is set/reset by software by setting
bits T12RS or T12RR, or it is reset by hardware according to the
function defined by bit field T12SSC.
A concurrent set/reset action on T12R (from T12SSC, T12RR or
T12RS) will have no effect. The bit T12R will remain unchanged.
Timer T12 is stopped.
0B
Timer T12 is running.
1B
STE12
5
rh
Timer T12 Shadow Transfer Enable
Bit STE12 enables or disables the shadow transfer of the T12 period
value, the compare values and passive state select bits and levels from
their shadow registers to the actual registers if a T12 shadow transfer
event is detected. Bit STE12 is cleared by hardware after the shadow
transfer.
A T12 shadow transfer event is a period-match while counting up or a
one-match while counting down.
The shadow register transfer is disabled.
0B
The shadow register transfer is enabled.
1B
CDIR
6
rh
Count Direction of Timer T12
This bit is set/reset according to the counting rules of T12.
T12 counts up.
0B
T12 counts down.
1B
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
CTM
7
rw
T12 Operating Mode
0
Edge-aligned Mode: T12 always counts up and continues
counting from zero after reaching the period value.
1
Center-aligned Mode: T12 counts down after detecting a periodmatch and counts up after detecting a one-match.
TCTR0H
Timer Control Register 0 High
7
6
Reset Value: 00H
5
4
3
2
1
0
STE
13
T13R
T13
PRE
T13CLK
r
rh
rh
rw
rw
0
Field
Bits
Type
Description
T13CLK
2:0
rw
Timer T13 Input Clock Select
Selects the input clock for timer T13 which is derived from the
peripheral clock according to the equation
fT13 = fCCU/2<T13CLK>.
000B fT13 = fCCU
001B fT13 = fCCU / 2
010B fT13 = fCCU / 4
011B fT13 = fCCU / 8
100B fT13 = fCCU / 16
101B fT13 = fCCU / 32
110B fT13 = fCCU / 64
111B fT13 = fCCU / 128
T13PRE
3
rw
Timer T13 Prescaler Bit
In order to support higher clock frequencies, an additional prescaler
factor of 1/256 can be enabled for the prescaler for T13.
The additional prescaler for T13 is disabled.
0B
The additional prescaler for T13 is enabled.
1B
T13R
4
rh
Timer T13 Run Bit
T13R starts and stops timer T13. It is set/reset by software by setting
bits T13RS or T13RR or it is set/reset by hardware according to the
function defined by bit fields T13SSC, T13TEC and T13TED.
A concurrent set/reset action on T13R (from T13SSC, T13TEC, T13RR
or T13RS) will have no effect. The bit T13R will remain unchanged.
Timer T13 is stopped.
0B
Timer T13 is running.
1B
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
STE13
5
rh
Timer T13 Shadow Transfer Enable
Bit STE13 enables or disables the shadow transfer of the T13 period
value, the compare value and passive state select bit and level from
their shadow registers to the actual registers if a T13 shadow transfer
event is detected. Bit STE13 is cleared by hardware after the shadow
transfer.
A T13 shadow transfer event is a period-match.
The shadow register transfer is disabled.
0B
The shadow register transfer is enabled.
1B
0
7:6
r
Reserved
Returns 0 if read.
Register TCTR2 controls the single-shot and the synchronization functionality of both timers T12 and T13. Both
timers can run in single-shot mode. In this mode, they stop their counting sequence automatically after one
counting period with a count value of zero. The single-shot mode and the synchronization feature of T13 to T12
allow the generation of events with a programmable delay after well-defined PWM actions of T12. For example,
this feature can be used to trigger AD conversions, after a specified delay (to avoid problems due to switching
noise), synchronously to a PWM event.
TCTR2L
Timer Control Register 2 Low
7
6
Reset Value: 00H
5
4
3
2
1
0
0
T13
TED
T13
TEC
T13
SSC
T12
SSC
r
rw
rw
rw
rw
Field
Bits
Type
Description
T12SSC
0
rw
Timer T12 Single Shot Control
This bit controls the single shot-mode of T12.
The single-shot mode is disabled, no hardware action on T12R.
0B
The single shot mode is enabled, the bit T12R is reset by
1B
hardware if:
– T12 reaches its period value in edge-aligned mode
– T12 reaches the value 1 while down counting in center-aligned
mode.
In parallel to the reset action of bit T12R, the bits CC6xST
(x = 0, 1, 2) are reset.
T13SSC
1
rw
Timer T13 Single Shot Control
This bit controls the single shot-mode of T13.
No hardware action on T13R
0B
The single-shot mode is enabled, the bit T13R is reset by
1B
hardware if T13 reaches its period value.
In parallel to the reset action of bit T13R, the bit CC63ST is reset.
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
T13TEC
4:2
rw
T13 Trigger Event Control
Bit field T13TEC selects the trigger event to start T13 (automatic set of
T13R for synchronization to T12 compare signals) according to
following combinations:
000B no action
001B set T13R on a T12 compare event on channel 0
010B set T13R on a T12 compare event on channel 1
011B set T13R on a T12 compare event on channel 2
100B set T13R on any T12 compare event on the channels 0, 1, or 2
101B set T13R upon a period-match of T12
110B set T13R upon a zero-match of T12 (while counting up)
111B set T13R on any edge of inputs CCPOSx
T13TED
6:5
rw
Timer T13 Trigger Event Direction
Bit field T13TED delivers additional information to control the automatic
set of bit T13R in the case that the trigger action defined by T13TEC is
detected.
00B no action
01B while T12 is counting up
10B while T12 is counting down
11B independent on the count direction of T12
0
7
r
Reserved
Returns 0 if read.
Example
If the timer T13 is intended to start at any compare event on T12 (T13TEC = 100B), the trigger event direction can
be programmed to:
•
•
•
counting up >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting up
counting down >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting down
independent from bit CDIR >> each T12 channel 0, 1, 2 compare match triggers T13R
The timer count direction is taken from the value of bit CDIR. As a result, if T12 is running in edge-aligned mode
(counting up only), T13 can only be started automatically if bit field T13TED = 01B or 11B.
TCTR2H
Timer Control Register 2 High
7
User’s Manual
6
Reset Value: 00H
5
4
3
2
1
0
0
T13
RSEL
T12
RSEL
r
rw
rw
398
Rev. 1.0, 2011-12-23
TLE983x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
T12RSEL
1:0
rw
Timer T12 External Run Selection
Bit field T12RSEL defines the event of signal T12HR that can set the
run bit T12R by hardware.
00B The external setting of T12R is disabled.
01B Bit T12R is set if a rising edge of signal T12HR is detected.
10B Bit T12R is set if a falling edge of signal T12HR is detected.
11B Bit T12R is set if an edge of signal T12HR is detected.
T13RSEL
3:2
rw
Timer T13 External Run Selection
Bit field T13RSEL defines the event of signal T13HR that can set the
run bit T13R by hardware.
00B The external setting of T13R is disabled.
01B Bit T13R is set if a rising edge of signal T13HR is detected.
10B Bit T13R is set if a falling edge of signal T13HR is detected.
11B Bit T13R is set if an edge of signal T13HR is detected.
0
7:4
r
Reserved
Returns 0 if read.
Register TCTR4 provides software-control (independent set and clear conditions) for the run bits T12R and T13R.
Furthermore, the timers can be reset (while running) and bits STE12 and STE13 can be controlled by software.
Reading these bits always returns 0.
TCTR4L
Timer Control Register 4 Low
Reset Value: 00H
7
6
5
4
3
2
1
0
T12
STD
T12
STR
T12
CNT
0
DT
RES
T12
RES
T12
RS
T12
RR
w
w
w
r
w
w
w
w
Field
Bits
Type
Description
T12RR
0
w
Timer T12 Run Reset
Setting this bit resets the T12R bit.
T12R is not influenced.
0B
T12R is cleared, T12 stops counting.
1B
T12RS
1
w
Timer T12 Run Set
Setting this bit sets the T12R bit.
T12R is not influenced.
0B
T12R is set, T12 counts.
1B
T12RES
2
w
Timer T12 Reset
0B
No effect on T12.
The T12 counter register is reset to zero. The switching of the
1B
output signals is according to the switching rules. Setting of
T12RES has no impact on bit T12R.
DTRES
3
w
Dead-Time Counter Reset
0B
No effect on the dead-time counters.
The three dead-time counter channels are reset to zero.
1B
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TLE983x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
T12CNT
5
w
Timer T12 Count Event
0B
No action
If enabled (PISEL2), timer T12 counts one step.
1B
T12STR
6
w
Timer T12 Shadow Transfer Request
0B
No action
STE12 is set, enabling the shadow transfer.
1B
T12STD
7
w
Timer T12 Shadow Transfer Disable
0B
No action
STE12 is reset without triggering the shadow transfer.
1B
0
4
r
Reserved
Returns 0 if read.
TCTR4H
Timer Control Register 4 High
Reset Value: 00H
7
6
5
T13
STD
T13
STR
T13
CNT
w
w
w
4
3
2
1
0
0
T13
RES
T13
RS
T13
RR
r
w
w
w
Field
Bits
Type
Description
T13RR
0
w
Timer T13 Run Reset
Setting this bit resets the T13R bit.
T13R is not influenced.
0B
T13R is cleared, T13 stops counting.
1B
T13RS
1
w
Timer T13 Run Set
Setting this bit sets the T13R bit.
T13R is not influenced.
0B
T13R is set, T13 counts.
1B
T13RES
2
w
Timer T13 Reset
0B
No effect on T13.
The T13 counter register is reset to zero. The switching of the
1B
output signals is according to the switching rules. Setting of
T13RES has no impact on bit T13R.
T13CNT
5
w
Timer T13 Count Event
0B
No action
If enabled (PISEL2), timer T13 counts one step.
1B
T13STR
6
w
Timer T13 Shadow Transfer Request
0B
No action
STE13 is set, enabling the shadow transfer.
1B
T13STD
7
w
Timer T13 Shadow Transfer Disable
0B
No action
STE13 is reset without triggering the shadow transfer.
1B
0
4:3
r
Reserved
Returns 0 if read.
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TLE983x
Capture/Compare Unit 6 (CCU6)
Note: A simultaneous write of a 1 to bits which set and reset the same bit will trigger no action. The corresponding
bit will remain unchanged.
17.9.6
Global Modulation Control Registers
Register MODCTR contains control bits enabling the modulation of the corresponding output signal by PWM
pattern generated by the timers T12 and T13. Furthermore, the multi-channel mode can be enabled as additional
modulation source for the output signals.
MODCTRL
Modulation Control Register Low
5
Reset Value: 00H
7
6
4
3
2
MCMEN
0
T12MODEN
rw
r
rw
1
0
Field
Bits
Type
Description
T12MODEN
5:0
rw
T12 Modulation Enable
Setting these bits enables the modulation of the corresponding
compare channel by a PWM pattern generated by timer T12. The bit
positions are corresponding to the following output signals:
Bit 0: modulation of CC60
Bit 1: modulation of COUT60
Bit 2: modulation of CC61
Bit 3: modulation of COUT61
Bit 4: modulation of CC62
Bit 5: modulation of COUT62
The enable feature of the modulation is defined as follows:
The modulation of the corresponding output signal by a T12
0B
PWM pattern is disabled.
The modulation of the corresponding output signal by a T12
1B
PWM pattern is enabled.
MCMEN
7
rw
Multi-Channel Mode Enable
0B
The modulation of the corresponding output signal by a multichannel pattern according to bit field MCMOUT is disabled.
The modulation of the corresponding output signal by a multi1B
channel pattern according to bit field MCMOUT is enabled.
0
6
r
Reserved
Returns 0 if read.
MODCTRH
Modulation Control Register High
7
6
ECT
13O
0
T13MODEN
rw
r
rw
User’s Manual
5
Reset Value: 00H
4
3
401
2
1
0
Rev. 1.0, 2011-12-23
TLE983x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
T13MODEN
5:0
rw
T13 Modulation Enable
Setting these bits enables the modulation of the corresponding
compare channel by a PWM pattern generated by timer T13. The bit
positions are corresponding to the following output signals:
Bit 0: modulation of CC60
Bit 1: modulation of COUT60
Bit 2: modulation of CC61
Bit 3: modulation of COUT61
Bit 4: modulation of CC62
Bit 5: modulation of COUT62
The enable feature of the modulation is defined as follows:
The modulation of the corresponding output signal by a T13
0B
PWM pattern is disabled.
The modulation of the corresponding output signal by a T13
1B
PWM pattern is enabled.
ECT13O
7
rw
Enable Compare Timer T13 Output
0B
The alternate output function COUT63 is disabled.
The alternate output function COUT63 is enabled for the PWM
1B
signal generated by T13.
0
6
r
Reserved
Returns 0 if read.
The register TRPCTR controls the trap functionality. It contains independent enable bits for each output signal and
control bits to select the behavior in case of a trap condition. The trap condition is a low-level on the CTRAP input
pin, which is monitored (inverted level) by bit IS.TRPF. While TRPF = 1 (trap input active), the trap state bit
IS.TRPS is set to 1.
TRPCTRL
Trap Control Register Low
7
User’s Manual
6
Reset Value: 00H
5
4
3
2
1
0
0
TRP
M2
TRP
M1
TRP
M0
r
rw
rw
rw
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Rev. 1.0, 2011-12-23
TLE983x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
TRPM0,
TRPM1
1:0
rw
Trap Mode Control Bits 1, 0
These two bits define the behavior of the selected outputs when leaving
the trap state after the trap condition has become inactive again.
A synchronization to the timer driving the PWM pattern permits to avoid
unintended short pulses when leaving the trap state. The combination
(TRPM1, TRPM0) leads to:
00B The trap state is left (return to normal operation according to
TRPM2) when a zero-match of T12 (while counting up) is
detected (synchronization to T12).
01B The trap state is left (return to normal operation according to
TRPM2) when a zero-match of T13 is detected (synchronization
to T13).
10B reserved
11B The trap state is left (return to normal operation according to
TRPM2) immediately without any synchronization to T12 or T13.
TRPM2
2
rw
Trap Mode Control Bit 2
0B
The trap state can be left (return to normal operation = bit
TRPS = 0) as soon as the input CTRAP becomes inactive. Bit
TRPF is automatically cleared by hardware if the input pin
CTRAP becomes 1. Bit TRPS is automatically cleared by
hardware if bit TRPF is 0 and if the synchronization condition
(according to TRPM0,1) is detected.
The trap state can be left (return to normal operation = bit
1B
TRPS = 0) as soon as bit TRPF is reset by software after the
input CTRAP becomes inactive (TRPF is not cleared by
hardware). Bit TRPS is automatically cleared by hardware if bit
TRPF = 0 and if the synchronization condition (according to
TRPM0,1) is detected.
0
7:3
r
Reserved
Returns 0 if read.
TRPCTRH
Trap Control Register High
Reset Value: 00H
7
6
TRP
PEN
TRP
EN
13
TRPEN
rw
rw
rw
User’s Manual
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4
3
403
2
1
0
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TLE983x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
TRPEN
5:0
rw
Trap Enable Control
Setting these bits enables the trap functionality for the following
corresponding output signals:
Bit 0: trap functionality of CC60
Bit 1: trap functionality of COUT60
Bit 2: trap functionality of CC61
Bit 3: trap functionality of COUT61
Bit 4: trap functionality of CC62
Bit 5: trap functionality of COUT62
The enable feature of the trap functionality is defined as follows:
The trap functionality of the corresponding output signal is
0B
disabled. The output state is independent from bit TRPS.
The trap functionality of the corresponding output signal is
1B
enabled. The output is set to the passive state while TRPS = 1.
TRPEN13
6
rw
Trap Enable Control for Timer T13
0B
The trap functionality for T13 is disabled. Timer T13 (if selected
and enabled) provides PWM functionality even while TRPS = 1.
The trap functionality for T13 is enabled. The timer T13 PWM
1B
output signal is set to the passive state while TRPS = 1.
TRPPEN
7
rw
Trap Pin Enable
0B
The trap functionality based on the input pin CTRAP is disabled.
A trap can only be generated by software by setting bit TRPF.
The trap functionality based on the input pin CTRAP is enabled.
1B
A trap can be generated by software by setting bit TRPF or by
CTRAP = 0.
Register PSLR defines the passive state level driven by the output pins of the module. The passive state level is
the value that is driven by the port pin during the passive state of the output. During the active state, the
corresponding output pin drives the active state level, which is the inverted passive state level. The passive state
level permits the adaptation of the driven output levels to the driver polarity (inverted, not inverted) of the
connected power stage. The bits in this register have shadow bit fields to permit a concurrent update of all PWMrelated parameters (bit field PSL is updated with T12_ST, whereas PSL63 is updated with T13_ST). The actually
used values can be read (attribute “rh”), whereas the shadow bits can only be written (attribute “w”).
PSLR
Passive State Level Register
Reset Value: 00H
7
6
PSL
63
0
PSL
rwh
r
rwh
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4
3
404
2
1
0
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TLE983x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
PSL
5:0
rwh
Compare Outputs Passive State Level
The bits of this bit field define the passive level driven by the module
outputs during the passive state. The bit positions are:
Bit 0: passive level for output CC60
Bit 1: passive level for output COUT60
Bit 2: passive level for output CC61
Bit 3: passive level for output COUT61
Bit 4: passive level for output CC62
Bit 5: passive level for output COUT62
The value of each bit position is defined as:
The passive level is 0.
0B
The passive level is 1.
1B
PSL63
7
rwh
Passive State Level of Output COUT63
This bit field defines the passive level of the output pin COUT63.
The passive level is 0.
0B
The passive level is 1.
1B
0
6
r
Reserved
Returns 0 if read.
Notes
1. Bit field PSL has a shadow register to allow for updates without undesired pulses on the output lines. The bits
are updated with the T12 shadow transfer. A read action targets the actually used values, whereas a write
action targets the shadow bits.
2. Bit field PSL63 has a shadow register to allow for updates without undesired pulses on the output line. The bit
is updated with the T13 shadow transfer. A read action targets the actually used values, whereas a write action
targets the shadow bits.
17.9.7
Multi-Channel Modulation Control Registers
Register MCMOUTS contains bits used as pattern input for the multi-channel mode and the Hall mode. This
register is a shadow register (that can be read and written) for register MCMOUT, which indicates the currently
active signals.
MCMOUTSL
Multi-Channel Mode Output Shadow Register Low
5
Reset Value: 00H
7
6
4
3
2
STR
MCM
0
MCMPS
w
r
rw
1
0
Field
Bits
Type
Description
MCMPS
5:0
rw
Multi-Channel PWM Pattern Shadow
Bit field MCMPS is the shadow bit field for bit field MCMP. The multichannel shadow transfer is triggered according to the transfer
conditions defined by register MCMCTR.
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TLE983x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
STRMCM
7
w
Shadow Transfer Request for MCMPS
Setting this bit during a write action leads to an immediate update of bit
field MCMP by the value written to bit field MCMPS. This functionality
permits an update triggered by software. When read, this bit always
delivers 0.
Bit field MCMP is updated according to the defined hardware
0B
action. The write access to bit field MCMPS does not modify bit
field MCMP.
Bit field MCMP is updated by the value written to bit field
1B
MCMPS.
0
6
r
Reserved
Returns 0 if read.
MCMOUTSH
Multi-Channel Mode Output Shadow Register High
5
Reset Value: 00H
7
6
4
3
2
1
STR
HP
0
CURHS
EXPHS
w
r
rw
rw
0
Field
Bits
Type
Description
EXPHS
2:0
rw
Expected Hall Pattern Shadow
Bit field EXPHS is the shadow bit field for bit field EXPH. The bit field is
transferred to bit field EXPH if an edge on the hall input pins CCPOSx
(x = 0, 1, 2) is detected.
CURHS
5:3
rw
Current Hall Pattern Shadow
Bit field CURHS is the shadow bit field for bit field CURH. The bit field
is transferred to bit field CURH if an edge on the hall input pins
CCPOSx (x = 0, 1, 2) is detected.
STRHP
7
w
Shadow Transfer Request for the Hall Pattern
Setting these bits during a write action leads to an immediate update of
bit fields CURH and EXPH by the value written to bit fields CURHS and
EXPH. This functionality permits an update triggered by software.
When read, this bit always delivers 0.
The bit fields CURH and EXPH are updated according to the
0B
defined hardware action. The write access to bit fields CURHS
and EXPHS does not modify the bit fields CURH and EXPH.
The bit fields CURH and EXPH are updated by the value written
1B
to the bit fields CURHS and EXPHS.
0
6
r
Reserved
Returns 0 if read.
Register MCMOUT shows the multi-channel control bits that are currently used. Register MCMOUT is defined as
follows:
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TLE983x
Capture/Compare Unit 6 (CCU6)
MCMOUTL
Multi-Channel Mode Output Register Low
5
Reset Value: 00H
7
6
4
3
2
0
R
MCMP
r
rh
rh
1
0
Field
Bits
Type
Description
MCMP
5:0
rh
Multi-Channel PWM Pattern
Bit field MCMP is written by a shadow transfer from bit field MCMPS. It
contains the output pattern for the multi-channel mode. If this mode is
enabled by bit MCMEN in register MODCTR, the output state of the
following output signal can be modified:
Bit 0: multi-channel state for output CC60
Bit 1: multi-channel state for output COUT60
Bit 2: multi-channel state for output CC61
Bit 3: multi-channel state for output COUT61
Bit 4: multi-channel state for output CC62
Bit 5: multi-channel state for output COUT62
The multi-channel patterns can set the related output to the passive
state.
While IDLE = 1, bit field MCMP is cleared.
The output is set to the passive state. The PWM generated by
0B
T12 or T13 is not taken into account.
The output can deliver the PWM generated by T12 or T13
1B
(according to register MODCTR).
R
6
rh
Reminder Flag
This reminder flag indicates that the shadow transfer from bit field
MCMPS to MCMP has been requested by the selected trigger source.
This bit is cleared when the shadow transfer takes place and while
MCMEN = 0.
Currently, no shadow transfer from MCMPS to MCMP is
0B
requested.
A shadow transfer from MCMPS to MCMP has been requested
1B
by the selected trigger source, but it has not yet been executed,
because the selected synchronization condition has not yet
occured.
0
7
r
Reserved
Returns 0 if read.
MCMOUTH
Multi-Channel Mode Output Register High
7
6
5
Reset Value: 00H
4
3
2
1
0
CURH
EXPH
r
rh
rh
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Rev. 1.0, 2011-12-23
TLE983x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
EXPH
2:0
rh
Expected Hall Pattern
Bit field EXPH is written by a shadow transfer from bit field EXPHS. The
contents are compared after every detected edge at the hall input pins
with the pattern at the hall input pins in order to detect the occurrence
of the next desired (= expected) hall pattern or a wrong pattern.
If the current hall pattern at the hall input pins is equal to the bit field
EXPH, bit CHE (correct hall event) is set and an interrupt request is
generated (if enabled by bit ENCHE).
If the current hall pattern at the hall input pins is not equal to the bit
fields CURH or EXPH, bit WHE (wrong hall event) is set and an
interrupt request is generated (if enabled by bit ENWHE).
CURH
5:3
rh
Current Hall Pattern
Bit field CURH is written by a shadow transfer from bit field
CURHS.The contents are compared after every detected edge at the
hall input pins with the pattern at the hall input pins in order to detect
the occurrence of the next desired (= expected) hall pattern or a wrong
pattern.
If the current hall input pattern is equal to bit field CURH, the detected
edge at the hall input pins has been an invalid transition (e.g. a spike).
0
7:6
r
Reserved
Returns 0 if read.
Note: The bits in the bit fields EXPH and CURH correspond to the hall patterns at the input pins CCPOSx
(x = 0, 1, 2) in the following order (EXPH.2, EXPH.1, EXPH.0), (CURH.2, CURH.1, CURH.0), (CCPOS2,
CCPOS.1, CCPOS0).
Register MCMCTR contains control bits for the multi-channel functionality.
MCMCTRL
Multi-Channel Mode Control Register Low
7
6
5
Reset Value: 00H
4
3
2
1
0
SWSYN
0
SWSEL
r
rw
r
rw
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Rev. 1.0, 2011-12-23
TLE983x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
SWSEL
2:0
rw
Switching Selection
Bit field SWSEL selects one of the following trigger request sources
(next multi-channel event) for the shadow transfer from MCMPS to
MCMP. The trigger request is stored in the reminder flag R until the
shadow transfer is done and flag R is cleared automatically with the
shadow transfer. The shadow transfer takes place synchronously with
an event selected in bit field SWSYN.
000B no trigger request will be generated
001B correct hall pattern on CCPOSx detected
010B T13 period-match detected (while counting up)
011B T12 one-match (while counting down)
100B T12 channel 1 compare-match detected (phase delay function)
101B T12 period match detected (while counting up) else reserved, no
trigger request will be generated
SWSYN
5:4
rw
Switching Synchronization
Bit field SWSYN triggers the shadow transfer between MCMPS and
MCMP if it has been requested before (flag R set by an event selected
by SWSEL). This feature permits the synchronization of the outputs to
the PWM source, that is used for modulation (T12 or T13).
00B direct; the trigger event directly causes the shadow transfer
01B T13 zero-match triggers the shadow transfer
10B a T12 zero-match (while counting up) triggers the shadow
transfer
11B reserved; no action
0
3, 6, 7
r
Reserved
Returns 0 if read.
MCMCTRH
Multi-Channel Mode Control Register High
7
6
5
Reset Value: 00H
4
3
2
1
0
0
STE
13U
STE
12D
STE
12U
r
rw
rw
rw
Field
Bits
Type
Description
STE12U
0
rw
Shadow Transfer Enable for T12 Upcounting
This bit enables the shadow transfer T12_ST if flag MCMOUT.R is set
or becomes set while a T12 period match is detected while counting up.
No action
0B
The T12_ST shadow transfer mechanism is enabled if
1B
MCMEN = 1.
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TLE983x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
STE12D
1
rw
Shadow Transfer Enable for T12 Downcounting
This bit enables the shadow transfer T12_ST if flag MCMOUT.R is set
or becomes set while a T12 one match is detected while counting
down.
No action
0B
The T12_ST shadow transfer mechanism is enabled if
1B
MCMEN = 1.
STE13U
2
rw
Shadow Transfer Enable for T13 Upcounting
This bit enables the shadow transfer T13_ST if flag MCMOUT.R is set
or becomes set while a T13 period match is detected.
No action
0B
The T13_ST shadow transfer mechanism is enabled if
1B
MCMEN = 1.
0
7:3
r
Reserved
Returns 0 if read.
17.9.8
Interrupt Control Registers
Register IS contains the individual interrupt request bits. This register can only be read; write actions have no
impact on the contents of this register. The software can set or reset the bits individually by writing to the registers
ISS (to set the bits) or to register ISR (to reset the bits).
The interrupt generation is independent from the value of the bits in register IS, e.g. the interrupt will be generated
(if enabled) even if the corresponding bit is already set. The trigger for an interrupt generation is the detection of
a set condition (by HW or SW) for the corresponding bit in register IS.
In compare mode (and hall mode), the timer-related interrupts are only generated while the timer is running (T1xR
= 1). In capture mode, the capture interrupts are also generated while the timer T12 is stopped.
Note: Not all bits in register IS can generate an interrupt. Other status bits have been added, that have a similar
structure for their set and clear actions. It is recommended that SW checks the interrupt bits bit-wisely
(instead of common OR over the bits).
ISL
Capture/Compare Interrupt Status Register Low
Reset Value: 00H
7
6
5
4
3
2
1
0
T12
PM
T12
OM
ICC
62F
ICC
62R
ICC
61F
ICC
61R
ICC
60F
ICC
60R
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type
Description
ICC6xR
(x = 0, 1, 2)
0, 2, 4
rh
Capture, Compare-Match Rising Edge Flag
In compare mode, a compare-match has been detected while T12 was
counting up. In capture mode, a rising edge has been detected at the
input CC6x.
The event has not yet occured since this bit has been reset for
0B
the last time.
The event described above has been detected.
1B
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TLE983x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
ICC6xF
(x = 0, 1, 2)
1, 3, 5
rh
Capture, Compare-Match Falling Edge Flag
In compare mode, a compare-match has been detected while T12 was
counting down. In capture mode, a falling edge has been detected at
the input CC6x.
The event has not yet occured since this bit has been reset for
0B
the last time.
The event described above has been detected.
1B
T12OM
6
rh
Timer T12 One-Match Flag
0B
A timer T12 one-match (while counting down) has not yet been
detected since this bit has been reset for the last time.
A timer T12 one-match (while counting down) has been detected.
1B
T12PM
7
rh
Timer T12 Period-Match Flag
0B
A timer T12 period-match (while counting up) has not yet been
detected since this bit has been reset for the last time.
A timer T12 period-match (while counting up) has been detected.
1B
ISH
Capture/Compare Interrupt Status Register High
Reset Value: 00H
7
6
5
4
3
2
1
0
STR
IDLE
WHE
CHE
TRP
S
TRP
F
T13
PM
T13
CM
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type
Description
T13CM
0
rh
Timer T13 Compare-Match Flag
0B
A timer T13 compare-match has not yet been detected since this
bit has been reset for the last time.
A timer T13 compare-match has been detected.
1B
T13PM
1
rh
Timer T13 Period-Match Flag
0B
A timer T13 period-match has not yet been detected since this bit
has been reset for the last time.
A timer T13 period-match has been detected.
1B
TRPF
2
rh
Trap Flag
The trap flag TRPF will be set by hardware if TRPPEN = 1 and
CTRAP = 0 or by software. If TRPM2 = 0, bit TRPF is reset by
hardware if the input CTRAP becomes inactive (TRPPEN = 1). If
TRPM2 = 1, bit TRPF must be reset by software in order to leave the
trap state.
The trap condition has not been detected.
0B
The trap condition has been detected (input CTRAP has been 0
1B
or by software).
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
TRPS
3
rh
Trap State
During the trap state, the selected outputs are set to the passive state.
The logic level driven during the passive state is defined by the
corresponding bit in register PSLR. Bit TRPS = 1 and TRPF = 0 can
occur if the trap condition is no longer active but the selected
synchronization has not yet taken place.
The trap state is not active.
0B
The trap state is active. Bit TRPS is set while bit TRPF = 1. It is
1B
reset according to the mode selected in register TRPCTR.
CHE
4
rh
Correct Hall Event
On every valid hall edge, the contents of EXPH are compared with the
pattern on pin CCPOSx and if equal bit CHE is set.
A transition to a correct (= expected) hall event has not yet been
0B
detected since this bit has been reset for the last time.
A transition to a correct (= expected) hall event has been
1B
detected.
WHE
5
rh
Wrong Hall Event
On every valid hall edge, the contents of EXPH are compared with the
pattern on pin CCPOSx. If both comparisons (CURH and EXPH with
CCPOSx) are not true, bit WHE (wrong hall event) is set.
A transition to a wrong hall event (not the expected one) has not
0B
yet been detected since this bit has been reset for the last time.
A transition to a wrong hall event (not the expected one) has been
1B
detected.
IDLE
6
rh
IDLE State
This bit is set together with bit WHE (wrong hall event) and it must be
reset by software.
No action.
0B
Bit field MCMP is cleared and held to 0, the selected outputs are
1B
set to passive state.
STR
7
rh
Multi-Channel Mode Shadow Transfer Request
This bit is set when a shadow transfer from MCMOUTS to MCMOUT
takes places in multi-channel mode.
The shadow transfer has not yet taken place.
0B
The shadow transfer has taken place.
1B
Register ISS contains individual interrupt request set bits to generate a CCU6 interrupt request by software.
Writing a 1 sets the bit(s) in register IS at the corresponding bit position(s) and can generate an interrupt event (if
available and enabled). All bit positions read as 0.
ISSL
Capture/Compare Interrupt Status Set Register Low
Reset Value: 00H
7
6
5
4
3
2
1
0
S
T12
PM
S
T12
OM
S
CC
62F
S
CC
62R
S
CC
61F
S
CC
61R
S
CC
60F
S
CC
60R
w
w
w
w
w
w
w
w
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
SCC60R
0
w
Set Capture, Compare-Match Rising Edge Flag
0B
No action
Bit CC60R in register IS will be set.
1B
SCC60F
1
w
Set Capture, Compare-Match Falling Edge Flag
0B
No action
Bit CC60F in register IS will be set.
1B
SCC61R
2
w
Set Capture, Compare-Match Rising Edge Flag
0B
No action
Bit CC61R in register IS will be set.
1B
SCC61F
3
w
Set Capture, Compare-Match Falling Edge Flag
0B
No action
Bit CC61F in register IS will be set.
1B
SCC62R
4
w
Set Capture, Compare-Match Rising Edge Flag
0B
No action
Bit CC62R in register IS will be set.
1B
SCC62F
5
w
Set Capture, Compare-Match Falling Edge Flag
0B
No action
Bit CC62F in register IS will be set.
1B
ST12OM
6
w
Set Timer T12 One-Match Flag
0B
No action
Bit T12OM in register IS will be set.
1B
ST12PM
7
w
Set Timer T12 Period-Match Flag
0B
No action
Bit T12PM in register IS will be set.
1B
ISSH
Capture/Compare Interrupt Status Set Register High
Reset Value: 00H
7
6
5
4
3
2
1
0
S
STR
S
IDLE
S
WHE
S
CHE
S
WHC
S
TRPF
S
T13
PM
S
T13
CM
w
w
w
w
w
w
w
w
Field
Bits
Type
Description
ST13CM
0
w
Set Timer T13 Compare-Match Flag
0B
No action
Bit T13CM in register IS will be set.
1B
ST13PM
1
w
Set Timer T13 Period-Match Flag
0B
No action
Bit T13PM in register IS will be set.
1B
STRPF
2
w
Set Trap Flag
0B
No action
Bits TRPF and TRPS in register IS will be set.
1B
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
SWHC
3
w
Software Hall Compare
0B
No action
The Hall compare action is triggered.
1B
SCHE
4
w
Set Correct Hall Event Flag
0B
No action
Bit CHE in register IS will be set.
1B
SWHE
5
w
Set Wrong Hall Event Flag
0B
No action
Bit WHE in register IS will be set.
1B
SIDLE
6
w
Set IDLE Flag
0B
No action
Bit IDLE in register IS will be set.
1B
SSTR
7
w
Set STR Flag
0B
No action
Bit STR in register IS will be set.
1B
Note: If the setting by hardware of the corresponding flags can lead to an interrupt, the setting by software has the
same effect.
Register ISR contains bits to individually clear the interrupt event flags by software. Writing a 1 clears the bit(s) in
register IS at the corresponding bit position(s). All bit positions read as 0.
ISRL
Capture/Compare Interrupt Status Reset Register Low
Reset Value: 00H
7
6
5
4
3
2
1
0
R
T12
PM
R
T12
OM
R
CC
62F
R
CC
62R
R
CC
61F
R
CC
61R
R
CC
60F
R
CC
60R
w
w
w
w
w
w
w
w
Field
Bits
Type
Description
RCC60R
0
w
Reset Capture, Compare-Match Rising Edge Flag
0B
No action
Bit CC60R in register IS will be reset.
1B
RCC60F
1
w
Reset Capture, Compare-Match Falling Edge Flag
0B
No action
Bit CC60F in register IS will be reset.
1B
RCC61R
2
w
Reset Capture, Compare-Match Rising Edge Flag
0B
No action
Bit CC61R in register IS will be reset.
1B
RCC61F
3
w
Reset Capture, Compare-Match Falling Edge Flag
0B
No action
Bit CC61F in register IS will be reset.
1B
RCC62R
4
w
Reset Capture, Compare-Match Rising Edge Flag
0B
No action
Bit CC62R in register IS will be reset.
1B
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
RCC62F
5
w
Reset Capture, Compare-Match Falling Edge Flag
0B
No action
Bit CC62F in register IS will be reset.
1B
RT12OM
6
w
Reset Timer T12 One-Match Flag
0B
No action
Bit T12OM in register IS will be reset.
1B
RT12PM
7
w
Reset Timer T12 Period-Match Flag
0B
No action
Bit T12PM in register IS will be reset.
1B
ISRH
Capture/Compare Interrupt Status Reset Register High
Reset Value: 00H
7
6
5
4
3
2
1
0
R
STR
R
IDLE
R
WHE
R
CHE
0
R
TRPF
R
T13
PM
R
T13
CM
w
w
w
w
r
w
w
w
Field
Bits
Type
Description
RT13CM
0
w
Reset Timer T13 Compare-Match Flag
0B
No action
Bit T13CM in register IS will be reset.
1B
RT13PM
1
w
Reset Timer T13 Period-Match Flag
0B
No action
Bit T13PM in register IS will be reset.
1B
RTRPF
2
w
Reset Trap Flag
0B
No action
Bit TRPF in register IS will be reset (not taken into account while
1B
input CTRAP = 0 and TRPPEN = 1.
RCHE
4
w
Reset Correct Hall Event Flag
0B
No action
Bit CHE in register IS will be reset.
1B
RWHE
5
w
Reset Wrong Hall Event Flag
0B
No action
Bit WHE in register IS will be reset.
1B
RIDLE
6
w
Reset IDLE Flag
0B
No action
Bit IDLE in register IS will be reset.
1B
RSTR
7
w
Reset STR Flag
0B
No action
Bit STR in register IS will be reset.
1B
0
3
r
Reserved
Returns 0 if read.
Register IEN contains the interrupt enable bits and a control bit to enable the automatic idle function in the case
of a wrong hall pattern.
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Capture/Compare Unit 6 (CCU6)
IENL
Capture/Compare Interrupt Enable Register Low
Reset Value: 00H
7
6
5
4
3
2
1
0
EN
T12
PM
EN
T12
OM
EN
CC
62F
EN
CC
62R
EN
CC
61F
EN
CC
61R
EN
CC
60F
EN
CC
60R
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
ENCC60R
0
rw
Capture, Compare-Match Rising Edge Interrupt Enable for
Channel 0
0B
No interrupt will be generated if the set condition for bit CC60R in
register IS occurs.
An interrupt will be generated if the set condition for bit CC60R in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPCC60.
ENCC60F
1
rw
Capture, Compare-Match Falling Edge Interrupt Enable for
Channel 0
0B
No interrupt will be generated if the set condition for bit CC60F in
register IS occurs.
An interrupt will be generated if the set condition for bit CC60F in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPCC60.
ENCC61R
2
rw
Capture, Compare-Match Rising Edge Interrupt Enable for
Channel 1
0B
No interrupt will be generated if the set condition for bit CC61R in
register IS occurs.
An interrupt will be generated if the set condition for bit CC61R in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPCC61.
ENCC61F
3
rw
Capture, Compare-Match Falling Edge Interrupt Enable for
Channel 1
0B
No interrupt will be generated if the set condition for bit CC61F in
register IS occurs.
An interrupt will be generated if the set condition for bit CC61F in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPCC61.
ENCC62R
4
rw
Capture, Compare-Match Rising Edge Interrupt Enable for
Channel 2
0B
No interrupt will be generated if the set condition for bit CC62R in
register IS occurs.
An interrupt will be generated if the set condition for bit CC62R in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPCC62.
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
ENCC62F
5
rw
Capture, Compare-Match Falling Edge Interrupt Enable for
Channel 2
0B
No interrupt will be generated if the set condition for bit CC62F in
register IS occurs.
An interrupt will be generated if the set condition for bit CC62F in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPCC62.
ENT12OM
6
rw
Enable Interrupt for T12 One-Match
0B
No interrupt will be generated if the set condition for bit T12OM in
register IS occurs.
An interrupt will be generated if the set condition for bit T12OM in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPT12.
ENT12PM
7
rw
Enable Interrupt for T12 Period-Match
0B
No interrupt will be generated if the set condition for bit T12PM in
register IS occurs.
An interrupt will be generated if the set condition for bit T12PM in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPT12.
IENH
Capture/Compare Interrupt Enable Register High
Reset Value: 00H
7
6
5
4
3
2
1
0
EN
STR
EN
IDLE
EN
WHE
EN
CHE
0
EN
TRPF
EN
T13
PM
EN
T13
CM
rw
rw
rw
rw
r
rw
rw
rw
Field
Bits
Type
Description
ENT13CM
0
rw
Enable Interrupt for T13 Compare-Match
0B
No interrupt will be generated if the set condition for bit T13CM in
register IS occurs.
An interrupt will be generated if the set condition for bit T13CM in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPT13.
ENT13PM
1
rw
Enable Interrupt for T13 Period-Match
0B
No interrupt will be generated if the set condition for bit T13PM in
register IS occurs.
An interrupt will be generated if the set condition for bit T13PM in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPT13.
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
ENTRPF
2
rw
Enable Interrupt for Trap Flag
0B
No interrupt will be generated if the set condition for bit TRPF in
register IS occurs.
An interrupt will be generated if the set condition for bit TRPF in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPERR.
ENCHE
4
rw
Enable Interrupt for Correct Hall Event
0B
No interrupt will be generated if the set condition for bit CHE in
register IS occurs.
An interrupt will be generated if the set condition for bit CHE in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPCHE.
ENWHE
5
rw
Enable Interrupt for Wrong Hall Event
0B
No interrupt will be generated if the set condition for bit WHE in
register IS occurs.
An interrupt will be generated if the set condition for bit WHE in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPERR.
ENIDLE
6
rw
Enable Idle
This bit enables the automatic entering of the idle state (bit IDLE will be
set) after a wrong hall event has been detected (bit WHE is set). During
the idle state, the bit field MCMP is automatically cleared.
The bit IDLE is not automatically set when a wrong hall event is
0B
detected.
The bit IDLE is automatically set when a wrong hall event is
1B
detected.
ENSTR
7
rw
Enable Multi-Channel Mode Shadow Transfer Interrupt
0B
No interrupt will be generated if the set condition for bit STR in
register IS occurs.
An interrupt will be generated if the set condition for bit STR in
1B
register IS occurs. The interrupt line that will be activated is
selected by bit field INPCHE.
0
3
r
Reserved
Returns 0 if read.
Register INP contains the interrupt node pointers allowing a flexible interrupt handling. These bit fields define
which service request output will be activated if the corresponding interrupt event occurs and the interrupt
generation for this event is enabled.
INPL
Capture/Compare Interrupt Node Pointer Register Low
7
6
5
4
Reset Value: 40H
3
2
1
0
INP
CHE
INP
CC62
INP
CC61
INP
CC60
rw
rw
rw
rw
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
INPCC60
1:0
rw
Interrupt Node Pointer for Channel 0 Interrupts
This bit field defines the interrupt output line, which is activated due to
a set condition for bit CC60R (if enabled by bit ENCC60R) or for bit
CC60F (if enabled by bit ENCC60F).
00B Interrupt output line SR0 is selected.
01B Interrupt output line SR1 is selected.
10B Interrupt output line SR2 is selected.
11B Interrupt output line SR3 is selected.
INPCC61
3:2
rw
Interrupt Node Pointer for Channel 1 Interrupts
This bit field defines the interrupt output line, which is activated due to
a set condition for bit CC61R (if enabled by bit ENCC61R) or for bit
CC61F (if enabled by bit ENCC61F).
00B Interrupt output line SR0 is selected.
01B Interrupt output line SR1 is selected.
10B Interrupt output line SR2 is selected.
11B Interrupt output line SR3 is selected.
INPCC62
5:4
rw
Interrupt Node Pointer for Channel 2 Interrupts
This bit field defines the interrupt output line, which is activated due to
a set condition for bit CC62R (if enabled by bit ENCC62R) or for bit
CC62F (if enabled by bit ENCC62F).
00B Interrupt output line SR0 is selected.
01B Interrupt output line SR1 is selected.
10B Interrupt output line SR2 is selected.
11B Interrupt output line SR3 is selected.
INPCHE
7:6
rw
Interrupt Node Pointer for the CHE Interrupt
This bit field defines the interrupt output line, which is activated due to
a set condition for bit CHE (if enabled by bit ENCHE) or for bit STR (if
enabled by bit ENSTR).
00B Interrupt output line SR0 is selected.
01B Interrupt output line SR1 is selected.
10B Interrupt output line SR2 is selected.
11B Interrupt output line SR3 is selected.
INPH
Capture/Compare Interrupt Node Pointer Register High
7
6
5
4
Reset Value: 39H
3
2
1
0
0
INP
T13
INP
T12
INP
ERR
r
rw
rw
rw
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type
Description
INPERR
1:0
rw
Interrupt Node Pointer for Error Interrupts
This bit field defines the interrupt output line, which is activated due to
a set condition for bit TRPF (if enabled by bit ENTRPF) or for bit WHE
(if enabled by bit ENWHE).
00B Interrupt output line SR0 is selected.
01B Interrupt output line SR1 is selected.
10B Interrupt output line SR2 is selected.
11B Interrupt output line SR3 is selected.
INPT12
3:2
rw
Interrupt Node Pointer for Timer T12 Interrupts
This bit field defines the interrupt output line, which is activated due to
a set condition for bit T12OM (if enabled by bit ENT12OM) or for bit
T12PM (if enabled by bit ENT12PM).
00B Interrupt output line SR0 is selected.
01B Interrupt output line SR1 is selected.
10B Interrupt output line SR2 is selected.
11B Interrupt output line SR3 is selected.
INPT13
5:4
rw
Interrupt Node Pointer for Timer T13 Interrupts
This bit field defines the interrupt output line, which is activated due to
a set condition for bit T13CM (if enabled by bit ENT13CM) or for bit
T13PM (if enabled by bit ENT13PM).
00B Interrupt output line SR0 is selected.
01B Interrupt output line SR1 is selected.
10B Interrupt output line SR2 is selected.
11B Interrupt output line SR3 is selected.
0
7:6
r
Reserved
Returns 0 if read.
17.10
TLE983x Module Implementation Details
This section describes the CCU6 module interfaces with the clock control, port connections, interrupt control, and
address decoding.
17.10.1
Interfaces of the CCU6 Module
An overview of the CCU6 kernel I/O interface is shown in Figure 122.
The Bus Peripheral Interface (BPI) enables the CCU6 kernel to be attached to the 8-bit Bus. The BPI consists of
a clock control logic which gates the clock input to the kernel, and an address decoder for Special Function
Registers (SFRs) in the CCU6 kernel.
The interrupt lines of the CCU6 are connected to the CPU interrupt controller via the SCU. An interrupt pulse can
be generated at one of the four interrupt output lines SRCx (x=0 to 4) of the module. More than one CCU6 interrupt
source can be connected to each CCU6 interrupt line.
The General Purpose IO (GPIO) Ports provide the interface from the CCU6 to the external world. Please refer to
Chapter 13 for Port implementation details.
The CCU6 kernel is clocked on PCLK frequency where fCCU = fPCLK.
Debug Suspend of Timers
The timers of CCU6, T12 and T13, can be suspended immediately when OCDS enters Monitor Mode and has the
Debug-Suspend signal activated – provided the respective timer suspend bits, T12SUSP and T13SUSP (in SCU
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Capture/Compare Unit 6 (CCU6)
SFR MODSUSP), are set. When suspended, the respective timer stops and its PWM outputs enabled for the trap
condition (TRPCTRH.TRPENx = 1) are set to respective passive levels (similar to TRAP state). In addition, all
CCU6 inputs are frozen. Refer to SCU Chapter 20.7 and OCDS chapter.
Flexible Peripheral Management (Kernel Clock Gating) of CCU6
When not in use, the CCU6 kernel may be disabled where the kernel clock input is gated. When the
PMCON1.CCU_DIS request bit is set, both T12 and T13 are immediately stopped and PWM outputs enabled for
the trap condition (TRPCTRH.TRPENx = 1) are set to respective passive levels (similar to TRAP state). In
addition, all CCU6 inputs are frozen. Finally, the kernel clock input is gated. Refer to SCU Chapter 20.6.
Figure 122 shows all interrupt and interface signals and GPIO interface associated with the CCU6 module kernel.
CC60
CC61
Interrupt
Controller
/CTRAP
SRC0
SRC1
SRC2
SRC3
P2.3/P0.2
CCPOS0
P2.1/P0.3/P1.3
CCPOS1
P2.3/P0.4/P1.4
CCPOS2
CC60
T12_SUSPEND
P0.4/P2.3
COUT60
T13_SUSPEND
Clock
Control
P2.7/P0.5/P1.2
fC C U
CCU6
Module
(Kernel )
CC61
COUT61
CC62
COUT62
Address
Decoder
COUT63
P0.5
Port
Control
P1.0/P2.1
P1.1
P1.3/P2.7
P1.4
P1.2
T12HRA/B
P2.1/P0.0
T13HRA/B
P2.7/P0.1
BPI
Figure 122 Interconnections of the CCU6 Module
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UART
18
UART
The UART provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive
simultaneously. It is also receive-buffered, i.e., it can commence reception of a second byte before a previously
received byte has been read from the receive register. However, if the first byte still has not been read by the time
reception of the second byte is complete, the previous byte will be lost. The serial port receive and transmit
registers are both accessed at Special Function Register (SFR) SBUF. Writing to SBUF loads the transmit register,
and reading SBUF accesses a physically separate receive register.
UART Features
•
•
•
•
•
•
Full-duplex asynchronous modes
– 8-Bit or 9-Bit data frames, LSB first
– fixed or variable baud rate
Receive buffered (1 Byte)
Multiprocessor communication
Interrupt generation on the completion of a data transmission or reception
Baude-rate generator with fractional divider for generating a wide range of baude rates
Hardware logic for break and synch Byte detection
In all modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is
initiated in the modes by the incoming start bit if REN = 1.
The serial interface also provides interrupt requests when transmission or reception of the frames has been
completed. The corresponding interrupt request flags are TI or RI, respectively. If the serial interrupt is not used
(i.e., serial interrupt not enabled), TI and RI can also be used for polling the serial interface.
18.1
UART Modes
The UART can be used in four different modes. In mode 0, it operates as an 8-Bit shift register. In mode 1, it
operates as an 8-Bit serial port. In modes 2 and 3, it operates as a 9-Bit serial port. The only difference between
mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in mode 3. The variable baud rate is
set by the underflow rate on the dedicated baud-rate generator.
The different modes are selected by setting bits SM0 and SM1 to their corresponding values, as shown in
Table 73.
Table 73
UART Modes
SM0
SM1
0
0
Mode 0: 8-Bit shift register
fPCLK/2
0
1
Mode 1: 8-Bit shift UART
Variable
1
0
Mode 2: 9-Bit shift UART
fPCLK/64 or fPCLK/32
1
1
Mode 3: 9-Bit shift UART
Variable
18.1.1
Operating Mode
Baud Rate
Mode 0, 8-Bit Shift Register, Fixed Baud Rate
In mode 0, the serial port behaves as an 8-bit shift register. Data is shifted in through RXD, and out through RXDO,
while the TXD line is used to provide a shift clock which can be used by external devices to clock data in and out.
The transmission cycle is activated by a write to SBUF. The data will be written to the transmit shift register with
a 1 at the 9th bit position. For the next seven machine cycles, the contents of the transmit shift register are shifted
right one position and a zero shifted in from the left so that when the MSB of the data byte is at the output position,
it has a 1 and a sequence of zeros to its left. The control block then executes one last shift before setting the TI bit.
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Reception is started by the condition REN = 1 and RI = 0. At the start of the reception cycle, 11111110B is written
to the receive shift register. In each machine cycle that follows, the contents of the shift register are shifted left one
position and the value sampled on the RXD line in the same machine cycle is shifted in from the right. When the
0 of the initial byte reaches the leftmost position, the control block executes one last shift, loads SBUF and sets
the RI bit.
The baud rate for the transfer is fixed at fPCLK/2 where fPCLK is the input clock frequency, i.e. one bit per machine
cycle.
18.1.2
Mode 1, 8-Bit UART, Variable Baud Rate
In mode 1, the UART behaves as an 8-bit serial port. A start bit (0), 8 data bits, and a stop bit (1) are transmitted
on TXD or received on RXD at a variable baud rate.
The transmission cycle is activated by a write to SBUF. The data are transferred to the transmit shift register and
a 1 is loaded to the 9th bit position (as in mode 0). At phase 1 of the machine cycle after the next rollover in the
divide-by-16 counter, the start bit is copied to TXD, and data is activated one bit time later. One bit time after the
data is activated, the data starts getting shifted right with zeros shifted in from the left. When the MSB gets to the
output position, the control block executes one last shift and sets the TI bit.
Reception is started by a high to low transition on RXD (sampled at 16 times the baud rate). The divide-by-16
counter is then reset and 1111 1111B is written to the receive register. If a valid start bit (0) is then detected (based
on two out of three samples), it is shifted into the register followed by 8 data bits. If the transition is not followed
by a valid start bit, the controller goes back to looking for a high to low transition on RXD. When the start bit reaches
the leftmost position, the control block executes one last shift, then loads SBUF with the 8 data bits, loads RB8
(SCON.2) with the stop bit, and sets the RI bit, provided RI = 0 (SCON.0), and either SM2 = 0 (SCON.5) (see
Section 18.2) or the received stop bit = 1. If none of these conditions is met, the received byte is lost.
The associated timings for transmit/receive in mode 1 are illustrated in Figure 123.
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TX
Clock
txd_en
lin_rx
_rdy
Transmit
SEND
Data
Shift
TXD
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
Bit
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
Bit
TI
RX
Clock
RXD
Receive
Bit Detector
Sample Times
Shift
RI
rxd
_finish
Figure 123 Serial Interface, Mode 1, Timing Diagram
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18.1.3
Mode 2, 9-Bit UART, Fixed Baud Rate
In mode 2, the UART behaves as a 9-bit serial port. A start bit (0), 8 data bits plus a programmable 9th bit and a
stop bit (1) are transmitted on TXD or received on RXD. The 9th bit for transmission is taken from TB8 (SCON.3)
while for reception, the 9th bit received is placed in RB8 (SCON.2).
The transmission cycle is activated by a write to SBUF. The data is transferred to the transmit shift register and
TB8 is copied into the 9th bit position. At phase 1 of the machine cycle following the next rollover in the divide-by16 counter, the start bit is copied to TXD and data is activated one bit time later. One bit time after the data is
activated, the data starts shifting right. For the first shift, a stop bit (1) is shifted in from the left and for subsequent
shifts, zeros are shifted in. When the TB8 bit gets to the output position, the control block executes one last shift
and sets the TI bit.
Reception is started by a high to low transition on RXD (sampled at 16 times of the baud rate). The divide-by-16
counter is then reset and 1111 1111B is written to the receive register. If a valid start bit (0) is then detected (based
on two out of three samples), it is shifted into the register followed by 8 data bits. If the transition is not followed
by a valid start bit, the controller goes back to looking for a high to low transition on RXD. When the start bit reaches
the leftmost position, the control block executes one last shift, then loads SBUF with the 8 data bits, loads RB8
(SCON.2) with the 9th data bit, and sets the RI bit, provided RI = 0 (SCON.0), and either SM2 = 0 (SCON.5) (see
Section 18.2) or the 9th bit = 1. If none of these conditions is met, the received byte is lost.
The baud rate for the transfer is fixed at fPCLK/64 or fPCLK/32.
18.1.4
Mode 3, 9-Bit UART, Variable Baud Rate
Mode 3 is the same as mode 2 in all respects except that the baud rate is variable.
The associated timings for transmit/receive in modes 2 and 3 are illustrated in Figure 124.
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TX
Clock
txd_en
lin_rx
_rdy
T r ans m it
SEND
Data
Shift
TXD
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
TB8
Stop
Bit
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
RB8
Stop
Bit
TI
RX
Clock
RXD
R ec eiv e
Bit Detector
Sample Times
Shift
RI
rxd
_finish
Figure 124 Serial Interface, Modes 2 and 3, Timing Diagram
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18.2
Multiprocessor Communication
Modes 2 and 3 have a special provision for multiprocessor communication using a system of address bytes with
bit 9 = 1 and data bytes with bit 9 = 0. In these modes, 9 data bits are received. The 9th data bit goes into RB8
(SCON.2). The communication always ends with one stop bit. The port can be programmed such that when the
stop bit is received, the serial port interrupt will be activated only if RB8 = 1.
This feature is enabled by setting bit SM2 in register SCON. One of the ways to use this feature in multiprocessor
systems is described in the following paragraph.
When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address
byte that identifies the target slave. An address byte differs from a data byte in the 9th bit. The 9th bit in an address
byte is 1 and in a data byte the 9th bit is 0. With SM2 = 1, no slave will be interrupted by a data byte. An address
byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being
addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming.
The slaves that were not being addressed retain their SM2 bits as set and ignore the incoming data bytes.
Note: Bit SM2 has no effect in mode 0. SM2 can be used in mode 1 to check the validity of the stop bit. In a mode
1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
18.3
Interrupts
The two UART interrupts can be separately enabled or disabled by setting or clearing their corresponding enable
bits in SCU SFR MODIEN. An overview of the UART interrupt sources is shown in Table 74.
Table 74
UART Interrupt Sources
Interrupt
Flag
Interrupt Enable Bit
Reception completed
SCON.RI
SCU_MODIEN.RIEN
Transmission completed
SCON.TI
SCU_MODIEN.TIEN
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18.4
Baud Rate Generation
There are several ways to generate the baud rate clock for the serial port, depending on the mode in which they
are operating.
The baud rates in modes 0 and 2 are fixed to fPCLK/2 and fPCLK/64 respectively, while the variable baud rate in
modes 1 and 3 is generated based on the setting of the Baud-rate generator in SCU (see Section 18.4.1).
“Baud rate clock” and “baud rate” must be distinguished from each other. The serial interface requires a clock rate
that is 16 times the baud rate for internal synchronization. Therefore, the UART baud-rate generator must provide
a “baud rate clock” to the serial interface where it is divided by 16 to obtain the actual “baud rate”. The abbreviation
fPCLK refers to the input clock frequency.
18.4.1
Baud-rate Generator
The baud-rate generator in SCU is used to generate the variable baud rate for the UART in modes 1 and 3. It has
programmable 11-bit reload value, 3-bit prescaler and 5-bit fractional divider.
The baud-rate generator clock is derived via a prescaler (fDIV) from the input clock fPCLK. The baud rate timer counts
downwards and can be started or stopped through the baud rate control run bit BCON.R. Each underflow of the
timer provides one clock pulse to the serial channel. The timer is reloaded with the 11-bit BR_VALUE stored in its
reload register BGL/BGH each time it underflows. The duration between underflows depends on the ‘n’ value in
the fractional divider, which can be selected by the bits BGL.FD_SEL. ‘n’ times out of 32, the timer counts one
cycle more than specified by BR_VALUE. The prescaler is selected by the bits BCON.BRPRE.
Register BGL/BH is the dual-function Baud-rate Generator/Reload register. Reading BGL/GBH returns the
contents of the timer, while writing to BGL (low byte) always updates the reload register.
The register BGL/BGH should be written only when BCON.R is 0. An auto-reload of the timer with the contents of
the reload register is performed one instruction cycle after the next time BCON.R is set. Any write to BGL/GBH,
while BCON.R is set, will be ignored.
The baud rate of the baud-rate generator depends on the following bits and register values:
•
•
•
•
Input clock fPCLK
Value of bit field BCON.BRPRE.
Value of bit field BGL.FD_SEL
Value of the 11-bit reload value BGL/BGH.BR_VALUE
Figure 125 shows a simplified block diagram of the baud rate generator.
fPCLK
fDIV
Prescaler
Baud rate timer
with
Fractional Divider
fBR
R
Figure 125 Simplifed Baud Rate Generator Block Diagram
The following formula calculate the final baud rate.
(10)
f PCLK
Baud rate = ------------------------------------------------------------------------------n-⎞
16 × PRE × ⎛ BR_VALUE + ----⎝
32⎠
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The value of PRE (prescaler) is chosen by the bit field BCON.BRPRE. BR_VALUE represents the contents of the
reload value, taken as unsigned 11-bit integer from the bit field BGL/BGH.BR_VALUE. n/32 is defined by the
fractional divider selection in bit field BGL.FDSEL.
The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for module clocks of 40 MHz and
24 MHz, the maximum achievable baud rate is 1.25 MBaud and 0.75 MBaud respectively.
Table 75 and Table 76 list various commonly used baud rates together with their corresponding parameter
settings and the deviation errors compared to the intended baud rate.
Table 75
Typical Baud Rates of UART (fPCLK = 40 MHz)
Baud rate
PRE
(fPCLK = 40 MHz)
Reload Value
(BR_VALUE)
115.2 kBaud
1 (BRPRE = 000)
21 (15H)
20 kBaud
1 (BRPRE = 000)
125 (7DH)
19.2 kBaud
1 (BRPRE = 000)
130 (82H)
9600 Baud
2 (BRPRE = 001)
4800 Baud
2400 Baud
BG
Register1)
Deviation
Error
22 (16H)
02B6H
+0.06%
0 (0H)
0FA0H
0.00%
7 (7H)
1047H
-0.01%
130 (82H)
7 (7H)
1047H
-0.01%
4 (BRPRE = 010)
130 (82H)
7 (7H)
1047H
-0.01%
8 (BRPRE = 011)
130 (82H)
7 (7H)
1047H
-0.01%
Numerator of
Fractional Value
(FD_SEL)
1) The value of the 16-bit BG register is obtained by concatenation the 11-bit BRVALUE and 5-bit FD_SEL into a 16-bit value.
Table 76
Typical Baud Rates of UART (fPCLK = 24 MHz)
Baud rate
PRE
(fPCLK = 24 MHz)
Reload Value
(BR_VALUE)
Numerator of
Fractional Value
(FD_SEL)
BG
Register1)
Deviation
Error
115.2 kBaud
1 (BRPRE = 000)
13 (0DH)
1 (01H)
01A1H
-0.08%
20 kBaud
1 (BRPRE = 000)
75 (4BH)
0 (00H)
0960H
+0.00%
19.2 kBaud
1 (BRPRE = 000)
78 (4EH)
4 (04H)
09C4H
+0.00%
9600 Baud
2 (BRPRE = 001)
78 (4EH)
4 (04H)
09C4H
+0.00%
4800 Baud
4 (BRPRE = 010)
78 (4EH)
4 (04H)
09C4H
+0.00%
2400 Baud
8 (BRPRE = 011)
78 (4EH)
4 (04H)
09C4H
+0.00%
1) The value of the 16-bit BG register is obtained by concatenation the 11-bit BRVALUE and 5-bit FD_SEL into a 16-bit value.
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18.5
LIN Support in UART
The UART module can be used to support the Local Interconnect Network (LIN) protocol for both master and slave
operations. The LIN baud rate detection feature, which consists of the hardware logic for Break and Synch Byte
detection, provides the capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART
module to be synchronized to the LIN baud rate for data transmission and reception.
18.5.1
LIN Protocol
LIN is a holistic communication concept for local interconnected networks in vehicles. The communication is based
on the SCI (UART) data format, a single-master/multiple-slave concept, a clock synchronization for nodes without
stabilized time base. An attractive feature of LIN is the self-synchronization of the slave nodes without a crystal or
ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the baud rate must be
calculated and returned with every message frame.
The structure of a LIN frame is shown in Figure 126. The frame consists of the:
•
•
•
•
header, which comprises a Sync Break (13-bit time low), Synch Byte (55H), and ID field
response time
data bytes (according to UART protocol)
checksum
Frame slot
Frame
Response
space
Header
Synch
Protected
identifier
Interframe
space
Response
Data 1
Data 2
Data N
Checksum
Figure 126 The Structure of LIN Frame
Each byte field is transmitted as a serial byte, as shown in Figure 127. The LSB of the data is sent first and the
MSB is sent last. The start bit is encoded as a bit with value zero (dominant) and the stop bit is encoded as a bit
with value one (recessive).
Byte field
Start
Bit
LSB
(bit 0)
MSB
(bit 7)
Stop
Bit
Figure 127 The Structure of Byte Field
The Sync Break is used to signal the beginning of a new frame. It is the only field that does not comply with
Figure 127. A Sync Break is always generated by the master task (in the Master Mode) and it must be at least 13
bits of dominant value, including the start bit, followed by a Sync Break Delimiter, as shown in Figure 128. The
Sync Break Delimiter will be at least one nominal bit time long.
A slave node will use a Sync Break detection threshold of 11 nominal bit times.
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Start
Bit
Break
delimit
Figure 128 The Sync Break Field
The Synch Byte is a specific pattern for the determination of the time base. The Sync Byte field consists of the
data value 55H, as shown in Figure 129.
A slave task is always able to detect the Sync Break/Synch sequence, even if it expects a byte field (assuming the
byte fields are separated from each other). If this happens, detection of the Sync Break/Synch sequence will abort
the transfer in progress and processing of the new frame will commence.
Start
Bit
Stop
Bit
Figure 129 The Synch Byte Field
The slave task will receive and transmit data when an appropriate ID is sent by the master:
1.
2.
3.
4.
5.
The slave waits for the Synch Break
The slave synchronizes on the Synch Byte
The slave snoops for the ID
According to the ID, the slave determines whether to receive or transmit data, or do nothing
When transmitting, the slave sends 2, 4 or 8 data bytes, followed by a Check Byte
18.5.2
LIN Header Transmission
LIN header transmission is only applicable in Master Mode. In the LIN communication, a master task decides when
and which frame is to be transferred on the bus. It also identifies a slave task to provide the data transported by
each frame. The information needed for the handshaking between the master and slave, tasks is provided by the
master task through the header part of the frame.
The header consists of a Sync Break and Sync Byte pattern followed by an identifier. Among these three fields,
only the Sync Break pattern cannot be transmitted as a normal 8-bit UART data. The Sync Break must contain a
dominant value of 13 bits or more to ensure proper synchronization of slave nodes.
In the LIN communication, a slave task is required to be synchronized at the beginning of the protected identifier
field of the frame. For this purpose, every frame starts with a sequence consisting of a Sync Break followed by a
Synch Byte field. This sequence is unique and provides enough information for any slave task to detect the
beginning of a new frame and to be synchronized at the start of the identifier field.
18.5.3
Automatic Synchronization to the Host
Upon entering LIN communication, a connection is established and the transfer speed (baud rate) of the serial
communication partner (host) is automatically synchronized in the following steps that are to be included in the
user software:
STEP 1: Initialize interface for reception and timer for baud rate measurement
STEP 2: Wait for an incoming LIN frame from host
STEP 3: Synchronize the baud rate to the host
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STEP 4: Enter for Master Request Frame or for Slave Response Frame
The next sections, Section 18.5.4, Section 18.5.5 and Section 18.5.6 provide some hints on setting up the
microcontroller for baud rate detection of LIN.
Note: Re-synchronization and setup of the baud rate has always to be done for every Master Request Header or
Slave Response Header LIN frame by user software.
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18.5.4
Initialization of Break/Synch Field Detection Logic
The LIN baud rate detection feature provides the capability to detect the baud rate within the LIN protocol using
Timer 2. Initialization consists of:
•
•
•
•
•
•
•
Setting of the serial port of the microcontroller to Mode 1 (8-bit UART, variable baud rate) for communication.
Providing the baud rate range via bit field BCON.BGSEL.
Toggling of the BCON.BRDIS bit (set the bit to 1 before clearing it back to 0) to initialize the Sync Break/Synch
detection logic.
Clearing all status flags LINST.BRK, LINST.EOFSYN and LINST.ERRSYN to 0.
Setting of Timer 2 to capture mode with falling edge trigger at pin T2EX. Setting of the bits T2MOD.EDGESEL
to 0 by default and T2CON.CP/RL2 to 1.
Enabling Timer 2 external events. T2CON. EXEN2 is set to 1. (EXF2 flag is set when a negative transition
occurs at pin T2EX)
Configuring of fT2 by bit field T2MOD.T2PRE.
18.5.5
Baud Rate Range Selection
The Sync Break/Synch Field detection logic supports a maximum number of bits in the Sync Break field as defined
by Equation (11).
(11)
4095
Maximum number of bits = Baud Rate × -------------------------------------------Sample Frequency
The sample frequency is given by Equation (12).
(12)
f PCLK
Sample Frequency = --------------------------BGSEL
8×2
If the maximum number of bits in the Break field is exceeded, the internal counter will overflow, which results in a
baudrate detection error. Therefore, an appropriate BGSEL value has to be selected for the required baudrate
detection range.
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The baud rate range defined by different BGSEL settings is shown in Table 77.
Table 77
BGSEL Bit Field Definition for Different Input Frequencies
fPCLK
BGSEL
Baud Rate Select for Detection
fpclk/(2184*2BGSEL) to fpclk/(72*2BGSEL)
40 MHz
00B
18.3 kHz to 555.6 kHz
01B
9.2 kHz to 277.8 kHz
10B
4.6 kHz to 138.9 kHz
11B
2.3 kHz to 69.4 kHz
00B
11 kHz to 333.3 kHz
01B
5.5 kHz to 166.7 kHz
10B
2.8 kHz to 83.3 kHz
11B
1.4 kHz to 41.7 kHz
24 MHz
Each BGSEL setting supports a range of baud rate for detection. If the baud rate used is outside the defined range,
the baud rate may not be detected correctly.
When fpclk = 40 MHz, the baud rate range between 18.3 kHz to 555.6 kHz can be detected. The following
examples serve as a guide to select the BGSEL value:
•
•
•
•
•
If the baud rate falls in the range of 2.3 kHz to 4.6 kHz, selected BGSEL value is “11B”.
If the baud rate falls in the range of 4.6 kHz to 9.2 kHz, selected BGSEL value is “10B”.
If the baud rate falls in the range of 9.2 kHz to 18.3 kHz, selected BGSEL value is “01B”.
If the baud rate falls in the range of 18.3 kHz to 555.6 kHz, selected BGSEL value is “00B”.
If the baud rate is 20 kHz, the possible values of BGSEL that can be selected are “00B”, “01B”, “10B”, and “11B”.
However, it is advisable to select “00B” for better detection accuracy.
The baud rate can also be detected when fpclk = 24 MHz, for which the baud rate range that can be detected is
between 1.4 kHz to 333.3 kHz.
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18.5.6
LIN Baud Rate Detection
The baud rate detection for LIN is shown in Figure 130, the Header LIN frame consists of the:
•
•
•
Sync Break (13 bit times low)
Sync Byte (55H)
Protected ID field
1st negative transition,
set T2RHEN bit
T2 automatically
starts
Last captured value of T2
upon negative transition
EOFSYN bit is set,
T2 is stopped
SYN CHAR (55H)
SYN BREAK
Start
Bit
Check the break field
flag bit BRK is set or not
Stop
Bit
Captured Value (8 bits)
Figure 130 LIN Auto Baud Rate Detection
With the first falling edge:
•
The Timer 2 External Start Enable bit (T2MOD.T2RHEN) is set. The falling edge at pin T2EX is selected by
default for Timer 2 External Start (bit T2MOD.T2REGS is 0).
With the second falling edge:
•
Start Timer 2 by the hardware.
With the third falling edge:
•
•
Timer 2 captures the timing of 2 bits of SYN byte.
Check the Break Field Flag bit LINST.BRK.
If the Sync Break Field Flag LINST.BRK is set, software may continue to capture 4/6/8 bits of Sync Byte. Finally,
the End of Sync Byte Flag (LINST.EOFSYN) is set, Timer 2 is stopped. T2 Reload/Capture register (RC2H/L) is
the time taken for 2/4/6/8 bits according to the implementation. Then the LIN routine calculates the actual baud
rate, sets the BRPRE and BGL/BGH values if the UART module uses the baud-rate generator for baud rate
generation.
After the third falling edge, the software may discard the current operation and continue to detect the next header
LIN frame if the following conditions were detected:
•
•
The Sync Break Field Flag LINST.BRK is not set, or
The Sync Byte Error Flag LINST.ERRSYN is set
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18.6
Register Description
18.6.1
UART Registers
UART uses the Special Function Registers (SFRs), SCON, SBUF, BCON, LINST, BGL and BGH. SCON is the
control register and SBUF is the data register. On reset, both SCON and SBUF return 00H. The serial port control
and status register is the SFR SCON. This register contains not only the mode selection bits, but also the 9th data
bit for transmit and receive (TB8 and RB8) and the serial port interrupt bits (TI and RI).
SBUF is the receive and transmit buffer of the serial interface. Writing to SBUF loads the transmit register and
initiates transmission. This register is used for both transmit and receive data. Transmit data is written to this
location and receive data is read from this location, but the two paths are independent.
Reading out SBUF accesses a physically separate receive register. The registers BCON, LINST, BGL and BGH
are paged SFRs and are described in Chapter 18.6.2 and Chapter 18.6.3.
SBUF
Serial Data Buffer
7
Reset Value: 00H
6
5
4
3
2
1
0
VAL
rwh
Field
Bits
Type
Description
VAL
[7:0]
rwh
Serial Interface Buffer Register
SCON
Serial Channel Control Register
Reset Value: 00H
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
rw
rw
rw
rw
rw
rwh
rwh
rwh
Field
Bits
Type
Description
RI
0
rwh
Receive Interrupt Flag
This is set by hardware at the end of the 8th bit on mode 0, or at the
half point of the stop bit in modes 1, 2, and 3. Must be cleared by
software.
TI
1
rwh
Transmit Interrupt Flag
This is set by hardware at the end of the 8th bit in mode 0, or at the
beginning of the stop bit in modes 1, 2, and 3. Must be cleared by
software.
RB8
2
rwh
Serial Port Receiver Bit 9
In modes 2 and 3, this is the 9th data bit received.
In mode 1, this is the stop bit received.
In mode 0, this bit is not used.
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Field
Bits
Type
Description
TB8
3
rw
Serial Port Transmitter Bit 9
In modes 2 and 3, this is the 9th data bit sent.
In mode 1, this bit is set to 1
In mode 0, this bit is set to 1
REN
4
rw
Enable Receiver of Serial Port
0B
Serial reception is disabled.
Serial reception is enabled.
1B
SM2
5
rw
Enable Serial Port Multiprocessor Communication in Modes 2 and 3
Mode 2 or 3:
- if SM2 = 1: RI will not be activated if the received 9th data bit (RB8)
is 0.
Mode 1:
- if SM2 = 1: RI will not be activated if no valid stop bit (RB8) was
received.
Mode 0:
- SM2 should be 0.
SM1,
SM0
6
7
rw
Serial Port Operating Mode Selection
00B Mode 0: 8-bit shift register, fixed baud rate (fPCLK/2).
01B Mode 1: 8-bit UART, variable baud rate.
10B Mode 2: 9-bit UART, fixed baud rate (fPCLK/64 or fPCLK/32).
11B Mode 3: 9-bit UART, variable baud rate.
18.6.2
Baud-rate Generator Control and Status Registers
BCON
Baud Rate Control Register
7
6
Reset Value: 00H
5
4
3
2
BGSEL
0
BRDIS
BRPRE
R
rw
r
rw
rw
rw
Field
Bits
Type
Description
R
0
rw
Baud Rate Generator Run Control Bit
0B
Baud-rate generator disabled.
Baud-rate generator enabled.
1B
1
0
Note: BR_VALUE should only be written if BCON.R = 0.
BRPRE
User’s Manual
[3:1]
rw
Prescaler Bit
Selects the input clock for fDIV which is derived from the peripheral
clock.
000B fDIV = fPCLK
001B fDIV = fPCLK/2
010B fDIV = fPCLK/4
011B fDIV = fPCLK/8
100B fDIV = fPCLK/16
101B fDIV = fPCLK/32
Others: reserved
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UART
Field
Bits
Type
Description
BRDIS
4
rw
Baud Rate Detection Disable
0B
Sync Break/Synch detection is enabled.
Sync Break/Synch detection is disabled.
1B
0
5
r
Reserved
Returns 0 if read; should be written with 0.
BGSEL
[7:6]
rw
Baud Rate Select for Detection
For different values of BGSEL, the baud rate range for detection is
defined by the following formula:
fpclk/(2184*2BGSEL) < baud rate range < fpclk/(72*2BGSEL)
where BGSEL = 00B, 01B, 10B, 11B.
See Table 77 for bit field BGSEL definition for different input
frequencies.
LINST
LIN Status Register
Reset Value: 00H
7
6
5
4
3
0
SYNEN
ERRSYN
EOFSYN
BRK
0
r
rw
rwh
rwh
rwh
r
1
0
Field
Bits
0
7, [2:0] r
Reserved
Returns 0 if read; should be written with 0.
BRK
3
rwh
Sync Break Field Flag
This bit is set by hardware and can only be cleared by software.
Sync Break Field is not detected.
0B
Sync Break Field is detected.
1B
EOFSYN
4
rwh
End of Sync Byte Interrupt Flag
This bit is set by hardware and can only be cleared by software.
End of Sync Byte is not detected.
0B
End of Sync Byte is detected.
1B
ERRSYN
5
rwh
Sync Byte Error Interrupt Flag
This bit is set by hardware and can only be cleared by software.
Error is not detected in Sync Byte.
0B
Error is detected in Sync Byte.
1B
SYNEN
6
rw
End of Sync Byte and Sync Byte Error Interrupts Enable
0B
End of Sync Byte and Sync Byte Error Interrupts are disabled.
End of Sync Byte and Sync Byte Error Interrupts are enabled.
1B
18.6.3
Type
2
Description
Baud-rate Generator Timer/Reload Registers
The baud rate Timer/Reload registers BGH/BGL contain the 11-Bit reload value for the baud rate timer and the 5Bit fractional divider selection.
Reading the register BGL returns the content of the lower three bits of the baud rate timer and the fractional divider
selector (FD_SEL). While reading the register BGH returns the content of the upper eight bits of the baud rate
timer.
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Writing to registers BGH/BGL loads the baud rate timer with the reload value and the fractional divider value. Prior
to setting a new baud rate by writing the BGH/BGL the run bit of the baud rate generator BCON.R needs to be set
to ‘0’. After the BGH/BGL registers are updated the run bit of the baud rate generator BCON.R may be set to ‘1’.
BGL
Baud Rate Timer/Reload Register, Low Byte
7
6
5
Reset Value: 00H
4
3
2
BR_VALUE
FD_SEL
rwh
rw
1
0
Field
Bits
Type
Description
FD_SEL
[4:0]
rw
Fractional Divider Selection
Selects the fractional divider to be n/32, where n is the value of
FD_SEL and is in the range of 0 to 31.
For example, writing 0001B to FD_SEL selects the fractional divider to
be1/32.
Note: Fractional divider has no effect if BR_VALUE = 000H .
[7:5]
BR_VALUE
rwh
Baud Rate Timer/Reload Value
The lower three bits of the 11-bit Baud Rate Timer/Reload value.
See description in BGH register.
BGH
Baud Rate Timer/Reload Register, High Byte
7
6
5
Reset Value: 00H
4
3
2
1
0
BR_VALUE
rwh
Field
Bits
Type
Description
BR_VALUE
[7:0]
rwh
Baud Rate Timer/Reload Value
The upper 8 bits of the 11-bit Baud Rate Timer/Reload value.
The definition of the 11-bit reload value is as follows:
000H Baud-rate timer is bypassed.
001H 1
002H 2
:
:
:
:
:
:
7FEH 2046
7FFH 2047
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UART
18.7
Register Map
Besides the SCON and SBUF registers, which can be accessed from both the standard (non-mapped) and
mapped SFR area, the rest of the UART’s SFRs are located in SCU page 5 of the standard area.
Table 78 lists the addresses of these SFRs.
Table 78
UART Module SFR Address List
Address
Register
98H
SCON
99H
SBUF
F2H (SCU Page 5)
BCON
F3H (SCU Page 5)
BGL
F4H (SCU Page 5)
BGH
F5H (SCU Page 5)
LINST
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UART
18.8
Interfaces of UART
An overview of the UART I/O interface is shown in Figure 131.
In mode 0 (the serial port behaves as a shift register) data is shifted in through RXD_1 and out through RXDO,
while the TXD_1 line is used to provide a shift clock which can be used by external devices to clock data in and
out. In modes 1, 2 and 3, the port behaves as an UART. Data is transmitted on TXD and received on RXD.
Data that is shifted into and out of the UART through RXD and TXD respectively, can be selected from different
sources. This selection is performed by the SCU via SFR-bit MODPISEL.URIOS.
RXD_0
TXD_0
Interrupt
Controller
f BR
UART_IRQ
Baud Rate
Generator
RXD
Clock
Control
f UART1
UART
Module
( Kernel )
Address
Decoder
TXD
RXD_1
SCU
Module
( Kernel )
RXDO
P0 .1 /RXD_1
TXD_ 1
P0.2/TXD_1
Port
Control
P0.0/RXDO
BPI
Figure 131 UART Module I/O Interface
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LIN Transceiver
19
LIN Transceiver
19.1
Features
General Features
•
•
•
•
•
Compliant to LIN 1.3, LIN 2.0 and LIN 2.1
Compatible to SAE J2602 (Slew Rate, Receiver hysteresis)
ESD HBM - 8kV
ESD IEC61000-2-4 - 6kV
DPI higher 34 dBm (100 kHz - 1000 MHz) without external components
Operation Modes Features
•
•
•
•
LIN Sleep Mode (LSLM)
LIN Receive-Only Mode (LROM)
LIN Normal Mode (LNM)
LIN High Voltage Input / Output Mode (LHVIO)
Operation Slope Mode Features
•
•
•
•
Normal Slope Mode
Low Slope Mode
Fast Slope Mode
Flash Mode
Wake-Up Features
•
LIN bus wake-up
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LIN Transceiver
VS
LIN Transceiver
30 k
XSFR
LIN
CTRL
Driver
TxD
GND_LIN
Transmitter
CTRL
STATUS
+ Curr. Limit. +
TSD
LIN-FSM
STATUS
Filter
Filter
RxD
Receiver
LIN_Wake
Sleep Comparator
GND_LIN
Figure 132 LIN Transceiver Block Diagram
19.2
Functional Description
The LIN Module is a transceiver for the Local Interconnect Network (LIN) compliant to the standards LIN1.3,
LIN2.0 and LIN2.1. It operates as a bus driver between the protocol controller and the physical network. The LIN
bus is a single wire, bi-directional bus typically used for in-vehicle networks, using baud rates between 2.4 kBaud
and 20 kBaud. Additionally baud rates up to 40 kBaud are implemented.
The LIN Module offers several different operation modes, including a LIN Sleep Mode and the LIN Normal Mode.
The integrated slope control allows to use several data transmission rates with optimized EMC performance. For
data transfer at the end of line, a Flash Mode up to 115 kBaud is also implemented.
The supported baudrates are:
•
•
•
•
Low Slope Mode for a transmission up to 10.4 kBaud
Normal Slope Mode for a transmission up to 20 kBaud
Fast Slope Mode for a transmission up to 40 kBaud
Flash Mode for a transmission up to 115 kBaud
19.2.1
LIN Normal Mode
The LIN Module is controlled by an internal state machine which determines the actual state of the transceiver.
This state machine is controllable by the XSFR interface.
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LIN Transceiver
LIN MODE CONTROL
LIN Sleep-Mode
(LSLM)
LSLM→LHVIOM
LHVIOM→LSLM
LNM→LSLM
LSLM→ LNM
LIN Normal-Mode
(LNM)
LSLM→LROM
LROM→LSLM
LNM→LROM
LROM→LNM
High Voltage IOMode
(LHVIO)
LIN Recieve-OnlyMode
(LROM)
Figure 133 XSFR controlled LIN Transceiver State machine
LIN Normal Mode (LNM)
In this mode it is possible to receive and transmit data with low slope, normal slope, fast slope or flash mode. Slope
Setting is locked during LIN Normal Mode to avoid destruction of Communication Process. This is blocked by
hardware.
LIN Transmitter Low Power Mode can be enabled in LIN Normal Mode by setting the Bit
LIN_CTRL_STS_2.LIN_LPM_EN. When this mode is selected the transmitter is only enabled if a LIN dominant
signal is sent.
LIN Receive-Only Mode (LROM)
In LIN Receive-Only Mode the transmitter is disabled. The receiver is active. This mode can be directly selected
by application software or is automatically set upon error detection.
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LIN Transceiver
LIN Sleep Mode (LSLM)
In this mode, the transmit and receive functions are disabled, the wake receiver is active. Minimum current
consumption is achieved. Wake up via LIN is possible. To disable the wake capability via LIN, Bit
LIN_CTRL_STS_3.LIN_WAKE_EN has to be set to 0.
LIN High Voltage Input / Output (LHVIO)
This mode is dedicated for using the LIN Transceiver as high voltage input / output. In LHVIO Mode the transceiver
can be controlled by the 2 XSFR bits LIN_HV_MODE in LIN_CTRL_STS_3 register and LIN_TXD in
LIN_CTRL_STS_2 register.
The transitions between the described states can only be executed when corresponding conditions are fulfilled.
The detailed description of the transitions can be found below.
LIN Sleep Mode (LSLM) - LIN Receive-Only Mode (LROM) Transition Description
•
•
LSLM - LROM transition is executed when:
– LIN_MODE is configured to LIN Receive-Only Mode and
– Feedback Signals of Mode and Slope Mode are ok and
– HV-Mode bit is not set
LROM - LSLM transition is executed when:
– LIN_MODE is configured to LIN Sleep Mode
LIN Sleep Mode (LSLM) - LIN Normal Mode (LNM) Transition Description
•
•
LSLM - LNM transition is executed when:
– LIN_MODE is configured to LIN Normal Mode and
– Feedback Signals of Mode and Slope Mode are ok and
– HV-Mode bit is not set and
– VS-Undervoltage Flag is not set
– LIN Transceiver LIN_OT_STS and LIN_OC_STS are not set and
– no TXD_TMOUT is set and
LNM - LSLM transition is executed when:
– LIN_MODE is configured LIN Sleep Mode
LIN Normal Mode (LNM) - LIN Receive-Only Mode (LROM) Transition Description
•
•
LNM - LROM transition is executed when
– LIN_MODE is configured to LIN Receive-Only Mode or
– Feedback Signals of Mode and Slope Mode are not ok or
– VS-Undervoltage Flag is set or
– LIN Transceiver LIN_OT_STS or LIN_OC_STS are set or
– TXD_TMOUT is set
LROM - LNM transition is executed when:
– LIN_MODE is configured to LIN Normal Mode and
– Feedback Signals of Mode and Slope Mode are ok and
– VS-Undervoltage Flag is not set and
– LIN Transceiver LIN_OT_STS and LIN_OC_STS are not set and
– no TXD_TMOUT is set
LIN Sleep Mode (LSLM) - LIN High Voltage Input / Output Mode (LHVIO) Transition Description
•
LSLM - LHVIO transition is executed when
– LIN_HV_MODE flag is set and
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•
– LIN_MODE is configured to LIN Normal Mode after LIN_HV_MODE flag was set and
– Feedback Signals of Mode and Slope Mode are ok and
– LIN Transceiver LIN_OT_STS and LIN_OC_STS are not set
LHVIO - LSLM transition is executed when:
– LIN_MODE is configured to LIN Sleep Mode and
– LIN_HV_MODE flag is set or
– Feedback Signals of Mode and Slope Mode are not ok or
– LIN Transceiver LIN_OT_STS or LIN_OC_STS are set
LIN Specifications 1.3 and 2.0, 2.1
The LIN specification 2.0 is a superset of the 1.3 version offering some additional features. However, it is possible
to use the LIN 1.3 slave node in a 2.0 node cluster, as long as the new features are not used. Vice versa it is
possible to use a LIN 2.0 node in the 1.3 cluster without using the new features.
The latest version of the LIN specification 2.1 has no changes regarding the physical layer specification of LIN 2.0.
19.2.2
LIN Transceiver Error Handling
The LIN Module provides error handling for three different cases:
LIN Transceiver TxD Timout
If the internal UART TxD signal is dominant for the time t > ttimeout, the TxD timeout function deactivates the LIN
transmitter output stage temporarily, by entering the LIN Receive-Only Mode. The transceiver remains in recesive
state. The TxD timeout function prevents the LIN bus from being blocked by a permanent low signal on the TxD
pin, caused by a failure. The failure is stored in the TXD_TMOUT flag. The transmitter stage is activated again
after the dominant timeout condition is removed and after the TXD_TMOUT flag is cleared by software.
LIN Receiver Overcurrent
If the LIN transmitter detcts an overcurrent condition I > IBUS,sc, the LIN transceiver stays in LIN Normal Mode and
the overcurrent status will be stored in the LIN_OC_STS flag. The ahort circuit current is limited to IBUS,sc. The
LIN_OC_STS flag can be cleared by software and will be set again as long as the above condition remains.
To generate an interrupt in case of LIN overcurrent detection, the corresponding interrupt can be enabled by
setting the LIN_OC_IE in the SYS_IRQ_CTRL_1 register. This interrupt is routed to XINTR9.
LIN Receiver Overtemperature
If the LIN transmitter detects an overtemperature condition the transmitter will be deactivated temporarily, by
entering the LIN Receive-Only Mode. The transceiver remains in recesive state. The failure is stored in the
LIN_OT_STS flag. The transmitter stage is activated again after the overtemperature condition is gone and after
the LIN_OT_STS flag is cleared by software.
To generate an interrupt in case of LIN overtemperature detection, the corresponding interrupt can be enabled by
setting the LIN_OT_IE in the SYS_IRQ_CTRL_1 register. This interrupt is routed to XINTR9.
19.2.3
Slope Modes
The LIN Module provides some additional slope mode features which can be used for EoL (End of Line)
programming or to reduce emission in case of usage of lower baudrates. The configurable slope modes are:
Normal Slope Mode
This mode is usually used to transmit and receive messages on the bus. The selected slew rate setting allows a
transmission rate of up to 20 kBaud.
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LIN Transceiver
Low Slope Mode
The usage of this mode is linked to a communication with lower baudrate. With this setting the emission of the
transmitter can be reduced. The selected slew rate setting allows a transmission rate of up to 10.4 kBaud.
Fast Slope Mode
In this mode it is also possible to transmit and receive messages on the bus. The selected slew rate setting allows
a transmission rate of up to 40 kBaud.
Flash Mode
In this mode it is possible to transmit and receive messages on the bus. Transmission rates of up to 115 kBaud
are allowed due the internal slew rate control. This mode can be used for EoL programming.
Change of Slope modes
It is not possible to change the slope modes if the module is operating in LIN Normal Mode to avoid transmission
errors. To change the slope mode for example from Normal Slope Mode to Flash Mode, it is necessary to change
to LIN Receive-Only Mode or LIN Sleep Mode, configure the desired slope mode and to go back to LIN Normal
Mode.
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LIN Transceiver
19.2.4
LIN Transceiver Status for Mode Selection
The LIN transceiver provides the possibility to monitor the on chip status through internally generated feedback
signals. This provides additional protection functionality for the application to avoid wrong configuration of the
transceiver, which may lead to a blocking of communication on the LIN Bus. The table below shows the decoding
of feedback signals to check the current status of the transceiver.
Table 79
Decoding of Feedback Signals for LIN Transmitter Mode Settings
LIN_MODE_F LIN_MODE_F
B_<2>
B<1>
LIN_MODE_F Remarks
B<0>
0
0
0
Mode Error
0
0
1
LIN Sleep Mode
0
1
0
Mode Error
0
1
1
Mode Error
1
0
0
Mode Error
1
0
1
LIN Receive-Only Mode
1
1
0
Mode Error
1
1
1
LIN Normal Mode
A Mode Error indicates a problem in the LIN configuration. If that applies, check the LIN software configuration,
and whenever this does not improve the feedbackmode it is recommended to enter Sleep Mode.
19.2.5
LIN Transceiver Slope Mode Status
The LIN transceiver provides the possibility to monitor the on chip statusof the slope control through internally
generated feedback signals. The table shows the decoding of the feedback signals.
Table 80
Slope Mode Status
LIN_FB_SM3
LIN_FB_SM2
LIN_FB_SM1
Remarks
0
0
0
LIN module not enabled
0
0
1
Low Slope Mode
0
1
0
Normal Slope Mode
0
1
1
Fast Slope mode
1
0
0
Flash Mode
1
0
1
Slope Mode Error
1
1
0
Slope Mode Error
1
1
1
Slope Mode Error
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LIN Transceiver
19.3
Register Definition
Table 81
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
LIN_CTRL_STS_1
LIN Transceiver Control and Status 1
12H
x000 0111B
LIN_CTRL_STS_2
LIN Control and Status 2
13H
xxx0 0x10B
LIN_CTRL_STS_3
LIN Control and Status 3
14H
1001 1xxxB
Register Definition,
The registers are addressed bytewise.
The LIN-Transceiver and the controlling finite state machine can be controlled by the following XSFR Registers.
LIN Transceiver Control and Status 1 Register
The register is reset by RESET_TYPE_3.
LIN_CTRL_STS_1
Offset
Reset Value
12H
x000 0111B
LIN Transceiver Control and Status 1
Register
7
6
5
4
3
2
1
Res
TXD_TMO
UT
LIN_OC_
STS
LIN_OT_
STS
LIN_M_S
M_ERR
LIN_MODE
Res
r
rwh
rwh
rwh
rwh
rw
r
Field
Bits
Type
Description
Res
7
r
Reserved
Always read as 1
TXD_TMOUT
6
rwh
LIN TXD time-out status
0B
NO_TIMEOUT no time-out occured
TIMEOUT time-out occured
1B
LIN_OC_STS
5
rwh
LIN Receiver Overcurrent Status
0B
no Overcurrent no overcurrent status occured
Overcurrent overcurrent status occured
1B
LIN_OT_STS
4
rwh
LIN Receiver Overtemperature Status
0B
no Overtemperature no overtemperature occured
Overtemperature overtemperature occured
1B
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LIN Transceiver
Field
Bits
Type
Description
LIN_M_SM_E
RR
3
rwh
LIN Transceiver Mode or Slope Mode Error
0B
no Mode or Slope Mode Error Status (see corresponding
Feedback registers)
Mode or Slope Mode Error Status (see corresponding Feedback
1B
registers)
LIN_MODE
2:1
rw
LIN transceiver power mode control
00B LIN Sleep Mode LIN module switched to LIN Sleep Mode
01B LIN Receive-Only Mode LIN module switched to LIN Receive Only
Mode
10B n.u. not used
11B LIN Normal Mode LIN module switched to LIN Normal Mode
Res
0
r
Reserved
Always read as 1
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LIN Transceiver
LIN Transceiver Control and Status 2 Register
The register is reset by RESET_TYPE_3.
LIN_CTRL_STS_2
LIN Transceiver Control and Status 2
Register
Offset
Reset Value
13H
xxx0 0x10B
7
6
5
LIN_FB_
SM3
LIN_FB_
SM2
LIN_FB_
SM1
r
r
r
Field
Bits
Type
Description
LIN_FB_SM3
7
r
Feedback Signal 3 for Slope Mode Setting
Coding see Table 80
LIN_FB_SM2
6
r
Feedback Signal 2 for Slope Mode Setting
Coding see Table 80
LIN_FB_SM1
5
r
Feedback Signal 1 for Slope Mode Setting
Coding see Table 80
LIN_SM
4:3
rw
LIN Transmitter Slope mode control
00B Normal Slope Mode for max. 20kBaud
01B Fast Slope Mode for max. 40 kBaud
10B Low Slope Mode for max. 10.4 kBaud
11B Flash Mode for max. 150kBaud
LIN_RXD
2
r
Output Signal of Receiver
Can be used to monitor the Receiver Output
LIN_TXD
1
rw
LIN Transmitter switch on (only used when LIN_HV_MODE is set)
0B
Pull Down LIN Line Transmitter is switched on
Pull Up Resistor is active Transmitter is switched off
1B
LIN_LPM_EN
0
rw
LIN Transmitter Low Power Mode Enable
0B
Low Power Mode disabled Transmitter is always on
Low Power Mode enabled Transmitter is automatically switched
1B
off (no pending transmit request)
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4
3
2
1
0
LIN_SM
LIN_RXD
LIN_TXD
LIN_LPM
_EN
rw
r
rw
rw
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LIN Transceiver
LIN Transceiver Control and Status 3 Register
The register is reset by RESET_TYPE_3.
LIN_CTRL_STS_3
Offset
Reset Value
14H
1001 1xxxB
LIN Transceiver Control and Status 3
Register
7
6
5
4
3
2
0
LIN_WAK
E_EN
Res
LIN_HV_
MODE
LIN_TXD
_TOEN
Res
LIN_MODE_FB
rw
r
rw
rwp
r
r
Field
Bits
Type
Description
LIN_WAKE_EN
7
rw
Wake enable
0B
DISABLE disable wake-up via LIN
ENABLE enable wake-up via LIN
1B
Res
6
r
Reserved
Always read as 0
LIN_HV_MODE
5
rw
LIN Transceiver High Voltage Input - Output Mode
0B
DISABLE LIN High Voltage Input / Output Mode Entry is
disabled
ENABLE LIN High Voltage Input / Output Mode Entry is enabled
1B
LIN_TXD_TOEN
4
rwp
Timeout enable
0B
DISABLE disable timeout
ENABLE enable timeout
1B
Res
3
r
Reserved
Always read as 1
LIN_MODE_FB
2:0
r
Feedback Signals for LIN Transmitter Mode Settings
Coding see Table 79
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High-Speed Synchronous Serial Interface
20
High-Speed Synchronous Serial Interface
This chapter describes the SSC module of the TLE983x. It contains the following sections:
•
•
•
Functional description of the SSC kernel
(see Section 20.1, Section 20.2 and Section 20.3)
SSC kernel register descriptions (see Section 20.4)
TLE983x implementation specific details and registers of the SSC module (see Section 20.5)
20.1
Introduction
The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and half-duplex serial synchronous
communication up to 20 MBaud (@ 40 MHz module clock). The serial clock signal can be generated by the SSC
itself (Master Mode) or can be received from an external master (Slave Mode). Data width, shift direction, clock
polarity, and phase are programmable. This allows communication with SPI-compatible devices. Transmission
and reception of data is double-buffered. A 16-bit baud-rate generator provides the SSC with a separate serial
clock signal.
Features
•
•
•
•
Master and Slave Mode operation
– Full-duplex or half-duplex operation
Flexible data format
– Programmable number of data bits: 2 to 8 bits
– Programmable shift direction: Least Significant Bit (LSB) or Most Significant Bit (MSB) shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift clock
Baud rate generation from 20 MBaud to 305.18 Baud (@ 40 MHz module clock)
Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Figure 134 shows all functional relevant interfaces associated with the SSC Kernel.
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High-Speed Synchronous Serial Interface
f hw _clk
Address
Decoder
EIR
MRSTA
MRSTB
MTSR
MTSRA
MTSRB
MRST
RIR
Master Slave
Interrupt
Control
SSC
Module
( Kernel )
Master
f cfg_ clk
Slave
Cloc
k
Control
TIR
BPI
Interface
Module
Port
Control
SCLKA
SCLKB
SCLK
Product
Interface
Figure 134 SSC Interface Diagram
20.2
General Operation
The SSC supports full-duplex and half-duplex synchronous communication up to 20 MBaud (@ 40 MHz module
clock). The serial clock signal can be generated by the SSC itself (Master Mode) or can be received from an
external master (Slave Mode). Data width, shift direction, clock polarity, and phase are programmable. This allows
communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit
baud-rate generator provides the SSC with a separate serial clock signal.
The SSC can be configured in a very flexible way, so it can be used with other synchronous serial interfaces, can
serve for master/slave or multimaster interconnections or can operate compatible with the popular SPI interface.
Thus, the SSC can be used to communicate with shift registers (I/O expansion), peripherals (e.g. EEPROMs, etc.)
or other controllers (networking). The SSC supports half-duplex and full-duplex communication. Data is
transmitted or received on lines TXD and RXD, normally connected with pins MTSR (Master Transmit/Slave
Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line MS_CLK (Master Serial
Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to pin SCLK.
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PCLK
Baud-rate
Generator
SS_CLK
Clock
Control
MS_CLK
Shift
Clock
RIR
SSC Control Block
Register CON
Status
Receive Int. Request
TIR
Transmit Int. Request
EIR
Error Int. Request
Control
TXD(Master)
Pin
Control
16-Bit Shift
Register
RXD(Slave)
TXD(Slave)
RXD(Master)
Transmit Buffer
Register TB
Receive Buffer
Register RB
Internal Bus
Figure 135 Synchronous Serial Channel SSC Block Diagram
20.2.1
Operating Mode Selection
The operating mode of the serial channel SSC is controlled by its control register CON. This register serves two
purposes:
•
•
During programming (SSC disabled by CON.EN = 0), it provides access to a set of control bits
During operation (SSC enabled by CON.EN = 1), it provides access to a set of status flags.
The shift register of the SSC is connected to both the transmit lines and the receive lines via the pin control logic
(see block diagram in Figure 135). Transmission and reception of serial data are synchronized and take place at
the same time, i.e. the same number of transmitted bits is also received. Transmit data is written into the Transmit
Buffer (TB) and is moved to the shift register as soon as this is empty. An SSC master (CON.MS = 1) immediately
begins transmitting, while an SSC slave (CON.MS = 0) will wait for an active shift clock. When the transfer starts,
the busy flag CON.BSY is set and the Transmit Interrupt Request line TIR will be activated to indicate that register
TB may be reloaded again. When the programmed number of bits (2 … 8) has been transferred, the content of
the shift register is moved to the Receive Buffer RB and the Receive Interrupt Request line RIR will be activated.
If no further transfer is pending (TB is empty), CON.BSY will be cleared at the same time. Software should not
modify CON.BSY, as this flag is hardware controlled.
Note: The SSC starts transmission and sets CON.BSY minimum two clock cycles after transmit data is written into
TB. Therefore, it is not recommended to poll CON.BSY to indicate the start and end of a single transmission.
Instead, interrupt service routine should be used if interrupts are enabled, or the interrupt flags IRCON1.TIR
and IRCON1.RIR should be polled if interrupts are disabled.
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Note: Only one SSC can be master at a given time.
The transfer of serial data bits can be programmed in many aspects:
•
•
•
•
•
•
The data width can be specified from 2 bits to 8 bits
A transfer may start with either the LSB or the MSB
The shift clock may be idle low or idle high
The data bits may be shifted with the leading edge or the trailing edge of the shift clock signal
The baud rate may be set from 305.18 Baud up to 20 MBaud (@ 40 MHz module clock)
The shift clock can be generated (MS_CLK) or can be received (SS_CLK)
These features allow the adaptation of the SSC to a wide range of applications requiring serial data transfer.
The Data Width Selection supports the transfer of frames of any data length, from 2-bit “characters” up to 8-bit
“characters”. Starting with the LSB (CON.HB = 0) allows communication with SSC devices in Synchronous Mode
or with 8051 like serial interfaces for example. Starting with the MSB (CON.HB = 1) allows operation compatible
with the SPI interface.
Regardless of the data width selected and whether the MSB or the LSB is transmitted first, the transfer data is
always right-aligned in registers TB and RB, with the LSB of the transfer data in bit 0 of these registers. The data
bits are rearranged for transfer by the internal shift register logic. The unselected bits of TB are ignored; the
unselected bits of RB will not be valid and should be ignored by the receiver service routine.
The Clock Control allows the adaptation of transmit and receive behavior of the SSC to a variety of serial
interfaces. A specific shift clock edge (rising or falling) is used to shift out transmit data, while the other shift clock
edge is used to latch in receive data. The bit CON.PH selects the leading edge or the trailing edge for each
function. The bit CON.PO selects the level of the shift clock line in the idle state. Thus, for an idle-high clock, the
leading edge is a falling one, a 1-to-0 transition (see Figure 136).
CON.
PO
CON.
PH
0
0
0
1
1
0
1
1
Shift Clock
MS_CLK/SS_CLK
Pins
MTSR/MRST
Transmit Data
First
Bit
Last
Bit
Latch Data
Shift Data
Figure 136 Serial Clock Phase and Polarity Options
20.2.2
Full-Duplex Operation
The various devices are connected through three lines. The definition of these lines is always determined by the
master: the line connected to the master’s data output line TXD is the transmit line; the receive line is connected
to its data input line RXD; the shift clock line is either MS_CLK or SS_CLK. Only the device selected for master
operation generates and outputs the shift clock on line MS_CLK. Since all slaves receive this clock, their pin SCLK
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must be switched to input mode. The output of the master’s shift register is connected to the external transmit line,
which in turn is connected to the slaves’ shift register input. The output of the slaves’ shift register is connected to
the external receive line in order to enable the master to receive the data shifted out of the slave. The external
connections are hard-wired, the function and direction of these pins is determined by the master or slave operation
of the individual device.
Note: The shift direction shown in the figure applies for MSB-first operation as well as for LSB-first operation.
When initializing the devices in this configuration, one device must be selected for master operation while all other
devices must be programmed for slave operation. Initialization includes the operating mode of the device’s SSC
and also the function of the respective port lines.
Master
Device #1
Device #2
Shift Register
Clock
Slave
Shift Register
MTSR
Transmit
MTSR
MRST
Receive
MRST
CLK
Clock
CLK
Clock
Device #3
Slave
Shift Register
MTSR
MRST
CLK
Clock
Figure 137 SSC Full-Duplex Configuration
The data output pins MRST of all slave devices are connected together onto the one receive line in the
configuration shown in Figure 137. During a transfer, each slave shifts out data from its shift register. There are
two ways to avoid collisions on the receive line due to different slave data:
•
•
Only one slave drives the line, i.e. enables the driver of its MRST pin. All the other slaves must have their MRST
pins programmed as input so only one slave can put its data onto the master's receive line. Only receiving data
from the master is possible. The master selects the slave device from which it expects data either by separate
select lines, or by sending a special command to this slave. The selected slave then switches its MRST line to
output until it gets a de-selection signal or command.
The slaves use open drain output on MRST. This forms a wired-AND connection. The receive line needs an
external pull-up in this case. Corruption of the data on the receive line sent by the selected slave is avoided
when all slaves not selected for transmission to the master only send ones (‘1’). Because this high level is not
actively driven onto the line, but only held through the pull-up device, the selected slave can pull this line
actively to a low-level when transmitting a zero bit. The master selects the slave device from which it expects
data either by separate select lines or by sending a special command to this slave.
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After performing the necessary initialization of the SSC, the serial interfaces can be enabled. For a master device,
the alternate clock line will now go to its programmed polarity. The alternate data line will go to either 0 or 1 until
the first transfer starts. After a transfer, the alternate data line will always remain at the logic level of the last
transmitted data bit.
When the serial interface is enabled, the master device can initiate the first data transfer by writing the transmit
data into register TB. This value is copied into the shift register if the shift register is empty. The first bit of the
transmit data (selected by CONL.HB) will be placed onto the TXD line with the next clock egde from the baud-rate
generator. The transmission starts if CON.EN is set to ‘1’. Depending on the selected clock phase, a clock pulse
will also be generated on the MS_CLK line. Simultaneously, with the opposite clock edge, the master latches and
shifts in the data detected at its input line RXD. This “exchanges” the transmit data with the receive data. Because
the clock line is connected to all slaves, their shift registers will be shifted synchronously with the master’s shift
register — shifting out the data contained in the registers, and shifting in the data detected at the input line. After
the preprogrammed number of clock pulses (via the data width selection), the data transmitted by the master is
contained in all the slaves’ shift registers, while the master’s shift register holds the data of the selected slave. In
the master and all slaves, the contents of the shift register are copied into the receive buffer RB and the receive
interrupt line RIR is activated.
A slave device will immediately output the selected first bit (MSB or LSB of the transfer data) at line RXD when the
contents of the transmit buffer are copied into the slave's shift register. Bit CON.BSY is not set until the first clock
edge at SS_CLK appears. The slave device will not wait for the next clock from the baud-rate generator, as the
master does. The reason for this is that, depending on the selected clock phase, the first clock edge generated by
the master may already be used to clock in the first data bit. Thus, the slave’s first data bit must already be valid
at this time.
Note: On the SSC, a transmission and a reception takes place at the same time, regardless of whether valid data
has been transmitted or received.
Note: The initialization of the CLK pin on the master requires some attention in order to avoid undesired clock
transitions, which may disturb the other devices. Before the clock pin is switched to output via the related
direction control register, the clock output level will be selected in the control register CON and the alternate
output be prepared via the related ALTSEL register, or the output latch must be loaded with the clock idle
level.
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20.2.3
Half-Duplex Operation
In a Half-Duplex Mode, only one data line is necessary for both receiving and transmitting of data. The data
exchange line is connected to both the MTSR and MRST pins of each device, the shift clock line is connected to
the SCLK pin.
The master device controls the data transfer by generating the shift clock, while the slave devices receive it. Due
to the fact that all transmit and receive pins are connected to the one data exchange line, serial data may be moved
between arbitrary stations.
Similar to Full-Duplex Mode, there are two ways to avoid collisions on the data exchange line:
•
•
Only the transmitting device may enable its transmit pin driver
The non-transmitting devices use open drain output and send only ones.
Because the data inputs and outputs are connected together, a transmitting device will clock in its own data at the
input pin (MRST for a master device, MTSR for a slave). By this method, any corruptions on the common data
exchange line are detected if the received data is not equal to the transmitted data.
Master
Device #1
Shift Register
Clock
Transmit
Device #2
Shift Register
MTSR
MTSR
MRST
MRST
CLK
Clock
Slave
CLK
Common
Transmit/
Receive Device #3
Line
Clock
Slave
Shift Register
MTSR
MRST
CLK
Clock
Figure 138 SSC Half-Duplex Configuration
20.2.4
Continuous Transfers
When the transmit interrupt request flag is set, it indicates that the transmit buffer TB is empty and ready to be
loaded with the next transmit data. If TB has been reloaded by the time the current transmission is finished, the
data is immediately transferred to the shift register and the next transmission will start without any additional delay.
On the data line, there is no gap between the two successive frames. For example, two byte transfers would look
the same as one word transfer. This feature can be used to interface with devices that can operate with or require
more than 8 data bits per transfer. It is just a matter of software, how long a total data frame length can be. This
option can also be used to interface to byte-wide and word-wide devices on the same serial bus, for instance.
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Note: Of course, this can happen only in multiples of the selected basic data width, because it would require
disabling/enabling of the SSC to reprogram the basic data width on-the-fly.
20.2.4.1
Port Control
The SSC uses three lines to communicate with the external world. Pin SCLK serves as the clock line, while pins
MRST (Master Receive/Slave Transmit) and MTSR (Master Transmit/Slave Receive) serve as the serial data
input/output lines. As shown in Figure 134 these three lines (SCLK as input, Master Receive, Slave Receive) have
all two inputs at the SSC Module kernel. Three bits in register PISEL define which of the two kernel inputs (A or
B) are connected. This feature allows for each of the three SSC communication lines to be connected to two inputs
coming from different port pins.
Operation of the SSC I/O lines depends on the selected operating mode (master or slave). The direction of the
port lines depends on the operating mode. The SSC will automatically use the correct kernel output or kernel input
line of the ports when switching modes. Port pins assigned as SSC I/O lines can be controlled in two ways:
•
•
By hardware
By software
When the SSC I/O lines are connected with dedicated pins typically hardware I/O control should be used. In this
case, the two output signals reflect directly the state of the CON.EN and CON.MS bits (the M/S select line is
inverted to the CON.MS bit definition).
When the SSC I/O lines are connected with bidirectional lines of general purpose I/O ports, typically software I/O
control should be used. In this case port registers must be programmed for alternate output and input selection.
When switching between master and slave mode, port registers must be reprogrammed.
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20.2.5
Baud Rate Generation
The serial channel SSC has its own dedicated 16-bit baud-rate generator with 16-bit reload capability, allowing
baud rate generation independent of the timers. Figure 135 shows the baud-rate generator. Figure 139 shows
the baud-rate generator of the SSC in more detail.
16-Bit Reload Register
fPCLK
. 2
.
16-Bit Counter
f MS_CLK/SS_CLK
fMS_CLK max in Master Mode< fPCLK /2
fSS_CLK max in Slave Mode < fPCLK /4
Figure 139 SSC Baud-rate Generator
The baud-rate generator is clocked with the module clock fhw_clk. The timer counts downwards. Register BR is the
dual-function Baud-rate Generator/Reload register. Reading BR, while the SSC is enabled, returns the contents
of the timer. Reading BR, while the SSC is disabled, returns the programmed reload value. In this mode, the
desired reload value can be written to BR.
Note: Never write to BR while the SSC is enabled.
The formulas below calculate either the resulting baud rate for a given reload value, or the required reload value
for a given baud rate:
Baud rate =
fhw_clk
BR =
2 * (<BR> + 1)
fhw_clk
2 * Baud rate
(13)
-1
<BR> represents the contents of the reload register, taken as an unsigned 16-bit integer, while baud rate is equal
to fMS_CLK/SS_CLK as shown in Figure 139.
The maximum baud rate that can be achieved when using a module clock of 40 MHz is 20 MBaud in Master Mode
(with <BR> = 0000H) or 10 MBaud in Slave Mode (with <BR> = 0001H).
Table 82 lists some possible baud rates together with the required reload values and the resulting bit times,
assuming a module clock of 40 MHz.
Table 82
Typical Baud Rates of the SSC (fhw_clk = 40 MHz)
Reload Value
Baud Rate (= fMS_CLK/SS_CLK)
Deviation
0000H
20 MBaud (only in Master Mode)
0.0%
0001H
10 MBaud
0.0%
0013H
1 MBaud
0.0%
0027H
500 kBaud
0.0%
00C7H
100 kBaud
0.0%
07CFH
10 kBaud
0.0%
4E1FH
1 kBaud
0.0%
FFFFH
305.18 Baud
0.0%
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20.2.6
Error Detection Mechanisms
The SSC is able to detect four different error conditions. Receive Error and Phase Error are detected in all modes;
Transmit Error and Baud Rate Error apply only to Slave Mode. When an error is detected, the respective error flag
is/can be set and an error interrupt request will be generated by activating the EIR line (see Figure 140) if enabled.
The error interrupt handler may then check the error flags to determine the cause of the error interrupt. The error
flags are not reset automatically but rather must be cleared by software after servicing. This allows servicing of
some error conditions via interrupt, while the others may be polled by software.
Note: The error interrupt handler must clear the associated (enabled) error flag(s) to prevent repeated interrupt
requests.
Bits in Register
CON
TEN
&
Transmit
TE
Error
REN
&
RE
Receive
>1
Error
Error Interrupt
EIR
PEN
Phase
Error
PE
BEN
Baud rate
Error
&
&
BE
Figure 140 SSC Error Interrupt Control
A Receive Error (Master or Slave Mode) is detected when a new data frame is completely received but the
previous data was not read out of the receive buffer register RB. This condition sets the error flag CON.RE and
the error interrupt request line EIR, when enabled via CON.REN. The old data in the receive buffer RB will be
overwritten with the new value and is irretrievably lost.
A Phase Error (Master or Slave Mode) is detected when the incoming data at pin MRST (Master Mode) or MTSR
(Slave Mode), sampled with the same frequency as the module clock, changes between one cycle before and two
cycles after the latching edge of the shift clock signal SCLK. This condition sets the error flag CON.PE and, when
enabled via CON.PEN, the error interrupt request line EIR.
Note: When receiving and transmitting data in parallel, phase errors occur if the baud rate is configured to
fhw_clk / 2.
A Baud Rate Error (Slave Mode) is detected when the incoming clock signal deviates from the programmed baud
rate by more than 100%, i.e. it is either more than double or less than half the expected baud rate. This condition
sets the error flag CON.BE and, when enabled via CON.BEN, the error interrupt request line EIR. Using this error
detection capability requires that the slave’s baud-rate generator is programmed to the same baud rate as the
master device. This feature detects false additional, or missing pulses on the clock line (within a certain frame).
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Note: If this error condition occurs and bit CON.REN = 1, an automatic reset of the SSC will be performed in case
of this error. This is done to re-initialize the SSC if too few or too many clock pulses have been detected.
Note: This error can occur after any transfer if the communication is stopped. This is the case due to the fact that
the SSC module supports back-to-back transfers for multiple transfers. In order to handle this, the baud rate
detector expects after a finished transfer immediately a next clock cycle for a new transfer.
A Transmit Error (Slave Mode) is detected when a transfer was initiated by the master (SS_CLK gets active) but
the transmit buffer TB of the slave was not updated since the last transfer. This condition sets the error flag
CON.TE and the error interrupt request line EIR, when enabled via CON.TEN. If a transfer starts while the transmit
buffer is not updated, the slave will shift out the ‘old’ contents of the shift register, which normally is the data
received during the last transfer. This may lead to corruption of the data on the transmit/receive line in half-duplex
mode (open drain configuration) if this slave is not selected for transmission. This mode requires that slaves not
selected for transmission only shift out ones; that is, their transmit buffers must be loaded with ‘FFFFH’ prior to any
transfer.
Note: A slave with push/pull output drivers not selected for transmission, will normally have its output drivers
switched. However, in order to avoid possible conflicts or misinterpretations, it is recommended to always
load the slave's transmit buffer prior to any transfer.
The cause of an error interrupt request (receive, phase, baud rate, transmit error) can be identified by the error
status flags in control register CON.
Note: In contrast to the error interrupt request line EIR, the error status flags CON.TE, CON.RE, CON.PE, and
CON.BE, are not reset automatically upon entry into the error interrupt service routine, but must be cleared
by software.
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20.3
Interrupts
The three SSC interrupts can be separately enabled or disabled by setting or clearing their corresponding enable
bits in SFR SCU_MODIEN.
For a detailed description of the various interrupts see Section 20.2. An overview is given in Table 83.
Table 83
SSC Interrupt Sources
Interrupt
Signal
Description
Transmission
starts
TIR
Indicates that the transmit buffer can be reloaded with new data.
Transmission
ends
RIR
The configured number of bits have been transmitted and shifted to the
receive buffer.
Receive Error
EIR
This interrupt occurs if a new data frame is completely received and the last
data in the receive buffer was not read.
Phase Error
EIR
This interrupt is generated if the incoming data changes between one cycle
before and two cycles after the latching edge of the shift clock signal SCLK.
Baud Rate Error
(Slave Mode
only)
EIR
This interrupt is generated when the incoming clock signal deviates from the
programmed baud rate by more than 100%.
Transmit Error
(Slave Mode
only)
EIR
This interrupt is generated when TB was not updated since the last transfer if
a transfer is initiated by a master.
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20.4
SSC Kernel Registers
20.4.1
Port Input Select Register
The PISEL register controls the receiver input selection of the SSC module.
PISEL
Port Input Select Register
7
Reset Value: 00H
6
5
4
3
2
1
0
0
CIS
SIS
MIS
r
rw
rw
rw
Field
Bits
Type
Description
MIS
0
rw
Master Mode Receiver Input Select
0B
Receiver input (Port A: P0.5) is selected.
Receiver input (Port B: P1.2) is selected.
1B
SIS
1
rw
Slave Mode Receiver Input Select
0B
Receiver input (Port A: P0.4) is selected.
Receiver input (Port B: P1.1) is selected.
1B
CIS
2
rw
Slave Mode Clock Input Select
0B
Clock input (Port A: P0.3) is selected.
Clock input (Port B: P1.0) is selected.
1B
0
7:3
r
Reserved
Returns 0 if read.
Note: Port A and Port B inputs of the SSC kernel are connected to the external pins of Port 0 and Port 1
respectively.
20.4.2
Configuration Register
The operating mode of the serial channel SSC is controlled by the control register CON. This register contains
control bits for mode and error check selection, and status flags for error identification. Depending on bit EN, either
control functions or status flags and master/slave control are enabled.
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CON.EN = 0: Programming Mode
CONL
Control Register Low
Reset Value: 00H
7
6
5
4
3
LB
PO
PH
HB
BM
rw
rw
rw
rw
rw
Field
Bits
Type
Description
BM
3:0
rw
Data Width Selection
2
1
0
Note: BM[3] is fixed to 0.
0000BReserved. Do not use this combination.
0001B0111BTransfer Data Width is 2 … 8 bits (<BM>+1).
HB
4
rw
Heading Control
0B
Transmit/Receive LSB First.
Transmit/Receive MSB First.
1B
PH
5
rw
Clock Phase Control
0B
Shift transmit data on the leading clock edge, latch on trailing
edge.
1
Latch receive data on leading clock edge, shift on trailing edge.
PO
6
rw
Clock Polarity Control
0B
Idle clock line is low, leading clock edge is low-to-high transition.
Idle clock line is high, leading clock edge is high-to-low transition.
1B
LB
7
rw
Loop Back Control
0B
Normal output.
Receive input is connected with transmit output (half-duplex
1B
mode).
CONH
Control Register High
Reset Value: 00H
7
6
5
4
3
2
1
0
EN
MS
0
AREN
BEN
PEN
REN
TEN
rw
rw
r
rw
rw
rw
rw
rw
Field
Bits
Type
Description
TEN
0
rw
Transmit Error Enable
0B
Ignore transmit errors.
Check transmit errors.
1B
REN
1
rw
Receive Error Enable
0B
Ignore receive errors.
Check receive errors.
1B
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Field
Bits
Type
Description
PEN
2
rw
Phase Error Enable
0B
Ignore phase errors.
Check phase errors.
1B
BEN
3
rw
Baud Rate Error Enable
0B
Ignore baud rate errors.
Check baud rate errors.
1B
AREN
4
rw
Automatic Reset Enable
0B
No additional action upon a baud rate error.
The SSC is automatically reset upon a baud rate error.
1B
MS
6
rw
Master Select
0B
Slave Mode. Operate on shift clock received via SCLK.
Master Mode. Generate shift clock and output it via SCLK.
1B
EN
7
rw
Enable Bit = 0
Transmission and reception disabled. Access to control bits.
0
5
r
Reserved
Returns 0 if read.
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CON.EN = 1: operating mode
CONL
Control Register Low
7
Reset Value: 00H
6
5
4
3
2
1
0
BC
r
rh
Field
Bits
Type
Description
BC
3:0
rh
Bit Count Field
Shift counter is updated with every shift bit.
0
Note: This bit field is not to be written to.
7:4
0
r
Reserved
Returns 0 if read.
CONH
Control Register High
Reset Value: 00H
7
6
5
4
3
2
1
0
EN
MS
0
BSY
BE
PE
RE
TE
rw
rw
r
rh
rwh
rwh
rwh
rwh
Field
Bits
Type
Description
TE
0
rwh
Transmit Error Flag
0B
No error.
Transfer starts with the slave’s transmit buffer not being updated.
1B
RE
1
rwh
Receive Error Flag
0B
No error.
Reception completed before the receive buffer was read.
1B
PE
2
rwh
Phase Error Flag
0B
No error.
Received data changes around sampling clock edge.
1B
BE
3
rwh
Baud Rate Error Flag
0B
No error.
More than factor 2 or 0.5 between slave’s actual and expected
1B
baud rate.
BSY
4
rh
Busy Flag
Set while a transfer is in progress.
Note: This bit is not to be written to.
MS
6
rw
Master Select Bit
0B
Slave Mode. Operate on shift clock received via SCLK.
Master Mode. Generate shift clock and output it via SCLK.
1B
EN
7
rw
Enable Bit = 1
Transmission and reception enabled. Access to status flags and M/S
control.
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Field
Bits
Type
Description
0
5
r
Reserved
Returns 0 if read.
Note: The target of an access to CON (control bits or flags) is determined by the state of CON.EN prior to the
access; that is, writing C057H to CON in programming mode (CON.EN = 0) will initialize the SSC (CON.EN
was 0) and then turn it on (CON.EN = 1). When writing to CON, ensure that reserved locations receive zeros.
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20.4.3
Baud Rate Timer Reload Register
The SSC baud rate timer reload register BR contains the 16-bit reload value for the baud rate timer.
BRL
Baud Rate Timer Reload Register Low
7
6
Reset Value: 00H
5
4
3
2
1
0
BR_VALUE
rw
Field
Bits
Type
Description
BR_VALUE
7:0
rw
Baud Rate Timer/Reload Register Value
Reading BR returns the 16-bit contents of the baud rate timer.
Writing BR loads the baud rate timer reload register with
BR_VALUE.
BRH
Baud Rate Timer Reload Register High
7
6
Reset Value: 00H
5
4
3
2
1
0
BR_VALUE
rw
Field
Bits
Type
Description
BR_VALUE
7:0
rw
Baud Rate Timer/Reload Register Value
Reading BR returns the 16-bit contents of the baud rate timer.
Writing BR loads the baud rate timer reload register with
BR_VALUE.
20.4.4
Transmitter Buffer Register
The SSC transmitter buffer register TB contains the transmit data value.
TBL
Transmitter Buffer Register Low
7
6
Reset Value: 00H
5
4
3
2
1
0
TB_VALUE
rw
Field
Bits
Type
Description
TB_VALUE
7:0
rw
Transmit Data Register Value
TB_VALUE is the data value to be transmitted. Unselected bits of
TB are ignored during transmission.
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20.4.5
Receiver Buffer Register
The SSC receiver buffer register RB contains the receive data value.
RBL
Receiver Buffer Register Low
7
6
Reset Value: 00H
5
4
3
2
1
0
RB_VALUE
rh
Field
Bits
Type
Description
RB_VALUE
7:0
rh
Receive Data Register Value
RB contains the received data value RB_VALUE. Unselected bits
of RB will be not valid and should be ignored.
20.5
TLE983x Module Implementation Details
This section describes:
•
•
The SSC module related interfaces such as port connections and interrupt control
All SSC module related registers with its addresses
Note: The most significant bit of BM field (CONL.3) is always fixed at 0. Thus the transfer and receive data width
is restricted at maximum 8 bits. Transfer Data Width is 2...8 bits (<BM>+1).
20.5.1
Interfaces of the SSC Module
An overview of the SSC kernel I/O interface is shown in Figure 141.
The Bus Peripheral Interface (BPI) enables the SSC kernel to be attached to the 8-bit Bus. The BPI consists of a
clock control logic which gates the clock input to the kernel, and an address decoder for Special Function Registers
(SFRs) in the SSC kernel.
The interrupt requests of the SSC are not connected directly to the CPU’s Interrupt Controller, but via the System
Control Unit (SCU). This is due to the fact that the total number of interrupts from all on-chip peripherals is greater
than the number of interrupt sources supported by the CPU’s Interrupt Controller. Thus the interrupt request
signals of the SSC are mapped to the Interrupt Controller by the SCU.
Note: Please refer to Chapter 20 for the SCU description.
The General Purpose IO (GPIO) Port provides the interface from the SSC to the external world.
Note: Please refer to Chapter 13 for the Ports description.
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RIR
f hw _clk
Address
Decoder
SSC
Module
( Kernel )
Master
TIR
MRSTA
MRSTB
MTSR
Slave
Clock
Control
EIR
MTSRA
MTSRB
MRST
Master Slave
SCU
(Interrupt
Management )
P0.3/SCLK_ 0
P0 .4/MTSR_0
Port
Control
P0 .5/MRST_0
P 1.0 /SCLK _1
SCLKA
SCLKB
P1 .1/MTSR_1
SCLK
P1.2/MRST_1
BPI
Figure 141 SSC Module I/O Interface
20.5.2
Register Mapping
The addresses of the kernel SFRs are listed in Table 84.
Table 84
SFR Address List
Address
Register
A9H
PISEL
AAH
CONL
ABH
CONH
ACH
TBL
ADH
RBL
AEH
BRL
AFH
BRH
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21
Measurement Unit
21.1
Features
The measurement unit is a functional unit that comprises the following associated sub-modules:
Module Features
•
•
•
•
•
•
•
1 x 8-Bit ADC (ADC2) with 10 inputs. 5 are for single ended input signals and 5 are for differential input signals.
Monitoring inputs voltage attenuators with two selectable attenuation settings: divide by 4 and divide by 6
Supply voltage attenuators with attenuation of VBAT_SENSE, VS, VDDP and VDDC.
VBG monitoring of 8-Bit ADC (ADC2) to guarantee functional safety requirements.
Low Side Switch current sensing of LS1 and LS2. Allows a scalable overcurrent prewarning.
Temperature sensor for monitoring the chip temperature and Low Side Switches temperature.
Supplement block with reference voltage generation, bias current generation, voltage buffer for Flash
reference voltage, voltage buffer for analog module reference voltage and test interface.
Table 85
Measurement functions and associated modules
Module
Name
Modules
Functions
Central Functions Bandgap reference circuit
Unit
The bandgap-reference sub-module provides two
reference voltages
1. A trimmable reference voltage for the implemented 8-bit
ADC. A local dedicated bandgap circuit is implemented to
avoid deterioration of the reference voltage arising e.g.
from crosstalk or ground voltage shift.
2. The reference voltage for the NVM module
8 Bit ADC (ADC2) 8-bit ADC module with 10
multiplexed inputs
1. 5 single-ended inputs 0 ... 1.3V
2. 5 differential inputs 0 ... 1.3V
(allocation see following overview figure)
10 Bit ADC
(ADC1)
10-bit ADC module with 8
multiplexed input channels - part of
µC subsystem
1. VBAT_SENSE measurement on channel 0 of ADC1.
2. VS measurement on channel 2 of ADC1.
3. MONx measurement on channel 6 of ADC1.
4. 5 additional (5V) analog inputs from Port 2.
Supply Voltage
Attenuator
Resistive supply voltage attenuator
Scales down the supply voltages of the system to the input
voltage range of ADC1 and ADC2.
Monitoring Input
Attenuator
Resistive attenuator for (HV)
Scales down 5 monitoring input voltages to the input
voltage range of the ADC1.
Central
Temperature Low Side
Temperature
Sensor
Temperature sensor readout
amplifier with two multiplexed ∆Vbe
sensing elements
Generates output voltages which are linear functions of
the local die (junction) temperature.
Measurement
Core Module
Digital signal processing and ADC
control unit
1. Generates the control signals for the 8-bit ADC2 and the
synchronous clock for the switched capacitor circuits,
2. Performs digital signal processing functions and
provides status outputs for the interrupt generation.
The structure of the measurement functions module is shown in Figure 142.
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VAREF
VS
* 0.252
CH0
5V
CH1
P2.1
* 0.252
CH2
UDIG
VREF
CH3
P2.3
MUX
P2.4
CH4
P2.5
CH5
A
D
10
/
SFR
ADC 1
CH6
CH7
P2.7
10 Bit ADC + UDIG
MON1
* 0.25 (0.166 )
MON2
* 0.25 (0.166 )
MON3
* 0.25 (0.166 )
MON4
* 0.25 (0.166 )
MON5
* 0.25 (0.166 )
VBAT_SENSE
M
U
X
Measurement-Unit
* 0.063
CH0
* 0.063
CH1
VDDP
* 0.2
CH2
VDDC
* 0.687
1. 23
V
CH3
VBG
DPP
CH4
MUX
n.u.
A
D
8
/
XSFR
CH5
CH6
Low Side 1
CH7
Low Side 2
TSENSE 1
ADC 2
CH8
TSENSE 2
CH9
Measurement Core
Figure 142 TLE983x Measurement Unit-Overview
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21.2
Measurement Functions Submodules
21.2.1
8-Bit - 10 Channel ADC Core
The 8-Bit ADC core operates at the VDDC supply voltage. This enables the user to operate the measurement
system down to reset threshold. The ADC can also be operated independently form the DPP unit. This enables
the user to build up a software controlled measurement cycle. The main features of the 8-Bit ADC core are listed
below.
Features
•
•
•
•
conversion time = 10 system clock cycles.
channel 0 - 4 dedicated for single ended signal measurement.
channel 5 - 9 dedicated for differential signal measurement.
scalable clock frequency from 10 - 30 MHz.
21.2.1.1
8-Bit ADC Channel Assignment
The assignment of the 10 channels of ADC2 is sketched below:
1.23
V
VBAT_SENSE
CH0
VS
CH1
VDDP
CH2
VDDC
CH3
VBG
CH4
n.u.
CH5
Low Side 1
CH6
Low Side 2
CH7
Central Temp Sensor
CH8
Low Side Temp Sensor
CH9
VREF
VREF
MUX
A
D
Figure 143 8-Bit ADC (ADC2) Channel Allocation
ADC2 Channel Assignment:
•
•
•
•
•
•
•
•
•
•
VBAT_SENSE Pin Voltage Measurement.
VS Pin Voltage Measurement.
VDDP Pin Voltage Measurement.
VDDC Pin Voltage Measurement.
ADC2 Reference Voltage Check.
n.u.
Low Side 1 Current Measurement.
Low Side 2 Current Measurement.
Device Temperature Measurement (Tj).
Low Side Temperature Measurement.
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21.2.1.2
Transfer Characteristics
The transfer function of ADC2 channel 0-4 can be expressed by the equation below:
⎛ V
⎞
ADC 2 out = floor ⎜ in + 1 ⎟
⎜ VLSB
⎟
⎝
⎠
(14)
where Vin is the single ended input voltage.
The transfer function of ADC2 channel 5-9 can be expressed by the equation below:
⎛ Vin
⎞
ADC 2out = floor ⎜
⋅1.247 + 1⎟
⎜ VLSB
⎟
⎝
⎠
(15)
where Vin is the differential input voltage. The LSB Voltage is calculated:
VLSB =
V
ref
256
(16)
where Vref is 1.227 V @ 27 °C:
A detailed specification of both A/D-converters is given in the Data Sheet, Chapter Electrical Characteristics.
21.2.1.3
8-Bit - 10 Channel Control Register
The ADC2 control register is located in the Measurement Core Module Block. The 10-Bit ADC (ADC1) is
described in Chapter 24.
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21.2.2
Monitoring Inputs Voltage Attenuators
The function of the monitoring voltage attenuators is to scale down the incoming voltages to provide them for the
on-board 10-Bit ADC. The voltage attenuators have the following features:
Features
•
•
•
Two selectable attenuation factors: 0.252 for a range between 0 and 18V and 0.166 for a range between 0
and 28V
High impedance OFF-state
Load dump protected
The next chapter lists the user configuration possibilities of the monitoring input voltage attenuators.
Note: It is important to disable the monitoring attenuators before entering Stop Mode. Otherwise false
wake-ups may be generated!
21.2.2.1
Monitoring Attenuators Control Register
Table 86
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
B9H
0x00 1111B
Monitoring Attenuators Control Register,
VMON_SEN_CTRL
VMON Sense Control Register
The registers are addressed bytewise.
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VMON Sense Control Register
The register is reset by RESET_TYPE_3.
VMON_SEN_CTRL
VMON Sense Control Register
7
6
Offset
Reset Value
B9H
0x00 1111B
5
4
3
1
0
Res
VMON_SE
N_SEL_*
VMON_SE
N_HRES*
VMON_SEN_MUX_SEL
VMON_SE
N_PD_N
r
rw
rw
rw
rw
Field
Bits
Type
Description
Res
7:6
r
Reserved
Always read as 0x
VMON_SEN_SEL_INRAN 5
GE
rw
Monitoring Input Attenuator Select Inputrange
0B
0 - 18V Range is selected
0 - 28V Range is selected
1B
VMON_SEN_HRESO_5V
4
rw
Monitoring Input Attenuator High Impedance Output
Control
0B
High Resistive Output Disable Connection to ADC
input low ohmic
High Resistive Output Enable Connection to ADC
1B
input high ohmic
VMON_SEN_MUX_SEL
3:1
rw
MON Sensing Input Selection Bit
001B MON1 selected
010B MON2 selected
011B MON3 selected
100B MON4 selected
101B MON5 selected
VMON_SEN_PD_N
0
rw
Monitoring Input Attenuator enable
0B
DISABLE Attenuator switched off
ENABLE Attenuator switched on
1B
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21.2.3
Supply Voltage Sense Attenuators
The supply voltage attenuator module scales down the input voltages to the input voltage range of the 8-bit ADC
and 10-Bit ADC. The Attenuator comprises the following functions:
Module Features:
•
•
•
•
•
Two high voltage attenuators for sensing the voltage at the external pins VBAT_SENSE and VS respectively.
Zener clamps are used to prevent over-voltage at the output if the input voltage exceeds the measurement
range, e.g. during a load dump condition (40V).
Attenuation factor for VS / VBAT_SENSE for 10-Bit ADC: 0.252 for a range between 0 to 18V
Attenuation factor for VS / VBAT_SENSE for 8-Bit ADC: 0.0625 for a range between 0 to 18V
Attenuation factor for VDDP for 8 Bit ADC: 0.2 for a range between 0 to 6V
Attenuation factor for VDDC for 8 Bit ADC: 0.687 for a range between 0 to 1.8V
The next chapter lists the configuration possibilities of the supply voltage attenuator. The function of the control
register bits is sketched below on the example of the VS-Attenuator:
VS- Attenuator
PD_N[0] = 1 | PD _N[1] = 1
VS
to ADC1
*0, 252
PD_N [0] = 0 & HRESO [0] = 0
to ADC2
*0,0625
PD_N [1] = 0 & HRESO [1] = 0
PD_N[0] = 1 | PD_N[1] = 1
GND_A
Figure 144 Purpose of Supply Votage Attenuator Control Bits
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21.2.3.1
Supply Voltage Sense Attenuators Control Register
Table 87
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Supply Voltage Sense Attenuators Control Register,
VSUPP_SEN_CTRL_1
VSUPPLY Sense Control Register 1
BBH
0011 1111B
VSUPP_SEN_CTRL_2
VSUPPLY Sense Control Register 2
F5H
0000 0000B
The registers are addressed bytewise.
VSUPPLY Sense Control 1 Register
The register is reset by RESET_TYPE_3.
VSUPP_SEN_CTRL_1
VSUPPLY Sense Control 1 Register
7
6
Offset
Reset Value
BBH
0011 1111B
5
0
Res
VSUP_SEN_PD_N
r
rw
Field
Bits
Type
Description
Res
7:6
r
Reserved
Always read as 0
VSUP_SEN_PD_N
5:0
rw
Supply Sensing Resistors Enable Bit1)
000000B all disabled
000001B VBAT_SENSE ADC1 and ADC2 enabled
000010B VBAT_SENSE ADC1 and ADC2 enabled
000100B VS ADC1 and ADC2 enabled
001000B VS ADC1 and ADC2 enabled
010000B VDDP enabled
100000B VDDC enabled
111111B all enabled
1) It is also allowed to have combinations of several supply sensing resistors enabled, e.g. for VBAT_SENSE and VS =
000101B. The fact that each bit can be controlled twice results from the way of implementation. Each of the corresponding
2 subsequent Bits have exactly the same meaning.
VSUPPLY Sense Control 2 Register
The register is reset by RESET_TYPE_3.
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VSUPP_SEN_CTRL_2
VSUPPLY Sense Control 2 Register
7
6
Offset
Reset Value
F5H
0000 0000B
5
0
Res
VSUP_SEN_HRESO
r
rw
Field
Bits
Type
Description
Res
7:6
r
Reserved
Always read as 0
VSUP_SEN_HRESO
5:0
rw
Supply Sensing High Resistive Output Control
000001B VBAT_SENSE ADC1 output tied to ground
000010B VBAT_SENSE ADC2 output tied to ground
000100B VS ADC1 output tied to ground
001000B VS ADC2 output tied to ground
010000B VDDP output tied to ground
100000B VDDC output tied to ground
111111B all enabled
21.2.4
Central and Low Side Temperature Sensor
This module is a combination of a main on-chip temperature sensor and a Low Side Switch temperature sensor.
Modules Features
•
•
•
•
Temperature range -40 …175°C
2 operation modes with
Mode 1 - temperature range corresponds to differential output voltage range 0 …1.2V (output voltage shift
enabled).
Mode 2 - temperature range corresponds to differential output voltage range 0.6 …1.2V.
The combined system temperature sensor plus ADC are calibrated in software using calibration figures that
are stored in the NVM during the production test.
A dedicated calibration transistor facilitates on-chip reference temperature measurement. Hardware trimming
is not implemented.
This temperature sensor, including two sensing elements, monitors the chip temperature and Low Side switch
temperature. One sensing element is placed in the center of the device to get the average device temperature
status and the other sensing element is placed between the two Low Side switch power stages.
The voltage calculation of the temperature is done with the following formula:
⎛ Vtemp
⎞
ADC2out = floor⎜
⋅ 1.247 + 1⎟
⎜ VLSB
⎟
⎝
⎠
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The LSB Voltage is calculated:
VLSB =
V
ref
256
(18)
Vtemp is the direct proportional to temperature input voltage and is calculated by:
VTEMP(T ) = a + b ⋅ (T − T0 )
(19)
where the coefficient a is 487 mV, b is 1.7 mV/K and T0 is 273 K:
The next chapter lists the registers to configure both temperature sensors.
21.2.4.1
Temperature Sensor Control Register
The Temperature Sensor is fully controllable by the XSFR Register listed below.
Table 88
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
B7H
0000 0101B
Temperature Sensor Control Register,
TEMPSENSE_CTRL
Temperature Sensor Control Register
The registers are addressed bytewise.
Temperature Sensor Control Register
The register is reset by RESET_TYPE_3.
TEMPSENSE_CTRL
Temperature Sensor Control Register
Offset
Reset Value
B7H
0000 0101B
7
2
1
0
Res
TS_MODE
Res
r
rwp
r
Field
Bits
Type
Description
Res
7:2
r
Reserved
Always read as 00001
TS_MODE
1
rwp
Main Temperature Sensor Mode Flag
0B
DISABLED decreased accuracy selected
ACTIVE increased accuracy selected
1B
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Measurement Unit
Field
Bits
Type
Description
Res
0
r
Reserved
Always read as 0
21.2.5
Supplement Modules
The purpose of the supplement modules is to enable an infrastructure, like reference voltages or reference
currents on the device, to guarantee a fail safe operation:
Module Features
•
•
•
•
Bandgap Reference Voltage with accuracy ± 1.5%.
Bandgap is monitored by an independent reference voltage.
ADC1 Reference with accuracy ± 1%.
ADC1 Reference has overload detection.
The following chapter lists the configuration possibilities of the on chip references.
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21.2.5.1
Supplement Modules Status Register
The following chapter lists the diagnosis and configuration possibilities of the supplement modules.
Table 89
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Supplement Modules Status Register,
REF1_STS
Reference 1 Status Register
B8H
1100 1x01B
REF2_CTRL
Reference 2 Control Register
BAH
0001 00x1B
PERIPHERAL_TEST
Peripheral Test Register
F7H
0000 0001B
The registers are addressed bytewise.
Reference 1 Status Register
The register is reset by RESET_TYPE_3.
REF1_STS
Reference 1 Status Register
7
6
Offset
Reset Value
B8H
1100 1x01B
5
4
3
0
Res
REFBG_U
PTHWAR*
REFBG_L
OTHWAR*
Res
r
rwh
rwh
r
Field
Bits
Type
Description
Res
7:6
r
Reserved
Always read as 11
REFBG_UPTHWARN_ST
S
5
rwh
Status for Overvoltage Threshold Measurement of
internal VAREF
0B
UPPER_TRIG_RESET write clears status
UPPER_TRIG_SET trigger status set
1B
REFBG_LOTHWARN_ST
S
4
rwh
Status for Undervoltage Threshold Measurement of
internal VAREF
0B
UPPER_TRIG_RESET write clears status
UPPER_TRIG_SET trigger status set
1B
Res
3:0
r
Reserved
Always read as 1x01
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Measurement Unit
Reference 2 Control Register
The register is reset by RESET_TYPE_3.
REF2_CTRL
Reference 2 Control Register
Offset
Reset Value
BAH
0001 00x1B
7
2
1
0
Res
VREF5V_
OVL_STS
VREF5V_
PD_N
r
rwh
rw
Field
Bits
Type
Description
Res
7:2
r
Reserved
Always read as 0
VREF5V_OVL_STS
1
rwh
ADC2 Bit Reference Voltage Generation Over Load Bit
0B
no OVERLOAD no OVERLOAD detected
OVERLOAD OVERLOAD detected
1B
VREF5V_PD_N
0
rw
ADC2 Bit Reference Voltage Generation Power Down Bit
0B
DISABLED Power Down
ACTIVE no Power Down
1B
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Peripheral Test Register
The register is reset by RESET_TYPE_3.
PERIPHERAL_TEST
Peripheral Test Register
7
6
Offset
Reset Value
F7H
0000 0001B
4
VAREF_M
EAS_EN
Res
rw
r
3
2
Res
1
0
ATBI_DI
FF_PD_N
Res
rw
r
Field
Bits
Type
Description
VAREF_MEAS_EN
7
rw
VAREF Measurement Enable
0B
DISABLED Power Down
ACTIVE no Power Down
1B
Res
6:2
r
Reserved
Always read as 0
ATBI_DIFF_PD_N
1
rw
Differential Analog Testbus Interface Power Down Bit
0B
DISABLED Power Down
ACTIVE no Power Down
1B
Res
0
r
Reserved
Always read as 0
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Measurement Core Module - ADC2
22
Measurement Core Module - ADC2
The basic function of this block is the digital postprocessing of several analog digitized measurement signals by
means of filtering, level comparison and interrupt generation. The measurement postprocessing block is built of
ten identical channel units attached to the outputs of the 10-channel 8-bit ADC (ADC2). It processes ten channels,
where the channel sequence and priorization is programmable within a wide range.
Features
•
•
•
•
•
•
8-Bit SAR ADC with a measurement capability within complete functional range
10 individually programmable channels split into two groups of user configurable and non user configurable
individually programmable channel priorization scheme for measurement unit
two independent filter stages with programmable low-pass and time filter characteristics for each channel
two channel configurations:
– programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis
– two individually programmable trigger thresholds with limit hysteresis settings
individually programmable interrupts and status for all channel thresholds
22.1
Functional Description
22.1.1
Basic Functions
TSENSE_SEL
4
/
MUX_SEL<3:0>
Channel Controller
(Sequencer)
ADC2 - XSFR
TSENSE
VBAT_SENSE
CH0
VS
CH1
VDDP
CH2
VDDC
CH3
VBG
CH4
n.u.
CH5
LS1
CH6
LS2
CH7
TS1
CH8
TS2
CH9
Digital Signal Processing
1st Order IIR
ADC2
VREF
MUX
A
D
8
/
Calibration Unit:
y= a + (1+b)*x
8
/
8
/
TH_UP_CHx
TH_LOW_CHx
+
+
1
/
+/-
UP_X_STS
1
/
+/-
LOW_X_STS
Figure 145 Module Block Diagram
The basic function of this unit is the digital signal processing of several analog digitized measurement signals by
means of filtering, level comparison and interrupt generation. The Measurement Core module processes ten
channels in a quasi parallel process.
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As shown in Figure 145, the ADC postprocessing consists of a channel controller, a 10-channel multiplexer and
the signal processing block, which filters and compares the sampled ADC2 values for each channel individually.
The channel control block controls the multiplexer sequencing on the analog side before the ADC and on the digital
domain after the ADC. The channel sequence can be controlled in a flexible way, which allows a certain degree
of channel prioritization.
This capability can be used e.g. to set a higher priority to supply voltage channels compared to the other channel
measurements. The Measurement Core Module offers additionally two different post-processing measurement
modes for over-/undervoltage detection and for two-level threshold detection.
Usually the external register settings should only be changed during the start-up phase of the postprocessing
module. Otherwise the signal processing might be disturbed. The Measurement Core Module will be reset by
Reset-Type 4.
22.1.1.1
ADC2 - Core (8-Bit ADC)
The 8-Bit ADC Core has a conversion time of 10 clock cycles. To calculate the latency of the ADC, the sampling
time configuration must be considered as well (this can be adjusted in MEAS_ADC2_CTRL2 register).
Considering the max. possible setting for this parameter, the latency is 32 clock cyles. Figure 146 shows the
timing of ADC2 related to the MI_CLK (also named CLK_ADC).
Tsamp
1
2
3
4
5
Tsar
MS
1
2
3
4
5
6
7
8
9
10
1
2
3
MS
CLK_ADC
SOC
EOC
SAMPLING
N+1
Channel N Sampling
N+1
N+1
N+2
ADC_RESULT-UPDATE
N-1
N-1
N
ADC_RESULT-ACCESS
N-1
N-1
N
MUX_SEL
N
ADC latches MUX_SEL (here channel N) to hold MUX in stable state
during sampling (here channel N)
Figure 146 ADC2 Timing description for sampling time adjustment
There are two measurement timing controlling mechanisms for the ADC2:
•
•
the sequencer is described in the chapter Channel Controller.
the sample time adjustment is described in the register MEAS_ADC2_CTRL2.
22.1.1.2
Channel Controller
The task of each channel controller is the prioritization of the individual measurement channels. The sequencing
scheme is illustrated in the example of the following table and is configurable.
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Table 90
Measurement channel sequence definition example (used as default sequence)
Measurement channel n
MSB
LSB
CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
MEAS_ADC2_SQ1_2_int [3:0],
MEAS_ADC2_SQ1
1
0
1
1
1
1
0
1
1
1
MEAS_ADC2_SQ1_2_int [7:4],
MEAS_ADC2_SQ2
0
1
1
1
1
0
1
0
0
0
MEAS_ADC2_SQ3_4_int [3:0],
MEAS_ADC2_SQ3
1
0
1
1
1
1
0
1
1
0
MEAS_ADC2_SQ3_4_int [7:4],
MEAS_ADC2_SQ4
0
1
1
1
1
0
1
0
0
1
MEAS_ADC2_SQ5_6_int [3:0],
MEAS_ADC2_SQ5
1
0
1
1
1
1
0
1
1
0
MEAS_ADC2_SQ5_6_int [7:4],
MEAS_ADC2_SQ6
0
1
1
1
1
0
1
0
0
0
MEAS_ADC2_SQ7_8_int [3:0],
MEAS_ADC2_SQ7
1
0
1
1
1
1
0
1
1
1
MEAS_ADC2_SQ7_8_int [7:4],
MEAS_ADC2_SQ8
0
1
1
1
1
0
1
0
0
0
MEAS_ADC2_SQ9_10_int [3:0],
MEAS_ADC2_SQ9
1
0
1
1
1
1
0
1
1
0
MEAS_ADC2_SQ9_10_int [7:4],
MEAS_ADC2_SQ10
0
1
1
1
1
0
1
0
0
1
The sequence registers MEAS_ADC2_SQx and MEAS_ADC2_SQx_y_int define the time sequence of the
measurement channels by the following rules:
•
•
•
The sequence registers define the measurement sequence and are evaluated from register 1 to 10 and for
each register from MSB to LSB, which defines a max. overall measurement periodicity of 100 sampling and
conversion cycles
If the individual bit in the sequence register is set to ’1’, the corresponding channel is measured
If the individual bit in the sequence register is not set, this measurement phase is skipped.
In the upper example, the resulting channel sequence is defined as:
CH9, CH7, CH6, CH5, CH4, CH2, CH1, CH0, CH8, CH7, CH6, CH5, CH3,......, CH8, CH7, CH6, CH5, CH3, CH0
Cannels 0 - 5 can be fully programmed. Several sequence registers, especially for channels 6-9, are protected to
ensure a fast update of measurement results used for internal diagnosis. Hence the channels 6 and 7 are
prioritized and are measured more often, the overall periodicity is mainly determined by these two channels. The
channels 0-5 are measured depending on the amount of ’1’ bits, written in the sequence registers. The following
equations can be used to calculate the periodicity of the required channel measurement.
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The overall measurement periodicity of all measurements in A/D conversion cycles is defined as:
N
10 ⎛ 10
⎞
= ∑ ⎜ ∑ SQ [n ]⎟
meas
m ⎟
m = 1⎜⎝ n = 1
⎠
(20)
The average measurement periodicity of channel n in A/D conversion cycles is defined as
⎞
⎛ 10
⎜ ∑ SQ [n ] ⎟
m ⎟
⎜
N
= ⎜ m =1
⎟
meas , n
T
⎟
⎜
meas
⎟
⎜
⎠
⎝
(21)
The timing of the analog MUX and the digital DEMUX is controlled by the channel controller accordingly. The
analog MUX with sample and hold stage needs one clock cycle for channel switching and the ADC consumes, as
default setting, 12 clock cycles for the sampling of the input voltage. The conversion time for a single channel
measurement value is 10 clock cycles. A modification of the sample time configuration will influence the
conversion time for each channel.
The channel controller has a partly fixed sequence register setting which cannot be changed by the user. The fixed
register setting is needed, to fulfill the sampling frequency requirements of the internal circuits, e.g. over-current
protection for the Low Side drivers.
The minimum measurement periodicity, which can be achieved, by enabling only channel 1 in the sequence
registers, depends on the MI_CLK frequency and is given by:
=
T
meas _ Ch1 _ min f
96
MI _ CLK
This following calculations include already the sampling time of ADC2. If all programmable channels are enabled,
the maximum periodicity is calculated:
(22)
T
=
meas _ Ch1 _ max f
240
MI _ CLK
(23)
For a MI_CLK frequency of 24 MHz, the channel 1 is measured with min. 4 µs. The maximum update time of
channel 1 with 24 MHz clock frequency is 10 µs. This is calculated with the assumption, that all channels are
enabled and channel1 is enabled in every sequence register. As a prerequisite for this calculation we take
MEAS_ADC2_CTRL2 = 4 (sample period = 14 MI_CLK clock cycles).
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22.1.1.2.1
Channel Controller Control Registers
The Channel Controller can be configured by the XSFR Register listed in Table 91. The registers which cannot
be written by the user have the attribute rwp. Those registers are:
MEAS_ADC2_SQ1_2_int, MEAS_ADC2_SQ3_4_int, MEAS_ADC2_SQ5_6_int, MEAS_ADC2_SQ7_8_int,
MEAS_ADC2_SQ9_10_int
They are reserved for configuring the measurement sequence for both Low Side switches and the two available
temperature sensors. In order to guarantee a fast shutdown of the Low Side switches in case of a over-current
situation and also a fast reaction to overtemperature conditions, this registers are not accessible to the user.
Table 91
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Channel Controller Control Registers,
MEAS_ADC2_CHx_EI
M
Channel Settings for Exceptional Interrupt
Measurement Register
1DH
0000 1000B
MEAS_ADC2_CTRL1
Measurement Unit Control 1 Register
2DH
0000 0000B
MEAS_ADC2_CTRL2
Measurement Unit Control 2 Register
2EH
0000 0100B
MEAS_ADC2_CTRL3
Measurement Unit Control 3 Register
2FH
x000 0011B
MEAS_ADC2_SQ1
Measurement Channel Enable Cycle 1 Register
30H
0011 0111B
MEAS_ADC2_SQ2
Measurement Channel Enable Cycle 2 Register
31H
0010 1000B
MEAS_ADC2_SQ3
Measurement Channel Enable Cycle 3 Register
32H
0011 0110B
MEAS_ADC2_SQ4
Measurement Channel Enable Cycle 4 Register
33H
0010 1001B
MEAS_ADC2_SQ5
Measurement Channel Enable Cycle 5 Register
34H
0011 0110B
MEAS_ADC2_SQ6
Measurement Channel Enable Cycle 6 Register
35H
0010 1000B
MEAS_ADC2_SQ7
Measurement Channel Enable Cycle 7 Register
36H
0011 0111B
MEAS_ADC2_SQ8
Measurement Channel Enable Cycle 8 Register
37H
0010 1000B
MEAS_ADC2_SQ9
Measurement Channel Enable Cycle 9 Register
38H
0011 0110B
MEAS_ADC2_SQ10
Measurement Channel Enable Cycle 10 Register
39H
0010 1001B
MEAS_ADC2_CTRL4
Measurement Unit Control 4 Register
43H
0000 0000B
MEAS_ADC2_SQ1_2_i Measurement Channel Enable Cycle 1 and 2
nt
Register
70H
0111 1011B
MEAS_ADC2_SQ3_4_i Measurement Channel Enable Cycle 3 and 4
nt
Register
71H
0111 1011B
MEAS_ADC2_SQ5_6_i Measurement Channel Enable Cycle 5 and 6
nt
Register
72H
0111 1011B
MEAS_ADC2_SQ7_8_i Measurement Channel Enable Cycle 7 and 8
nt
Register
73H
0111 1011B
MEAS_ADC2_SQ9_10_ Measurement Channel Enable Cycle 9 and 10
int
Register
74H
0111 1011B
86H
0000 0000B
MEAS_ADC2_CTRL5
Measurement Unit Control 5 Register
The registers are addressed bytewise.
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Measurement Unit Control 1 Register
This register is dedicated for controlling the calibration unit of the measurement core module. The respective
channel calibration can be enabled or disabled by the bits listed below.
The register is reset by RESET_TYPE_4.
MEAS_ADC2_CTRL1
Measurement Unit Control 1 Register
7
6
Offset
Reset Value
2DH
0000 0000B
5
0
RES
CALIB_EN
r
rw
Field
Bits
Type
Description
RES
7:6
r
Reserved
Always read as 0
CALIB_EN
5:0
rw
Calibration Enable for Channels 0 to 5
000000B Channel Calibration disable calibration units for
channels 0 to 5 are disabled
000001BChannel 0 Calibration enable channel 0 data will be
calibrated
000010BChannel 1 Calibration enable channel 1 data will be
calibrated
000100BChannel 2 Calibration enable channel 2 data will be
calibrated
001000BChannel 3 Calibration enable channel 3 data will be
calibrated
010000BChannel 4 Calibration enable channel 4 data will be
calibrated
100000BChannel 5 Calibration enable channel 5 data will be
calibrated
111111BChannel Calibration enable calibration units for
channels 0 to 5 are enabled
Measurement Unit Control 2 Register
This register is used for controlling the calibration unit of channels 6-9 of the measurement core module. Bit [7:4 ]
of this register are protected for the purpose mentioned at the beginning of this chapter. Furthermore this register
contains the sample time adjustment for ADC2. The default value is 14 clock cycles. Values above 14 clock cycles
are not recommended, because they increase the overall response time of the measurement system. Less than
14 clock cycles will decrease the accuracy of the conversion result.
The register is reset by RESET_TYPE_4.
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MEAS_ADC2_CTRL2
Measurement Unit Control 2 Register
7
Offset
Reset Value
2EH
0000 0100B
4
3
0
CALIB_EN_int
ADC2_SAMPLE_TIME_int
rwp
rw
Field
Bits
Type
Description
CALIB_EN_int
7:4
rwp
Calibration Enable for Channels 6 to 9
00H Channel Calibration disable calibration units for
channels 6 to 9 are disabled
01H Channel 6 Calibration enable channel 6 data will be
calibrated
02H Channel 7 Calibration enable channel 7 data will be
calibrated
04H Channel 8 Calibration enable channel 8 data will be
calibrated
08H Channel 9 Calibration enable channel 9 data will be
calibrated
0FH Channel Calibration enable calibration units for
channels 6 to 9 are enabled
rw
Sample time of ADC2
0H
MICLK4 4 MI_CLK clock periods
MICLK6 6 MI_CLK clock periods
1H
MICLK8 8 MI_CLK clock periods
2H
MICLK10 10 MI_CLK clock periods
3H
MICLK12 12 MI_CLK clock periods
4H
MICLK14 14 MI_CLK clock periods
5H
MICLK16 16 MI_CLK clock periods
6H
MICLK18 18 MI_CLK clock periods
7H
MICLK20 20 MI_CLK clock periods
8H
MICLK22 22 MI_CLK clock periods
9H
AH n.u. not used
BH n.u. not used
CH n.u. not used
DH n.u. not used
EH n.u. not used
FH n.u. not used
ADC2_SAMPLE_TIME_int 3:0
Measurement Unit Control 3 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_CTRL3
Offset
Reset Value
Measurement Unit Control 3 Register
2FH
x000 0011B
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7
6
1
0
MCM_RDY
RES
MCM_PD_
N
r
r
rw
Field
Bits
Type
Description
MCM_RDY
7
r
Ready Signal for MCM1) after Reset
0B
MCM Not Ready Measurement Core Module in
startup phase
MCM Ready Measurement Core Module start-up
1B
phase finished
RES
6:1
r
Reserved
Always read as 0
MCM_PD_N
0
rw
Power Down Signal for MCM
0B
MCM Disabled Measurement Core Module
Disabled
MCM Enabled Measurement Core Module
1B
Enabled
1) MCM = Measurement Core Module
Measurement Unit Control 4 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_CTRL4
Measurement Unit Control 4 Register
7
6
Offset
Reset Value
43H
0000 0000B
5
0
Res
ADC2_FILT_OUT_SEL_5_0
rw
Field
Bits
Type
Description
RES
7:6
rwp
Reserved
Always read as 0
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Field
Bits
ADC2_FILT_OUT_SEL_ 5:0
5_0
Type
Description
rw
Output Filter Selection for Channels 0 to 5
00H ADC2 Raw Data can be monitored in the
corresponding ADC2_FILT_OUTx Registers .
01H Channel 0 Data enabled for ADC2_FILT_OUT0
Register
02H Channel 1 IIR Data enabled for ADC2_FILT_OUT1
Register
04H Channel 2 IIR Data enabled for ADC2_FILT_OUT2
Register
08H Channel 3 IIR Data enabled for ADC2_FILT_OUT3
Register
10H Channel 4 IIR Data enabled for ADC2_FILT_OUT4
Register
20H Channel 5 IIR Data enabled for ADC2_FILT_OUT5
Register
3fH For Channels 5-0 IIR Data is enabled for
ADC2_FILT_OUTx Registers .
Measurement Unit Control 5 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_CTRL5
Measurement Unit Control 5 Register
7
5
Offset
Reset Value
86H
0000 0000B
4
0
Res
ADC2_FILT_OUT_SEL_9_6
rw
Field
Bits
Type
Description
RES
7:5
rwp
Reserved
Always read as 0
rw
Output Filter Selection for Channels 6 to 9
00H ADC2 Raw Data can be monitored in the
corresponding ADC2_FILT_OUTx Registers .
01H Channel 6 IIR Data enabled for ADC2_FILT_OUT6
Register .
02H Channel 7 IIR Data enabled for ADC2_FILT_OUT7
Register .
04H Channel 8 IIR Data enabled for ADC2_FILT_OUT8
Register .
08H Channel 9 IIR Data enabled for ADC2_FILT_OUT9
Register .
3fH For Channels 9-6 IIR Data is enabled for
ADC2_FILT_OUTx Registers .
ADC2_FILT_OUT_SEL_ 4:0
9_6
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Measurement Channel Enable Cycle 1 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ1
Measurement Channel Enable Cycle 1
Register
7
6
Offset
Reset Value
30H
0011 0111B
5
0
RES
ADC2_SQ1
r
rw
Field
Bits
Type
Description
RES
7:6
r
Reserved
Always read as 0
ADC2_SQ1
5:0
rw
Sequence 1 channel enable
xx xxx1B CH0_EN Channel 0 enable
xx xx1xB CH1_EN Channel 1 enable
xx x1xxB CH2_EN Channel 2 enable
xx 1xxxB CH3_EN Channel 3 enable
x1 xxxxB CH4_EN Channel 4 enable
1x xxxxB CH5_EN Channel 5 enable
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Measurement Core Module - ADC2
Measurement Channel Enable Cycle 2 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ2
Measurement Channel Enable Cycle 2
Register
7
6
Offset
Reset Value
31H
0010 1000B
5
0
RES
ADC2_SQ2
r
rw
Field
Bits
Type
Description
RES
7:6
r
Reserved
Always read as 0
ADC2_SQ2
5:0
rw
Sequence 2 channel enable
xx xxx1B CH0_EN Channel 0 enable
xx xx1xB CH1_EN Channel 1 enable
xx x1xxB CH2_EN Channel 2 enable
xx 1xxxB CH3_EN Channel 3 enable
x1 xxxxB CH4_EN Channel 4 enable
1x xxxxB CH5_EN Channel 5 enable
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Measurement Channel Enable Cycle 1 and 2 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ1_2_int
Offset
Reset Value
70H
0111 1011B
Measurement Channel Enable Cycle 1 and 2
Register
7
4
3
0
ADC2_SQ2_int
ADC2_SQ1_int
rwp
rwp
Field
Bits
Type
Description
ADC2_SQ2_int
7:4
rwp
Sequence 2 channel enable
xxx1xxxxB CH6_EN Channel 6 enable
xx1xxxxxB CH7_EN Channel 7 enable
x1xxxxxxB CH8_EN Channel 8 enable
1xxxxxxxB CH9_EN Channel 9 enable
ADC2_SQ1_int
3:0
rwp
Sequence 1 channel enable
xxxxxxx1B CH6_EN Channel 6 enable
xxxxxx1xB CH7_EN Channel 7 enable
xxxxx1xxB CH8_EN Channel 8 enable
xxxx1xxxB CH9_EN Channel 9 enable
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Measurement Channel Enable Cycle 3 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ3
Measurement Channel Enable Cycle 3
Register
7
6
Offset
Reset Value
32H
0011 0110B
5
0
RES
ADC2_SQ3
r
rw
Field
Bits
Type
Description
RES
7:6
r
Reserved
Always read as 0
ADC2_SQ3
5:0
rw
Sequence 3 channel enable
xx xxx1B CH0_EN Channel 0 enable
xx xx1xB CH1_EN Channel 1 enable
xx x1xxB CH2_EN Channel 2 enable
xx 1xxxB CH3_EN Channel 3 enable
x1 xxxxB CH4_EN Channel 4 enable
1x xxxxB CH5_EN Channel 5 enable
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Measurement Channel Enable Cycle 4 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ4
Measurement Channel Enable Cycle 4
Register
7
6
Offset
Reset Value
33H
0010 1001B
5
0
RES
ADC2_SQ4
r
rw
Field
Bits
Type
Description
RES
7:6
r
Reserved
Always read as 0
ADC2_SQ4
5:0
rw
Sequence 4 channel enable
xx xxx1B CH0_EN Channel 0 enable
xx xx1xB CH1_EN Channel 1 enable
xx x1xxB CH2_EN Channel 2 enable
xx 1xxxB CH3_EN Channel 3 enable
x1 xxxxB CH4_EN Channel 4 enable
1x xxxxB CH5_EN Channel 5 enable
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Measurement Channel Enable Cycle 3 and 4 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ3_4_int
Offset
Reset Value
71H
0111 1011B
Measurement Channel Enable Cycle 3 and 4
Register
7
4
3
0
ADC2_SQ4_int
ADC2_SQ3_int
rwp
rwp
Field
Bits
Type
Description
ADC2_SQ4_int
7:4
rwp
Sequence 4 channel enable
xxx1xxxxB CH6_EN Channel 6 enable
xx1xxxxxB CH7_EN Channel 7 enable
x1xxxxxxB CH8_EN Channel 8 enable
1xxxxxxxB CH9_EN Channel 9 enable
ADC2_SQ3_int
3:0
rwp
Sequence 3 channel enable
xxxxxxx1B CH6_EN Channel 6 enable
xxxxxx1xB CH7_EN Channel 7 enable
xxxxx1xxB CH8_EN Channel 8 enable
xxxx1xxxB CH9_EN Channel 9 enable
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Measurement Channel Enable Cycle 5 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ5
Measurement Channel Enable Cycle 5
Register
7
6
Offset
Reset Value
34H
0011 0110B
5
0
RES
ADC2_SQ5
r
rw
Field
Bits
Type
Description
RES
7:6
r
Reserved
Always read as 0
ADC2_SQ5
5:0
rw
Sequence 5 channel enable
xx xxx1B CH0_EN Channel 0 enable
xx xx1xB CH1_EN Channel 1 enable
xx x1xxB CH2_EN Channel 2 enable
xx 1xxxB CH3_EN Channel 3 enable
x1 xxxxB CH4_EN Channel 4 enable
1x xxxxB CH5_EN Channel 5 enable
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Measurement Channel Enable Cycle 6 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ6
Measurement Channel Enable Cycle 6
Register
7
6
Offset
Reset Value
35H
0010 1000B
5
0
RES
ADC2_SQ6
r
rw
Field
Bits
Type
Description
RES
7:6
r
Reserved
Always read as 0
ADC2_SQ6
5:0
rw
Sequence 6 channel enable
xx xxx1B CH0_EN Channel 0 enable
xx xx1xB CH1_EN Channel 1 enable
xx x1xxB CH2_EN Channel 2 enable
xx 1xxxB CH3_EN Channel 3 enable
x1 xxxxB CH4_EN Channel 4 enable
1x xxxxB CH5_EN Channel 5 enable
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Measurement Channel Enable Cycle 5 and 6 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ5_6_int
Offset
Reset Value
72H
0111 1011B
Measurement Channel Enable Cycle 5 and 6
Register
7
4
3
0
ADC2_SQ6_int
ADC2_SQ5_int
rwp
rwp
Field
Bits
Type
Description
ADC2_SQ6_int
7:4
rwp
Sequence 6 channel enable
xxx1xxxxB CH6_EN Channel 6 enable
xx1xxxxxB CH7_EN Channel 7 enable
x1xxxxxxB CH8_EN Channel 8 enable
1xxxxxxxB CH9_EN Channel 9 enable
ADC2_SQ5_int
3:0
rwp
Sequence 5 channel enable
xxxxxxx1B CH6_EN Channel 6 enable
xxxxxx1xB CH7_EN Channel 7 enable
xxxxx1xxB CH8_EN Channel 8 enable
xxxx1xxxB CH9_EN Channel 9 enable
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Measurement Channel Enable Cycle 7 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ7
Measurement Channel Enable Cycle 7
Register
7
6
Offset
Reset Value
36H
0011 0111B
5
0
RES
ADC2_SQ7
r
rw
Field
Bits
Type
Description
RES
7:6
r
Reserved
Always read as 0
ADC2_SQ7
5:0
rw
Sequence 7 channel enable
xx xxx1B CH0_EN Channel 0 enable
xx xx1xB CH1_EN Channel 1 enable
xx x1xxB CH2_EN Channel 2 enable
xx 1xxxB CH3_EN Channel 3 enable
x1 xxxxB CH4_EN Channel 4 enable
1x xxxxB CH5_EN Channel 5 enable
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Measurement Channel Enable Cycle 8 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ8
Measurement Channel Enable Cycle 8
Register
7
6
Offset
Reset Value
37H
0010 1000B
5
0
RES
ADC2_SQ8
r
rw
Field
Bits
Type
Description
RES
7:6
r
Reserved
Always read as 0
ADC2_SQ8
5:0
rw
Sequence 8 channel enable
xx xxx1B CH0_EN Channel 0 enable
xx xx1xB CH1_EN Channel 1 enable
xx x1xxB CH2_EN Channel 2 enable
xx 1xxxB CH3_EN Channel 3 enable
x1 xxxxB CH4_EN Channel 4 enable
1x xxxxB CH5_EN Channel 5 enable
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Measurement Channel Enable Cycle 7 and 8 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ7_8_int
Measurement Channel Enable Cycle 7 and 8
Register
7
Field
Offset
Reset Value
73H
0111 1011B
4
3
0
ADC2_SQ8_int
ADC2_SQ7_int
rwp
rwp
Type
Description
ADC2_SQ8_in 7:4
t
rwp
Sequence 8 channel enable
xxx1xxxxB CH6_EN Channel 6 enable
xx1xxxxxB CH7_EN Channel 7 enable
x1xxxxxxB CH8_EN Channel 8 enable
1xxxxxxxB CH9_EN Channel 9 enable
ADC2_SQ7_in 3:0
t
rwp
Sequence 7 channel enable
xxxxxxx1B CH6_EN Channel 6 enable
xxxxxx1xB CH7_EN Channel 7 enable
xxxxx1xxB CH8_EN Channel 8 enable
xxxx1xxxB CH9_EN Channel 9 enable
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Measurement Core Module - ADC2
Measurement Channel Enable Cycle 9 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ9
Measurement Channel Enable Cycle 9
Register
7
6
Offset
Reset Value
38H
0011 0110B
5
0
RES
ADC2_SQ9
r
rw
Field
Bits
Type
Description
RES
7:6
r
Reserved
Always read as 0
ADC2_SQ9
5:0
rw
Sequence 9 channel enable
xx xxx1B CH0_EN Channel 0 enable
xx xx1xB CH1_EN Channel 1 enable
xx x1xxB CH2_EN Channel 2 enable
xx 1xxxB CH3_EN Channel 3 enable
x1 xxxxB CH4_EN Channel 4 enable
1x xxxxB CH5_EN Channel 5 enable
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Measurement Channel Enable Cycle 10 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ10
Measurement Channel Enable Cycle 10
Register
7
6
Offset
Reset Value
39H
0010 1001B
5
0
RES
ADC2_SQ10
r
rw
Field
Bits
Type
Description
RES
7:6
r
Reserved
Always read as 0
ADC2_SQ10
5:0
rw
Sequence 10 channel enable
xx xxx1B CH0_EN Channel 0 enable
xx xx1xB CH1_EN Channel 1 enable
xx x1xxB CH2_EN Channel 2 enable
xx 1xxxB CH3_EN Channel 3 enable
x1 xxxxB CH4_EN Channel 4 enable
1x xxxxB CH5_EN Channel 5 enable
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Measurement Channel Enable Cycle 9 and 10 Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_SQ9_10_int
Measurement Channel Enable Cycle 9 and 10
Register
7
Field
Offset
Reset Value
74H
0111 1011B
4
3
0
ADC2_SQ10_int
ADC2_SQ9_int
rwp
rwp
Type
Description
ADC2_SQ10_i 7:4
nt
rwp
Sequence 10 channel enable
xxx1xxxxB CH6_EN Channel 6 enable
xx1xxxxxB CH7_EN Channel 7 enable
x1xxxxxxB CH8_EN Channel 8 enable
1xxxxxxxB CH9_EN Channel 9 enable
ADC2_SQ9_in 3:0
t
rwp
Sequence 9 channel enable
xxxxxxx1B CH6_EN Channel 6 enable
xxxxxx1xB CH7_EN Channel 7 enable
xxxxx1xxB CH8_EN Channel 8 enable
xxxx1xxxB CH9_EN Channel 9 enable
User’s Manual
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Measurement Core Module - ADC2
Channel Setting for Exceptional Interrupt Measurement Register
The register is reset by RESET_TYPE_4.
MEAS_ADC2_CHx_EIM
Channel Settings for Exceptional Interrupt
Measurement Register
7
Offset
Reset Value
1DH
0000 1000B
4
3
0
RES
ADC2_EIM_CHx
r
rw
Field
Bits
Type
Description
RES
7:4
r
Reserved
Always read as 0
ADC2_EIM_C
Hx
3:0
rw
channel set for exceptional interrupt measurement
0000B
CH0_EN Channel 0 enable
CH1_EN Channel 1 enable
0001B
CH2_EN Channel 2 enable
0010B
CH3_EN Channel 3 enable
0011B
CH4_EN Channel 4 enable
0100B
CH5_EN Channel 5 enable
1000B
CH6_EN Channel 6 enable
1001B
CH7_EN Channel 7 enable
1010B
CH8_EN Channel 8 enable
1011B
CH9_EN Channel 9 enable
1100B
n.u. not used
xxxxB
n.u. not used
xxxxB
n.u. not used
xxxxB
n.u. not used
xxxxB
n.u. not used
xxxxB
22.1.1.3
Calibration Unit
The calibration unit of the Measurement Core module is dedicated to cancel out offset and gain errors out of the
signal chain. The following chapters describe the usage and setup of the calibration unit.
22.1.1.3.1
Method for determining the Calibration Parameters
The module can be used to correct gain and offset errors caused by non-idealities in the measurement chain.
Those 1st order non-idealities are:
•
•
•
Offset and gain error of ADC2
Offset and gain error of the attenuator (especially voltage measurement)
Offset and gain error of reference voltage
All these factors are summed up in the overall Gain (factor b) and overall Offset (adder a) of the complete
measurement chain. They are calculated from a two point test result and stored inside the NVM.
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Note: The calibration of the VBAT_SENSE pin and the HV-Monitoring pins is based on an external 1 kΩ
resistor. The usage of a resistor with another value will lead to a wrong measurement result.
22.1.1.3.2
Setup of Calibration Unit
Each channel has its own calibration unit and thus also its dedicated gain and offset parameter. These parameters
are stored in a 100TP page of the Flash Module. After each reset of RESET_TYPE_4 these coefficients are
downloaded from NVM into the corresponding registers. These values are used by the calibration unit for result
correction. The figure below shows the formula performed by the calibration unit and the required XSFR-Register
to control its functionality.
Calibration Unit
8
0
ALU-16 Bit signed :
y = a + (1+b)*x
8
1
x
ADC2_CALOFFS_CHx
ADC2 Raw Data
8
ADC2_CALLGAIN_CHx
8
8
CALIB_EN
ADC2 - XSFR
Figure 147 Structure of calibration unit
.
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22.1.1.3.3
Calibration Unit Control Registers
The Calibration Unit can be configured by the XSFR Register shown below. The registers which cannot be written
by the user have the attribute rwp. Those registers are:
ADC2_CALOFFS_CH6,
ADC2_CALGAIN_CH6,
ADC2_CALOFFS_CH7,
ADC2_CALGAIN_CH7,
ADC2_CALOFFS_CH8, ADC2_CALGAIN_CH8, ADC2_CALOFFS_CH9, ADC2_CALGAIN_CH9.
They are required for calibration of the ADC2 measurement for both Low Side switches and the two temperature
sensors. In order to guarantee an accurate shutdown of the Low Side switches in over-current condition and also
in case of overtemperature, these registers cannot be modified by the application.
Table 92
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Calibration Unit Control Registers,
ADC2_CALOFFS_CH7
ADC2 Offset Calibration Value Channel 7 Register 77H
0000 0000B
ADC2_CALOFFS_CH6
ADC2 Offset Calibration Value Channel 6 Register 75H
0000 0000B
ADC2_CALGAIN_CH6
ADC2 Gain Calibration Value Channel 6 Register 76H
0001 0100B
ADC2_CALGAIN_CH7
ADC2 Gain Calibration Value Channel 7 Register 78H
0001 0100B
ADC2_CALOFFS_CH8
ADC2 Offset Calibration Value Channel 8 Register 79H
0000 0000B
ADC2_CALGAIN_CH8
ADC2 Gain Calibration Value Channel 8 Register 7AH
0000 0000B
ADC2_CALOFFS_CH9
ADC2 Offset Calibration Value Channel 9 Register 7BH
0000 0000B
ADC2_CALGAIN_CH9
ADC2 Gain Calibration Value Channel 9 Register 7CH
0000 0000B
ADC2_CALOFFS_CH0
ADC2 Offset Calibration Value Channel 0 Register BCH
0000 0000B
ADC2_CALGAIN_CH0
ADC2 Gain Calibration Value Channel 0 Register BDH
0000 0000B
ADC2_CALOFFS_CH1
ADC2 Offset Calibration Value Channel 1 Register BEH
0000 0000B
ADC2_CALGAIN_CH1
ADC2 Gain Calibration Value Channel 1 Register BFH
0000 0000B
ADC2_CALOFFS_CH2
ADC2 Offset Calibration Value Channel 2 Register C0H
0000 0000B
ADC2_CALGAIN_CH2
ADC2 Gain Calibration Value Channel 2 Register C1H
0000 0000B
ADC2_CALOFFS_CH3
ADC2 Offset Calibration Value Channel 3 Register C2H
0000 0000B
ADC2_CALGAIN_CH3
ADC2 Gain Calibration Value Channel 3 Register C3H
0000 0000B
ADC2_CALOFFS_CH4
ADC2 Offset Calibration Value Channel 4 Register C4H
0000 0000B
ADC2_CALGAIN_CH4
ADC2 Gain Calibration Value Channel 4 Register C5H
0000 0000B
ADC2_CALOFFS_CH5
ADC2 Offset Calibration Value Channel 5 Register C6H
0000 0000B
ADC2_CALGAIN_CH5
ADC2 Gain Calibration Value Channel 5 Register C7H
0000 0000B
The registers are addressed bytewise.
ADC2 Offset Calibration Value Channel 0 Register
The register is reset by RESET_TYPE_4.
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ADC2_CALOFFS_CH0
Offset
Reset Value
BCH
0000 0000B
ADC2 Offset Calibration Value Channel 0
Register
7
0
ADC2_CALOFFS_CH0
rw
Field
Bits
Type
Description
ADC2_CALOFFS_CH0
7:0
rw
Offset Calibration for channel 0
For ADC results without calibration set CALIB_EN_0 = 0
ADC2 Gain Calibration Value Channel 0 Register
The register is reset by RESET_TYPE_4.
ADC2_CALGAIN_CH0
Offset
Reset Value
BDH
0000 0000B
ADC2 Gain Calibration Value Channel 0
Register
7
0
ADC2_CALGAIN_CH0
rw
Field
Bits
Type
Description
ADC2_CALGAIN_CH0
7:0
rw
Gain Calibration for channel 0
For ADC results without calibration set CALIB_EN_0 = 0
ADC2 Offset Calibration Value Channel 1 Register
The register is reset by RESET_TYPE_4.
ADC2_CALOFFS_CH1
ADC2 Offset Calibration Value Channel 1
Register
Offset
Reset Value
BEH
0000 0000B
7
0
ADC2_CALOFFS_CH1
rw
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Field
Bits
Type
Description
ADC2_CALOFFS_CH1
7:0
rw
Offset Calibration for channel 1
For ADC results without calibration set CALIB_EN_1 = 0
ADC2 Gain Calibration Value Channel 1 Register
The register is reset by RESET_TYPE_4.
ADC2_CALGAIN_CH1
Offset
Reset Value
BFH
0000 0000B
ADC2 Gain Calibration Value Channel 1
Register
7
0
ADC2_CALGAIN_CH1
rw
Field
Bits
Type
Description
ADC2_CALGAIN_CH1
7:0
rw
Gain Calibration for channel 1
For ADC results without calibration set CALIB_EN_1 = 0
ADC2 Offset Calibration Value Channel 2 Register
The register is reset by RESET_TYPE_4.
ADC2_CALOFFS_CH2
ADC2 Offset Calibration Value Channel 2
Register
Offset
Reset Value
C0H
0000 0000B
7
0
ADC2_CALOFFS_CH2
rw
Field
Bits
Type
Description
ADC2_CALOFFS_CH2
7:0
rw
Offset Calibration for channel 2
For ADC results without calibration set CALIB_EN_2 = 0
ADC2 Gain Calibration Value Channel 2 Register
The register is reset by RESET_TYPE_4.
ADC2_CALGAIN_CH2
Offset
Reset Value
ADC2 Gain Calibration Value Channel 2
Register
C1H
0000 0000B
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7
0
ADC2_CALGAIN_CH2
rw
Field
Bits
Type
Description
ADC2_CALGAIN_CH2
7:0
rw
Gain Calibration for channel 2
For ADC results without calibration set CALIB_EN_2 = 0
ADC2 Offset Calibration Value Channel 3 Register
The register is reset by RESET_TYPE_4.
ADC2_CALOFFS_CH3
ADC2 Offset Calibration Value Channel 3
Register
Offset
Reset Value
C2H
0000 0000B
7
0
ADC2_CALOFFS_CH3
rw
Field
Bits
Type
Description
ADC2_CALOFFS_CH3
7:0
rw
Offset Calibration for channel 3
For ADC results without calibration set CALIB_EN_3 = 0
ADC2 Gain Calibration Value Channel 3 Register
The register is reset by RESET_TYPE_4.
ADC2_CALGAIN_CH3
ADC2 Gain Calibration Value Channel 3
Register
Offset
Reset Value
C3H
0000 0000B
7
0
ADC2_CALGAIN_CH3
rw
Field
Bits
Type
Description
ADC2_CALGAIN_CH3
7:0
rw
Gain Calibration for channel 3
For ADC results without calibration set CALIB_EN_3 = 0
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ADC2 Offset Calibration Value Channel 4 Register
The register is reset by RESET_TYPE_4.
ADC2_CALOFFS_CH4
Offset
Reset Value
C4H
0000 0000B
ADC2 Offset Calibration Value Channel 4
Register
7
0
ADC2_CALOFFS_CH4
rw
Field
Bits
Type
Description
ADC2_CALOFFS_CH4
7:0
rw
Offset Calibration for channel 4
For ADC results without calibration set CALIB_EN_4 = 0
ADC2 Gain Calibration Value Channel 4 Register
The register is reset by RESET_TYPE_4.
ADC2_CALGAIN_CH4
Offset
Reset Value
C5H
0000 0000B
ADC2 Gain Calibration Value Channel 4
Register
7
0
ADC2_CALGAIN_CH4
rw
Field
Bits
Type
Description
ADC2_CALGAIN_CH4
7:0
rw
Gain Calibration for channel 4
For ADC results without calibration set CALIB_EN_4 = 0
ADC2 Offset Calibration Value Channel 5 Register
The register is reset by RESET_TYPE_4.
ADC2_CALOFFS_CH5
ADC2 Offset Calibration Value Channel 5
Register
Offset
Reset Value
C6H
0000 0000B
7
0
ADC2_CALOFFS_CH5
rw
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Field
Bits
Type
Description
ADC2_CALOFFS_CH5
7:0
rw
Offset Calibration for channel 5
For ADC results without calibration set CALIB_EN_5 = 0
ADC2 Gain Calibration Value Channel 5 Register
The register is reset by RESET_TYPE_4.
ADC2_CALGAIN_CH5
Offset
Reset Value
C7H
0000 0000B
ADC2 Gain Calibration Value Channel 5
Register
7
0
ADC2_CALGAIN_CH5
rw
Field
Bits
Type
Description
ADC2_CALGAIN_CH5
7:0
rw
Gain Calibration for channel 5
For ADC results without calibration set CALIB_EN_5 = 0
ADC2 Offset Calibration Value Channel 6 Register
The register is reset by RESET_TYPE_4. This register is a protected register (Type is rwp) and thus cannot be
written by software.
ADC2_CALOFFS_CH6
ADC2 Offset Calibration Value Channel 6
Register
Offset
Reset Value
75H
0000 0000B
7
0
ADC2_CALOFFS_CH6
rwp
Field
Bits
Type
Description
ADC2_CALOFFS_CH6
7:0
rwp
Offset Calibration for channel 6
For ADC results without calibration set CALIB_EN_6 = 0
ADC2 Gain Calibration Value Channel 6 Register
The register is reset by RESET_TYPE_4. This register is a protected register (Type is rwp) and thus cannot be
written by software.
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ADC2_CALGAIN_CH6
Offset
Reset Value
76H
0001 0100B
ADC2 Gain Calibration Value Channel 6
Register
7
0
ADC2_CALGAIN_CH6
rwp
Field
Bits
Type
Description
ADC2_CALGAIN_CH6
7:0
rwp
Gain Calibration for channel 6
For ADC results without calibration set CALIB_EN_6 = 0
ADC2 Offset Calibration Value Channel 7 Register
The register is reset by RESET_TYPE_4. This register is a protected register (Type is rwp) and thus cannot be
written by software.
ADC2_CALOFFS_CH7
ADC2 Offset Calibration Value Channel 7
Register
Offset
Reset Value
77H
0000 0000B
7
0
ADC2_CALOFFS_CH7
rwp
Field
Bits
Type
Description
ADC2_CALOFFS_CH7
7:0
rwp
Offset Calibration for channel 7
For ADC results without calibration set CALIB_EN_7 = 0
ADC2 Gain Calibration Value Channel 7 Register
The register is reset by RESET_TYPE_4. This register is a protected register (Type is rwp) and thus cannot be
written by software.
ADC2_CALGAIN_CH7
ADC2 Gain Calibration Value Channel 7
Register
Offset
Reset Value
78H
0001 0100B
7
0
ADC2_CALGAIN_CH7
rwp
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Field
Bits
Type
Description
ADC2_CALGAIN_CH7
7:0
rwp
Gain Calibration for channel 7
For ADC results without calibration set CALIB_EN_7 = 0
ADC2 Offset Calibration Value Channel 8 Register
The register is reset by RESET_TYPE_4. This register is a protected register (Type is rwp) and thus cannot be
written by software.
ADC2_CALOFFS_CH8
Offset
Reset Value
79H
0000 0000B
ADC2 Offset Calibration Value Channel 8
Register
7
0
ADC2_CALOFFS_CH8
rwp
Field
Bits
Type
Description
ADC2_CALOFFS_CH8
7:0
rwp
Offset Calibration for channel 8
For ADC results without calibration set CALIB_EN_8 = 0
ADC2 Gain Calibration Value Channel 8 Register
The register is reset by RESET_TYPE_4. This register is a protected register (Type is rwp) and thus cannot be
written by software.
ADC2_CALGAIN_CH8
Offset
Reset Value
7AH
0000 0000B
ADC2 Gain Calibration Value Channel 8
Register
7
0
ADC2_CALGAIN_CH8
rwp
Field
Bits
Type
Description
ADC2_CALGAIN_CH8
7:0
rwp
Gain Calibration for channel 8
For ADC results without calibration set CALIB_EN_8 = 0
ADC2 Offset Calibration Value Channel 9 Register
The register is reset by RESET_TYPE_4. This register is a protected register (Type is rwp) and thus cannot be
written by software.
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ADC2_CALOFFS_CH9
ADC2 Offset Calibration Value Channel 9
Register
Offset
Reset Value
7BH
0000 0000B
7
0
ADC2_CALOFFS_CH9
rwp
Field
Bits
Type
Description
ADC2_CALOFFS_CH9
7:0
rwp
Offset Calibration for channel 9
For ADC results without calibration set CALIB_EN_9 = 0
ADC2 Gain Calibration Value Channel 9 Register
The register is reset by RESET_TYPE_4. This register is a protected register (Type is rwp) and thus cannot be
written by software.
ADC2_CALGAIN_CH9
ADC2 Gain Calibration Value Channel 9
Register
Offset
Reset Value
7CH
0000 0000B
7
0
ADC2_CALGAIN_CH9
rwp
Field
Bits
Type
Description
ADC2_CALGAIN_CH9
7:0
rwp
Gain Calibration for channel 9
For ADC results without calibration set CALIB_EN_9 = 0
22.1.1.4
IIR-Filter
Every channel of the digital signal path includes a first order IIR Filter to suppress noise. The structure of the IIR
Filter is shown in the picture below.
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IIR Filter
Coeff a
r-shift
·(1 - a)
r-shift
12
+
12
limit
+
-
+
12
8
IIR_Data
8
Calib_Raw_Data
12
T
Figure 148 IIR-Filter Implemention Structure
H
(z ) =
IIR
b
1− a ⋅ z−1
(24)
This filter allows an effective suppression of high-frequency components like noise or crosstalk caused by HFcomponents in order to avoid the generation of unwanted interrupts. The coefficient b can be expressed as:
b =1− a
(25)
The IIR Filter transfer function is shown in the figure below.
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l=2
l=4
l=8
l=16
Figure 149 IIR filter transfer function for different filter length fl (1MHz corresponds to 1/2*channel
sampling frequency)
22.1.1.4.1
Filter delay time and cutoff frequencies
The IIR filter’s step response time constant is equivalent to the group delay at ω=0: .
(26)
(27)
Table 93 summarizes the main filter characteristics.
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Table 93
IIR filter characteristics
Filter coefficient
Group delay at=ω0
Normalized -3dB
frequency 1)
-3dB frequency
@ fs_ch/2=250 kHz
a
τ[samples]
f-3dB/(fs_ch/2)
f-3dB [Hz]
-1
2
4.2568e-02
1.0642e+04
-2
4
2.0550e-02
5.1376e+03
-3
2
8
1.0107e-02
2.5267e+03
2-4
16
5.0130e-03
1.2532e+03
2
2
1) The filter’s - 3dB frequency is normalized to half the channel sampling frequency (Nyquist frequency)
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22.1.1.4.2
IIR Filter Control Registers
The IIR Filter can also be configured by the XSFR Register shown below. The registers which cannot be written
by the user have the attribute rwp. Those registers are:
ADC2_FILTCOEFF6_9, ADC2_FILT_UP_CTRL_6_9, ADC2_FILT_LO_CTRL_6_9.
They are used for configuring the filter coefficient a and b. Further they control the lower and upper limit
measurement for both Low Side switches and the two temperature sensors. In order to guarantee a fast shutdown
of the Low Side switches in case of an over-current situation and also a fast reaction to overtemperature
conditions, these registers cannot be modified by the application.
Table 94
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
IIR Filter Control Registers,
ADC2_FILTCOEFF0_3
Filter Coefficients ADC2 Channel 0-3 Register
3AH
1010 1010B
ADC2_FILTCOEFF4_5
Filter Coefficients ADC2 Channel 4-5 Register
3BH
1010 1010B
ADC2_FILT_UP_CTRL
_0_5
Upper Threshold Filter Enable Channel 0-5
Register
3CH
0011 1111B
ADC2_FILT_LO_CTRL
_0_5
Lower Threshold Filter Enable Channel 0-5
Register
3DH
0011 1111B
ADC2_FILT_OUT0
ADC2 Channel 0 Result Register
3EH
xxxx xxxxB
ADC2_FILT_OUT1
ADC2 or Filter Output Channel 1 Register
3FH
xxxx xxxxB
ADC2_FILT_OUT2
ADC2 or Filter Output Channel 2 Register
40H
xxxx xxxxB
ADC2_FILT_OUT3
ADC2 or Filter Output Channel 3 Register
41H
xxxx xxxxB
ADC2_FILT_OUT4
ADC2 or Filter Output Channel 4 Register
42H
xxxx xxxxB
ADC2_FILTCOEFF6_9
Filter Coefficients ADC2 Channel 6-9 Register
7DH
1101 0101B
ADC2_FILT_UP_CTRL
_6_9
Upper Threshold Filter Enable Channel 6-9
Register
7FH
0000 1111B
ADC2_FILT_LO_CTRL
_6_9
Lower Threshold Filter Enable Channel 6-9
Register
80H
0000 1111B
ADC2_FILT_OUT5
ADC2 or Filter Output Channel 5 Register
81H
xxxx xxxxB
ADC2_FILT_OUT6
ADC2 or Filter Output Channel 6 Register
82H
xxxx xxxxB
ADC2_FILT_OUT7
ADC2 or Filter Output Channel 7 Register
83H
xxxx xxxxB
ADC2_FILT_OUT8
ADC2 or Filter Output Channel 8 Register
84H
xxxx xxxxB
ADC2_FILT_OUT9
ADC2 or Filter Output Channel 9 Register
85H
xxxx xxxxB
The registers are addressed bytewise.
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Filter Coefficients ADC2 Channel 0-3 Register
The register is reset by RESET_TYPE_4.
ADC2_FILTCOEFF0_3
Filter Coefficients ADC2 Channel 0-3
Register
7
6
5
Offset
Reset Value
3AH
1010 1010B
4
3
2
1
0
ADC2_FILTCOEF
F_CH3
ADC2_FILTCOEF
F_CH2
ADC2_FILTCOEF
F_CH1
ADC2_FILTCOEF
F_CH0
rw
rw
rw
rw
Field
Type
Description
ADC2_FILTCOEFF_CH3 7:6
rw
Filter Coefficients ADC channel 3
00B 1/2 average 2 samples
01B 1/4 average 4 samples
10B 1/8 average 8 samples
11B 1/16 average 16 samples
ADC2_FILTCOEFF_CH2 5:4
rw
Filter Coefficients ADC channel 2
00B 1/2 average 2 samples
01B 1/4 average 4 samples
10B 1/8 average 8 samples
11B 1/16 average 16 samples
ADC2_FILTCOEFF_CH1 3:2
rw
Filter Coefficients ADC channel 1
00B 1/2 average 2 samples
01B 1/4 average 4 samples
10B 1/8 average 8 samples
11B 1/16 average 16 samples
ADC2_FILTCOEFF_CH0 1:0
rw
Filter Coefficients ADC channel 0
00B 1/2 average 2 samples
01B 1/4 average 4 samples
10B 1/8 average 8 samples
11B 1/16 average 16 samples
User’s Manual
Bits
526
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Filter Coefficients ADC2 Channel 4-5 Register
The register is reset by RESET_TYPE_4.
ADC2_FILTCOEFF4_5
Filter Coefficients ADC2 Channel 4-5
Register
7
Offset
Reset Value
3BH
1010 1010B
4
3
2
0
RES
ADC2_FILTCOEF
F_CH5
ADC2_FILTCOEF
F_CH4
r
rw
rw
Field
Bits
Type
Description
RES
7:4
r
Reserved
Always read as 1010
ADC2_FILTCOEFF_CH5 3:2
rw
Filter Coefficients ADC channel 5
00B 1/2 average 2 samples
01B 1/4 average 4 samples
10B 1/8 average 8 samples
11B 1/16 average 16 samples
ADC2_FILTCOEFF_CH4 1:0
rw
Filter Coefficients ADC channel 4
00B 1/2 average 2 samples
01B 1/4 average 4 samples
10B 1/8 average 8 samples
11B 1/16 average 16 samples
User’s Manual
1
527
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Filter Coefficients ADC2 Channel 6-9 Register
The register is reset by RESET_TYPE_4.
ADC2_FILTCOEFF6_9
Filter Coefficients ADC2 Channel 6-9
Register
7
6
5
Offset
Reset Value
7DH
1101 0101B
4
3
2
1
0
ADC2_FILTCOEF
F_CH9
ADC2_FILTCOEF
F_CH8
ADC2_FILTCOEF
F_CH7
ADC2_FILTCOEF
F_CH6
rwp
rwp
rwp
rwp
Field
Type
Description
ADC2_FILTCOEFF_CH9 7:6
rwp
Filter Coefficients ADC channel 9
00B 1/2 average 2 samples
01B 1/4 average 4 samples
10B 1/8 average 8 samples
11B 1/16 average 16 samples
ADC2_FILTCOEFF_CH8 5:4
rwp
Filter Coefficients ADC channel 8
00B 1/2 average 2 samples
01B 1/4 average 4 samples
10B 1/8 average 8 samples
11B 1/16 average 16 samples
ADC2_FILTCOEFF_CH7 3:2
rwp
Filter Coefficients ADC channel 7
00B 1/2 average 2 samples
01B 1/4 average 4 samples
10B 1/8 average 8 samples
11B 1/16 average 16 samples
ADC2_FILTCOEFF_CH6 1:0
rwp
Filter Coefficients ADC channel 6
00B 1/2 average 2 samples
01B 1/4 average 4 samples
10B 1/8 average 8 samples
11B 1/16 average 16 samples
User’s Manual
Bits
528
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Upper Threshold Filter Enable Channel 0-5 Register
The register is reset by RESET_TYPE_4.
ADC2_FILT_UP_CTRL_0_5
Offset
Reset Value
3CH
0011 1111B
Upper Threshold Filter Enable Channel 0-5
Register
7
6
5
4
3
2
1
0
RES
ADC2_FI
LTUP_5_
EN
ADC2_FI
LTUP_4_
EN
ADC2_FI
LTUP_3_
EN
ADC2_FI
LTUP_2_
EN
ADC2_FI
LTUP_1_
EN
ADC2_FI
LTUP_0_
EN
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
RES
7:6
r
Reserved
Always read as 0
ADC2_FILTUP_5_EN
5
rw
Upper threshold filter enable ch 5
0B
disable
enable
1B
ADC2_FILTUP_4_EN
4
rw
Upper threshold filter enable ch 4
0B
disable
enable
1B
ADC2_FILTUP_3_EN
3
rw
Upper threshold filter enable ch 3
0B
disable
enable
1B
ADC2_FILTUP_2_EN
2
rw
Upper threshold filter enable ch 2
0B
disable
enable
1B
ADC2_FILTUP_1_EN
1
rw
Upper threshold filter enable ch 1
0B
disable
enable
1B
ADC2_FILTUP_0_EN
0
rw
Upper threshold filter enable ch 0
0B
disable
enable
1B
User’s Manual
529
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Upper Threshold Filter Enable Channel 6-9 Register
The register is reset by RESET_TYPE_4.
ADC2_FILT_UP_CTRL_6_9
Upper Threshold Filter Enable Channel 6-9
Register
7
Offset
Reset Value
7FH
0000 1111B
4
3
2
1
0
RES
ADC2_FI
LTUP_9_
EN
ADC2_FI
LTUP_8_
EN
ADC2_FI
LTUP_7_
EN
ADC2_FI
LTUP_6_
EN
r
rwp
rwp
rwp
rwp
Field
Bits
Type
Description
RES
7:4
r
Reserved
Always read as 0
ADC2_FILTUP_9_EN
3
rwp
Upper threshold filter enable ch 9
0B
disable
enable
1B
ADC2_FILTUP_8_EN
2
rwp
Upper threshold filter enable ch 8
0B
disable
enable
1B
ADC2_FILTUP_7_EN
1
rwp
Upper threshold filter enable ch 7
0B
disable
enable
1B
ADC2_FILTUP_6_EN
0
rwp
Upper threshold filter enable ch 6
0B
disable
enable
1B
User’s Manual
530
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Lower Threshold Filter Enable Channel 0-5 Register
The register is reset by RESET_TYPE_4. Setting this register enables the IIR filter structure for the postprocessing
of the lower threshold.
ADC2_FILT_LO_CTRL_0_5
Offset
Reset Value
3DH
0011 1111B
Lower Threshold Filter Enable Channel 0-5
Register
7
6
5
4
3
2
1
0
RES
ADC2_FI
LTLO_5_
EN
ADC2_FI
LTLO_4_
EN
ADC2_FI
LTLO_3_
EN
ADC2_FI
LTLO_2_
EN
ADC2_FI
LTLO_1_
EN
ADC2_FI
LTLO_0_
EN
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
RES
7:6
r
Reserved
Always read as 0
ADC2_FILTLO_5_EN
5
rw
Lower threshold filter enable ch 5
0B
disable
enable
1B
ADC2_FILTLO_4_EN
4
rw
Lower threshold filter enable ch 4
0B
disable
enable
1B
ADC2_FILTLO_3_EN
3
rw
Lower threshold filter enable ch 3
0B
disable
enable
1B
ADC2_FILTLO_2_EN
2
rw
Lower threshold filter enable ch 2
0B
disable
enable
1B
ADC2_FILTLO_1_EN
1
rw
Lower threshold filter enable ch 1
0B
disable
enable
1B
ADC2_FILTLO_0_EN
0
rw
Lower threshold filter enable ch 0
0B
disable
enable
1B
User’s Manual
531
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Lower Threshold Filter Enable Channel 6-9 Register
The register is reset by RESET_TYPE_4. Setting this register enables the filter structure for the measurement of
the lower threshold. This can be used e.g. as shutdown signal for the system, in case of supply loss
ADC2_FILT_LO_CTRL_6_9
Lower Threshold Filter Enable Channel 6-9
Register
7
Offset
Reset Value
80H
0000 1111B
4
3
2
1
0
RES
ADC2_FI
LTLO_9_
EN
ADC2_FI
LTLO_8_
EN
ADC2_FI
LTLO_7_
EN
ADC2_FI
LTLO_6_
EN
r
rwp
rwp
rwp
rwp
Field
Bits
Type
Description
RES
7:4
r
Reserved
Always read as 0
ADC2_FILTLO_9_EN
3
rwp
Lower threshold filter enable ch 9
0B
disable
enable
1B
ADC2_FILTLO_8_EN
2
rwp
Lower threshold filter enable ch 8
0B
disable
enable
1B
ADC2_FILTLO_7_EN
1
rwp
Lower threshold filter enable ch 7
0B
disable
enable
1B
ADC2_FILTLO_6_EN
0
rwp
Lower threshold filter enable ch 6
0B
disable
enable
1B
User’s Manual
532
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
ADC2 or Filter Output Channel 0 Register
The register is reset by RESET_TYPE_3. This register reflects the current value of channel 0 of the measurement
chain, which is assigned to VBAT_SENSE measurement. The result register contains either the ADC2 raw output
date or the corresponding data postprocessed by the filter, depending on the setting of the bit
ADC2_FILTUP_x_EN located in register ADC2_FILT_UP_CTRL_0_5.
ADC2_FILT_OUT0
ADC2 Channel 0 Result Register
Offset
Reset Value
3EH
xxxx xxxxB
7
0
ADC2_OUT_CH0
r
Field
Bits
Type
Description
ADC2_OUT_CH0
7:0
r
ADC2 raw data or filter output value channel 0
For ADC2 output set ADC2_FILTUP_0_EN = 0
ADC2 or Filter Output Channel 1 Register
The register is reset by RESET_TYPE_3.
ADC2_FILT_OUT1
ADC2 or Filter Output Channel 1 Register
Offset
Reset Value
3FH
xxxx xxxxB
7
0
ADC2_OUT_CH1
r
Field
Bits
Type
Description
ADC2_OUT_CH1
7:0
r
ADC2 raw data or filter output value channel 1
For ADC2 results without calibration set
ADC2_FILTUP_1_EN = 0
User’s Manual
533
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
ADC2 or Filter Output Channel 2 Register
The register is reset by RESET_TYPE_3.
ADC2_FILT_OUT2
ADC2 or Filter Output Channel 2 Register
Offset
Reset Value
40H
xxxx xxxxB
7
0
ADC2_OUT_CH2
r
Field
Bits
Type
Description
ADC2_OUT_CH2
7:0
r
ADC2 raw data or filter output value channel 2
For ADC2 results without calibration set
ADC2_FILTUP_2_EN = 0
ADC2 or Filter Output Channel 3 Register
The register is reset by RESET_TYPE_3.
ADC2_FILT_OUT3
ADC2 or Filter Output Channel 3 Register
Offset
Reset Value
41H
xxxx xxxxB
7
0
ADC2_OUT_CH3
r
Field
Bits
Type
Description
ADC2_OUT_CH3
7:0
r
ADC2 raw data or filter output value channel 3
For ADC2 results without calibration set
ADC2_FILTUP_3_EN = 0
User’s Manual
534
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
ADC2 or Filter Output Channel 4 Register
The register is reset by RESET_TYPE_3.
ADC2_FILT_OUT4
ADC2 or Filter Output Channel 4 Register
Offset
Reset Value
42H
xxxx xxxxB
7
0
ADC2_OUT_CH4
r
Field
Bits
Type
Description
ADC2_OUT_CH4
7:0
r
ADC2 raw data or filter output value channel 4
For ADC2 results without calibration set
ADC2_FILTUP_4_EN = 0
ADC2 or Filter Output Channel 5 Register
The register is reset by RESET_TYPE_3.
ADC2_FILT_OUT5
ADC2 or Filter Output Channel 5 Register
Offset
Reset Value
81H
xxxx xxxxB
7
0
ADC2_OUT_CH5
r
Field
Bits
Type
Description
ADC2_OUT_CH5
7:0
r
ADC2 raw data or filter output value channel 5
For ADC2 results without calibration set
ADC2_FILTUP_5_EN = 0
User’s Manual
535
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
ADC2 or Filter Output Channel 6 Register
The register is reset by RESET_TYPE_3.
ADC2_FILT_OUT6
ADC2 or Filter Output Channel 6 Register
Offset
Reset Value
82H
xxxx xxxxB
7
0
ADC2_OUT_CH6
r
Field
Bits
Type
Description
ADC2_OUT_CH6
7:0
r
ADC2 raw data or filter output value channel 6
For ADC2 results without calibration set
ADC2_FILTUP_6_EN = 0
ADC2 or Filter Output Channel 7 Register
The register is reset by RESET_TYPE_3.
ADC2_FILT_OUT7
ADC2 or Filter Output Channel 7 Register
Offset
Reset Value
83H
xxxx xxxxB
7
0
ADC2_OUT_CH7
r
Field
Bits
Type
Description
ADC2_OUT_CH7
7:0
r
ADC2 raw data or filter output value channel 7
For ADC2 results without calibration set
ADC2_FILTUP_7_EN = 0
ADC2 or Filter Output Channel 8 Register
The register is reset by RESET_TYPE_3.
ADC2_FILT_OUT8
ADC2 or Filter Output Channel 8 Register
Offset
Reset Value
84H
xxxx xxxxB
7
0
ADC2_OUT_CH8
r
User’s Manual
536
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Field
Bits
Type
Description
ADC2_OUT_CH8
7:0
r
ADC2 raw data or filter output value channel 8
For ADC2 results without calibration set
ADC2_FILTUP_8_EN = 0
ADC2 or Filter Output Channel 9 Register
The register is reset by RESET_TYPE_3.
ADC2_FILT_OUT9
ADC2 or Filter Output Channel 9 Register
Offset
Reset Value
85H
xxxx xxxxB
7
0
ADC2_OUT_CH9
r
Field
Bits
Type
Description
ADC2_OUT_CH9
7:0
r
ADC2 raw data or filter output value channel 9
For ADC2 results without calibration set
ADC2_FILTUP_9_EN = 0
User’s Manual
537
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
22.1.1.5
Signal Processing
up/down counter
(integrator)
Upper Ch. X
comparator
comparator
FILTUP_X_EN
STH_ UP_CHX
8
0
1
+
1
Calib_Raw_Data 8
8
2
TH_UP_CHX
EX
OR
IIR _Data
8
8
1
TH_LO_CHX
±1
reset
8
8
=
1
CNT_UP_
CHX
S
R
UP_X_STS
=
0
HYST_UP_CHX
STH _LO_ CHX
1
+
8
3 to 8
DEC
MMODE_UV
FILTLO_X_EN
0
CNT_UP_
CHX
stop (+1)
2
EX
OR
CNT_LO_
CHX
stop (+1)
3 to 8
DEC
±1
reset
8
1
=
CNT_LO_
CHX
0
MMODE_OV
8
S
LO_X_STS
R
=
HYST_LO_CHX
Postprocessing
Lower Ch. X
Figure 150 Postprocessing channel block diagram for voltage and temperature measurements
As shown in Figure 150 an adjustable IIR filter can be applied to the upper and the lower measurement channel,
which averages 2, 4, 8 or 16 measurement values continuously. The filtered signal or the demultiplexed ADC
output signal ADC2_OUT_CHx is compared with an upper threshold ADC2_TH_UP_CHx and a lower threshold
ADC2_TH_LO_CHx. When the thresholds are exceeded the comparator outputs get active. Thus, for the under/overvoltage measurement mode (MMODE UV/OV= ’1’) of the upper and lower segment, a freely adjustable
hysteresis can be defined. In any of these cases the ADC2_HYST_UP_CHx and ADC2_HYST_LO_CHx values
must be set to ’0’. For the independent 2-level measurement mode (MMODE_UV/OV = ’0’) certain hysteresis
values can be set by ADC2_HYST_UP_CHx and ADC2_HYST_LO_CHx instead.
In addition to the first filter stage, the second filters acting as pulse counters and thus integrate the comparator
output values SADC2_TH_UP_CHx/ADC2_TH_LO_CHx until an individual upper and lower timing threshold
2ADC2_CNT_UP_CHx/ADC2_CNT_LO_CHx is reached. When reaching the upper timing threshold 2ADC2_CNT_UP_CHx, the upper
counter increment is stalled and the status output ADC2_UP_x_STS is set. For MMODE_OV = 1, the inverted
lower comparator output signal SADC2_TH_LO_CHx is normalized again. When the output signal is above
ADC2_TH_LO_CHx, the lower counter is incremented until the max. threshold 2ADC2_CNT_LO_CHx is reached.
Individual interrupts for the upper and lower channel can be triggered with the rising edge of the status signals
ADC2_UP_x_STS/ADC_2LO_x_STS.
In general the IIR filter stage suppresses higher frequency noise effectivly and the triggering with the upper and
lower threshold ADC2_TH_UP_CHx/ADC2_TH_LO_CHx is depending on the measured values. Hence short
high-level spikes might pass the thresholds. In opposite to the first stage, the second filter stage has in addition
the charecterisitc of a time filter, which is less dependent on the measurement value but on event duration of
SADC2_TH_LO_CHx/ADC2_TH_UP_CHx, as generated by the first comparator stage. Therefore the second stage has a lower
noise suppression performance for higher frequencies and also adds a delay for the trigger time proportional to
2ADC2_CNT_LO_CHx/ADC2_CNT_UP_CHx.
User’s Manual
538
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
a) MMODE_OV/UV = 0 (range control)
filters/counter disabled
ADC_OUT
(VBAT)
overvoltage
detection
ADC2_TH_UP_CH_x
undervoltage
detection
HYST_UP > 0
HYST_LO > 0
ADC2_TH_LO_CH_x
time
ADC2_LO_x_STS
time
ADC2_UP_x_STS
time
b) MMODE_OV = 1 (overvoltage mode)
filters/counter disabled
ADC_OUT
(TEMP)
ADC2_TH_UP_CH_x
level 2
detection
level 1
detection
HYST > 0
ADC2_TH_LO_CH_x
time
ADC2_LO_x_STS
time
ADC2_UP_x_STS
time
c) MMODE_UV = 1 (undervoltage mode)
filters/counter disabled
ADC_OUT
(VBAT)
ADC2_TH_UP_CH_x
level 1
detection
level 2
detection
ADC2_TH_LO_CH_x
HYST > 0
time
ADC2_LO_x_STS
time
ADC2_UP_x_STS
time
Figure 151 Measurement examples of a measurement channel with disabled filters
Figure 151 shows three examples, an over- and undervoltage detection (e.g. VBAT_SENSE monitoring), a 2-step
overvoltage and a 2-step undervoltage detection. The modes MMODE_OV/UV = 1 can be used as prewarning for
the application software (e.g. close to over-temperature or supply undervoltage).
User’s Manual
539
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
22.1.1.5.1
Postprocessing Control Registers
The following registers control the signal posprocessing for the generation of the status flags inside SCU_PM
Module.
Table 95
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Postprocessing Control Registers,
ADC2_TH0_UPPER
Upper Comparator Trigger Level Channel 0
Register
46H
1110 1010B
ADC2_TH1_UPPER
Upper Comparator Trigger Level Channel 1
Register
47H
1111 1101B
ADC2_TH2_UPPER
Upper Comparator Trigger Level Channel 2
Register
48H
1110 0100B
ADC2_TH3_UPPER
Upper Comparator Trigger Level Channel 3
Register
49H
1110 0100B
ADC2_TH4_UPPER
Upper Comparator Trigger Level Channel 4
Register
4AH
1000 0110B
ADC2_CNT0_UPPER
Upper Counter Trigger Level Channel 0 Register
4EH
0001 1010B
ADC2_CNT1_UPPER
Upper Counter Trigger Level Channel 1 Register
4FH
0001 1011B
ADC2_CNT2_UPPER
Upper Counter Trigger Level Channel 2 Register
50H
0001 0011B
ADC2_CNT3_UPPER
Upper Counter Trigger Level Channel 3 Register
51H
0001 0010B
ADC2_CNT4_UPPER
Upper Counter Trigger Level Channel 4 Register
52H
0001 0010B
ADC2_TH0_LOWER
Lower Comparator Trigger Level Channel 0
Register
56H
0100 1110B
ADC2_TH1_LOWER
Lower Comparator Trigger Level Channel 1
57H
0100 0111B
ADC2_TH2_LOWER
Lower Comparator Trigger Level Channel 2
Register
58H
1011 1011B
ADC2_TH3_LOWER
Lower Comparator Trigger Level Channel 3
Register
59H
1011 1001B
ADC2_TH4_LOWER
Lower Comparator Trigger Level Channel 4
Register
5AH
0111 1001B
ADC2_CNT0_LOWER
Lower Counter Trigger Level Channel 0 Register
5EH
0001 0010B
ADC2_CNT1_LOWER
Lower Counter Trigger Level Channel 1 Register
5FH
0001 0011B
ADC2_CNT2_LOWER
Lower Counter Trigger Level Channel 2 Register
60H
0001 0011B
ADC2_CNT3_LOWER
Lower Counter Trigger Level Channel 3 Register
61H
0001 0010B
ADC2_CNT4_LOWER
Lower Counter Trigger Level Channel 4 Register
62H
0000 1010B
ADC2_MMODE0_3
Overvoltage Measurement Mode of Channel 0-3
Register
6CH
0000 0000B
ADC2_MMODE4_5
Overvoltage Measurement Mode of Channel 4-5
Register
6DH
0000 1000B
ADC2_TH5_UPPER
Upper Comparator Trigger Level Channel 5
Register
89H
0011 1111B
User’s Manual
540
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Table 95
Register Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Reset Value
ADC2_TH8_UPPER
Upper Comparator Trigger Level Channel 8
Register
8CH
1100 0110B
ADC2_TH9_UPPER
Upper Comparator Trigger Level Channel 9
Register
8DH
1101 0010B
ADC2_CNT5_UPPER
Upper Counter Trigger Level Channel 5 Register
91H
0001 0010B
ADC2_CNT8_UPPER
Upper Counter Trigger Level Channel 8 Register
94H
0001 1010B
ADC2_CNT9_UPPER
Upper Counter Trigger Level Channel 9 Register
95H
0001 1010B
ADC2_TH5_LOWER
Lower Comparator Trigger Level Channel 5
Register
9AH
0011 0010B
ADC2_TH6_LOWER
Lower Comparator Trigger Level Channel 6
Register
9BH
0011 1001B
ADC2_TH7_LOWER
Lower Comparator Trigger Level Channel 7
Register
9CH
0011 1001B
ADC2_TH8_LOWER
Lower Comparator Trigger Level Channel 8
Register
9DH
1011 1010B
ADC2_TH9_LOWER
Lower Comparator Trigger Level Channel 9
Register
9EH
1100 0110B
ADC2_CNT5_LOWER
Lower Counter Trigger Level Channel 5 Register
A2H
0000 1010B
ADC2_CNT6_LOWER
Lower Counter Trigger Level Channel 6 Register
A3H
0000 1010B
ADC2_CNT7_LOWER
Lower Counter Trigger Level Channel 7 Register
A4H
0000 1010B
ADC2_CNT8_LOWER
Lower Counter Trigger Level Channel 8 Register
A5H
0000 1010B
ADC2_CNT9_LOWER
Lower Counter Trigger Level Channel 9 Register
A6H
0000 1010B
The registers are addressed bytewise.
Overvoltage Measurement Mode of Channnel 0-3 Register
The register is reset by RESET_TYPE_4.
ADC2_MMODE0_3
Overvoltage Measurement Mode of Channel
0-3 Register
7
6
5
Offset
Reset Value
6CH
0000 0000B
4
3
2
1
0
ADC2_MMODE_3
ADC2_MMODE_2
ADC2_MMODE_1
ADC2_MMODE_0
rw
rw
rw
rw
User’s Manual
541
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Field
Bits
Type
Description
ADC2_MMODE_3
7:6
rw
Measurement mode ch 3
00B MMODE0 upper & lower voltage/limit measurement
01B MMODEUV undervoltage/-limit measurement
10B MMODEOV overvoltage/-limit measurement
11B RESERVED reserved
ADC2_MMODE_2
5:4
rw
Measurement mode ch 2
00B MMODE0 upper & lower voltage/limit measurement
01B MMODEUV undervoltage/-limit measurement
10B MMODEOV overvoltage/-limit measurement
11B RESERVED reserved
ADC2_MMODE_1
3:2
rw
Measurement mode ch 1
00B MMODE0 upper & lower voltage/limit measurement
01B MMODEUV undervoltage/-limit measurement
10B MMODEOV overvoltage/-limit measurement
11B RESERVED reserved
ADC2_MMODE_0
1:0
rw
Measurement mode ch 0
00B MMODE0 upper & lower voltage/limit measurement
01B MMODEUV undervoltage/-limit measurement
10B MMODEOV overvoltage/-limit measurement
11B RESERVED reserved
User’s Manual
542
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Overvoltage Measurement Mode of Channel 4-5 Register
The register is reset by RESET_TYPE_4.
ADC2_MMODE4_5
Overvoltage Measurement Mode of Channel
4-5 Register
7
Offset
Reset Value
6DH
0000 1000B
4
3
2
1
0
RES
ADC2_MMODE_5
ADC2_MMODE_4
r
rw
rw
Field
Bits
Type
Description
RES
7:4
r
Reserved
Always read as 0
ADC2_MMODE_5
3:2
rw
Measurement mode ch 5
00B MMODE0 upper & lower voltage/limit measurement
01B MMODEUV undervoltage/-limit measurement
10B MMODEOV overvoltage/-limit measurement
11B RESERVED reserved
ADC2_MMODE_4
1:0
rw
Measurement mode ch 4
00B MMODE0 upper & lower voltage/limit measurement
01B MMODEUV undervoltage/-limit measurement
10B MMODEOV overvoltage/-limit measurement
11B RESERVED reserved
User’s Manual
543
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Upper Comparator Trigger Level Channel 0 Register
The register is reset by RESET_TYPE_4.
ADC2_TH0_UPPER
Upper Comparator Trigger Level Channel 0
Register
Offset
Reset Value
46H
1110 1010B
7
0
ADC2_TH_UP_CH0
rw
Field
Bits
Type
Description
ADC2_TH_UP_CH0
7:0
rw
Channel 0 upper trigger level
00H min. threshold value = 0
FFH max. threshold value = 255
Upper Comparator Trigger Level Channel 1 Register
The register is reset by RESET_TYPE_4.
ADC2_TH1_UPPER
Upper Comparator Trigger Level Channel 1
Register
Offset
Reset Value
47H
1111 1101B
7
0
ADC2_TH_UP_CH1
rw
Field
Bits
Type
Description
ADC2_TH_UP_CH1
7:0
rw
Channel 1 upper trigger level
00H min. threshold value = 0
FFH max. threshold value = 255
User’s Manual
544
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Upper Comparator Trigger Level Channel 2 Register
The register is reset by RESET_TYPE_4.
ADC2_TH2_UPPER
Upper Comparator Trigger Level Channel 2
Register
Offset
Reset Value
48H
1110 0100B
7
0
ADC2_TH_UP_CH2
rw
Field
Bits
Type
Description
ADC2_TH_UP_CH2
7:0
rw
Channel 2 upper trigger level
00H min. threshold value = 0
FFH max. threshold value = 255
Upper Comparator Trigger Level Channel 3 Register
The register is reset by RESET_TYPE_4.
ADC2_TH3_UPPER
Upper Comparator Trigger Level Channel 3
Register
Offset
Reset Value
49H
1110 0100B
7
0
ADC2_TH_UP_CH3
rw
Field
Bits
Type
Description
ADC2_TH_UP_CH3
7:0
rw
Channel 3 upper trigger level
00H min. threshold value = 0
FFH max. threshold value = 255
User’s Manual
545
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Upper Comparator Trigger Level Channel 4 Register
The register is reset by RESET_TYPE_4.
ADC2_TH4_UPPER
Upper Comparator Trigger Level Channel 4
Register
Offset
Reset Value
4AH
1000 0110B
7
0
ADC2_TH_UP_CH4
rw
Field
Bits
Type
Description
ADC2_TH_UP_CH4
7:0
rw
Channel 4 upper trigger level
00H min. threshold value = 0
FFH max. threshold value = 255
Upper Comparator Trigger Level Channel 5 Register
The register is reset by RESET_TYPE_4.
ADC2_TH5_UPPER
Upper Comparator Trigger Level Channel 5
Register
Offset
Reset Value
89H
0011 1111B
7
0
ADC2_TH_UP_CH5
rw
Field
Bits
Type
Description
ADC2_TH_UP_CH5
7:0
rw
Channel 5 upper trigger level
00H min. threshold value = 0
FFH max. threshold value = 255
Upper Comparator Trigger Level Channel 8 Register
The register is reset by RESET_TYPE_4.
ADC2_TH8_UPPER
Offset
Reset Value
Upper Comparator Trigger Level Channel 8
Register
8CH
1100 0110B
User’s Manual
546
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
7
0
ADC2_TH_UP_CH8
rw
Field
Bits
Type
Description
ADC2_TH_UP_CH8
7:0
rw
Channel 8 upper trigger level
00H
min. threshold value = 0
FFH max. threshold value = 255
Upper Comparator Trigger Level Channel 9 Register
The register is reset by RESET_TYPE_4.
ADC2_TH9_UPPER
Upper Comparator Trigger Level Channel 9
Register
Offset
Reset Value
8DH
1101 0010B
7
0
ADC2_TH_UP_CH9
rw
Field
Bits
Type
Description
ADC2_TH_UP_CH9
7:0
rw
Channel 9 upper trigger level
00H
min. threshold value = 0
FFH max. threshold value = 255
User’s Manual
547
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Upper Counter Trigger Level Channel 0 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT0_UPPER
Upper Counter Trigger Level Channel 0
Register
7
5
Offset
Reset Value
4EH
0001 1010B
4
3
2
0
RES
ADC2_HYST_UP_
CH0
ADC2_CNT_UP_CH0
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_UP_CH0
4:3
rw
Channel 0 upper hysteresis
0H
HYSTOFF hysteresis switched off
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_UP_CH0
2:0
rw
Upper timer trigger threshold channel 0
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
User’s Manual
548
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Upper Counter Trigger Level Channel 1 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT1_UPPER
Upper Counter Trigger Level Channel 1
Register
7
5
Offset
Reset Value
4FH
0001 1011B
4
3
2
0
RES
ADC2_HYST_UP_
CH1
ADC2_CNT_UP_CH1
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_UP_CH1
4:3
rw
Channel 1 upper hysteresis
0H
HYSTOFF hysteresis switched off
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_UP_CH1
2:0
rw
Upper timer trigger threshold channel 1
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
User’s Manual
549
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Upper Counter Trigger Level Channel 2 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT2_UPPER
Upper Counter Trigger Level Channel 2
Register
7
5
Offset
Reset Value
50H
0001 0011B
4
3
2
0
RES
ADC2_HYST_UP_
CH2
ADC2_CNT_UP_CH2
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_UP_CH2
4:3
rw
Channel 2 upper hysteresis
0H
HYSTOFF hysteresis switched off
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_UP_CH2
2:0
rw
Upper timer trigger threshold channel 2
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
User’s Manual
550
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Upper Counter Trigger Level Channel 3 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT3_UPPER
Upper Counter Trigger Level Channel 3
Register
7
5
Offset
Reset Value
51H
0001 0010B
4
3
2
0
RES
ADC2_HYST_UP_
CH3
ADC2_CNT_UP_CH3
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_UP_CH3
4:3
rw
Channel 3 upper hysteresis
0H
HYSTOFF hysteresis switched off
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_UP_CH3
2:0
rw
Upper timer trigger threshold channel 3
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
User’s Manual
551
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Upper Counter Trigger Level Channel 4 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT4_UPPER
Upper Counter Trigger Level Channel 4
Register
7
5
Offset
Reset Value
52H
0001 0010B
4
3
2
0
RES
ADC2_HYST_UP_
CH4
ADC2_CNT_UP_CH4
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_UP_CH4
4:3
rw
Channel 4 upper hysteresis
0H
HYSTOFF hysteresis switched off
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_UP_CH4
2:0
rw
Upper timer trigger threshold channel 4
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
User’s Manual
552
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Upper Counter Trigger Level Channel 5 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT5_UPPER
Upper Counter Trigger Level Channel 5
Register
7
5
Offset
Reset Value
91H
0001 0010B
4
3
2
0
RES
ADC2_HYST_UP_
CH5
ADC2_CNT_UP_CH5
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_UP_CH5
4:3
rw
Channel 5 upper hysteresis
0H
HYSTOFF hysteresis switched off
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_UP_CH5
2:0
rw
Upper timer trigger threshold channel 5
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
User’s Manual
553
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Upper Counter Trigger Level Channel 8 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT8_UPPER
Upper Counter Trigger Level Channel 8
Register
7
5
Offset
Reset Value
94H
0001 1010B
4
3
2
0
RES
ADC2_HYST_UP_
CH8
ADC2_CNT_UP_CH8
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_UP_CH8
4:3
rw
Channel 8 upper hysteresis
0H
HYSTOFF hysteresis switched off
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_UP_CH8
2:0
rw
Upper timer trigger threshold channel 8
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
User’s Manual
554
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Upper Counter Trigger Level Channel 9 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT9_UPPER
Upper Counter Trigger Level Channel 9
Register
7
5
Offset
Reset Value
95H
0001 1010B
4
3
2
0
RES
ADC2_HYST_UP_
CH9
ADC2_CNT_UP_CH9
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_UP_CH9
4:3
rw
Channel 9 upper hysteresis
0H
HYSTOFF hysteresis switched off
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_UP_CH9
2:0
rw
Upper timer trigger threshold channel 9
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
User’s Manual
555
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Lower Comparator Trigger Level Channel 0 Register
The register is reset by RESET_TYPE_4.
ADC2_TH0_LOWER
Lower Comparator Trigger Level Channel 0
Register
Offset
Reset Value
56H
0100 1110B
7
0
ADC2_TH_LO_CH0
rw
Field
Bits
Type
Description
ADC2_TH_LO_CH0
7:0
rw
Channel 0 lower trigger level
00H
Min. threshold value
FFH Max. threshold value
Lower Comparator Trigger Level Channel 1
The register is reset by RESET_TYPE_4.
ADC2_TH1_LOWER
Lower Comparator Trigger Level Channel 1
Offset
Reset Value
57H
0100 0111B
7
0
ADC2_TH_LO_CH1
rw
Field
Bits
Type
Description
ADC2_TH_LO_CH1
7:0
rw
Channel 1 lower trigger level
00H
Min. threshold value
FFH Max. threshold value
User’s Manual
556
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Lower Comparator Trigger Level Channel 2 Register
The register is reset by RESET_TYPE_4.
ADC2_TH2_LOWER
Lower Comparator Trigger Level Channel 2
Register
Offset
Reset Value
58H
1011 1011B
7
0
ADC2_TH_LO_CH2
rw
Field
Bits
Type
Description
ADC2_TH_LO_CH2
7:0
rw
Channel 2 lower trigger level
00H
Min. threshold value
FFH Max. threshold value
Lower Comparator Trigger Level Channel 3 Register
The register is reset by RESET_TYPE_4.
ADC2_TH3_LOWER
Lower Comparator Trigger Level Channel 3
Register
Offset
Reset Value
59H
1011 1001B
7
0
ADC2_TH_LO_CH3
rw
Field
Bits
Type
Description
ADC2_TH_LO_CH3
7:0
rw
Channel 3 lower trigger level
00H
Min. threshold value
FFH Max. threshold value
User’s Manual
557
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Lower Comparator Trigger Level Channel 4 Register
The register is reset by RESET_TYPE_4.
ADC2_TH4_LOWER
Lower Comparator Trigger Level Channel 4
Register
Offset
Reset Value
5AH
0111 1001B
7
0
ADC2_TH_LO_CH4
rw
Field
Bits
Type
Description
ADC2_TH_LO_CH4
7:0
rw
Channel 4 lower trigger level
00H
Min. threshold value
FFH Max. threshold value
Lower Comparator Trigger Level Channel 5 Register
The register is reset by RESET_TYPE_4.
ADC2_TH5_LOWER
Lower Comparator Trigger Level Channel 5
Register
Offset
Reset Value
9AH
0011 0010B
7
0
ADC2_TH_LO_CH5
rw
Field
Bits
Type
Description
ADC2_TH_LO_CH5
7:0
rw
Channel 5 lower trigger level
00H
Min. threshold value
FFH Max. threshold value
User’s Manual
558
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Lower Comparator Trigger Level Channel 6 Register
The register is reset by RESET_TYPE_4.
ADC2_TH6_LOWER
Lower Comparator Trigger Level Channel 6
Register
Offset
Reset Value
9BH
0011 1001B
7
0
ADC2_TH_LO_CH6
rw
Field
Bits
Type
Description
ADC2_TH_LO_CH6
7:0
rw
Channel 6 lower trigger level
00H
Min. threshold value
FFH Max. threshold value
Lower Comparator Trigger Level Channel 7 Register
The register is reset by RESET_TYPE_4.
ADC2_TH7_LOWER
Lower Comparator Trigger Level Channel 7
Register
Offset
Reset Value
9CH
0011 1001B
7
0
ADC2_TH_LO_CH7
rw
Field
Bits
Type
Description
ADC2_TH_LO_CH7
7:0
rw
Channel 7 lower trigger level
00H
Min. threshold value
FFH Max. threshold value
Lower Comparator Trigger Level Channel 8 Register
The register is reset by RESET_TYPE_4.
ADC2_TH8_LOWER
Offset
Reset Value
Lower Comparator Trigger Level Channel 8
Register
9DH
1011 1010B
User’s Manual
559
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
7
0
ADC2_TH_LO_CH8
rw
Field
Bits
Type
Description
ADC2_TH_LO_CH8
7:0
rw
Channel 8 lower trigger level
00H
Min. threshold value
FFH Max. threshold value
Lower Comparator Trigger Level Channel 9 Register
The register is reset by RESET_TYPE_4.
ADC2_TH9_LOWER
Lower Comparator Trigger Level Channel 9
Register
Offset
Reset Value
9EH
1100 0110B
7
0
ADC2_TH_LO_CH9
rw
Field
Bits
Type
Description
ADC2_TH_LO_CH9
7:0
rw
Channel 9 lower trigger level
00H
Min. threshold value
FFH Max. threshold value
User’s Manual
560
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Lower Counter Trigger Level Channel 0 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT0_LOWER
Lower Counter Trigger Level Channel 0
Register
7
5
Offset
Reset Value
5EH
0001 0010B
4
3
2
0
RES
ADC2_HYST_LO_
CH0
ADC2_CNT_LO_CH0
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_LO_CH0
4:3
rw
Channel 0 lower hysteresis
Clock cycles
HYSTOFF hysteresis switched off
0H
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_LO_CH0
2:0
rw
Lower timer trigger threshold channel 0
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
User’s Manual
561
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Lower Counter Trigger Level Channel 1 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT1_LOWER
Lower Counter Trigger Level Channel 1
Register
7
5
Offset
Reset Value
5FH
0001 0011B
4
3
2
0
RES
ADC2_HYST_LO_
CH1
ADC2_CNT_LO_CH1
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_LO_CH1
4:3
rw
Channel 1 lower hysteresis
Clock cycles
HYSTOFF hysteresis switched off
0H
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_LO_CH1
2:0
rw
Lower timer trigger threshold channel 1
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
User’s Manual
562
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Lower Counter Trigger Level Channel 2 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT2_LOWER
Lower Counter Trigger Level Channel 2
Register
7
5
Offset
Reset Value
60H
0001 0011B
4
3
2
0
RES
ADC2_HYST_LO_
CH2
ADC2_CNT_LO_CH2
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_LO_CH2
4:3
rw
Channel 2 lower hysteresis
Clock cycles
HYSTOFF hysteresis switched off
0H
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_LO_CH2
2:0
rw
Lower timer trigger threshold channel 2
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
User’s Manual
563
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Lower Counter Trigger Level Channel 3 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT3_LOWER
Lower Counter Trigger Level Channel 3
Register
7
5
Offset
Reset Value
61H
0001 0010B
4
3
2
0
RES
ADC2_HYST_LO_
CH3
ADC2_CNT_LO_CH3
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_LO_CH3
4:3
rw
Channel 3 lower hysteresis
Clock cycles
HYSTOFF hysteresis switched off
0H
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_LO_CH3
2:0
rw
Lower timer trigger threshold channel 3
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
User’s Manual
564
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Lower Counter Trigger Level Channel 4 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT4_LOWER
Lower Counter Trigger Level Channel 4
Register
7
5
Offset
Reset Value
62H
0000 1010B
4
3
2
0
RES
ADC2_HYST_LO_
CH4
ADC2_CNT_LO_CH4
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_LO_CH4
4:3
rw
Channel 4 lower hysteresis
Clock cycles
HYSTOFF hysteresis switched off
0H
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_LO_CH4
2:0
rw
Lower timer trigger threshold channel 4
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
User’s Manual
565
Rev. 1.0, 2011-12-23
TLE983x
Measurement Core Module - ADC2
Lower Counter Trigger Level Channel 5 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT5_LOWER
Lower Counter Trigger Level Channel 5
Register
7
5
Offset
Reset Value
A2H
0000 1010B
4
3
2
0
RES
ADC2_HYST_LO_
CH5
ADC2_CNT_LO_CH5
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_LO_CH5
4:3
rw
Channel 5 lower hysteresis
Clock cycles
HYSTOFF hysteresis switched off
0H
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_LO_CH5
2:0
rw
Lower timer trigger threshold channel 5
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
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Lower Counter Trigger Level Channel 6 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT6_LOWER
Lower Counter Trigger Level Channel 6
Register
7
5
Offset
Reset Value
A3H
0000 1010B
4
3
2
0
RES
ADC2_HYST_LO_
CH6
ADC2_CNT_LO_CH6
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_LO_CH6
4:3
rw
Channel 6 lower hysteresis
Clock cycles
HYSTOFF hysteresis switched off
0H
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_LO_CH6
2:0
rw
Lower timer trigger threshold channel 6
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
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Lower Counter Trigger Level Channel 7 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT7_LOWER
Lower Counter Trigger Level Channel 7
Register
7
5
Offset
Reset Value
A4H
0000 1010B
4
3
2
0
RES
ADC2_HYST_LO_
CH7
ADC2_CNT_LO_CH7
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_LO_CH7
4:3
rw
Channel 7 lower hysteresis
Clock cycles
HYSTOFF hysteresis switched off
0H
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_LO_CH7
2:0
rw
Lower timer trigger threshold channel 7
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
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Lower Counter Trigger Level Channel 8 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT8_LOWER
Lower Counter Trigger Level Channel 8
Register
7
5
Offset
Reset Value
A5H
0000 1010B
4
3
2
0
RES
ADC2_HYST_LO_
CH8
ADC2_CNT_LO_CH8
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_LO_CH8
4:3
rw
Channel 8 lower hysteresis
Clock cycles
HYSTOFF hysteresis switched off
0H
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_LO_CH8
2:0
rw
Lower timer trigger threshold channel 8
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
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Lower Counter Trigger Level Channel 9 Register
The register is reset by RESET_TYPE_4.
ADC2_CNT9_LOWER
Lower Counter Trigger Level Channel 9
Register
7
5
Offset
Reset Value
A6H
0000 1010B
4
3
2
0
RES
ADC2_HYST_LO_
CH9
ADC2_CNT_LO_CH9
r
rw
rw
Field
Bits
Type
Description
RES
7:5
r
Reserved
Always read as 0
ADC2_HYST_LO_CH9
4:3
rw
Channel 9 lower hysteresis
Clock cycles
HYSTOFF hysteresis switched off
0H
HYST4 hysteresis = 4
1H
HYST8 hysteresis = 8
2H
HYST16 hysteresis = 16
3H
ADC2_CNT_LO_CH9
2:0
rw
Lower timer trigger threshold channel 9
0H
1 clock cycle
2 clock cycles
1H
4 clock cycles
2H
8 clock cycles
3H
16 clock cycles
4H
32 clock cycles
5H
64 clock cycles
6H
128 clock cycles
7H
22.1.1.6
Start-up behavior after reset
After the end of a reset phase the measurement sources and the post-processing units need some time for
settling. In order to avoid undesired triggering of interrupts until the measurement signal acquisition is in a steady
state, the status signals are forced to zero during the start-up phase.
The end of the start-up phase is indicated by the ready signal MCM_RDY.
Measurement Core start-up procedure:
the start-up time of the complete signal chain is ~ 90 us @ 24 MHz (2180 ADC clock cycles). For the start-up
procedure the IIR-filter coefficients are set to a = 0.5 (fastest response time).
Note: at the end of the start-up phase some of the channel filters are not completely settled in order to
achieve a sufficiently short duration of the start-up phase.
22.1.1.7
Measurement Core response time
The response time Tresp of the postprocessing channels depends on the following settings:
•
Channel sequence
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•
•
•
•
IIR filter coefficients
Counter threshold
ADC sampling time
ADC conversion latency
In this context Tresp is defined as the delay between a voltage step at the ADC multiplexer input and the change of
a status output signal at a defined threshold value.
The channel sequence determines the (average) measurement rate fmeas,n=1/Tmeas,n of a postprocessing channel,
where Tmeas,n is the (average) time between two measurements of the same channel. Using the periodicity
definition of Equation (21) Tmeas,n becomes:
(
Tmeas,n = Nmeas,n ⋅ Tconv +Tsamp
)
(28)
Tconv denotes the conversion time of the ADC and Tsamp the sampling time.
For measurements requiring short response times it has to be taken into account that the channel sequencing
involves a sampling time uncertainty, which equals 0 to Tmeas,n.
The response time of the MTA-filter and the counter-filter can be defined as TMTA = FILTLEN_CHX × Tmeas,n and
TCNT = CNT_CHX × Tmeas,n, respectively.
The overall response time is calculated by adding up all the previously defined delay times:
(
)
Tresp,n = Nmeas,n ⋅(FILTLEN,n +CNT,n )⋅ Tconv +Tsamp +Tuncertain +Tlatency
(29)
It is important to consider that channel 6-9 are internal channels and as a consequence they cannot be
programmed in the sequencer.
DPP-Unit
Tsamp2 + Tconv2 =(k+10)* Tmi_clk ; default setting k=2; extended sampling times with factor k= 3,4,6 using the XSFR
register ADC_SAMPLE_TIME
Tlatency = 0 µs
Tuncertain = 0...Tmeas,n
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22.1.1.8
Response time calculation example
The following example shows the response time calculation of the over-current detection signal path for the
lowside switch (unit 2, channels 0/1):
Nmeas=4;
Tmi_clk = 41.6 ns (fmi_clk=24 MHz);
Tsamp2 + Tconv2 = (2+10)* Tmi_clk=0.5µs
CNT=4;
FILTLEN=4;
Example for Step response time calculation: Tresp = 4*(4+4)*0.5 µs + 0...2 µs = 16...18 µs
22.1.1.9
Postprocessing Default Values
The following table shows the assigned measurements of the particular channels and the reset default values
which read from FW during power-up. Since the channels 6-9 of the unit are exclusively used for internal
measurements, they can only be partly accessed by the application software.
Table 96
Channel allocation and postprocessing default settings (effective after reset)
Hysteresis 3)
IIR - Filter 4) Counters
60H
2H (8)
2H (8)
19 V
F3H
3H (16)
6.5 V
53H
2H (8)
18 V
E6H
3H (16)
4.5 V
BBH
2H (8)
5.5 V
E4H
2H (8)
1.35 V
D2H
2H (8)
1.6 V
F9H
2H (8)
Channel /
MMODE 1)
Analog Digital
Ch. 0 / 0H
VBAT_SENSE
7.5 V
Ch. 1 / 0H
VS
Ch. 2 / 0H
VDDP
Ch. 3 / 0H
VDDC
Ch. 6/ 2H
LS1_CS
Ch. 7/ 2H
LS2_CS
2)
V
H
(8)
V
H
(8)
V
H
(8)
V
H
(8)
H
H
(16)
H
H
(16)
Ch. 8/ 2H
TEMP1
V
User’s Manual
Functional Description
5)
2H (8)
2H (8)
2H (8)
1H (4)
1H (4)
2H (8)
572
2H (8)
Battery voltage sense input, lower
2H (8)
upper
3H (8)
Battery supply voltage input, lower
3H (8)
upper
3H (8)
+5V port supply voltage, lower
3H (8)
Upper (UV-pre-warning threshold or
OV-warning)
2H (4)
Core supply voltage, lower
2H (4)
Upper (OV-warning)
2H (4)
Low Side switch 1 over-current prewarning, lower
2H (4)
Low Side switch 1 over-current
detection threshold, upper
2H (4)
Low Side switch 1 over-current prewarning, lower
2H (4)
Low Side switch 1 over-current
detection threshold, upper
3H (8)
On-chip central temperature sensor
operated in mode 1 (high sensitivity):
pre-warning threshold corresponds
to 125°C
4H (16)
Upper temperature threshold
corresponding to 150°C
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Table 96
Channel allocation and postprocessing default settings (effective after reset)
Channel /
MMODE 1)
Analog Digital
Ch. 9/ 2H
TEMP_LS
V
H
H
(8)
V
H
H
(16)
2)
Hysteresis 3)
IIR - Filter 4) Counters
Functional Description
5)
2H (8)
3H (8)
Low-side switch temperature sensor:
lower hysteresis threshold value
corresponding to approx. 150°C
3H (8)
Upper channel over-temperature
threshold corresponding to 200°C.
The hysteresis corresponds to
approximately 32°C.
1) MMODE of each channel is defined by XSFR reset values: 0H range control, 1H under-voltage mode, 2H over-voltage
mode.
2) register: ADC2_TH_LO_CHx / ADC2_TH_UP_CHx
3) register: ADC2_HYST_LO_CHx / ADC2_HYST_UP_CHx; selectable decimal values [0, 4, 8, 16]
4) register: ADC2_FILTLEN_CHx
5) register: ADC2_CNT_LO_CHx / ADC2_CNT_UP_CHx; selectable decimal values [2021...27
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23
Analog Digital Converter (ADC)
23.1
Overview
The ADC module contains several building blocks that can be defined and implemented independently from the
others. These are mainly the:
•
•
Analog input multiplexer (selecting the channel to be converted)
Analog converter stage (e.g. capacitor network and comparator as part of the AD converter)
Digital control part of the analog converter stage (control of the AD conversion itself to generate the conversion
result). The blocks listed above are in the analog part, the blocks listed below are in the digital part. The
interface in between is the Barracuda interface.
Digital data handling and conversion request part (which mechanisms trigger which conversions and what
happens with the result)
Bus interface to device-internal data bus (including interrupt control and register accesses)
analog part
analog input
0
...
analog input
n-1
digital part
AD converter
conversion
control
Barracuda
•
•
•
data (result)
handling
request
control
digital clock fADCD
analog clock fADCA
bus
interface
fBUS
ADC8_overv_blocks
Figure 152 ADC Overview of Building Blocks
23.2
Functional Features
The functional features of an ADC module can be split into two groups. One group belongs to the analog part and
the converter itself and the parameters of the conversion. The other describes the features of the digital part, such
as the start and sequencing of conversions, as well as the handling of the conversion results.
Features of the Analog Part
•
•
•
•
•
•
Operating voltage range from 3 V to 5 V (5 V nominal, degradation accepted for lower voltages)
Input multiplexer width of up to 8 analog input channels
Performance requirements for 10-bit resolution (@fADCI maximum = 16.5 MHz):
– conversion time about 1 µs to 1.5 µs, TUE of 2 LSB @ operating voltage 5 V
Programmable sample time (in periods of fADCI)
Cancel feature for running conversions
Wide range of accepted analog clock frequencies fADCA and clock duty cycles (minimum high and low times)
Features of the Digital Part
•
•
•
•
Independent result registers
Different conversion request sources (e.g. external events, autoscan, programmable sequence, etc.)
Possibility to program different sampling times for the analog input channels
Possibility to cancel running conversions on demand and to restart them automatically
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Analog Digital Converter (ADC)
•
•
•
•
•
•
Modular approach for combining the different request sources (no mixed registers)
Avoid read-modify-store instructions, the program should work with move-instructions only
Flexible interrupt generation and interrupt service node assignment
Support very low system frequencies (result data must not be lost when running with fADCI = 16.5 MHz and
conversion periods of about 1 µs)
Structure must fit to different architectures (for later re-use)
Synchronous data exchange between the digital part and the analog part
23.3
Structure of Digital Part
This leads to the following structure of the digital part. It comprises:
•
•
•
•
•
•
Different conversion request sources with independent registers and a standardized interface. The request
sources are used to trigger conversions due to external events (e.g. synchronization to PWM signals, pins,
etc.), sequencing schemes, etc.
An arbiter which regularly scans the request sources to find the channel with the highest priority for the next
conversion. The priority of each source can be programmed individually to obtain the required flexibility to
cover the desired range of applications.
Control registers for each channel defining the behavior of each analog input (such as the interrupt behavior,
a pointer to a result register, etc.).
Input class register to deliver the channel control information from a centralized location (e.g. selection of
sample time).
A set of result registers (instead of one result register per analog input channel). This reduces the number of
implemented bits.
A decimation stage for conversion results, adding the incoming result to the value already stored in the targeted
result register. This stage allows fast consecutive conversions without the risk of data loss if the CPU is running
at a low clock frequency.
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23.4
Digital Part: Functional Description
The functional description of the digital part of the ADC is detailed in this section.
23.4.1
Overview
Figure 153 shows the ADC block diagram.
channel control n-1
request source s-1
.. .
. ..
arbiter
channel control 0
request source 0
input class 1
analog input n-1
.. .
analog input0
analog
part
result register r-1
. ..
data
reduct.
input class 0
result register 0
ADC8_blocks _overv
Figure 153 ADC Block Diagram
The digital part of the ADC module is scalable concerning many functionalities:
•
•
•
•
n analog inputs (here: n = 8) with n channel control registers (0 – 7)
– the channel control defines how the conversion has to be done
c input classes (here: c = 2)
– the input classes define the behavior (sample time) of the analog input
r result registers (here: r = 4)
– the result registers store the conversion results and control the data reduction
s request sources (here: s = 2)
– the request sources trigger the analog conversions
The arbiter continuously polls the request sources to find the channel that has to be converted with the highest
priority. The channel control information defines which result register is the target of the conversion result. The
control of the selected result register enables or disables the data reduction filter. The data reduction block allows
the accumulation of conversion results for anti-aliasing filtering or for averaging.
A pseudo-parallel sampling on two analog inputs is possible by converting the channels A-B-B-A in a
sequence quickly one after the other. To perform this speed-critical operation, the result register for A is configured
to store the sum of both conversions of channel A. Similarly, the result register for B is configured to store the sum
of both conversions of channel B. In addition, all four conversions must be executed without any CPU load with
one trigger event. To achieve this, a 4-stage queue (at least) for the sequential request source is required. The
CPU only has to read both result registers after the last conversion.
23.4.2
Clocking Scheme
The different parts of the ADC are driven by clock signals that are generated from a single common clock fADC,
which is the clock of the bus to which the ADC module is connected.
•
fADCD is input clock for the digital part. This clock is used for the arbiter (defines the duration of an arbitration
round) and other digital control structures (e.g., internal state machines, registers and interrupt generation).
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•
•
fADCA is input clock for the analog part.
fADCI is internal clock for the analog part (defines the time base for conversion length and sample time). This
clock is generated internally in the analog part, based on the input clock fADCA to generate a correct duty cycle
for the analog components.
In order to allow a wide range of input frequencies, the frequency fADCI is programmable. Since the internal clock
for the analog part fADCI is limited to a maximum frequency of 16.5 MHz, the ADC-clock prescaler must be
programmed to a value that ensures fADCI does not exceed 16.5 MHz. The prescaler ratio is selected by bitfield
CTC in register GLOBCTR. A larger ratio can be selected when the maximum performance of the ADC is not
required.
fADC = fBUS
fADCD
arbiter
registers
interrupts
digital part
fADCA
CTC
÷ 64
÷ 32
÷ 16
÷ 8 MUX
÷4
÷3
÷2
÷1
fADCI
analog
components
clock prescaler
analog part
Figure 154 Clocking Scheme
23.4.3
Request Source Arbiter
The arbiter block permanently polls the request sources (round-robin principle) in order to find the analog channel
that has to be converted with the highest priority. In each arbitration slot, the arbiter polls the signals of one request
source. The sum of all arbitration slots is called arbitration cycle.
Each request source has a programmable source priority, located in the arbiter. Starting with request source 0,
the arbiter checks if a request source has a pending request for a conversion. If more than one request source is
found with the same priority level and a pending conversion request, the request source that has been found first
is selected.
23.4.3.1
Arbiter Timing
The period tARB of a complete arbiter round is given as:
tARB = 4 x tADCD,
(30)
where tADCD is the period of an arbiter clock cycle and is equal to the module clock period tADC.
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23.4.3.2
Conversion Start Modes
At the end of each arbitration round, the arbiter has found the request source with the highest priority and a
pending conversion request. This arbitration result is stored for further actions.
If the analog part is idle, a conversion can be started immediately. If a conversion is currently running, the
arbitration result is compared to the priority of the currently running conversion. In the case that the current
conversion has the same or a higher priority, it is normally completed. Immediately after the completion, the next
conversion can be started. As soon as the analog part is idle and the arbiter has output a conversion request, the
conversion will be started. In the case that the new conversion request has a higher priority than a current
conversion, two different conversion start modes exist:
•
•
Wait-for-Start: In this mode, the current conversion is completed normally. The pending conversion request will
be treated immediately after the conversion is finished. The conversion start takes place as soon as possible.
Cancel-Inject-Repeat: In this mode, the current conversion is aborted immediately if a new request with a
higher priority has been found. The new conversion is started as soon as possible after the abort action. The
aborted conversion request is restored in the request source that has requested the aborted conversion. As a
result, it takes part in the next arbitration round.
The priority of an active request source (incl. pending or active conversion) must not be changed by software.
The abort will not be accepted during the last 3 clock cycles of a running conversion.
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23.4.4
Parallel Request Sources
23.4.4.1
Overview
A parallel request source generates one or more channel conversion requests in parallel. The requests are always
treated one after the other in a predefined sequence (higher channel numbers before lower channel numbers).
Each parallel request source consists of a conversion request control register and a conversion request pending
register. The contents of the conversion request control register are copied (overwrite) to the conversion request
pending register when a selected event occurs. The type of the event defines the behavior and the trigger of the
request source.
23.4.4.2
Request Pending Unit
As long as the content of the conversion pending register is not 0, the request source can take part in the source
arbitration. The bit position of the pending bit being 1 with the highest bit number is delivering the channel number
REQCHNR. In order to take part in the source arbitration, both the signals, REQCHNRV and REQPND, must be 1.
All conversion pending bits ORed together deliver an intermediate signal PND to generate REQCHNRV and
REQPND. The signal PND can be gated with an externally generated request source gating signal REQGT. The
signal REQCHNRV is generated directly by PND, see Figure 155.
data written
by CPU
conversion request control register
LDE
ENGT
0
parallel load
conversion request pending register
...
1
bitwise
set/reset
by arbiter
bitwise OR
PND
REQGT
AND
REQPND
REQCHNRV
ADC8_par_reqsrc_rpu
Figure 155 Request Pending
The bits in the conversion request pending register can be set or reset bitwise by the arbiter, according to:
•
•
Bitwise Set:
Bit x is set by the arbiter if the conversion of channel x has been requested by the source and the conversion
is aborted.
Bitwise Reset:
Bit x is reset by the arbiter if the conversion of channel x has been requested by the source and the conversion
is started.
The inputs REQGT and REQTR are synchronized to the module clock.
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23.4.4.3
Source Function Control Unit
The load event for the parallel load can be:
•
•
•
•
An external trigger at the selected input line REQTR
A write operation to a specific address of the conversion request control register
A write operation with LDEV = 1 to the request source mode register
A source internal action (e.g. autoscan = conversion finished and PND = 0)
Each bit in the conversion request control/pending registers corresponds to one analog input channel. The bit
position defines directly the channel number. The corresponding bit in the conversion request pending register is
automatically reset when the arbiter indicates the start of conversion for this channel. The bit is set again
automatically when the arbiter indicates that the conversion has been aborted. These rules apply only if the
request source has triggered the conversion.
A source interrupt can be generated (if enabled) when a conversion (requested by this source) is finished while
PND = 0.
23.4.4.4
Autoscan
The autoscan is a functionality of a parallel source. If enabled for autoscan mode, the load event takes place when
the conversion is finished while PND is 0 and RSIND = 1.
23.4.4.5
External Trigger
The synchronization to an external trigger event for a parallel source (and also a sequential source) is supported
by coupling the reload event to a request trigger input REQTR.
23.4.4.6
Software Control
The load event for a parallel source can also be generated under software control. Therefore, two different
possibilities exist.
The conversion request control register can be written at two different addresses (CRCR1 and CRPR1). Accessed
at one address, the write action only changes the bits in this register. Accessed at the other address, the load event
will take place one clock cycle after the write access. This automatic load event can be used to start conversions
with a single move operation. In this case, the information about the channels to be converted is given as argument
in the move instruction.
The second possibility is to write LDEV = 1 by software. In this case, the trigger for the load event does not contain
any information about the channels to be converted, but always takes the content of the conversion request control
register. Therefore, the conversion request control register can be written at a second address without triggering
the load event.
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Analog Digital Converter (ADC)
23.4.5
Sequential Request Sources
23.4.5.1
Overview
A sequential request source requests one conversion after the other. The amount of channels requested for
conversion depends on the length of the sequential buffer queue (number of queue stages). This number can vary
from implementation to implementation, starting at 1 (1-stage queue, only Q0R0 is available). E.g. for a 4-stage
queue, the registers Q0R0, Q1R0, Q2R0 and Q3R0 are available.
Each queue stage stores the requested channel number and some additional control information. As a result, the
order of channels to be converted is freely programmable without restrictions in the sequence. The additional
control information is used to enable the request source interrupt (when the requested channel conversion is
finished) and to enable the automatic refill process.
A sequential source consists of a certain number of queue stages, one backup stage and a mode control register.
The backup stage stores the information about the latest conversion requested after it has been aborted. If the
backup register contains an aborted request (V = 1), it is treated before the entries in the queue stages. This
implies that only the bit V in the backup register is cleared when the requested conversion is started. If the bit V in
the backup register is not set, the bit V in the queue stage 0 is reset when the requested conversion is started.
abort of
conversion
backup stage (CHNR, RF, ENSI, EXTR)
reset
start of
conversion
switch to next
queue stage
V
set
queue stage 0 (CHNR, RF, ENSI, EXTR)
V
OR
V
ADC8_seq_reqsrc_base
Figure 156 Base Structure of a Sequential Source
The request source can take part in the source arbitration if the backup stage or the queue stage 0 contains a valid
request (V = 1). The REQGT input allows additional gating with the external signal.
The inputs REQGT and REQTR are synchronized to the module clock.
While a sequential queue is enabled with the automatic refill feature activated, the software should not write data
to the source. Software can be used if the refill feature is disabled or the source is not enabled.
23.4.5.2
Multi-Stage Sequential Sources
A sequential source can contain intermediate stages storing conversion requests (q stages, numbered from 0 to
q-1). These stages can be considered as conversion request queue. Only the register queue 0 can be read, the
register of the other stages are internal.
The write address to enter a conversion request is given by the write-only queue input register QINR0. If there is
still an empty stage (V = 0) in the queue, the written value will be stored there (bit V becomes set). In the case that
a requested conversion is aborted after its start, its setting is stored in the backup register (V becomes 1).
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data written
by CPU
w
queue input register
1
queue stage q-1
V
intermediate queue stages
V
queue stage 0 (CHNR, RF, ENSI)
V
start of
conversion
abort of
conversion
backup stage (CHNR, RF, ENSI)
rh
set
reset
rh
queue stage 1
V
OR
ADC8_seq_reqsrc_flow
Figure 157 Multi-Stage Queue
If bit V of a queue stage n-1 is 0 while bit V of the stage n is 1, the content of stage n is copied to the stage n-1
and bit V of stage n is reset.
23.4.5.3
Sequential Source Control
The conversion request of a sequential source is controlled by the following mechanisms. If the conversion
requested by the source is not related to an external trigger event (EXTR = 0), the valid bit V = 1 directly requests
the conversion by setting REQPND and REQCHNRV to 1. If V = 0 in this case, no conversion will be requested.
A gating mechanism allows the user to enable/disable conversion requests according to the signal REQGT or to
ignore this signal.
CEV
requested
conversion
started
OR
w
TREV
OR
AND
set
clear
EV
w
rh
ENTR
AND
V
rw
rh
REQTR
EXTR
1
rh
0
ENGT
rw
0
00
1
01
REQGT
10
11
AND
REQPND
REQCHNRV
ADC8_seq_reqsrc_control
Figure 158 Sequential Source Control
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If the requested conversion is sensitive to an external trigger event (EXTR = 1), the signal REQTR can be taken
into account (with ENTR = 1) or the software can write TREV = 1. Both actions set the event flag EV. The event
flag EV = 1 indicates that the (external) event has taken place and a conversion can be requested (EV can be set
only if a conversion request is valid by V = 1 and EXTR = 1). In this case, the signal REQCHNRV is derived from
bit EV.
In the queue backup register, bit EXTR is always considered as 0. If a queue controlled conversion has been
started and aborted due to a higher priority conversion, the aborted conversion will be restarted without waiting for
a new trigger event.
23.4.6
Wait-for-Read Mode
The wait-for-read mode is a feature of all request sources used to allow the CPU (or other parts) to treat each
conversion result independently without the risk of data loss. The data loss can occur if the CPU does not read a
conversion result in a result register before a new result overwrites the previous one.
In wait-for-read mode, the conversion request REQPND generated by a request source for a specific channel will
be disabled if the targeted result register contains valid data (indicated by the valid flag being set). Each result
register contains a valid flag VF. The targeted result register is known from the channel register of the requested
conversion. Conversion of the requested channel will not start unless the valid flag of the targeted result register
is cleared (data is invalid). The wait-for-read mode for a result register can be enabled by setting bit WFR.
23.4.7
Conversion Start
In the last slot of the arbitration round, the arbiter has found the channel with the highest priority to be converted.
It stores the channel number, the selected sample time and the targeted result register settings. This set of data
has to be consistent during the complete conversion.
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23.4.8
Result Generation
23.4.8.1
Overview
The result generation in the digital part consists of different parts:
•
•
•
•
An interface to the analog part, delivering the result after the conversion is finished.
A limit checking unit, comparing the conversion result to two selected boundary values. An interrupt can be
generated according to the limit check result.
A data reduction filter, accumulating the conversion results. The accumulation is done by adding the new
conversion result to the value stored in the selected result register.
A set of result registers (numbering 4), storing the conversion results. The software can read the conversion
result from the result registers. The result register used to store the conversion result is selected individually
for each input channel.
analog
part
conversion
result
from channel
control
result
buffer
boundary value
add/sub
result register 0
VF
result register 1
VF
.. .
0
result register x
result path control
limit check control
data red. control
VF
channel interrupt
DRC
event interrupt
ADC8_result_path
Figure 159 Result Path
23.4.8.2
Result Path
The limit checking and the data reduction filter are based on a common adder/subtract structure. In the first step,
the incoming result is compared with BOUND0, then with BOUND1. Depending on the result flags (lower-than
compare), the limit checking unit can generate a channel interrupt. It can become active when the valid result of
the data reduction filter is stored in the selected result register.
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n
new
result in
buffer?
y
compare result with
BOUND0
BOUND0
compare result with
BOUND1
BOUND1
data reduction filter
limit checking
channel
interrupt
ADC8_result_flow
Figure 160 Conversion Result Flow
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23.4.8.3
Data Reduction Filter
Figure 161 shows a sequence with DRCTR = 01B, i.e. 2 values are accumulated.
conversion
ready
DRCTR = 1
c0
c1
c2
c3
c4
c5
c6
c7
c8
running
conversion
r0
r1
r2
r3
r4
r5
r6
r7
delivered
result
0
1
0
1
0
1
0
1
0
DRC
0
r0
r0 +
r1
r2
r2 +
r3
r4
r4 +
r5
r6
r6 +
r7
content of result register x
DRCTR = 0
valid flag for result register x
VF
0
0
0
0
0
0
0
0
0
DRC
0
r0
r1
r2
r3
r4
r5
r6
r7
content of result register x
valid flag for result register x
VF
ADC8_DRC
Figure 161 Data Reduction Flow
The data reduction filter adds the incoming result to the value already stored in the result register and decrements
the data reduction counter DRC. When DRC becomes 0 (by decrementing or reloading), a result register event
can be generated and the valid bit (VF) for the result register becomes set.
If DRC is 0 and a new conversion result comes in, DRC is reloaded with its reload value (defined by the result
register control) and the value of 0 is added to the conversion result (instead of the former result register content).
Then, the complete result is stored in the selected result register and the valid bit is set.
If DRC is not 0 and a new conversion result comes in, DRC is decremented by one and the value stored in the
selected result register is added to the conversion result. After this addition, the complete result is stored in the
selected result register, but the valid bit is not set.
This allows to have an identical cycle behavior of the path to the result register, with the data reduction filter being
enabled or disabled. Furthermore, an overflow of the result register is avoided, because a maximum of 2
conversion results are added (a 10 bit result added two times delivers a maximum of 11 bits). An example is shown
in Figure 161.
23.4.8.4
Result Register View
Conversion results (10-bit or 8-bit) are stored left-aligned in internal result registers. Two additional bits store the
overflow resulting from data accumulation (if selected). The result registers RESR[A]xH/L return different views of
the respective results (see Figure 162):
•
Standard application read view:
This view returns the standard data section, i.e. a 10-bit conversion result or an 8-bit result padded with zeros.
RESRxH returns the upper 8 bits of the result, RESRxL returns the lower bits of a 10-bit conversion and the
3-bit channel number.
If enabled by RCRx.VFCR = 1 the corresponding valid flag is cleared upon reading the high byte of the result
register.
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•
Accumulated read view:
This view returns the upper 11 bits of an accumulated conversion result, i.e. bits [10:0] if 2 values are added,
or bits [11:1] if 3 or 4 values are added. RESRAxH returns the upper 8 bits of the result, RESRAxL returns
three lower bits of the accumulated result and the 3-bit channel number.
If enabled by RCRx.VFCR = 1 the corresponding valid flag is cleared upon reading the high byte of the result
register.
Because the result value is returned left-aligned, the data reduction level (count) determines which part is
returned:
– Data reduction count 0 or 1: bits 10...0 of accumulated 11-bit result
– Data reduction count 2 or 3: bits 11...1 of accumulated 12-bit result
When the data reduction filter is disabled (DRCTR = 00B), the conversion results can be read from either
RESRxH/L or RESRAxH/L. 8-bit conversion results can be read from RESRxH with a single instruction.
Hence, depending on the application requirement, the user can choose to read from the different views.
RESRxH
11 10
9
8
7
6
5
RESRxL 0
4
3
1
0
RESRxL
RESRAxH
RESRAxH
2
RESRxL
Standard view
Internal Result
Accum. view (0/1)
Accum. view (2/3)
MC_ADC_READVIEWS
Figure 162 Result Register View
Note: 8-bit results are stored left-aligned, padded with two zero bits.
The result registers are described in Section 23.7.16.
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23.4.9
Interrupt Structure
The ADC module always provides 2 service request outputs SR[1:0], available at the module boundary. They can
be activated by different interrupt sources.
The interrupt structure of the ADC supports two different types of interrupt sources:
•
•
Channel Interrupts: Activated by the completion of any conversion of an input channel. They are enabled
according to the control bits for the limit checking. The settings are defined individually for each input channel.
Event Interrupts: Activated by events of the request sources (e.g. queue, etc.) or module internal events, such
as the result register accumulation.
request
sources
to SR0
event interrupt
unit
to SR1
interrupt
compressor
arbiter
analog
part
limit
check
unit
channel
interrupt
routing
SR0
SR1
to SR0
to SR1
ADC8_ints_overv
Figure 163 Interrupt Overview
The interrupt compressor is an OR-combination of all incoming interrupt pulses for each of the SR lines.
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23.4.9.1
Event Interrupts
event x
event 1
to SR1
event 0
to SR0
to SR0
EVINF0
interrupt
enable 0
to SR1
...
interrupt
trigger 0
AND
to SR1
to SR1
EVINP0
Figure 164 Event Interrupt Structure
The event interrupt block is connected to event generation parts of the ADC. Events can be generated by the
request sources and also by the result registers. An event is signaled by a high pulse at the corresponding event
input. The event interrupt enable bits are located in the sources or in the result register control. An interrupt node
pointer for each event allows to select the targeted service output line.
For the TLE983x, the following event interrupt triggers are supported:
Request source events:
•
•
Event 0: Request source event of the request source located in arbitration slot 0.
Event 1: Request source event of the request source located in arbitration slot 1.
Result register events:
•
•
•
•
Event 4: Result register event of the result register 0.
Event 5: Result register event of the result register 1.
Event 6: Result register event of the result register 2.
Event 7: Result register event of the result register 3.
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23.4.9.2
Channel Interrupts
The channel interrupts occur when a conversion is finished and the selected limit checking condition is met. As a
result, only one channel interrupt can be activated at a time. An interrupt can be triggered according to the limit
checking result. The conversion result is compared to two boundaries, which can be selected for each channel.
request
sources
boundaries
BOUND0
BOUND1
conversion finished
arbiter
analog
part
channel number
result
limit
check
unit
channel interrupt
trigger
channel number
channel
interrupt
routing
to SR0
to SR1
ADC8_channel_ints_overv
Figure 165 Channel Interrupt Overview
The limit checking unit selects two boundaries (BOUND0 and BOUND1) to compare values for the conversion
result. With these two boundaries, the conversion result space is split into three areas:
•
•
•
Area I: The conversion result is below both boundaries.
Area II: The conversion result is between both boundaries or is equal to one of the boundaries.
Area III: The conversion result is above both boundaries.
After a conversion has been finished, a channel interrupt can be triggered according to the following conditions
(selected by the limit check control bitfield LCC):
•
•
•
•
•
•
•
•
LCC = 000: No trigger, the channel interrupt is disabled.
LCC = 001: A channel interrupt is generated if the conversion result is not in Area I.
LCC = 010: A channel interrupt is generated if the conversion result is not in Area II.
LCC = 011: A channel interrupt is generated if the conversion result is not in Area III.
LCC = 100: A channel interrupt is always generated (regardless of the boundaries).
LCC = 101: A channel interrupt is generated if the conversion result is in Area I.
LCC = 110: A channel interrupt is generated if the conversion result is in Area II.
LCC = 111: A channel interrupt is generated if the conversion result is in Area III.
The channel specific interrupt node pointer CHINPx selects which service request output (SR[1:0]) will be
activated upon a channel interrupt trigger, see Figure 166.
channel
interrupt
trigger
CHINF1
CHINP1
CHINFx
CHINPx
to SR0
. ..
CHINP0
. ..
CHINF0
channel
number
to SR1
ADC8_channel_ints_routing
Figure 166 Channel Interrupt Routing
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23.5
TLE983x Request Sources
For the TLE983x, two request sources are available:
•
•
Source 0: 4-stage sequential source
Source 1: Parallel source
REQTR1
REQGT1
slot 1
source 1
request
arbiter
REQTR0
REQGT0
slot 0
source 0
request
ADC8_LE_sources
Figure 167 Request Sources
Each source has its own request trigger input, REQTRx, and its own request gating input, REQGTx.
ETRx0
ADC Module
ETRx1
...
rising
edge
detect
ETRx7
ETRxB
REQTRx
syn. stages
ETRxC
ETRxD
ETRSELx
SYNENx
ETSSELx
EGTx
syn. stages
REQGTx
ADC_external_trigger_gating _input
Figure 168 External Trigger and Gating Inputs
The desired request trigger input REQTRx source is selected via input multiplexers controlled by bitfields
ETRSR.ETSSELx and ETRCR.ETRSELx. It is possible to bypass the synchronization stages if the trigger request
comes synchronous to ADC. This selection can be done via bit ETRCR.SYNENx.
For the request gating inputs REQGTx, synchronization stages are available for the asynchronous gating inputs.
Control registers can be found on Page 27-598, the inputs are listed on Page 27-626.
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23.6
External Multiplexer Control
If an application requires more analog inputs channels than available on the TLE983x, external analog
multiplexers can be added to extend the number of analog channels. The three output signals EMUX[2:0] can
control 1-out-of-8 external multiplexers.
Registers EMCTR and EMENR configure the control behavior of the external multiplexers. Bitfield EMUX selects
the actual external channel. This selection can either be controlled by software (write to bitfield SETEMUX, applied
with next conversion start) or automatically by the scan function.
The external multiplexer support can be enabled for each input channel CH0 to CH7 and supports several modes
(selected in register EMENR):
•
•
•
Software control without any HW control (EMUXEN = 0):
Automatic control of the external multiplexer is disabled, bitfield EMUX is always updated by write actions to
bitfield SETEMUX. Bitfield EMSAMPLE has no effect on the sample time.
Hardware control without scan (EMUXEN = 1, SCANEN = 0):
Bitfield EMUX is updated from bitfield SETEMUX with each conversion start of the channel selected by
EMUXCHNR. Bitfield EMSAMPLE controls the sample time for the first conversion with a new EMUX value.
Hardware control with scan (EMUXEN = 1, SCANEN = 1):
Bitfield EMUX is updated after each conversion of the channel selected by EMUXCHNR. If EMUX = 0 it is
reloaded from bitfield SETEMUX, otherwise it is decremented by 1. Bitfield EMSAMPLE controls the sample
time for each conversion of the selected channel. Two multiplexer control schemes can be selected:
– Single-input scan (TROEN = 0):
An autoscan sequence converting the channel selected by EMUXCHNR leads to one conversion of the
multiplexed channel (trigger option disabled). Bitfield EMUX is update for each completed auto scan
sequence.
The scan sequence in the example (Figure 169, assuming SETEMUX = 010B) is:
4-32-2-1-0--4-31-2-1-0--4-30-2-1-0--4-32-2-1-0--...
– Multi-input scan (TROEN = 1):
When the channel selected by EMUXCHNR is converted, a new conversion request is triggered as long as
bitfield EMUX > 0. In a scan request source, this sets the corresponding pending bit. In a queued request
source, this sets the valid bit of the backup stage.
All inputs of the external multiplexer are scanned during a single autoscan sequence, beginning with the
channel selected by bitfield SETEMUX.
The scan sequence in the example (Figure 169, assuming SETEMUX = 010B) is:
4-32-31-30-2-1-0--4-32-31-30-2-1-0--...
Note: It is recommended to write the start value of the first scan sequence to SETEMUX while EMUXEN = 0.
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Analog Digital Converter (ADC)
ADC kernel
CH3
REXT1
CEXT1
CH4
External analog
8-to-1 multiplexer
REXT
CEXT
ADC
channel
control
CH30
REXT2
EMUX[2:0]
CEXT2
CH31
REXT2
CEXT2
EMUX
control
...
Extended input
signals
CEXT
Internal MUX
REXT
. ..
Direct
input signals
CH0
CH37
REXT2
CEXT2
MC_ADC_EXTMUX
Figure 169 External Analog Multiplexer Example
In the shown example, an external multiplexer is connected to channel CH3 (the additional analog inputs are
designated CH30 ...CH37).
Many applications will use buffer capacitors or even RC filters on the analog inputs. If an external multiplexer is
used, local filters are likely to be placed at its inputs (REXT2-CEXT2 on CH3x in Figure 169). For applications where
the external multiplexer is located far from the ADC analog input, it is recommended to add an RC filter directly at
the analog input of the ADC (REXT1-CEXT1 on CH3 in Figure 169).
Note: Each RC filter limits the bandwidth of the analog input signal.
The RC filters used with an external multiplexer change the impedance for the corresponding analog input
channel, compared to other channels. This can be compensated by using another input class selecting a longer
sample phase. The sample phase must be long enough to let the input signal settle.
When the external multiplexer switches (EMUX[2:0] changes), the required sample time to let the input settle is
even longer. This is automatically compensated by applying the alternative sample phase length (selected by
register EMSTR) instead of the one given by the input class for the first conversion after EMUX[2:0] has changed.
If this first conversion is aborted due to a higher priority request, the repeated conversion also uses the value of
EMSTR.
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Analog Digital Converter (ADC)
23.7
Register Summary and Description
The registers of the ADC organized into 8 pages. Therefore, offset values appear several times in the following
description. A summary can be found in Section 23.8.1.
23.7.1
Paging Mechanism
SFR ADC_PAGE, at address D1H, contains the page value and the page control information.
ADC_PAGE
Page Register for ADC
7
6
(D1H)
5
4
Reset Value: 00H
3
2
1
OP
STNR
PAGE
w
w
rwh
0
Field
Bits
Type
Description
PAGE
[3:0]
rwh
Page Bits
When written, the value indicates the new page address.
When read, the value indicates the currently active page = addr
[y:x+1]
STNR
[5:4]
w
Storage Number
This number indicates which storage bitfield is the target of the
operation defined by bit OP.
If OP = 10B,
the contents of PAGE are saved in STx before being overwritten with
the new value.
If OP = 11B,
the contents of PAGE are overwritten by the contents of STx. The
value written to the bit positions of PAGE is ignored.
00B ST0 is selected.
01B ST1 is selected.
10B ST2 is selected.
11B ST3 is selected.
OP
[7:6]
w
Operation
0XB Manual page mode. The value of STNR is ignored and PAGE
is directly written.
10B New page programming with automatic page saving. The
value written to the bit positions of PAGE is stored. In parallel,
the former contents of PAGE are saved in the storage bitfield
STx indicated by STNR.
11B Automatic restore page action. The value written to the bit
positions PAGE is ignored and instead, PAGE is overwritten by
the contents of the storage bitfield STx indicated by STNR.
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23.7.2
Global Control
The global control register contains bits for controlling the analog converter and the conversion delay.
GLOBCTR
Global Control Register
(CAH)
5
4
Reset Value: 18H
7
6
3
2
1
ANON
DW
CTC
0
rw
rw
rw
r
0
Field
Bits
Type
Description
CTC
[5:3]
w
Conversion Time Control
This bitfield defines the divider ratio for the divider stage of the
internal analog clock fADCI. This clock provides the internal time base
for the conversion and sample time calculations.
000B fADCI = fADCA
001B fADCI = 1/2 x fADCA
010B fADCI = 1/3 x fADCA
011B fADCI = 1/4 x fADCA (default)
100B fADCI = 1/8 x fADCA
101B fADCI = 1/16 x fADCA
110B fADCI = 1/32 x fADCA
111BfADCI = 1/64 x fADCA
DW
6
rw
Data Width
This bitfield defines how many bits are converted for the result.
The result is 10 bits wide (default).
0B
The result is 8 bits wide.
1B
ANON
7
rw
Analog Part Switched On
This bit enables the analog part of the ADC module and defines its
operation mode.
The analog part is switched off and conversions are not
0B
possible.
To achieve minimal power consumption, the internal analog
circuitry is in its power-down state and the generation of fADCI
is stopped.
The analog part of the ADC module is switched on and
1B
conversions are possible. The automatic power-down
capability of the analog part is disabled.
0
[3:0]
r
Reserved
Returns 0 if read; should be written with 0.
23.7.3
Global Status
The status register contains bits indicating the current status of a conversion.
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GLOBSTR
Global Status Register
7
6
(CBH)
5
4
Reset Value: 00H
3
2
1
0
0
CHNR
0
SAMPLE
BUSY
r
rh
r
rh
rh
Field
Bits
Type
Description
BUSY
0
rh
Analog Part Busy
This bit indicates that a conversion is currently active.
The analog part is idle.
0B
A conversion is currently active.
1B
SAMPLE
1
rh
Sample Phase
This bit indicates that an analog input signal is currently sampled.
The analog part is not in the sampling phase.
0B
The analog part is in the sampling phase.
1B
CHNR
[5:3]
rh
Channel Number
This bitfield indicates which analog input channel is currently
converted. This information is updated when a new conversion is
started.
0
2, [7:6]
r
Reserved
Returns 0 if read; should be written with 0.
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23.7.4
Priority and Arbitration Register
The priority and arbitration register contains bits to define the request source priority and the conversion start
mode. It also contains bits to enable/disable the conversion request treatment in the arbitration slots.
PRAR
Priority and Arbitration Register
(CCH)
Reset Value: 00H
7
6
5
4
3
2
1
0
ASEN1
ASEN0
0
ARBM
CSM1
PRIO1
CSM0
PRIO0
rw
rw
r
rw
rw
rw
rw
rw
Field
Bits
Type
Description
PRIO0
0
rw
Priority of Request Source 0
This bit defines the priority of the sequential request source 0.
Low priority
0B
High priority
1B
CSM0
1
rw
Conversion Start Mode of Request Source 0
This bit defines the conversion start mode of the sequential request
source 0.
The wait-for-start mode is selected.
0B
The cancel-inject-repeat mode is selected.
1B
PRIO1
2
rw
Priority of Request Source 1
This bit defines the priority of the parallel request source 1.
Low priority
0B
High priority
1B
CSM1
3
rw
Conversion Start Mode of Request Source 1
This bit defines the conversion start mode of the parallel request
source 1.
The wait-for-start mode is selected.
0B
The cancel-inject-repeat mode is selected.
1B
ARBM
4
rw
Arbitration Mode
This bit defines which arbitration mode is selected.
Permanent arbitration (default).
0B
Arbitration started by pending conversion request
1B
ASENx
(x = 0 - 1)
[7:6]
rw
Arbitration Slot x Enable
Each bit enables an arbitration slot of the arbiter round. ASEN0
enables arbitration slot 0, ASEN1 enables slot 1.
The corresponding arbitration slot is disabled. Conversions are
0B
not requested, pending conversion request of a request source
connected to slot x is not taken into account for arbitration. If
the arbiter shall not be running continuously (ARBM=1), no
conversion request of the request source for arbitration slot x
must be active. Clear conversion requests of the related
request source before disabling an arbitration slot.
The corresponding arbitration slot is enabled. Conversions are
1B
requested for the request source with pending request bit(s).
0
5
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
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TLE983x
Analog Digital Converter (ADC)
23.7.5
External Trigger Select/Control Registers
The external triggers can be selected from a number of sources. The external source select register selects from
several sources, the external trigger control register represents one of these sources and selects one of a group
of external trigger input signal sources. Synchronization of the external trigger input can be enabled.
For the signals that can be selected, please refer to Table 100 “ADC Trigger Interconnection” on Page 27-626.
ETRSR
External Trigger Select Register
7
6
(D2H)
5
4
Reset Value: 00H
3
2
1
0
0
ETSSEL1
0
ETSSEL0
r
rw
r
rw
Field
Bits
Type
Description
ETSSELx
(x = 0 - 1)
[1:0], [5:4]
rw
External Trigger Source Select for Req. Source x
Selects the external trigger input signal source.
00B Use the input selected by ETCTR.ETRSELx
01B Select input signal ETRxB
10B Select input signal ETRxC
11B Select input signal ETRxD
0
[3:2], [7:6]
r
Reserved
Returns 0 if read; should be written with 0
User’s Manual
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TLE983x
Analog Digital Converter (ADC)
Register ETRCR selects an input for option ETRSR.ETSSELx = 00B and control the synchronization.
ETRCR
External Trigger Control Register
5
(CFH)
4
Reset Value: 00H
7
6
3
2
1
SYNEN1
SYNEN0
ETRSEL1
ETRSEL0
rw
rw
rw
rw
0
Field
Bits
Type
Description
ETRSELx
(x = 0 - 1)
[2:0], [5:3]
rw
External Trigger Selection for Request Source x
Selects a trigger input for option ETSSELx = 00B.
000B Select input signal ETRx0
001B Select input signal ETRx1
...
111B Select input signal ETRx7
SYNENx
(x = 0 - 1)
[7:6]
rw
Synchronization Enable
0B
Synchronizing stage is not in external trigger input REQTRx
path.
Synchronizing stage is in external trigger input REQTRx path.
1B
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TLE983x
Analog Digital Converter (ADC)
23.7.6
Channel Control Registers
The channel control registers contain bits to select the targeted result register and to control the check mechanism.
The channel control register 0 defines the settings for the input channel 0, etc.
CHCTRx (x = 0 - 5)
Channel Control Register x
CHCTRx (x = 6 - 7)
Channel Control Register x
7
6
5
(CAH + x * 1)
Reset Value: 00H
(CCH + x * 1)
Reset Value: 00H
4
3
2
1
0
ICLSEL
LCC
0
0
RESRSEL
rw
rw
rw
r
rw
Field
Bits
Type
Description
RESRSEL
[1:0]
rw
Result Register Selection
Selects the target for the conversion result(s).
00B Use result register 0
01B Use result register 1
10B Use result register 2
11B Use result register 3
LCC
[6:4]
rw
Limit Check Control
This bitfield defines the behavior of the limit checking mechanism.
See coding in Section 23.4.9.2.
ICLSEL
7
rw
Input Class Selection
Defines the channel-specific parameters.
Select input class 0
0B
Select input class 1
1B
0
2, 3
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
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TLE983x
Analog Digital Converter (ADC)
23.7.7
Input Class Registers
The input class registers select the sample time for each input class.
INPCR0
Input Class 0 Register
INPCR1
Input Class 1 Register
7
6
5
(CEH)
Reset Value: 00H
(CDH)
Reset Value: 00H
4
3
2
1
0
STC
rw
Field
Bits
Type
Description
STC
[7:0]
rw
Sample Time Control
This bitfield defines the additional length of the sample time, given in
terms of fADCI clock cycles.
A sample time of 2 analog clock cycles is extended by the
programmed value.
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TLE983x
Analog Digital Converter (ADC)
23.7.8
Conversion Request Control Register
The conversion request control register contains the bits that are copied to the pending register when the load
event occurs. This register can be accessed at two different addresses (one read view, two write views). One
address for read and write access is the address given for CRCR1. The second address for write actions is given
for CRPR1. A write operation to CRPR1 leads to a data write to the bits in CRCR1 with an automatic load event
one clock cycle later.
CRCR1
Conversion Request Control Register 1
(CAH)
Reset Value: 00H
7
6
5
4
3
2
1
CH7
CH6
CH5
CH4
0
rwh
rwh
rwh
rwh
r
0
Field
Bits
Type
Description
CHx
(x = 4 - 7)
x
rwh
Channel Bit x
Each bit corresponds to one analog channel, the channel number x
is defined by the bit position in the register. The corresponding bit x
in the conversion request pending register will be overwritten by this
bit when the load event occurs.
The analog channel x will not be requested for conversion by
0B
this request source.
The analog channel x will be requested for conversion by this
1B
request source.
User’s Manual
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Rev. 1.0, 2011-12-23
TLE983x
Analog Digital Converter (ADC)
23.7.9
Conversion Request Pending Register
The conversion request pending register contains the bits that request a conversion of the corresponding analog
channel. The bits in this register have only a read view. A write operation to this address leads to a data write to
CRCR1 with an automatic load event one clock cycle later.
CRPR1
Conversion Request Pending Register 1
(CBH)
Reset Value: 00H
7
6
5
4
3
2
1
CHP7
CHP6
CHP5
CHP4
0
rwh
rwh
rwh
rwh
r
0
Field
Bits
Type
Description
CHPx
(x = 4 - 7)
x
rwh
Channel Pending Bit x
Write view: A write to this address targets the bits in register CRCR1.
Read view: Each bit corresponds to one analog channel; the channel
number x is defined by the bit position in the register.
The arbiter automatically resets (at start of conversion) or sets it
again (at abort of conversion) for the corresponding analog channel.
The analog channel x is not requested for conversion by the
0B
parallel request source.
The analog channel x is requested for conversion by the
1B
parallel request source.
Note: The bits that can be read from this register location are generally ‘rh’. They cannot be modified directly by a
write operation. A write operation modifies the bits in CRCR1 (that is why they are marked ‘rwh’) and leads
to a load event one clock cycle later.
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TLE983x
Analog Digital Converter (ADC)
23.7.10
Conversion Request Mode Register
The conversion request mode registers contains bits used to set the request source in the desired mode.
CRMR1
Conversion Request Mode Register 1
(CCH)
Reset Value: 00H
7
6
5
4
3
2
1
0
REQGT
LDEV
CLRPND
SCAN
ENSI
ENTR
ENGT
rh
w
w
rw
rw
rw
rw
Field
Bits
Type
Description
ENGT
[1:0]
rw
Enable Gate
This bit enables the gating functionality for the request source.
00B The gating line is permanently 0.
The source is switched off.
01B The gating line is permanently 1.
The source is switched on.
10B The gating input is directly used.
The source is switched on if REQGTx = 1.
11B The gating input is inverted.
The source is switched on if REQGTx = 0.
Only the 00B and 01B options are selectable, since REQGTx = 1
always.
ENTR
2
rw
Enable External Trigger
0B
External trigger disabled
A rising edge at the selected trigger input REQTR generates
1B
the load event
ENSI
3
rw
Enable Source Interrupt
This bit enables the request source interrupt. This interrupt can be
generated when the last pending conversion is completed for this
source (while PND = 0).
The source interrupt is disabled.
0B
The source interrupt is enabled.
1B
SCAN
4
rw
Autoscan Enable
This bit enables the autoscan functionality. If enabled, the load event
is automatically generated when a conversion (requested by this
source) is completed and PND = 0.
The autoscan functionality is disabled.
0B
The autoscan functionality is enabled.
1B
CLRPND
5
w
Clear Pending Bits
0B
No action
The bits in register CRPR1 are reset.
1B
LDEV
6
w
Generate Load Event
0B
No action
The load event is generated.
1B
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TLE983x
Analog Digital Converter (ADC)
Field
Bits
Type
Description
REQGT
7
rh
Request Gate Level
This bit monitors the level at the REQGT input.
The level is 0.
0B
The level is 1.
1B
Returns 1 when read.
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TLE983x
Analog Digital Converter (ADC)
23.7.11
Queue Mode Register
The queue mode register contains bits used to set the request source in the desired mode.
QMR0
Queue Mode Register
(CDH)
Reset Value: 00H
7
6
5
4
3
2
1
0
CEV
TREV
FLUSH
CLRV
0
ENTR
ENGT
w
w
w
w
r
rw
rw
Field
Bits
Type
Description
ENGT
[1:0]
rw
Enable Gate
This bit enables the gating functionality for the request source.
00B The gating line is permanently 0.
The source is switched off.
01B The gating line is permanently 1.
The source is switched on.
10B The gating input is directly used.
The source is switched on if REQGTx = 1.
11B The gating input is inverted.
The source is switched on if REQGTx = 0.
Only the 00B and 01B options are selectable, since REQGTx = 1
always.
ENTR
2
rw
Enable External Trigger
This bit enables the external trigger possibility. If enabled, bit EV is
set if a rising edge is detected at the external trigger input REQTR
when at least one V bit is set in register Q0R0 or QBUR0.
External trigger disabled
0B
The external trigger is enabled
1B
CLRV
4
w
Clear V Bits
0B
No action
The bit V in register Q0R0 or QBUR0 is reset. If QBUR0.V = 1,
1B
then QBUR0.V is reset. If QBUR0.V = 0, then Q0R0.V is reset.
FLUSH
5
w
Flush Queue
0B
No action
All bits V in the queue registers and bit EV are reset. The queue
1B
contains no more valid entry.
TREV
6
w
Trigger Event
0B
No action
A trigger event is generated by software. If the source waits for
1B
a trigger event, a conversion request is started.
CEV
7
w
Clear Event Bit
0B
No action
Bit EV is cleared.
1B
0
3
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
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TLE983x
Analog Digital Converter (ADC)
23.7.12
Queue Status Register
The queue status register contains bits indicating the status of the sequential source.
QSR0
Queue Status Register
(CEH)
Reset Value: 20H
7
6
5
4
3
2
1
0
REQGT
0
EMPTY
EV
0
FILL
rh
r
rh
rh
r
rh
Field
Bits
Type
Description
FILL
[1:0]
rh
Filling Level
This bitfield indicates how many entries are valid in the sequentialsourced queue. It is incremented each time a new entry is written to
QINR0, decremented each time a requested conversion has been
finished. A new entry is ignored if the filling level has reached its
maximum value. If EMPTY bit = 1, there are no valid entries in the
queue.
00B If EMPTY bit = 0, there is 1 valid entry in the queue.
01B If EMPTY bit = 0, there are 2 valid entries in the queue.
10B If EMPTY bit = 0, there is 3 valid entry in the queue.
11B If EMPTY bit = 0, there are 4 valid entries in the queue.
EV
4
rh
Event Detected
This bit indicates that an event has been detected while V = 1. Once
set, this bit is reset automatically when the requested conversion is
started.
An event has not been detected.
0B
An event has been detected.
1B
EMPTY
5
rh
Queue Empty
This bit indicates if the sequential source contains valid entries. A
new entry is ignored if the queue is filled (EMPTY = 0).
The queue is filled with 'FILL+1' valid entries in the queue.
0B
The queue is empty, no valid entries are present in the queue.
1B
REQGT
7
rh
Request Gate Level
This bit monitors the level at the REQGT input.
The level is 0.
0B
The level is 1.
1B
Returns 1 when read.
0
[3:2], 6
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
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TLE983x
Analog Digital Converter (ADC)
23.7.13
Queue 0 Register
The queue 0 register contains bits for monitoring the status of the current sequential request.
Q0R0
Queue 0 Register 0
(CFH)
Reset Value: 00H
7
6
5
4
3
2
1
EXTR
ENSI
RF
V
0
REQCHNR
rh
rh
rh
rh
r
rh
0
Field
Bits
Type
Description
REQCHNR
[2:0]
rh
Request Channel Number
This bitfield indicates the channel number that will be or is currently
requested.
V
4
rh
Request Channel Number Valid
This bit indicates if the data in REQCHNR, RF, ENSI and EXTR is
valid. Bit V is set when a valid entry is written to the queue input
register QINR0 (or by an update by intermediate queue registers).
The data is not valid.
0B
The data is valid.
1B
RF
5
rh
Refill
This bit indicates if the pending request is discarded after being
executed (conversion start) or if it is automatically refilled in the top
position of the request queue.
The request is discarded after conversion start.
0B
The request is refilled in the queue after conversion start.
1B
ENSI
6
rh
Enable Source Interrupt
This bit indicates if a source interrupt will be generated when the
conversion is completed. The interrupt trigger becomes activated if
the conversion requested by the source has been completed and
ENSI = 1.
The source interrupt generation is disabled.
0B
The source interrupt generation is enabled.
1B
EXTR
7
rh
External Trigger
This bit defines if the conversion request is sensitive to an external
trigger event.
The event flag (bit EV) indicates if an external event has taken place
and a conversion can be requested.
Bit EV is not used to start conversion request.
0B
Bit EV is used to start conversion request.
1B
0
3
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
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TLE983x
Analog Digital Converter (ADC)
23.7.14
Queue Backup Register
The queue backup register contains bits for monitoring the status of an aborted sequential request. The registers
QBUR0 and QINR0 share the same register address. A read operation at this register address will deliver the ‘rh’
bits of the QBUR0 register. A write operation to this address will target the ‘w’ bits of The QINR0 register.
QBUR0
Queue Backup Register 0
(D2H)
Reset Value: 00H
7
6
5
4
3
2
1
EXTR
ENSI
RF
V
0
REQCHNR
rh
rh
rh
rh
r
rh
0
Field
Bits
Type
Description
REQCHNR
[2:0]
rh
Request Channel Number
This bitfield is updated by bitfield Q0R0.REQCHNR when the
conversion requested by Q0R0 is started.
V
4
rh
Request Channel Number Valid
This bit indicates if the data in REQCHNR, RF, ENSI, and EXTR is
valid. Bit V is set if a running conversion is aborted. It is reset when
the conversion is started.
The backup register does not contain valid data, because the
0B
conversion described by this data has not been aborted.
The data is valid. The aborted conversion is requested before
1B
taking into account what is requested by Q0R0.
RF
5
rh
Refill
This bit is updated by bit Q0R0.RF when the conversion requested
by Q0R0 is started.
ENSI
6
rh
Enable Source Interrupt
This bit is updated by bit Q0R0.ENSI when the conversion requested
by Q0R0 is started.
EXTR
7
rh
External Trigger
This bit is updated by bit Q0R0.EXTR when the conversion
requested by Q0R0 is started.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
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TLE983x
Analog Digital Converter (ADC)
23.7.15
Queue Input Register
The queue input register is the entry register for sequential requests. The registers QBUR0 and QINR0 share the
same register address. A read operation at this register address will deliver the ‘rh’ bits of the QBUR0 register. A
write operation to this address will target the ‘w’ bits of The QINR0 register.
QINR0
Queue Input Register 0
(D2H)
4
Reset Value: 00H
7
6
5
3
2
1
EXTR
ENSI
RF
0
REQCHNR
w
w
w
r
w
Field
Bits
Type
Description
REQCHNR
[2:0]
w
Request Channel Number
This bitfield defines the requested channel number.
RF
5
w
Refill
This bit defines the refill functionality.
ENSI
6
w
Enable Source Interrupt
This bit defines the source interrupt functionality.
EXTR
7
w
External Trigger
This bit defines the external trigger functionality.
0
[4:3]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
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TLE983x
Analog Digital Converter (ADC)
23.7.16
Result Registers
The conversion results of each analog input channel can be stored in one of 4 conversion result registers (selected
by bitfield RESRSEL in the associated channel control register CHCTRx). This structure provides different
locations for the conversion results of different groups of channels. Depending on the application needs (data
reduction, auto-scan, etc.), the user can distribute the conversion results to minimize CPU load or to be more
tolerant against interrupt latency. The result registers, optionally, deliver the channel number that has lead to the
latest update of the result register.
The results can be read via two different read views, i.e. via different registers at different addresses. Depending
on the selected operating mode, the result registers return different portions of the results. The read views are
described in Section 23.4.8.4.
RESRxL (x = 0 - 2)
Result Register x Low
RESR3L
Result Register 3 Low
7
6
(CAH + x * 2)
Reset Value: 00H
(D2H)
Reset Value: 00H
5
4
3
2
1
RESULT[1:0]
0
VF
DRC
CHNR
rh
r
rh
rh
rh
0
Field
Bits
Type
Description
CHNR
[2:0]
rh
Channel Number
The channel number of the latest register update.
If the external multiplexer control is enabled, bits CHNR[2:0] are
replaced by the multiplexer setting EMUX[2:0].
DRC
3
rh
Data Reduction Counter
Indicates if conversion results have still to be accumulated for the
final result of the data reduction. The valid flag is set and a result
event is generated when this bitfield becomes 0 (by counting or by
reload).
Accumulation complete, the final result is available in the result
0B
register.
More conversion results to be added. The valid flag is cleared
1B
when this bitfield is set to 1.
VF
4
rh
Valid Flag for Result Register x
This bit indicates that the contents of the result register x are valid.
No new valid data available
0B
Result register x contains valid data.
1B
RESULT[1:0]
[7:6]
rh
Conversion Result
8-bit conversion: 00B
10-bit conversion: result[1:0]
0
5
r
Reserved
Returns 0 if read; should be written with 0.
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TLE983x
Analog Digital Converter (ADC)
RESRxH (x = 0 - 2)
Result Register x High
RESR3H
Result Register 3 High
7
6
5
(CBH + x * 2)
Reset Value: 00H
(D3H)
Reset Value: 00H
4
3
2
1
0
RESULT[9:2]
rh
Field
Bits
Type
Description
RESULT[9:2]
[7:0]
rh
Conversion Result
Upper 8 bits of the conversion result or the result of the data
reduction filter.
8-bit conversion: result[7:0]
10-bit conversion: result[9:2]
RESRAxL (x = 0 - 2)
Result Register x, View A Low
RESRA3L
Result Register 3, View A Low
7
6
5
(CAH + x * 2)
Reset Value: 00H
(D2H)
Reset Value: 00H
4
3
2
1
RESULT[b:a]
VF
DRC
CHNR
rh
rh
rh
rh
0
Field
Bits
Type
Description
CHNR
[2:0]
rh
Channel Number
The channel number of the latest register update.
If the external multiplexer control is enabled, bits CHNR[2:0] are
replaced by the multiplexer setting EMUX[2:0].
DRC
3
rh
Data Reduction Counter
Indicates if conversion results have still to be accumulated for the
final result of the data reduction. The valid flag is set and a result
event is generated when this bitfield becomes 0 (by counting or by
reload).
Accumulation complete, the final result is available in the result
0B
register.
More conversion results to be added. The valid flag is cleared
1B
when this bitfield is set to 1.
VF
4
rh
Valid Flag for Result Register x
This bit indicates that the contents of the result register x are valid.
The result register x does not contain valid data.
0B
The result register x contains valid data.
1B
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TLE983x
Analog Digital Converter (ADC)
Field
Bits
Type
Description
RESULT[b:a]
[7:5]
rh
Conversion Result
Lower bits of the result of the data reduction filter.
8-bit conversion:
DRCTR = 0xB: result[0], padded with 00B
DRCTR = 1xB: result[1:0], padded with 0B
10-bit conversion:
DRCTR = 0xB: result[2:0]
DRCTR = 1xB: result[3:1]
RESRAxH (x = 0 - 2)
Result Register x, View A High
RESRA3H
Result Register 3, View A High
7
6
5
(CBH + x * 2)
Reset Value: 00H
(D3H)
Reset Value: 00H
4
3
2
1
0
RESULT[d:c]
rh
Field
Bits
Type
Description
RESULT[d:c]
[7:0]
rh
Conversion Result
Upper 8 bits of the result of the data reduction filter.
8-bit conversion:
DRCTR = 0xB: result[8:1]
DRCTR = 1xB: result[9:2]
10-bit conversion:
DRCTR = 0xB: result[10:3]
DRCTR = 1xB: result[11:4]
User’s Manual
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TLE983x
Analog Digital Converter (ADC)
23.7.17
Clear Valid Flag Register
Writing a 1 to a bit position in the valid flag clear register VFCR clears the corresponding valid flag in registers
RESRx/RESRAx. If a hardware event triggers the setting of a bit VF and the corresponding bit VFCx = 1, bit VF
is cleared (software overrules hardware).
VFCR
Valid Flag Clear Register
7
(CEH)
6
5
4
Reset Value: 00H
3
2
1
0
0
VFC3
VFC2
VFC1
VFC0
r
w
w
w
w
Field
Bits
Type
Description
VFCx (x = 0 - 3)
x
w
Clear Valid Flag for Result Register x
0B
No action
Clear bits VF and DRC in register RESR[A]xL.
1B
0
[7:4]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
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TLE983x
Analog Digital Converter (ADC)
23.7.18
Result Control Registers
The result control registers contain bits to control the behavior of the result registers and to monitor their status.
RCRx (x = 0 - 3)
Result Control Register x
(CAH + x * 1)
Reset Value: 00H
7
6
5
4
3
2
1
0
VFCTR
WFR
0
IEN
0
DRCTR
rw
rw
r
rw
r
rw
Field
Bits
Type
Description
DRCTR
[1:0]
rw
Data Reduction Control
Defines the number of accumulated conversion results for data
reduction. The data reduction counter DRC is loaded with this value.
00B Accumulate 1 conversion result value
(data reduction mode is disabled)
01B Accumulate 2 conversion result values
10B Accumulate 3 conversion result values
11B Accumulate 4 conversion result values
IEN
4
rw
Interrupt Enable
This bit enables the event interrupt related to the result register x. An
event interrupt can be generated when DRC is set to 0 (after
decrementing or by reload).
The event interrupt is disabled.
0B
The event interrupt is enabled.
1B
WFR
6
rw
Wait-for-Read Mode
This bit enables the wait-for-read mode for result register x.
The wait-for-read mode is disabled.
0B
The wait-for-read mode is enabled.
1B
VFCTR
7
rw
Valid Flag Control
This bit enables the reset of valid flag (by read access to high byte)
for result register x.
VF unchanged by read access to RESRxH/RESRAxH.
0B
(default)
VF reset by read access to RESRxH/RESRAxH.
1B
0
5, [3:2]
r
Reserved
Returns 0 if read; should be written with 0.
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Analog Digital Converter (ADC)
23.7.19
Channel Interrupt Flag Register
The channel interrupt flag register CHINFR monitors the activated channel interrupt flags.
CHINFR
Channel Interrupt Flag Register
(CAH)
Reset Value: 00H
7
6
5
4
3
2
1
0
CHINF7
CHINF6
CHINF5
CHINF4
CHINF3
CHINF2
CHINF1
CHINF0
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type
Description
CHINFx
(x = 0 - 7)
x
rh
Interrupt Flag for Channel x
This bit monitors the status of the channel interrupt x.
A channel interrupt for channel x has not occured.
0B
A channel interrupt for channel x has occured.
1B
23.7.20
Clear Channel Interrupt Register
Writing a 1 to a bit position in the channel interrupt clear register CHINCR clears the corresponding channel
interrupt flag in register CHINFR. If a hardware event triggers the setting of a bit CHINFx and CHINCx = 1, the bit
CHINFx is cleared (software overrules hardware).
CHINCR
Channel Interrupt Clear Register
(CBH)
Reset Value: 00H
7
6
5
4
3
2
1
0
CHINC7
CHINC6
CHINC5
CHINC4
CHINC3
CHINC2
CHINC1
CHINC0
w
w
w
w
w
w
w
w
Field
Bits
Type
Description
CHINCx
(x = 0 - 7)
x
w
Clear Interrupt Flag for Channel x
0B
No action
Bit CHINFR.x is reset.
1B
23.7.21
Set Channel Interrupt Register
Writing a 1 to a bit position in the channel interrupt set register CHINSR sets the corresponding channel interrupt
flag in register CHINFR and generates an interrupt pulse.
CHINSR
Channel Interrupt Set Register
(CCH)
Reset Value: 00H
7
6
5
4
3
2
1
0
CHINS7
CHINS6
CHINS5
CHINS4
CHINS3
CHINS2
CHINS1
CHINS0
w
w
w
w
w
w
w
w
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Analog Digital Converter (ADC)
Field
Bits
Type
Description
CHINSx
(x = 0 - 7)
x
w
Set Interrupt Flag for Channel x
0B
No action
Bit CHINFR.x is set and an interrupt pulse is generated.
1B
23.7.22
Channel Interrupt Node Pointer Registers
The bitfields in these registers define the service request output SRx (= interrupt output line x) that is activated if
a channel interrupt is generated.
CHINPR
Channel Interrupt Node Pointer Register
(CDH)
Reset Value: 00H
7
6
5
4
3
2
1
0
CHINP7
CHINP6
CHINP5
CHINP4
CHINP3
CHINP2
CHINP1
CHINP0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
CHINPx
(x = 0 - 7)
x
rw
Interrupt Node Pointer for Channel x
This bit defines which SR lines becomes activated if the channel x
interrupt is generated.
The line SR0 becomes activated.
0B
The line SR1 becomes activated.
1B
23.7.23
Event Interrupt Flag Register
The event interrupt flag register EVINFR monitors the activated event interrupt flags.
EVINFR
Event Interrupt Flag Register
(CEH)
7
6
5
4
EVINF7
EVINF6
EVINF5
EVINF4
rh
rh
rh
rh
Reset Value: 00H
3
2
1
0
0
EVINF1
EVINF0
r
rh
rh
Field
Bits
Type
Description
EVINFx
(x = 0 - 1, 4 - 7)
[1:0],
[7:4]
rh
Interrupt Flag for Event x
This bit monitors the status of the event interrupt x.
An event interrupt for event x has not occured.
0B
An event interrupt for event x has occured.
1B
0
[3:2]
r
Reserved
Returns 0 if read; should be written with 0.
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TLE983x
Analog Digital Converter (ADC)
23.7.24
Clear Event Interrupt Register
Writing a 1 to a bit position in the event interrupt clear register EVINCR clears the corresponding event interrupt
flag in register EVINFR. If a hardware event triggers the setting of a bit EVINFx and EVINCx = 1, the bit EVINFx
is cleared (software overrules hardware).
EVINCR
Event Interrupt Clear Flag Register
(CFH)
7
6
5
4
EVINC7
EVINC6
EVINC5
EVINC4
w
w
w
w
Reset Value: 00H
3
2
1
0
0
EVINC1
EVINC0
r
w
w
Field
Bits
Type
Description
EVINCx
(x = 0 - 1, 4 - 7)
[1:0], [7:4]
w
Clear Interrupt Flag for Event x
0B
No action
Bit EVINFR.x is reset.
1B
0
[3:2]
r
Reserved
Returns 0 if read; should be written with 0.
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TLE983x
Analog Digital Converter (ADC)
23.7.25
Set Event Interrupt Register
Writing a 1 to a bit position in the event interrupt set register EVINSR sets the corresponding event interrupt flag
in register EVINFR and generates an interrupt pulse (if the interrupt is enabled).
EVINSR
Event Interrupt Set Flag Register
(D2H)
7
6
5
4
EVINS7
EVINS6
EVINS5
EVINS4
w
w
w
w
Reset Value: 00H
3
2
1
0
0
EVINS1
EVINS0
r
w
w
Field
Bits
Type
Description
EVINSx
(x = 0 - 1, 4 - 7)
[1:0], [7:4]
w
Set Interrupt Flag for Event x
0B
No action
Bit EVINFR.x is set.
1B
0
[3:2]
r
Reserved
Returns 0 if read; should be written with 0.
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Analog Digital Converter (ADC)
23.7.26
Event Interrupt Node Pointer Registers
The bitfields in these registers define the service request output SRx (= interrupt output line x) that is activated if
an event interrupt is generated.
EVINPR
Event Interrupt Node Pointer Register
(D3H)
7
6
5
4
EVINP7
EVINP6
EVINP5
EVINP4
rw
rw
rw
rw
Reset Value: 00H
3
2
1
0
0
EVINP1
EVINP0
r
rw
rw
Field
Bits
Type
Description
EVINPx
(x = 0 - 1, 4 - 7)
[1:0], [7:4]
rw
Interrupt Node Pointer for Event x
This bit defines which SR lines becomes activated if the event x
interrupt is generated.
The line SR0 becomes activated.
0B
The line SR1 becomes activated.
1B
0
[3:2]
r
Reserved
Returns 0 if read; should be written with 0.
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Analog Digital Converter (ADC)
23.7.27
External Multiplexer Control
The External Multiplexer Enable Register defines which analog input channel is used to control the settings of an
external analog multiplexer and defines its operating mode.
EMENR
External Multiplexer Enable Reg.
(CFH)
Reset Value: 00H
7
6
5
4
3
2
1
0
EMUXEN
SCANEN
TROEN
0
0
EMUXCHNR
rw
rw
rw
r
r
rw
Field
Bits
Type
Description
EMUXCHNR
[2:0]
rw
Channel Number for External Multiplexer
If external multiplexer control is enabled (EMUXEN = 1), this bitfield
defines the analog ADC input channel connected to the external
analog multiplexer.
TROEN
5
rw
Trigger Option Enable
Selects the scan mode behavior of the external multiplexer (if
enabled).
Single-input scan: convert one extended channel per scan
0B
sequence
Multi-input scan: convert a series of extended channels per
1B
scan sequence
SCANEN
6
rw
Scan Enable
Enables the automatic handling of the external multiplexer during
scan sequences.
Hardware control without scan
0B
Hardware control with scan: bitfield EMUX is automatically
1B
modified during scan sequences
EMUXEN
7
rw
External Multiplexer Control Enable
Enables the automatic control of the external multiplexer.
Software control: an external multiplexer is controlled by
0B
software only
Hardware control: the external multiplexer is automatically
1B
controlled by the ADC’s hardware
0
3, 4
r
Reserved
Returns 0 if read; should be written with 0.
The External Multiplexer Control Register controls an external analog multiplexer.
EMCTR
External Multiplexer Control Reg.
7
6
5
(D2H)
4
Reset Value: 00H
3
2
1
0
EMUX
0
SETEMUX
r
rh
r
rw
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Analog Digital Converter (ADC)
Field
Bits
Type
Description
SETEMUX
[2:0]
rw
Setting of External Multiplexer
Defines the update value for bitfield EMUX.
The update options depend on the selected operating mode.
EMUX
[6:4]
rh
Current Setting for External Multiplexer
Selects an input on the external multiplexer via outputs EMUX[2:0].
Bitfield EMUX is updated from bitfield SETEMUX.
The update options depend on the selected operating mode.
0
3, 7
r
Reserved
Returns 0 if read; should be written with 0.
The External Multiplexer Sample Time Register defines the alternative sample phase length for extended
conversions.
EMSTR
Ext. Multiplexer Sample Time Reg.
7
6
5
(D3H)
4
Reset Value: 00H
3
2
1
0
EMSAMPLE
rw
Field
Bits
Type
Description
EMSAMPLE
[7:0]
rw
External Multiplexer Sampling Time
Defines the alternative sample phase length for external multiplexer
control. This value replaces the standard sample time configuration
(STC in register INPCRx, Page 27-601) for conversions where the
external multiplexer setting has changed.
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TLE983x
Analog Digital Converter (ADC)
23.7.28
Limit Check Boundary Registers
The bitfields in registers LCBRx define the four MSBs of the compare values (boundaries) used by the limit
checking unit. The values defined in bitfields BOUND0 and BOUND1 are concatenated with either four (8-bit
conversion) or six (10-bit conversion) 0s at the end to form the final value used for comparison with the converted
result. For example, the reset value of BOUND1 (BH) will translate into B0H for an 8-bit comparison, and 2C0H for
a 10-bit comparison.
Each limit check boundary register is associated with one analog input channel.
LCBRx (X = 0-7)
Limit Check Boundary Register x
7
6
5
(CAH + x)
4
Reset Value: B7H
3
2
1
BOUND1
BOUND0
rw
rw
0
Field
Bits
Type
Description
BOUNDy
(y = 0 - 1)
[3:0],
[7:4]
rw
Boundary for Limit Checking
This bitfield defines the four MSBs of the compare value used by the
limit checking unit. The result of the limit check is used for interrupt
generation.
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Analog Digital Converter (ADC)
23.8
Module Implementation Details
This section describes the ADC module interfaces with the clock control, port connections, interrupt control,
address decoding, and the on-chip modules.
The Bus Peripheral Interface (BPI) enables the ADC kernel to be attached to the 8-bit bus. The BPI consists of a
clock control logic which gates the clock input to the kernel, and an address decoder for Special Function Registers
(SFRs) in the ADC kernel.
The interrupt requests of the ADC are not connected directly to the CPU’s Interrupt Controller, but via the System
Control Unit (SCU). This is due to the fact that the total number of interrupts from all on-chip peripherals is greater
than the number of interrupt sources supported by the CPU’s Interrupt Controller. Thus the interrupt request
signals of the ADC are mapped to the Interrupt Controller by the SCU.
Note: Pls refer to the SCU Chapter for details.
The General Purpose Input (GPI) Port provides the interface from the ADC to the external world.
Note: Pls refer to the Ports Chapter for details.
23.8.1
Address Map
The BPI of the ADC supports the local address extension mechanism; hence, the SFRs of the ADC kernel are
organized into 8 pages. Please refer to Memory Architecture Chapter for details on the local address extension.
The addresses of the kernel SFRs are listed in Table 97 and Table 98.
Table 97
SFR Address List for Pages 0 – 3
Address
Page 0
Page 1
Page 2
Page 3
CAH
GLOBCTR
CHCTR0
RESR0L
RESRA0L
CBH
GLOBSTR
CHCTR1
RESR0H
RESRA0H
CCH
PRAR
CHCTR2
RESR1L
RESRA1L
CDH
INPCR1
CHCTR3
RESR1H
RESRA1H
CEH
INPCR0
CHCTR4
RESR2L
RESRA2L
CFH
ETRCR
CHCTR5
RESR2H
RESRA2H
D2H
ETRSR
CHCTR6
RESR3L
RESRA3L
D3H
–
CHCTR7
RESR3H
RESRA3H
Table 98
SFR Address List for Pages 4 – 7
Address
Page 4
Page 5
Page 6
Page 7
CAH
RCR0
CHINFR
CRCR1
LCBR0
CBH
RCR1
CHINCR
CRPR1
LCBR1
CCH
RCR2
CHINSR
CRMR1
LCBR2
CDH
RCR3
CHINPR
QMR0
LCBR3
CEH
VFCR
EVINFR
QSR0
LCBR4
CFH
EMENR
EVINCR
Q0R0
LCBR5
D2H
EMCTR
EVINSR
QBUR0/QINR0
LCBR6
D3H
EMSTR
EVINPR
–
LCBR7
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TLE983x
Analog Digital Converter (ADC)
23.8.2
Analog Connections
The analog channels of the TLE983x are connected to external and to on-chip sources.
Table 99
ADC Analog Connections in TLE983x
Signal
from/to
Module
I/O to
ADC0
Can be used to/as, connected to
Power supply and standard reference
VDD
VSS
see pinning
chapter
I
analog power supply
I
analog power supply
VAREF
I
positive analog reference
VAGND
I
negative analog reference
Analog input channels
CH0
---1)
I
Vbat_sense
CH1
P2.1
I
analog input channel 1
1)
CH2
---
I
VS
CH3
P2.3
I
analog input channel 3
CH4
P2.4
I
analog input channel 4
CH5
P2.5
I
analog input channel 5
I
CH60: MON1
CH6
1)
---
CH61: MON2
CH62: MON3
CH63: MON4
CH64: MON5
CH65: Reserved
CH66: Reserved
CH67: Reserved
CH7
P2.7
I
analog input channel 7
1) Connected to internal (on-chip) signals.
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Analog Digital Converter (ADC)
23.8.3
Digital Connections
The external request trigger inputs of the ADC are connected to the selected (multiplexed) output signals from onchip modules. These output signals correspond to the trigger inputs at the module boundary and can be used to
trigger conversion requests for both the parallel and sequential request sources. Table 100 summarizes which
signals are connected to which inputs.
The trigger signals are selected via registers ETRSR and ETRCR, Page 27-591
Table 100
ADC Trigger Interconnection
ADC Input
Connected to
ETR00
ETR10
T13PM
ETR01
ETR11
T13CM
ETR02
ETR12
T12PM
ETR03
ETR13
T12CM0
ETR04
ETR14
T12CM1
ETR05
ETR15
T12CM2
ETR06
ETR16
STR
Shadow transfer in multi-channel mode
ETR07
ETR17
CHE
Correct hall event in multi-channel mode
ETR0B
ETR1B
T21_trigger
ETR0C
ETR1C
T2_trigger
ETR0D
ETR1D
Reserved
The external gating inputs (EGT0, EGT1) of the ADC are held permanently at 1.
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High-Voltage Monitor Input
24
High-Voltage Monitor Input
24.1
Features
Features
•
•
•
•
High-voltage input with VS/2 threshold voltage
Wake capability for power saving modes
Level sensitive wake-up feature configurable for transitions from low to high, high to low or both directions
MON inputs can also be evaluated with ADC1 in Acti1234ve Mode, using adjustable threshold values (see also
Chapter 16).
24.2
Functional Description
This module is dedicated to monitor external voltage levels above or below a specified threshold. Each MONx pin
can further be used to detect a wake-up event by detecting a level change by crossing the selected threshold. This
applies to any power mode. Further more each MONx pin can be sampled by the ADC1 as analog input.
VS
MONx
MONx
Filter
MON_int
Logic
XSFR
Figure 170 Monitoring Input Block Diagram
For a wake-up on a positive voltage transition, the MONx_RISE bit has to be configured. For a wake-up on a
negative voltage transition, the corresponding bit MONx_FALL has to be set. This configuration can also be used
for an edge detection in active mode.
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High-Voltage Monitor Input
As the system provides the functionality of cyclic sense, the MONx can be configured as a wake-up source for this
mode. This is done by setting the bit MONx_CYC.
To enter power saving mode of the monitor input the Bit MONx_NSLEEP must be set to 0. With the transition of
the Bit from 1 to 0 the level on the monitor input is saved for wake transition detection. The MONx_NSLEEP Bit is
not changed by the hardware and therefore must be set and reset manually.
The MONx also includes an input circuit with pull-up (can be activated by MONx_PU bit) and pull-down (can be
activated by MONx_PD Bit) current sources to define a certain voltage level with open inputs and a filter function
to avoid wake-up events caused by unwanted voltage transients at the module input.
When automatic current source selection is enabled, a voltage level at the MONx input of VMON_th < VMONx < Vs1V activates the pull-up current source. If the MONx voltage is between 1 V < VMONx < VMON_th the pull-down sink
is activated, providing stable levels at the monitor inputs. Below and above these voltage ranges the current is
minimized to a leakage current. This automatic activation of the current sources, has to be done by setting
MONx_PU and MONx_PD bit to one at the same time.
Note: In case a Monitoring Input is deactivated by setting bit MONx_EN to zero, it can neither be used as
a wake-up source nor can it be used to detect logic levels!
VMONth_min VMONth_max
IMON
Pull-down
current
VS - 1V
VS
VMON
1V
Pull-up
current
MONx_Currents
Figure 171 Module - HV_MON Input Characteristics for switchable pull current and static pull-down (on
top) or pull-up
The following tables provides an overview of the configuration possibilities on the MON_INs via XSFR.
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High-Voltage Monitor Input
Table 101 includes all pull-up and pull-down setup scenarios which can be chosen for one MONx. Table 102
shows an overview of the available states of a MONx.
Table 101
Pull-Up / Pull-Down Input Current
MONx_PU
MONx_PD
Output Current
l0
0
leakage current
l0
1
pull-down
1
0
pull-up
1
1
switchable
1)
Description
pull-up/down current source disabled
pull-down current source enabled (for low active switches)
pull-up current source enabled (for high active switches)
2)
pull-up/down depending on input voltage
1) all current sources switched off.
2) will be automatically switched by the MONx circuit depending on level of input signal.
Table 102
MONx_EN and MONx_NSleep MON Mode definition
MONx_EN
MONx_NSLEE Mode
P
Description
0
0
disabled1)
Monitoring input is disabled (no wake-up possible!)
0
1
disabled
Monitoring input is disabled (no wake-up possible!)
1
0
power saving
mode
Monitoring input is set to power saving mode (use for device
Sleep Mode and Stop Mode)
1
1
normal mode
Monitoring input is in active mode
1) if a MONx is disabled it cannot be used as a wake-up source anymore.
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High-Voltage Monitor Input
24.3
Register Definition
This chapter describes the configuration registers for MON1-MON5.
The registers listed below are located in the XSFR address space. To access them, no paging is required.
Table 103
Registers Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Register Definition, Monitor Input Registers
MON1_CTRL_STS
MON1 Control Status
0DH
x100 0111B
MON2_CTRL_STS
MON2 Control Status
0EH
x100 0111B
MON3_CTRL_STS
MON3 Control Status
0FH
x100 0111B
MON4_CTRL_STS
MON4 Control Status
10H
x100 0111B
MON5_CTRL_STS
MON5 Control Status
11H
x100 0111B
The register is addressed bytewise.
24.3.1
Monitor Input Registers
The monitor input registers are part of the PMU. This is due to the fact that this circuit requires supply and clock,
during system wide sleep and Stop modes.
MON1 Control Status Register
The register is reset by RESET_TYPE_2.
MON1_CTRL_STS
MON1 Control Status Register
Offset
Reset Value
0DH
x100 0111B
7
6
5
4
3
2
1
0
MON1_ST
S
MON1_NS
LEEP
MON1_PU
MON1_PD
MON1_CY
C
MON1_RI
SE
MON1_FA
LL
MON1_EN
r
rwp
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
MON1_STS
7
r
MON1 Status Input
0B
MON input has low status
MON input has high status
1B
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High-Voltage Monitor Input
Field
Bits
Type
Description
MON1_NSLEEP
6
rw
MON1 Sleep Bit
Note: This Bit must always be set to zero, when entering
Sleep Mode or Stop Mode, to reach a reduced
current consumption
0B
1B
MON1_PU
5
rw
level on the monitor input is saved for wake
transition detection
level on the monitor input is not saved for wake
transition detection
Pull-Up Current Source for MON1 Input Enable
Note: Works only if MON1_EN is enabled
0B
1B
MON1_PD
4
rw
Pull-up source disabled
Pull-up source enabled
Pull-Down Current Source for MON1 Input Enable
Note: Works only if MON1_EN is enabled
0B
1B
MON1_CYC
3
rw
Pull-down source disabled
Pull-down source enabled
MON1 for Cycle Sense Enable
Note: Works only if MON1_EN is enabled
0B
1B
MON1_RISE
2
rw
Cycle Sense disabled
Cycle Sense enabled
MON1 Wake-up on Rising Edge Enable
Note: Works only if MON1_EN is enabled
0B
1B
MON1_FALL
1
rw
Wake-up disabled
Wake-up enabled
MON1 Wake-up on Falling Edge Enable
Note: Works only if MON1_EN is enabled
0B
1B
MON1_EN
User’s Manual
0
rw
Wake-up disabled
Wake-up enabled
MON1 Enable
0B
MON1 disabled
MON1 enabled
1B
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High-Voltage Monitor Input
MON2 Control Status Register
The register is reset by RESET_TYPE_2.
MON2_CTRL_STS
MON2 Control Status Register
Offset
Reset Value
0EH
x100 0111B
7
6
5
4
3
2
1
0
MON2_ST
S
MON2_NS
LEEP
MON2_PU
MON2_PD
MON2_CY
C
MON2_RI
SE
MON2_FA
LL
MON2_EN
r
rwp
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
MON2_STS
7
r
MON2 Status Input
0B
MON input has low status
MON input has high status
1B
MON2_NSLEEP
6
rw
MON2 Sleep Bit
Note: This Bit must always be set to zero, when entering
Sleep Mode or Stop Mode, to reach a reduced
current consumption
0B
1B
MON2_PU
5
rw
level on the monitor input is saved for wake
transition detection
level on the monitor input is not saved for wake
transition detection
Pull-Up Current Source for MON2 Input Enable
Note: Works only if MON2_EN is enabled
0B
1B
MON2_PD
4
rw
Pull-up source disabled
Pull-up source enabled
Pull-Down Current Source for MON2 Input Enable
Note: Works only if MON2_EN is enabled
0B
1B
MON2_CYC
3
rw
Pull-down source disabled
Pull-down source enabled
MON2 for Cycle Sense Enable
Note: Works only if MON2_EN is enabled
0B
1B
MON2_RISE
2
rw
Cycle Sense disabled
Cycle Sense enabled
MON2 Wake-up on Rising Edge Enable
Note: Works only if MON2_EN is enabled
0B
1B
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Wake-up disabled
Wakeup enabled
Rev. 1.0, 2011-12-23
TLE983x
High-Voltage Monitor Input
Field
Bits
Type
Description
MON2_FALL
1
rw
MON2 Wake-up on Falling Edge Enable
Note: Works only if MON2_EN is enabled
0B
1B
MON2_EN
User’s Manual
0
rw
Wake-up disabled
Wake-up enabled
MON2 Enable
0B
MON2 disabled
MON2 enabled
1B
633
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TLE983x
High-Voltage Monitor Input
MON3 Control Status Register
The register is reset by RESET_TYPE_2.
MON3_CTRL_STS
MON3 Control Status Register
Offset
Reset Value
0FH
x100 0111B
7
6
5
4
3
2
1
0
MON3_ST
S
MON3_NS
LEEP
MON3_PU
MON3_PD
MON3_CY
C
MON3_RI
SE
MON3_FA
LL
MON3_EN
r
rwp
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
MON3_STS
7
r
MON3 Status Input
0B
MON input has low status
MON input has high status
1B
MON3_NSLEEP
6
rw
MON3 Sleep Bit
Note: This Bit must always be set to zero, when entering
Sleep Mode or Stop Mode, to reach a reduced
current consumption
0B
1B
MON3_PU
5
rw
level on the monitor input is saved for wake
transition detection
level on the monitor input is not saved for wake
transition detection
Pull-Up Current Source for MON3 Input Enable
Note: Works only if MON3_EN is enabled
0B
1B
MON3_PD
4
rw
Pull-up source disabled
Pull-up source enabled
Pull-Down Current Source for MON3 Input Enable
Note: Works only if MON3_EN is enabled
0B
1B
MON3_CYC
3
rw
Pull-down source disabled
Pull-down source enabled
MON3 for Cycle Sense Enable
Note: Works only if MON3_EN is enabled
0B
1B
MON3_RISE
2
rw
Cycle Sense disabled
Cycle Sense enabled
MON3 Wake-up on Rising Edge Enable
Note: Works only if MON3_EN is enabled
0B
1B
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634
Wake-up disabled
Wake-up enabled
Rev. 1.0, 2011-12-23
TLE983x
High-Voltage Monitor Input
Field
Bits
Type
Description
MON3_FALL
1
rw
MON3 Wake-up on Falling Edge Enable
Note: Works only if MON3_EN is enabled
0B
1B
MON3_EN
User’s Manual
0
rw
Wake-up disabled
Wake-up enabled
MON3 Enable
0B
MON3 disabled
MON3 enabled
1B
635
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TLE983x
High-Voltage Monitor Input
MON4 Control Status Register
The register is reset by RESET_TYPE_2.
MON4_CTRL_STS
MON4 Control Status Register
Offset
Reset Value
10H
x100 0111B
7
6
5
4
3
2
1
0
MON4_ST
S
MON4_NS
LEEP
MON4_PU
MON4_PD
MON4_CY
C
MON4_RI
SE
MON4_FA
LL
MON4_EN
r
rwp
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
MON4_STS
7
r
MON4 Status Input
0B
MON input has low status
MON input has high status
1B
MON4_NSLEEP
6
rw
MON4 Sleep Bit
Note: This Bit must always be set to zero, when entering
Sleep Mode or Stop Mode, to reach a reduced
current consumption
0B
1B
MON4_PU
5
rw
level on the monitor input is saved for wake
transition detection
level on the monitor input is not saved for wake
transition detection
Pull-Up Current Source for MON4 Input Enable
Note: Works only if MON4_EN is enabled
0B
1B
MON4_PD
4
rw
Pull-up source disabled
Pull-up source enabled
Pull-Down Current Source for MON4 Input Enable
Note: Works only if MON4_EN is enabled
0B
1B
MON4_CYC
3
rw
Pull-down source disabled
Pull-down source enabled
MON4 for Cycle Sense Enable
Note: Works only if MON4_EN is enabled
0B
1B
MON4_RISE
2
rw
Cycle Sense disabled
Cycle Sense enabled
MON4 Wake-up on Rising Edge Enable
Note: Works only if MON4_EN is enabled
0B
1B
User’s Manual
636
Wake-up disabled
Wake-up enabled
Rev. 1.0, 2011-12-23
TLE983x
High-Voltage Monitor Input
Field
Bits
Type
Description
MON4_FALL
1
rw
MON4 Wake-up on Falling Edge Enable
Note: Works only if MON4_EN is enabled
0B
1B
MON4_EN
User’s Manual
0
rw
Wake-up disabled
Wake-up enabled
MON4 Enable
0B
MON4 disabled
MON4 enabled
1B
637
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TLE983x
High-Voltage Monitor Input
MON5 Control Status Register
The register is reset by RESET_TYPE_2.
MON5_CTRL_STS
MON5 Control Status Register
Offset
Reset Value
11H
x100 0111B
7
6
5
4
3
2
1
0
MON5_ST
S
MON5_NS
LEEP
MON5_PU
MON5_PD
MON5_CY
C
MON5_RI
SE
MON5_FA
LL
MON5_EN
r
rwp
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
MON5_STS
7
r
MON5 Status Input
0B
MON input has low status
MON input has high status
1B
MON5_NSLEEP
6
rw
MON5 Sleep Bit
Note: This Bit must always be set to zero, when entering
Sleep Mode or Stop Mode, to reach a reduced
current consumption
0B
1B
MON5_PU
5
rw
level on the monitor input is saved for wake
transition detection
level on the monitor input is not saved for wake
transition detection
Pull-Up Current Source for MON5 Input Enable
Note: Works only if MON5_EN is enabled
0B
1B
MON5_PD
4
rw
Pull-up source disabled
Pull-up source enabled
Pull-Down Current Source for MON5 Input Enable
Note: Works only if MON5_EN is enabled
0B
1B
MON5_CYC
3
rw
Pull-down source disabled
Pull-down source enabled
MON5 for Cycle Sense Enable
Note: Works only if MON5_EN is enabled
0B
1B
MON5_RISE
2
rw
Cycle Sense disabled
Cycle Sense enabled
MON5 Wake-up on Rising Edge Enable
Note: Works only if MON5_EN is enabled
0B
1B
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638
Wake-up disabled
Wake-up enabled
Rev. 1.0, 2011-12-23
TLE983x
High-Voltage Monitor Input
Field
Bits
Type
Description
MON5_FALL
1
rw
MON5 Wake-up on Falling Edge Enable
Note: Works only if MON5_EN is enabled
0B
1B
MON5_EN
User’s Manual
0
rw
Wake-up disabled
Wake-up enabled
MON5 Enable
0B
MON5 disabled
MON5 enabled
1B
639
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TLE983x
High Side Switches
25
25.1
High Side Switches
Features
The High Side switch is optimized for driving resistive loads. Only small line inductance are allowed. Typical
applications are single or multiple LEDs of a dashboard, switch illumination or other loads that require a High Side
switch.
A cyclic switch activation during Sleep Mode or Stop Mode of the system is also available.
Functional Features
•
•
•
•
•
•
•
•
Multi purpose High Side switch for resistive load connections (only small line inductances are allowed)
Overcurrent detection with thresholds: 8 mA (also used for Open Load detection), 50 mA, 100 mA, 150 mA
Cyclic switch activation in Sleep Mode and Stop Mode with cyclic sense support and reduced driver capability:
max. 40 mA
Open Load detection in off mode with two different thresholds: Ground (0V, for functional safety) and 0,67 * VS
Off-state open load detection operates with two different test currents: 75 µA and 750 µA
PWM capability up to 25 kHz (with disabled slew rate control only)
Robust output for off board ECU connection
Slew rate control
VS
OCTH_SEL
8 mA
50 mA
100 mA
150 mA
OC-Detection
CyclicDriver
XSFR
ON
Driver
OLTH_SEL
HS
0V
0.67*Vs
OL-Detection
6.8 nF
High Side
Figure 172 High Side Module Block Diagram
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High Side Switches
25.2
Functional Description
The High Side switch can be used for external communication or for the control of LEDs and other loads. The
module output can be controlled by PWM.
The High Side switch can be controlled in three different ways:
•
•
•
In Normal mode the output stage is fully controllable through the XSFR Registers HSx_CTRL. Protection
functions as overcurrent, overtemperature and open load detection are available.
The PWM Mode can also be enabled by a HSx_CTRL - XSFR bit. The PWM configuration has to be done in
the corresponding PWM Module. All protection functions are also available in this mode. The maximum PWM
frequency must not exceed 25 kHz (disabled slew rate control only).
The High Side switch provides also the possibility of cyclic switch in all low power modes (Sleep Mode and
Stop Mode). In this configuration it has limited functionality with limited current capability. Diagnostic functions
are not available in this mode.
25.2.1
Normal Operation
In normal operation mode the High Side switch is intended to drive mainly resistive loads with a small wiring related
inductance. The maximum load current is 150 mA. The main features provided by the High Side switch module
are the following:
•
•
•
•
•
Slew Rate Control for improved EMI behavior. The slew rate control can also be disabled by the
corresponding bit in the HSx_CTRL - XSFR.
Overcurrent Detection with four different thresholds: 8 mA, 50 mA, 100 mA and 150 mA. To configure the
proper overcurrent threshold the corresponding bits HSx_OC_SEL in the HSx_CTRL - XSFR have to be set.
If an overcurrent condition is present, the High Side switch will be automatically turned off. In parallel the flag
HSx_OC_STS is set. To enable the High Side switch again, it is recommended to reset the HSx_ON flag, then
to clear the HSx_OC_STS bit and to try again to turn the switch on. Clearing only the HSx_OC_STS flag, would
also turn the switch automatically on. If the overcurrent condition is still present, the switch will be disabled once
again.
Overtemperature Protection, to protect the switches against overtemperature. If overtemperature appears,
the switch will shutdown and the corresponding bit HSx_OT_STS is set. To enable again the High Side switch,
the same procedure as for the overcurrent condition is recommended.
On-State Open Load Detection is done with the lowest overcurrent threshold. If the current delivered by the
High Side switch is lower than 8 mA, HSx_OL_STS is set. The detection of an open load condition has no
influence on the High Side switch. The detailed principle of the On-State Open Load detection is shown in the
chapter Sub-Module ON-State Open Load Detection.
Off-State Open Load Detection with two different thresholds and currents: 0V (functional safety) and
0.67*VS. The available test currents are 75 µA and 750 µA in off state. This Open Load detection is not
automatically active and has to be configured. If an open load is detected, the bit HSx_OL_STS is set. The
detection of an open load condition has no influence on the High Side switch. The detailed principle of the OffState Open Load detection is shown in the chapter Sub-Module OFF-State Open Load Detection.
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High Side Switches
25.2.2
PWM Operation
In PWM mode the High Side switch has to be first enabled by the corresponding bits in the HSx_CTRL register.
The related bits are described below.
VS
HS_ON
1
HS_PWM
PWM_CHx
&
≥1
&
HS
Figure 173 Combinatorial Control of High Side switch in PWM Mode.
To avoid any output glitches on the HSx output, the HSx_PWM bit should be set first. After the function is enabled
for PWM operation the corresponding PWM unit can be enabled.
For frequencies higher than 10 kHz, the slew rate control has to be switched off. Otherwise the internal
power dissipation of the switch might damage the device.
25.2.3
Cyclic Switching in Low Power Mode
In the cyclic sense power-saving mode the High Side switch cyclically supplies an external switch arrangement for
a short time, just long enough to detect the position of the switches. The configuration procedure to use the High
Side switch for cyclic sense operation, is described in the chapter Power Management Unit.
25.2.4
Sub-Module ON-State Open Load Detection
The High Side Open Load detection in ON State is mainly performed by the overcurrent detection and its
selectable lowest threshold of 8 mA.
To enable the Open Load detection, bit HSx_ON and also HSx_OL_EN have to be set to one.
The detection mechanism starts after the HSx_OL_DTIME delay time, in which the detection is passive (also
checking if overcurrent status is active). This delay ensures that the OC Detection can at least be active for
HSx_OL_DTIME given in units of µs.
After the delay is passed, the measurement to check the load status, will be performed.
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High Side Switches
25.2.5
Sub-Module OFF-State Open Load Detection
To enable the Open Load detection, bit HSx_ON must be zero and HSx_OL_EN have to be set to one. Figure 174
shows the detection principle of the Off-State Open Load detection. It is based on a test current, which is applied
to the external load. The resulting voltage (Itest*Rload) at the load is then compared with the open-load threshold
voltage 0,67*VS. If the voltage is greater than the threshold, the circuit indicates the Open Load state
(HSx_OL_STS = 1).
VS
OL_EN
IOL
PLDMOS
OFF
HS
Ileak
Rs
OL
Load
VOLTH
GND_A
GND_Ext.
GND_Ext .
High Side
Figure 174 OFF-state Open Load detection principle
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High Side Switches
25.3
Register Definition
Table 104
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Register Definition, High Side Switch Register
HS1_CTRL
High Side switch 1 Control
17H
0000 0000B
HS1_CTRL2
High Side switch 1 Control 2
18H
0011 1000B
HS1_OL_DTIME
High Side 1 Open Load Dead Time
F8H
0000 1000B
Register Definition, High Side Switch 2 Register
HS2_CTRL
High Side Switch 2 Control
1EH
0000 0000B
HS2_CTRL2
High Side Switch 2 Configuration
1FH
0011 1000B
HS2_OL_DTIME
High Side 2 Open Load Dead Time
F8H
0000 1000B
The registers are addressed bytewise.
25.3.1
High Side Switch Register
High Side switch 1 Control Register
The register is reset by RESET_TYPE_3.
HS1_CTRL
High Side switch 1 Control Register
Offset
Reset Value
17H
0000 0000B
7
6
5
4
3
2
1
0
HS1_OC_
STS
HS1_OL_
STS
HS1_OT_
STS
Res
HS1_OL_
EN
HS1_ON
HS1_PWM
HS1_EN
rwh
rwh
r
rw
rw
rw
rw
Field
Bits
Type
Description
HS1_OC_STS
7
rwh
High Side 1 Overcurrent Status
0B
no Overcurrent no overcurrent Condition occurred;
write clears status.
Overcurrent overcurrent occurred; switch is
1B
automatically shutdown.
HS1_OL_STS
6
rwh
High Side 1 Open Load Status
0B
NORMAL normal load, write clears status
OPEN LOAD open load detected
1B
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High Side Switches
Field
Bits
Type
Description
HS1_OT_STS
5
rwh
High Side 1 Overtemperature Status
0B
no Overtemperature no overtemperature occurred,
write clears status.
Overtemperature overtemperature occurred; switch
1B
is automatically shutdown.
Res
4
r
Reserved
Always read as 0
HS1_OL_EN
3
rw
High Side 1 Open Load Detection Enable
0B
DISABLE disable open load detection
ENABLE enable open load detection
1B
HS1_ON
2
rw
High Side 1 On
0B
OFF HS driver off
ON HS driver on
1B
HS1_PWM
1
rw
High Side 1 PWM Enable
0B
DISABLE disables control by PWM input
ENABLE enables control by PWM input
1B
HS1_EN
0
rw
High Side 1 Enable
0B
DISABLE HS circuit power off
ENABLE HS circuit power on
1B
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High Side Switches
High Side switch 1 Control 2 Register
The register is reset by RESET_TYPE_3.
HS1_CTRL2
High Side switch 1 Control 2 Register
Offset
Reset Value
18H
0011 1000B
7
6
5
4
3
2
1
HS1_IOL
_SEL
HS1_OL_
TH_SEL
Res
HS1_OC_SEL
Res
HS1_SRC
TL_OFF
rw
rw
r
rw
r
r
Field
Bits
Type
Description
HS1_IOL_SEL
7
rw
High Side 1 Open Load Current Selection
0B
750 Open Load Test Current 750 µA
75 Open Load Test Current 75 µA
1B
HS1_OL_TH_SEL
6
rw
High Side 1 Open Load Threshold Selection
0B
VOLTH0 threshold 0 (0V)
VOLTH1 threshold 1 (0,67 x VS)
1B
Res
5
r
Reserved
Always read as 1
HS1_OC_SEL
4:3
rw
High Side 1 Overcurrent Threshold Selection
0H
IOCTH0 8 mA min.
IOCTH1 50 mA min.
1H
IOCTH1 100 mA min.
2H
IOCTH3 150 mA min.
3H
Res
2:1
r
Reserved
Always read as 0
HS1_SRCTL_OFF
0
r
High Side 1 Slew Rate Control Off
0B
Enabled Slew Rate Control is enabled
Disabled Slew Rate Control is disabled
1B
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High Side Switches
High Side 1 Open Load Dead Time Register
The register is reset by RESET_TYPE_4.
HS1_OL_DTIME
High Side 1 Open Load Dead Time Register
Offset
Reset Value
F8H
0000 0000B
7
3
2
0
Res
HS1_OL_DTIME_SEL
r
rw
Field
Bits
Type
Description
Res
7:3
r
Reserved
Always read as 0
HS1_OL_DTIME_SEL
2:0
rw
Overcurrent Filter Time Select for HS1
000B 16_us 16 µs filter time
001B 32_us 32 µs filter time
010B 64_us 64 µs filter time
011B 128_us 128 µs filter time
100B 256_us 256 µs filter time
101B 512_us 512 µs filter time
110B 1024_us 1024 µs filter time
111B 2048_us 2048 µs filter time
25.3.2
High Side Switch 2 Register
High Side Switch 2 Control Register
The register is reset by RESET_TYPE_3.
HS2_CTRL
High Side Switch 2 Control Register
Offset
Reset Value
1EH
0000 0000B
7
6
5
4
3
2
1
0
HS2_OC_
STS
HS2_OL_
STS
HS2_OT_
STS
Res
HS2_OL_
EN
HS2_ON
HS2_PWM
HS2_EN
rwh
rwh
rwh
r
rw
rw
rw
rw
Field
Bits
Type
Description
HS2_OC_STS
7
rwh
High Side 2 Overcurrent Status
0B
no Overcurrent no overcurrent condition occurred;
write clears status.
Overcurrent overcurrent occurred; switch is
1B
automatically shutdown.
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High Side Switches
Field
Bits
Type
Description
HS2_OL_STS
6
rwh
High Side 2 Open Load Status
0B
NORMAL normal load, write clears status
OPEN LOAD open load detected
1B
HS2_OT_STS
5
rwh
High Side 2 Overtemperature Status
0B
no overtemperature no overtemperature occurred,
write clears status.
Overtemperature overtemperature occurred; switch
1B
is automatically shutdown.
Res
4
r
Reserved
Always read as 0
HS2_OL_EN
3
rw
High Side 2 Open Load Detection Enable
0B
DISABLE disable open load detection
ENABLE enable open load detection
1B
HS2_ON
2
rw
High Side 2 on
0B
OFF HS2 driver off
ON HS2 driver on
1B
HS2_PWM
1
rw
High Side 2 PWM Enable
0B
DISABLE disables control by PWM input
ENABLE enables control by PWM input
1B
HS2_EN
0
rw
High Side 2 Enable
0B
DISABLE HS2 circuit power off
ENABLE HS2 circuit power on
1B
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High Side Switches
High Side Switch 2 Configuration Register
The register is reset by RESET_TYPE_3.
HS2_CTRL2
High Side Switch 2 Configuration Register
Offset
Reset Value
1FH
0011 1000B
7
6
5
4
3
2
1
HS2_IOL
_SEL
HS2_OL_
TH_SEL
Res
HS2_OC_SEL
Res
HS2_SRC
TL_OFF
rw
rw
r
rw
r
r
Field
Bits
Type
Description
HS2_IOL_SEL
7
rw
Selection of Open Load Current
0B
750 Open Load Test Current 750 µA
1HB 75 Open Load Test Current 75 µA
HS2_OL_TH_SEL
6
rw
High Side 1 Open Load Threshold Selection
0B
VOLTH0 threshold 0 (0V)
VOLTH1 threshold 1 (0,67 x VS)
1B
Res
5
r
Reserved
Always read as 1
HS2_OC_SEL
4:3
rw
Overcurrent threshold selection
0H
reserved
IOCTH1 50 mA min.
1H
IOCTH1 100 mA min.
2H
IOCTH3 150 mA min.
3H
Res
2:1
r
Reserved
Always read as 0
HS2_SRCTL_OFF
0
r
High Side 2 Slew Rate Control Off
0B
Enabled Slew Rate Control is enabled
Disabled Slew Rate Control is disabled
1B
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High Side Switches
High Side 2 Open Load Dead Time Register
The register is reset by RESET_TYPE_4.
HS2_OL_DTIME
High Side 2 Open Load Dead Time Register
Offset
Reset Value
F8H
0000 0000B
7
3
2
0
Res
HS2_OL_DTIME_SEL
r
r
Field
Bits
Type
Description
Res
7:3
r
Reserved
Always read as 0
HS2_OL_DTIME_SEL
2:0
rw
Overcurrent Filter Time Select for HS2
000B 16_us 16 µs filter time
001B 32_us 32 µs filter time
010B 64_us 64 µs filter time
011B 128_us 128 µs filter time
100B 256_us 256 µs filter time
101B 512_us 512 µs filter time
110B 1024_us 1024 µs filter time
111B 2048_us 2048 µs filter time
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Low Side Switch
26
26.1
Low Side Switch
Features
The general purpose low-side switch is optimized to control an on-board relay. The low-side switch provides
embedded protection functions including overcurrent and overtemperature detection. The module is designed for
on-board connections.
Measures for standard ESD (HBM) and EMC robustness are implemented.
Functional Features
•
•
•
•
•
•
Multi purpose low-side switch
– configurable overcurrent protection with automatic shutdown
– configurable overtemperature protection with automatic shutdown
Optimized for relay driver
– PWM relay driver (see also Application hints)
– simple relay driver
Integrated clamping
PWM capability up to 25 kHz (referring to the corresponding Data Sheet)
Selectable PWM source: PWM-Unit or CCU6
Current drive capability up to a specified value
Applications hints
•
It is not recommended to use the switch in PWM Mode without external free wheeling diode. See
Chapter 26.2.2.1
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Low Side Switch
LS
Clamp
XSFR
ON
Driver
300 mA
OC-Detection
Low Side
LSGND
Figure 175 Module Block Diagram
26.2
Functional Description
The low-side switch can be used for driving relays or resistive loads. The module output can be controlled by PWM
as well.
The Low Side switch can be controlled in two ways:
•
•
In Normal mode the output stages are fully controllable through the XSFR registers LSx_CTRL. Protection
functions as overcurrent detection and overtemperature detection are available.
The PWM Mode can also be enabled by LSx_CTRL - XSFR. The PWM configuration must be done in the
corresponding PWM Module. Also here all protection functions are available.
26.2.1
Normal Operation
In normal operation mode the Low Side switch is intended to drive relays or resistive loads with a small wiring
related inductance. The maximum load current is 250 mA. The features provided by the Low-Side switch:
•
•
Slew Rate Control for improved EMI behavior
Several Diagnosis functions, as programmable overcurrent detection and programmable overtemperature
detection are implemented. They are performed by the Measurement Unit.
26.2.1.1
Overcurrent Detection and Shutdown
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Low Side Switch
The overcurrent diagnosis of the Low Side switch is performed by the Measurement Unit. ADC2 evaluates
permanently the current flowing through both Low Side switches. Channel 6 is used for Low Side 1 and Channel
7 for Low Side 2. When overcurrent is detected in one of the switches, it will be shutdown and in parallel the
dedicated LSx_OC_STS bit is set.
To enable again the Low Side switch, it is recommended to reset the LSx_ON flag, then to clear the LSx_OC_STS
Bit and to try again to turn the switch on. Clearing only the LSx_OC_STS flag, would also turn the switch
automatically on. If the overcurrent condition is still present, it would be disabled once again.
Both Low Side switches are monitored and controlled by the Measurement Unit. Therefore adjustment for a kind
of prewarning threshold can be made. The current value for the prewarning is programmable and an interrupt can
be generated to indicate that the shutdown threshold will be approached. These prewarning flags are grouped
together in the SCU_PM module. The corresponding programmable threshold comparator registers are located in
the Measurement Core module.
26.2.1.2
Overtemperature Detection and Shutdown
The overtemperature monitoring of the Low Side switch is as well performed by the Measurement Unit. ADC2
evaluates permanently the temperature of both Low Side switches. Channel 9 is used for both Low Side switches.
When overtemperature is detected both switches are shutdown and in parallel the dedicated LSx_OT_STS bits
are set.
The reason for the simultaneous shutdown of both Low Side switches is the availability of only one temperature
sensor for both Low Side switches. This sensor is placed in the middle of the two power stages.
The fact, that both Low Side switches are evaluated by the Measurement Unit, makes it possible, to provide for
the overtemperature protection a flexibility of adjustment in the way of a prewarning threshold. Here the user can
decide at which Low Side switch temperature value he will be informed, that he operates near the shutdown
threshold. These prewarning flags are grouped together in the SCU_PM module. The corresponding adjustable
thresholds are located in the Measurement Core module.
26.2.2
Operation of Low Side Switch in PWM Mode
The Low Side switch can also be operated in PWM Mode. To enable the PWM Mode of the Low-Side switch, the
corresponding bits LSx_PWM and LSx_ON in the control register LSx_CTRL have to be set. The implemented
combinatorial logic is shown in the next figure.
LS
LS_ON
1
LS_PWM
PWM_CHx
&
≥1
&
GND_LS
Figure 176 Module PWM Usage of Low Side Switch
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Low Side Switch
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Low Side Switch
26.2.2.1
Application Requirement for Low Side Switch in PWM Mode
The Low Side switch is not designed, to handle the amount of energy, which is generated by switching an inductive
load in PWM Mode. Therefore an external free wheeling diode is required to absorb the generated energy. The
picture below shows the possible application diagram for this case.
VBAT
External
Diode for
PWM
VS
LS
Clamp
XSFR
ON
Driver
LSGND
500 mA
OC-Detection
Low Side
Figure 177 Module Block Diagram (with interconnects and ext. components).
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Low Side Switch
26.3
Register Definition
Table 105
Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
Register Definition, Low-Side Switches Registers
LS1_CTRL
Low-Side Switch 1 Control
15H
0000 0000B
LS2_CTRL
Low-Side Switch 2 Control
16H
0000 0000B
The registers are addressed bytewise.
26.3.1
Low-Side Switches Registers
Low-Side Switch 1 Control
The register is reset by RESET_TYPE_3.
LS1_CTRL
Low-Side Switch 1 Control
Offset
Reset Value
15H
0000 0000B
7
6
5
4
3
2
1
0
LS1_OT_
STS
LS1_OC_
STS
LS1_VCL
_STS
Res
Res
LS1_ON
LS1_PWM
LS1_EN
rwh
rwh
rwh
r
r
rw
rw
rw
Field
Bits
Type
Description
LS1_OT_STS
7
rwh
Low-Side switch 1 Overtemperature Status
This bit indicates an overtemperature situation at the Low Side
switch
active Overtemperature has occured
1B
passive no overtemperature occured
0B
LS1_OC_STS
6
rwh
Low-Side switch 1 Overcurrent Status
This bit indicates an overcurrent situation at the Low Side
switch
active overcurrent has occured
1B
passive no overcurrent occured
0B
Res
5:3
r
Reserved
Always read as 0
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Low Side Switch
Field
Bits
Type
Description
LS1_ON
2
rw
Low-Side switch 1 On/Off
0B
OFF switches LS1 off
ON turns on LS1
1B
LS1_PWM
1
rw
Low-Side switch 1 PWM Enable
0B
DISABLE normal mode controlled by LS1_ON
ENABLE enables LS1 for PWM mode
1B
LS1_EN
0
rw
Low-Side switch 1 Enable
0B
DISABLE disables LS1
ENABLE enables LS1
1B
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Low Side Switch
Low-Side Switch 2 Control
The register is reset by RESET_TYPE_3.
LS2_CTRL
Low-Side Switch 2 Control
Offset
Reset Value
16H
0000 0000B
7
6
5
4
3
2
1
0
LS2_OT_
STS
LS2_OC_
STS
LS2_VCL
_STS
Res
Res
LS2_ON
LS2_PWM
LS2_EN
rwh
rwh
rwh
r
r
rw
rw
rw
Field
Bits
Type
Description
LS2_OT_STS
7
rwh
Low-Side switch 2 Overtemperature Status
This bit indicates an overtemperature situation at the Low Side
switch
active overtemperature has occured
1B
passive no overtemperature occured
0B
LS2_OC_STS
6
rwh
Low-Side switch 2 Overcurrent Status
This bit indicates an Overcurrent situation at the Low Side
switch
active overcurrent has occured
1B
passive no overcurrent occured
0B
Res
5:3
r
Reserved
Always read as 0
LS2_ON
2
rw
Low-Side switch 2 On/Off
0B
OFF switches LS2 off
ON turns on LS2
1B
LS2_PWM
1
rw
Low-Side switch 2 PWM Enable
0B
DISABLE normal mode controlled by LS2_ON
ENABLE enables LS2 for PWM mode
1B
LS2_EN
0
rw
Low-Side switch 2 Enable
0B
DISABLE disables LS2
ENABLE enables LS2
1B
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PWM Generator
27
PWM Generator
27.1
Features
The PWM Generator provides up to three configurable PWM channels in order to drive the low-side switches LS1,
LS2 and the High Side switches HS1 and HS2 in a PWM mode.
Functional Features
•
•
•
programmable modulation frequency per channel
programmable duty-cycle per channel with glitch-free reprogramming
Duty-cycle range from 0 % ... 100 % in steps of 0.5 %
0
1
2
3
ls1_pwm_o
0
1
2
3
ls2_pwm_o
0
1
2
3
hs1_pwm_o
0
1
2
3
hs2_pwm__o
PWM 1
PWM2
XSFR
ccu6_int_o
TIMER 3
EXT_INT_O
TO_TRINP_SEL
ccu6_ch0__o
ccu6_ch1__o
0
1
2
3
0
1
ap_t2ex__o
0
1
ap_t21ex__o
MOD_PWM
Figure 178 Module block diagram of the PWM module and the included PWM switching matrix
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PWM Generator
27.2
Functional Description
The PWM Module comprises several functionalities concerning the PWM control of the System Power Switches
which are described in the following chapters.
27.2.1
PWM - Basic Functions
CCLK
FREQx_PREDIV
FREQx _DIV
DUTY_CYCLEx
/ 2PREDIV
/ DIV
PWM
channel x
PWM_CHx
Figure 179 Module block diagram of each single channel x
Figure 180 Programmable output clock frequency fPWM for a 24 MHz CCLK input frequency
The output frequency fPWMx is defined by:
⎞ ⎛ 1 ⎞
1
1
⎛
⎞ ⎛
⎟⎟ ⋅ ⎜
f PWMx = ⎜ FREQ⋅PREDIV ⎟ ⋅ ⎜⎜
⎟
⎝2
⎠ ⎝ (FREQ⋅ DIV +1) ⎠ ⎝ 200⎠
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PWM Generator
The ON-time of the connected power switches corresponds to the programmable duty-cycle and can be adjusted
from 0% to 100% with a fixed step size of 0,5 %. The hardware ensures, that any on-the-fly reprogramming of the
duty-cycle will avoid glitches at the modulated outputs completely. The output duty-cycle dcPWMx in % is given by:
⎛ DUTYCYCLEx ⎞
dcPWMx = ⎜
⎟[%]
2
⎝
⎠
27.2.2
PWM - Switches Control
pwm1
pwm2
lss1_pwm_o
ccu6_ch0
ccu6_ch1
lss1_pwm_inp_sel
Figure 181 PWM Control for LS1
pwm1
pwm2
lss2_pwm_o
ccu6_ch0
ccu6_ch1
lss2_pwm_inp_sel
Figure 182 PWM Control for LS2
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PWM Generator
pwm1
pwm2
hss1_pwm_o
ccu6_ch0
ccu6_ch1
hss1_pwm_inp_s
el
Figure 183 PWM Control for HS1
pwm1
pwm2
hss2_pwm_o
ccu6_ch0
ccu6_ch1
hss2_pwm_inp_s
el
Figure 184 PWM Control for HS2
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27.3
Register Definition
Table 106
Register Overview
Register Short Name
Register Long Name
Offset Address
Page Number
B0H
665
B1H
668
B2H
667
Register Definition, PWM-Module Registers
PWMGEN1_FREQ_DIV PWM1 Frequency Divider
PWMGEN1_DUTY_CY
CLE
PWM1 Duty Cycle
PWMGEN2_FREQ_DIV PWM2 Frequency Divider
PWMGEN2_DUTY_CY
CLE
PWM2 Duty Cycle
B3H
669
PWMGEN_CTRL
PWM Control Register
C8H
663
PWMGEN_OUT_CTRL
Low Side PWM Control Register
C9H
664
The registers are addressed bytewise.
27.3.1
PWM-Module Registers
PWM Control Register
The register is reset by RESET_TYPE_3.
PWMGEN_CTRL
PWM Control Register
7
Offset
Reset Value
C8H
0000 0000B
4
3
2
1
0
SPARE_64_7_6
T21_TRI
GG_SEL
T2_TRIG
G_SEL
PWM2_PD
_N
PWM1_PD
_N
rwp
rw
rw
rw
rw
Field
Bits
Type
Description
Res
7:4
r
Reserved
Always read as 0
T21_TRIGG_SEL
3
rw
Timer 21 Trigger Selection
0H
PWM2 Trigger PWM Unit 2 is triggering Timer 21
PWM1 Trigger PWM Unit 1 is triggering Timer 21
1H
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PWM Generator
Field
Bits
Type
Description
T2_TRIGG_SEL
2
rw
Timer 2 Trigger Selection
0H
PWM1 Trigger PWM Unit 1 is triggering Timer 2
PWM2 Trigger PWM Unit 2 is triggering Timer 2
1H
PWM2_PD_N
1
rw
Power Down for PWM Unit 2
0H
DISABLE PWM 2 unit is off
ENABLE PWM 2 unit is on
1H
PWM1_PD_N
0
rw
Power Down for PWM Unit 1
0H
DISABLE PWM 1 unit is off
ENABLE PWM 1 unit is on
1H
PWM Output Control Register
The register is reset by RESET_TYPE_3.
PWMGEN_OUT_CTRL
PWM Output Control Register
7
6
5
Offset
Reset Value
C9H
0000 0000B
4
3
2
1
0
HS2_PWM_INP_S
EL
HS1_PWM_INP_S
EL
LS2_PWM_INP_S
EL
LS1_PWM_INP_S
EL
rw
rw
rw
rw
Field
Bits
Type
Description
HS2_PWM_INP_SEL
7:6
rw
High Side 2 PWM Input Selection
0H
PWM1 High Side 2 PWM input connected to PWM1
module output
PWM2 High Side 2 PWM input connected to PWM2
1H
module output
CCU6_CH0 High Side 2 PWM input connected to capture
2H
compare unit channel 0 output
CCU6_CH1 High Side 2 PWM input connected to capture
3H
compare unit channel 1 output
HS1_PWM_INP_SEL
5:4
rw
High Side 1 PWM Input Selection
0H
PWM2 High Side 1 PWM input connected to PWM2
module output
PWM1 High Side 1 PWM input connected to PWM1
1H
module output
CCU6_CH1 High Side 1 PWM input connected to capture
2H
compare unit channel 1 output
CCU6_CH0 High Side 1 PWM input connected to capture
3H
compare unit channel 0 output
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PWM Generator
Field
Bits
Type
Description
LS2_PWM_INP_SEL
3:2
rw
Low Side 2 PWM Input Selection
0H
CCU6_CH0 Low Side 2 PWM input connected to capture
compare unit channel 0 output
CCU6_CH1 Low Side 2 PWM input connected to capture
1H
compare unit channel 1 output
PWM1 Low Side 2 PWM input connected to PWM1
2H
module output
PWM2 Low Side 2 PWM input connected to PWM2
3H
module output
LS1_PWM_INP_SEL
1:0
rw
Low Side 1 PWM Input Selection
0H
CCU6_CH1 Low Side 1 PWM input connected to capture
compare unit channel 1 output
CCU6_CH0 Low Side 1 PWM input connected to capture
1H
compare unit channel 0 output
PWM2 Low Side 1 PWM input connected to PWM2
2H
module output
PWM1 Low Side 1 PWM input connected to PWM1
3H
module output
PWM1 Frequency Divider Register
The register is reset by RESET_TYPE_3.
The following registers have a shadowing mechanism to avoid output glitches of the PWM module during on-thefly reprogramming. This special register type owns the attribute rws.
PWMGEN1_FREQ_DIV
PWM1 Frequency Divider Register
7
5
Offset
Reset Value
B0H
0100 0000B
4
0
FREQ1_PREDIV
FREQ1_DIV
rws
rws
Field
Bits
Type
Description
FREQ1_PREDIV
7:5
rws
Frequency prescaling divider value for PWM Unit 1
fPWM1 = fCCLK/(2FREQ1_PREDIV)/(FREQ1_DIV+1)/200
DIV1 CCLK/200/(FREQ1_DIV+1)
0H
DIV2 CCLK/400/(FREQ1_DIV+1)
1H
DIV4 CCLK/800/(FREQ1_DIV+1)
2H
...B ...
DIV128 CCLK/25600/(FREQ1_DIV+1)
7H
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PWM Generator
Field
Bits
Type
Description
FREQ1_DIV
4:0
rws
Frequency divider value 2 for PWM Unit 1
00H DIV1 CCLK/2FREQ1_PREDIV)/200
01H DIV2 CCLK/2FREQ1_PREDIV)/400
02H DIV3 CCLK/2FREQ1_PREDIV)/600
...B ...
1FH DIV32 CCLK/2FREQ1_PREDIV/6400
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PWM Generator
PWM2 Frequency Divider Register
The register is reset by RESET_TYPE_3.
PWMGEN2_FREQ_DIV
PWM2 Frequency Divider Register
7
5
Offset
Reset Value
B2H
0100 0000B
4
0
FREQ2_PREDIV
FREQ2_DIV
rws
rws
Field
Bits
Type
Description
FREQ2_PREDIV
7:5
rws
Frequency prescaling divider value for PWM Unit 2
fPWM2 = fCCLK/(2FREQ2_PREDIV)/(FREQ2_DIV+1)/200
DIV1 CCLK/200/(FREQ2_DIV+1)
0H
DIV2 CCLK/400/(FREQ2_DIV+1)
1H
DIV4 CCLK/800/(FREQ2_DIV+1)
2H
...H ...
DIV128 CCLK/25600/(FREQ2_DIV+1)
7H
FREQ2_DIV
4:0
rws
Frequency divider value 2 for PWM Unit 2
00H DIV1 CCLK/2FREQ2_PREDIV)/200
01H DIV2 CCLK/2FREQ2_PREDIV)/400
02H DIV3 CCLK/2FREQ2_PREDIV)/600
...H ...
1FH DIV32 CCLK/2FREQ2_PREDIV/6400
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PWM Generator
PWM1 Duty Cycle Register
The register is reset by RESET_TYPE_3.
PWMGEN1_DUTY_CYCLE
Offset
Reset Value
PWM1 Duty Cycle Register
B1H
0110 0100B
7
0
DUTY_CYCLE1
rws
Field
Bits
Type
Description
DUTY_CYCLE1
7:0
rws
Duty cycle value for PWM Unit 1
On-time percentage
PWMOFF 0% duty cycle, constantly off
0H
DUTY1 0,5% duty cycle
1H
DUTY2 1% duty cycle
2H
...B ...
C8H DUTY200 100% duty cycle, constantly on
C9H RESERVED reserved
...B ...
FFH RESERVED reserved
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PWM Generator
PWM2 Duty Cycle Register
The register is reset by RESET_TYPE_3.
PWMGEN2_DUTY_CYCLE
Offset
Reset Value
PWM2 Duty Cycle Register
B3H
0110 0100B
7
0
DUTY_CYCLE2
rws
Field
Bits
Type
Description
DUTY_CYCLE2
7:0
rws
Duty cycle value for PWM Unit 2
On-time percentage
PWMOFF 0% duty cycle, constantly off
0H
DUTY1 0,5% duty cycle
1H
DUTY2 1% duty cycle
2H
...B ...
C8H DUTY200 100% duty cycle, constantly on
C9H RESERVED reserved
...B ...
FFH RESERVED reserved
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Switched Capacitor Amplifier
28
Switched Capacitor Amplifier
28.1
Functional Description
The switched capacitor amplifier (sc-amplifier) in Figure 28-1 can be used to measure near ground differential
voltages via the 8-bit ADC. Its gain is digitally programmable through internal control registers. The circuit employs
a Correlated Double Sampling technique (CDS) to cancel offset voltage and low frequency (1/f) noise of the
operational amplifier. A small constant voltage, that is derived from the bandgap reference voltage, is added to the
sc-amplifier output stage. This feature is useful in order to adapt the output voltage to the input range of the ADC,
if the overall sc-amplifier has a negative input offset voltage. The ADC converts the analog input voltage to an 8bit data word which is further processed in the digital post-processing unit see (see Chapter 22).
Linear calibration has to be applied to achieve high gain accuracy.
Figure 28-1 shows how the sc-amplifier can be used as a low-side current sense amplifier where the motor current
is converted to a voltage by means of a shunt resistor Rsh. A differential amplifier input is used in order to eliminate
measurement errors due to voltage drop across the stray resistance Rstray and differences between the external
and internal ground. The operating voltage range of the amplifier inputs is referred to the ground of the integrated
circuit. If the voltage at one or both inputs is out of the operating range it has to be taken into account that the input
circuit is overloaded and needs a certain specified recovery time. Furthermore an external series resistor is
required to limit the reverse current in case the input voltage goes temporarily below the minimum allowed limit of
0.3V.
In general, the external low pass filter should provide suppression of EMI and anti-aliasing filtering for the (sampled
data) switched-capacitor amplifier. The low pass capacitors must be much larger than the input sampling
capacitors of the amplifier to keep the sampling error at the filter capacitance negligible. (For this reason, the antialiasing filter cannot be implemented internally in a cost effective way.)
VBAT
M
VREF
1.23V
Motor
Current
VP
Anti-Aliasing
LP Filter
RLP
OA_IP
SC Amplifier
Low Pass
Filter
8
RSH
CLP
RLP
VN
8
8-bit ADC
LP
OA_IN
RStray
GNDA
SC_CLK_2M
Ext. GND
3 bit
Gain
Control
VOVS
2 bit
Corner
Frequency
Control
Figure 28-1 Simplified application diagram
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Switched Capacitor Amplifier
28.1.1
Main Amplifier Characteristics
The main characteristics are derived from the main underlying application conditions
•
•
•
Programmable gain: OPA_GAIN = 8, 12, 16, 20
A suitable sampling frequency of the sc-amplifier is fs = 2 MHz. In the SOC this is the system clock divided by
the number of clock cycles needed for one A/D-conversion.
The anti-aliasing filter has to provide sufficient attenuation at fs-fb (approximately 50dB). Where fb is the
intended signal bandwidth fb < fs/2. Attenuation of interfering high frequency also helps to achieve EMI
robustness
Example: required settling time is 5 μs, which corresponds to a time constant of 3 tau. The resulting -3dB
corner frequency of a single pole anti aliasing filter is ~ 95kHz. The resistor for this filter should be RLP = 2.7kΩ.
This results in a capacitor CLP = 620 pF.
The equivalent input resistance Req of the sampling input capacitors is expected to be less than 500 kΩ. The
average input current flowing through the low pass resistor RLP causes a voltage measurement error
proportional to the value of RLP. RLP = 2.7kΩ would lead to a measurement error of less than 1%. Since this
error is almost constant 0over the lifetime it can be corrected through system calibration.
28.2
SC-Amplifier Transfer Characteristic
The transfer characteristic can be described by the equation
Vod = ( Adm ⋅ (Vid + Vidos ) ± Acm ⋅ Δ Vicm ) + Voos
(28.1)
wherein the parameters and variables are defined as follows:
•
•
•
•
•
•
•
•
•
•
Vid = VOA_IP - VOA_IN - differential input voltage
Vios - input referred differential mode offset voltage
Voos - output offset voltage, not including differential mode offset
Vicm = (Vip+Vim)/2 - common mode voltage at the inputs of the amplifier
∆Vicm = Vicmmax - Vicmmin
∆Vios (Tj) Temperature drift of the input offset
∆Voos (Tj) Temperature drift of the output offset
Adm - programmable differential gain
Acm - common mode gain due to circuit imperfections (predominantly capacitor mismatch)
Vod - differential output voltage
The amplification factors are defined as
Adm
Δ Vcim = 0
=
Δ Vod
Δ Vid
(28.2)
and
Acm
Δ Vid = 0
User’s Manual
=
Δ Vocm
1
=
Δ Vicm
CMR
(28.3)
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Switched Capacitor Amplifier
wherein CMR is the common mode rejection (suppression) of the circuit. In many applications it is useful to
describe the error caused by common mode gain with the parameter Common Mode Rejection:
CMMR =
Adm
Acm
(28.4)
With these definitions the transfer function becomes:
Δ Vicm ⎞
⎛
Vod = Adm ⋅ ⎜ Vid + Δ Vidos ±
⎟ + Δ Voos
CMMR ⎠
⎝
(28.5)
Note: Remark all offsets will be calibrated during production. The remaining offsets (∆Vios (Tj), ∆Voos (Tj)) are
mainly caused by temperature drift (with effective gain of 25 the expected temperature drift is +-2LSB)
28.3
ADC Code Calculation
The differential output voltage Vod is converted to an ADC code by the following equation:
⎞
⎛ Vod
ADC 2 out = trunc ⎜
⋅ 1 . 247 + 1 ⎟
⎝ VLSB
⎠
(28.6)
wherein the parameter VLSB is defined as follows:
VLSB
=
Vref
256
(28.7)
where Vref is 1.227 V @ 27 °C:
28.4
Operational Amplifier Control Register
The next chapter lists the configuration possibilities of the switched capacitor amplifier used for external current
sensing.
Table 28-1 Register Overview
Register Short Name
Register Long Name
Offset Address
Reset Value
A7H
0000 0000B
Operational Amplifier Control Register,
OPA_CTRL_STS
Operational Amplifier Control
The registers are addressed bytewise.
The following register consists of control and status bits. This Register is cleared by every reset.
Operational Amplifier Control and Status
The register is reset by RESET_TYPE_3.
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Switched Capacitor Amplifier
OPA_CTRL_STS
Operational Amplifier Control and Status
Offset
Reset Value
A7H
0000 0000B
7
6
5
4
1
0
Res
OPA_UPT
HWARN_*
OPA_LOT
HWARN_*
OPA_GAIN
OPA_EN
r
rw
rw
rw
rw
Field
Bits
Type
Description
Res
7
r
Reserved
Always read as 0
OPA_UPTHWARN_STS
6
rw
Operational Amplifier Upper Threshold Warning (MU)
Status
0B
INACTIVE no status set
ACTIVE status set
1B
OPA_LOTHWARN_STS
5
rw
Operational Amplifier Lower Threshold Warning (MU)
Status
0B
INACTIVE no interrupt status set
ACTIVE at least one interrupt status set
1B
OPA_GAIN
4:1
rw
Operational Amplifier Gain Setting
x00xB 8 Gain Factor 8
x01xB 12 Gain Factor 12
x10xB 16 Gain Factor 16
x11xB 20 Gain Factor 20
OPA_EN
0
rw
Operational Amplifier Enable
0B
DISABLE OPA switched off
ENABLE OPA switched on
1B
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On-Chip Debug Support (OCDS)
29
On-Chip Debug Support (OCDS)
The TLE983x includes an OCDS system, which provides convenient debugging, controlled directly by an external
tool via debug interface pins.
OCDS Components
•
•
Debug Interface
OCDS Module
On-Chip Debug Support (OCDS)
The OCDS system (Figure 185) supports a broad range of debug features including breakpoints and the tracing
of memory locations. A typical application of the OCDS is to debug user software running on the TLE983x in a real
time system environment.
Physical
Interface
On-Chip Debug System (OCDS)
Debug Interface
OCDS
Debugger
Tool
DAP
JTAG
2
Monitor
RAM
Break I/F
Injection I/F
CPU status
CPU
SoC
P11_Debug-Overall_Structure
Figure 185 OCDS Block Diagram
The OCDS is controlled by an external tool via the Debug Interface. The physical interface is DAP with two pins.
The memory mapped OCDS registers are accessible via the DAP interface. As an alternative the OCDS can be
controlled by a debug monitor program, which communicates with the tool over a user interface like LIN. The
OCDS system interacts with the CPU through a software debug monitor.
OCDS System Features
•
•
•
•
•
•
•
Hardware and software breakpoints
Trigger action can be CPU-halt, monitor call and/or data transfer
Read/write access to the whole address space
Single stepping
Non intrusive debugging (no debug monitor needed)
Debug also possible over user interface like LIN (with debug monitor)
DAP interface
29.1
Debug Interface
The Debug Interface allows to access OCDS resources. Data can be transferred to/from all on-chip memories and
memory mapped control registers.
User’s Manual
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Rev. 1.0, 2011-12-23
TLE983x
On-Chip Debug Support (OCDS)
Features and Functions
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•
•
•
Independent interface for OCDS
DAP tool access interfaces
Generic memory access functionality
Independent data transfer channel for e.g. programming of flash memory
Attention: The DAP clock frequency must be below the current CPU frequency.
DAP (Device Access Port) Interface
The DAP interface is a device access port standardized for Infineon microcontrollers. It reduces the pin count to
two pins and offers high noise immunity and robustness.
This interface consists of the signals:
•
•
DAP0 - clock
DAP1 - Serial data input/output
29.2
OCDS Module
The application of the OCDS Module is to debug user software running on the CPU in the customer’s system. This
is done with an external debugger, which controls the OCDS Module via the independent Debug Interface.
Features
•
•
•
•
•
•
Hardware, software and external pin breakpoints
Hardware trigger generation for breakpoints and external pin output
– Four single address or two address ranges for instruction or data
– Combination of instruction (range) and data address (range)
– Combination of data address (range) and data value (range)
– Task ID, optional in combination with address (range) for instruction or data
– Masked comparisons for addresses and data
The OCDS can also be configured by a debug monitor program
Single stepping with monitor or CPU halt
Higher priority interrupts can still be served if CPU is halted
Instruction pointer visible in Halt Mode
Basic Concept
The on chip debug concept is split up into two parts. The first part covers the generation of debug events and the
second part defines what actions are taken when a debug event is generated.
•
•
Debug events:
– Hardware Breakpoints
– Software Breakpoints
–
Debug event actions:
– Halt Mode of the CPU
– Call a Monitor
User’s Manual
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Rev. 1.0, 2011-12-23
TLE983x
On-Chip Debug Support (OCDS)
Debug Event Sources
Hardware
Triggers
Debug Actions
HALT the CPU
Programmable
combination
Debug
Event
Processing
SBRK Instruction Executed
CALL a Monitor
Transfer Triggered
OCDS_Basic_Concept.vsd
Figure 186 OCDS Concept: Block Diagram
29.2.1
Debug Events
The Debug Events can come from a few different sources.
Hardware Breakpoints
The Hardware Breakpoint is a debug-event, raised when a single or a combination of multiple trigger-signals are
matching with the programmed conditions. Typically hardware triggers are specified by the execution of an
instruction from a predefined instruction address.
Software Breakpoints
A special SBRK (Software BReaK) instruction is defined. It can be used for instance by a debugger to temporarily
replace code held in RAM in order to implement Software Breakpoints. When the SBRK instruction has been
decoded and it reaches the execute stage, the whole pipeline is canceled including the SBRK instruction. This
implies that the next instruction will be fetched from the address the SBRK was found at.
The further behavior is dependent on how OCDS has been programmed:
•
•
if the OCDS is enabled and the software breakpoints are also enabled, then the CPU goes into Halt Mode
if the OCDS is disabled or the software breakpoints are disabled, then the Software Break Trap is executed
29.2.2
Debug Actions
When the OCDS is enabled and a debug event is generated, one of the following actions is taken:
Halt Mode
Upon this Action the OCDS Module sends a Break-Request to the CPU.
The CPU accepts this request, if the OCDS Break Level is higher than current CPU priority level. In case a BreakRequest is accepted, the system suspends execution with halting the instruction flow.
The Halt Mode can be still interrupted by higher priority user interrupts. It then relies on the external debugger
system to interrogate the target purely through reading and updating via the debug interface.
User’s Manual
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Rev. 1.0, 2011-12-23
TLE983x
On-Chip Debug Support (OCDS)
Call a Monitor
One of the possible actions to be taken when a debug event is raised is to call a Monitor Program. This quick entry
to a Monitor allows a flexible debug environment to be defined which is capable of satisfying many of the
requirements for efficient debugging of a real time system. In the common case the Monitor has the highest priority
and can not be interrupted by any other requesting source.
It is also possible to have an Interruptible Monitor Program. In such a case safety critical code can be still served
while the Monitor (Debugger) is active, which gives a maximum flexibility to the user.
User’s Manual
677
Rev. 1.0, 2011-12-23
Edition 2011-12-23
Published by
Infineon Technologies AG
81726 Munich, Germany
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