LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide June 2009 Revision: EB26_02.6 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Introduction This document describes the features and functionality of the LatticeMico32™/DSP Development Board for LatticeECP2™ devices. This board is designed as a hardware platform for design and development with the LatticeMico32 microprocessor, as well as for the LatticeMico8™ microcontroller, and for various DSP functions. Note: There are two versions of this board, named version 1 (v1) and version 2 (v2). Differences between the v1 and v2 boards are described in this document as required. The appendices of this document contain schematics of both versions. In summary, v2 boards include the following changes: • Copper plating indicates v2 in text (HPEminiv2) • A pushbutton has been added for USB reset. This allows the FPGA to be reset independently from the USB Cable circuitry. • Boards are populated with a MachXO-2280 device (v1 boards were populated with a MachXO-640). • Board color is blue, and board is fully RoHS compliant. This document describes the numerous functional elements of the board. The schematics of the board can be found in the appendices at the end of this document. Features • Lattice ECP2-50 FPGA with 48 kLUTs, 387 kbit of Embedded Block RAM, 18 sysDSP™ blocks, 72 18x18 multipliers, 6 PLLs, and 500 user I/O pins • Lattice MachXO™ with 640 LUTs and 6.1 kbit of RAM • Serial Flash with at least 8 Mbit for non-volatile storage of FPGA configuration data. • DDR SODIMM socket for DDR SDRAM modules (DDR1, 100-133MHz, 32-bit data bus) • Parallel Flash 2x128 Mbit, organized as 8M 32-bit words • SRAM 2x4 Mbit, organized as 256K 32-bit words • USB 2.0 connector and integrated ispDOWNLOAD® cable for JTAG programming the FPGA • Flywire connector for programming using an ispDOWNLOAD cable (available separately) • 9-pin RS232 serial port (230 Kbps) • 15-pin VGA (64 color encoding) • Ethernet 10/100 M full/half duplex • Two USB 2.0 compatible host connectors • One USB 2.0 compatible target connector • One USB OTG (On-the-Go) connector • Expansion connector with 46 user I/Os • 12x12 prototyping area for the integration of individual components (connections to the FPGA) • Sigma Delta D/A converter • Two SATA interfaces with four LVDS signal pairs for high-speed data transfer (Note: Full SATA implementation is not supported) • AC’97 Stereo Audio Codec with line input and output • LCD connector for character displays, with contrast potentiometer • 25 MHz oscillator with clock distribution buffer 2 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor • Eight LEDs with test points for each LED • Two-character 7-segment display • Green LED to indicate the proper operation of the 3.3V and 2.5 V power supplies • Blue LED which shows the configuration status (“DONE”) • Red LED to signal that the FPGA can be configured (“INIT”) • Yellow LED indicating the FPGA PROGRAM# I/O is asserted (“PROGRAM#”) • 3x4 key matrix • Four DIP switches • Single step key • Program key to initiate the configuration sequence of the FPGA from SPI Flash memory • Reset key • 5V power supply • Switching regulator for the generation of the 3.3V I/O voltage, the 2.5V DDR and LVDS voltages and the 1.2V core voltage Getting Started 1. Unpack all components and compare them to the packaging list. All boards leave the factory fully tested. Detailed information can be found in the Troubleshooting section of this document. 2. Place the board in front of you so that the keyboard is on the left side. 3. Take the regulated DC power supply which has been supplied with the package and connect it to the power jack on the board. Two green power-on LEDs will illuminate to confirm that power is correctly applied to the board (regulating 5V to 3.3V and 2.5V). 4. To check the basic functionality, please see the Troubleshooting section of this document. A number of example and demonstration programs are available for the LatticeMico32/DSP Development Board for LatticeECP2. Check the Lattice web site at: www.latticesemi.com/boards (and navigate to the correct board) to find additional documentation, such as the LatticeMico32 Tutorial, which describes how to use the LatticeMico32 System software to develop microprocessor solutions for this board. Additional sample programs are included with the LatticeMico32 System software. Check the software help to find these examples. Note: Unless described otherwise, positional statements (left, right etc.) refer to the board positioned in front of you so that the key pad is in the bottom left corner. Related Literature • LatticeMico32 Development Kit User’s Guide: This guide includes a tutorial for using the LatticeMico32 System software with the LatticeMico32/DSP Development Board. This document is written for the first generation board (with LatticeECP-33 FPGA), which is similar to the board described in this document. While this document may be useful, please remember there are differences in the designs of these boards. Be sure to check the Lattice web site for updates to this document as well. These documents can be downloaded from the Lattice web site at: www.latticesemi.com/boards. Select the FPGA/FPSC Boards -> LatticeMico32/DSP Development board for LatticeECP2 and click on the User Manuals link. 3 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Overview The following block diagram gives you an overview of the functionality of your LatticeMico32/DSP Development Board. Subsequent pages illustrate the position of connectors, user interfaces, and modules. Figure 1. LatticeMico32/DSP Development Board Block Diagram AC97 Ethernet 10/100 RS232 LatticeECP2-50 To PC 672 fpBGA PRG 3p LVDS SATA 3p LVDS SATA Expansion Connector Table 1. Board Defaults Item LatticeECP2-50 LCD Backlight (X5) Configuration Switch Type FPGA Default Status Programmed Jumper Open TMS Switch Off (Down) Sigma Delta DAC Converter Jumper Open Contrast Control Reostat Variable 4-place DIP - Logic 1 Switch SODIMM DDR 400 Setting (X18) Jumper Off Comments The bitstream is based on Example PlatformA and the LED7SegsTest_ecp2 project. The LED7SegsTest_ecp2.mem and LED7SegsTest_ecp2.bit files are included in the LED7SegsTest_ecp2 project. Visual indications of operation are: • Left to Right and Right to Left scanning of the 8 LEDs. • Upcount and roll over of the 7 segment displays from 0 to 99 decimal at ~1 second intervals. Backlight is off. LatticeECP2-50 FPGA can be programmed. Not set to any specific level. Logic 0 on selected pins - see Table 18. Shorts Pins Set to below DDR400 memory use. 1 and 2 4 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Peripheral Interfaces This section describes all peripheral interfaces of the LatticeMico32/DSP Development Board for LatticeECP2 in alphabetical order. Figure 2 shows the position of peripheral interfaces available on the board. Figure 2. Peripheral Interfaces (Version 1 Board Shown in this Figure) Power Plug RS232 Connector Audio Line In Line Out Ethernet 10/100M VGA Connector Mini USB OTG Connector USB Host Connector 2.5V Testpoint 3.3V Testpoint DDR SDRAM Sockel GND Testpoint 1.2V Testpoint SATA LVDS Connectors CLK Testpoint Flywire Connector High-Speed USB for Configuration Expansion Connector Sigma Delta DAC Connector LCD Connector In Version 2 of this board, the on-board USB cable circuit has been updated. USB Reset Pushbutton (v.2 board) 1. A USB RESET# pushbutton has been added. The Version 1 board includes a single Reset pushbutton that resets both the LatticeECP2 FPGA and the USB cable. The addition of the USB RESET# button allows the FPGA to be reset independent from the USB cable circuit. MachXO-640 (v.1 board), MachXO-2280 (v.2 board) 2. In the Version 2 board, the MachXO device has been changed from a MachXO640 to a MachXO2280 device. 5 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Audio Interface The audio interface has two connectors for 3.5 mm stereo jacks. The upper one is for line-out, the lower for line-in. They are connected to the audio codec LM4549B by National Semiconductor. Table 2. Audio Codec U1001 Pin Definitions Pin FPGA Pin Pin 6 AC97_BITCLK Signal Name B24 47 AC97_EAPD Signal Name FPGA Pin 2 AC97_EXT_CLK D25 11 AC97_RESET# B25 8 AC97_SDATA_IN C26 5 AC97_SDATA_OUT C25 10 AC97_SYNC D24 C23 Detailed information on the audio codec can be found at the National Semiconductor website at www.national.com. Clock Sources A 25MHz oscillator supplies the FPGA (pin AD15), the CPLD (pin A8), the Ethernet controller and the Expansion Connector (pin 29 of X12). The frequency can be measured via testpoint CLK. To generate other clock frequencies use the PLLs of the FPGA. You can find detailed information on the usage of the PLLs on the Lattice website and in the LatticeECP2/M Family Data Sheet. The USB controller requires a 24MHz quartz for configuration. Another 12MHz quartz supplies the USB host/peripheral controller. Note: Since the Ethernet controller demands a 25MHz clock, no other basic clock can be used. Use the PLLs of the FPGA to generate custom frequencies. DDR SODIMM Socket for DDR SDRAM Modules The board includes a standard DDR1 SODIMM socket with 200 contacts (DDR SDRAM Module is not included). The upper four bytes of the data bus (D[63:32]) are not connected. Thus, only half of the capacity of the memory module is available. The DDR SODIMM socket is factory configured to provide a regulated 2.5V. DDR400 modules require a power supply of 2.6V (±0.1V). Using a jumper on connector X21 (below the 5V power supply jack), the DDR power supply can be changed to suit the needs of DDR400 modules. Note: If you want to use the DDR SDRAM interface with a 16-bit data bus, provide your HDL design with an additional input port that is assigned to pin P9 of bank 6 (connected to schematic net DDR_VREF). Do not use this signal in your design. Deactivate the internal pull-up of the pin in the ispLEVER software. It safeguards the DDR RAM memory from getting an incorrect supply voltage which will happen when the pin is unused at a data bus width of 16 bits. When using a 32-bit data bus, you do not have to assign this pin—ispLEVER will take care of it automatically. 6 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 3. DDR SODIMM Socket (X4) - Data Bus Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 11 DDR_DQS0 AE6 47 DDR_DQS2 AB3 12 DDR_DM0 AF6 48 DDR_DM2 AB2 5 DDR_DQ0 AD9 41 DDR_DQ16 AE2 7 DDR_DQ1 AD4 43 DDR_DQ17 AD1 13 DDR_DQ2 Y5 49 DDR_DQ18 AD2 17 DDR_DQ3 AD8 53 DDR_DQ19 AD3 6 DDR_DQ4 AC8 42 DDR_DQ20 AC1 8 DDR_DQ5 AB8 44 DDR_DQ21 AC2 14 DDR_DQ6 AF7 50 DDR_DQ22 Y5 18 DDR_DQ7 AE7 54 DDR_DQ23 Y6 25 DDR_DQS1 AA6 61 DDR_DQS3 T1 26 DDR_DM1 AB6 62 DDR_DM3 T2 19 DDR_DQ8 AF5 55 DDR_DQ24 V1 23 DDR_DQ9 AE5 59 DDR_DQ25 U1 29 DDR_DQ10 AD5 65 DDR_DQ26 P4 31 DDR_DQ11 AC5 67 DDR_DQ27 P5 20 DDR_DQ12 AF4 56 DDR_DQ28 P6 24 DDR_DQ13 AE4 60 DDR_DQ29 N3 30 DDR_DQ14 AD4 66 DDR_DQ30 N4 32 DDR_DQ15 AC4 68 DDR_DQ31 N5 Table 4. DDR SODIMM Socket (X4) - Address Bus Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 112 DDR_A0 AD10 111 DDR_A1 AD14 110 DDR_A2 AB12 109 DDR_A3 AC12 108 DDR_A4 AD12 107 DDR_A5 AB13 106 DDR_A6 AC13 105 DDR_A7 AD13 102 DDR_A8 AB15 101 DDR_A9 AB14 115 DDR_A10 AC10 100 DDR_A11 AC14 99 DDR_A12 AD14 123 DDR_A13 AB10 117 DDR_BA0 AD7 116 DDR_BA1 AC7 Table 5. DDR SODIMM Socket (X4) - Other Signals Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 35 DDR_CK0+ AE12 37 DDR_CK0- AF12 160 DDR_CK1+ Y1 158 DDR_CK1- AA2 96 DDR_CKE0 AF11 95 DDR_CKE1 AF10 118 DDR_RAS# AE9 119 DDR_WE# AE10 120 DDR_CAS# AF9 121 DDR_S0# AF8 122 DDR_S1# AE8 7 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Ethernet Interface An Intel LXT971A is included for Ethernet PHY. This is an IEEE-compliant Fast Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications, full and half duplex. For more information, please refer to the data sheet of this component. Each board has its own unique MAC address so that no conflicts with other components in the network will occur. Specify this MAC address for synthesis of Ethernet designs. It can be found on the sticker at the bottom side of your board. Table 6. Ethernet Controller U0801 Pin Definition Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 4 HPE_RESOUT# AE24 42 ETH_MDIO N25 43 ETH_MDC M26 45 ETH_RXD3 W25 46 ETH_RXD2 W26 47 ETH_RXD1 Y26 48 ETH_RXD0 AA26 49 ETH_RXDV R25 52 ETH_RXCLK L26 53 ETH_RXER P26 54 ETH_TXER U26 55 ETH_TXEN R26 56 ETH_TXCLK L25 57 ETH_TXD0 V26 58 ETH_TXD1 V25 59 ETH_TXD2 V24 60 ETH_TXD3 V23 62 ETH_COL P25 63 ETH_CRS N26 64 ETH_MDINTR# W24 Expansion Connector The expansion connector provides 46 user I/Os connected to the FPGA. The remaining pins serve as power and clock supplies for expansion boards. The expansion connector is configured as two 2x20 100mil centered pin headers (X12 and X13). Tables 7 and 8 describe the connections to the FPGA. Table 7. Expansion Connector X13 Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 1 GND — 2 NC (coding) — 3 VCC2V5 — 4 EXPCON_IO29 H4 5 EXPCON_IO30 H5 6 EXPCON_IO31 H6 7 EXPCON_IO32 H7 8 EXPCON_IO33 H8 9 EXPCON_IO34 G1 10 EXPCON_IO35 G2 11 EXPCON_IO36 G3 12 EXPCON_IO37 G4 13 EXPCON_IO38 F1 14 EXPCON_IO39 F2 15 EXPCON_IO40 F5 16 EXPCON_IO41 F6 17 EXPCON_IO42 E1 18 EXPCON_IO43 E2 19 EXPCON_IO44 E3 20 EXPCON_IO45 E4 21 VCC5V0 — 22 GND — 23 VCC2V5 — 24 GND — 25 VCC3V3 — 26 GND — 27 VCC3V3 — 28 GND — 29 EXPCON_OSC — 30 GND — 31 EXPCON_CLKIN — 32 GND — 33 EXPCON_CLKOUT — 34 GND — 35 VCC3V3 — 36 GND — 8 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 7. Expansion Connector X13 (Continued) Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 37 VCC3V3 — 38 GND — 39 VCC3V3 — 40 GND — FPGA Pin Pin Signal Name FPGA Pin Table 8. Expansion Connector X14 Pin Signal Name 1 HPE_RESET# — 2 GND — 3 EXPCON_IO0 R1 4 EXPCON_IO1 R2 5 EXPCON_IO2 P1 6 EXPCON_IO3 P2 7 EXPCON_IO4 N1 8 EXPCON_IO5 M6 9 EXPCON_IO6 L2 10 EXPCON_IO7 L5 11 EXPCON_IO8 L6 12 EXPCON_IO9 L7 13 EXPCON_IO10 L8 14 EXPCON_IO11 K1 15 EXPCON_IO12 K2 16 EXPCON_IO13 K3 17 EXPCON_IO14 K4 18 EXPCON_IO15 K5 19 GND — 20 VCC3V3 — 21 EXPCON_IO16 K6 22 GND — 23 EXPCON_IO17 K7 24 GND — 25 EXPCON_IO18 K8 26 GND — 27 EXPCON_IO19 J1 28 EXPCON_IO20 J2 29 EXPCON_IO21 J3 30 GND — 31 EXPCON_IO22 J4 32 EXPCON_IO23 J5 33 EXPCON_IO24 J8 34 GND — 35 EXPCON_IO25 J9 36 EXPCON_IO26 H1 37 EXPCON_IO27 H2 38 CARDSEL# D1 39 EXPCON_IO28 H3 40 GND — ispDOWNLOAD Cable Connector There are two ways to configure the programmable Lattice devices on the board. The USB connector requires a standard USB cable, and is described later in this document. Connector X3 is available to connect a Lattice ispDOWNLOAD cable. An ispDOWNLOAD cable is used to program IEEE 1532 compliant programmable devices. Lattice provides either a parallel port or a USB port download cable. The FPGA and CPLD are programmed using the cable and ispVM® programming software. Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP2 FPGA device and render the board inoperable. DIP switch SW03021 controls the device to be configured: the FPGA or the MachXO. If it is on (in top position), the MachXO is selected; if off, the FPGA is selected. The ispVM System software can be downloaded from the Lattice web site at: www.latticesemi.com/ispvm. Note: Do not change the switch when the configuration of a device is in progress! 1. Caption on the board: CONF. 9 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Note: The board as configured from the factory, has a built-in USB ispDOWNLOAD cable. The built-in cable and an external ispDOWNLOAD cable cannot be used at the same time. Doing so may damage the board. Table 9. ispDOWNLOAD Connector X4 Pin Definition Pin Signal Name Pin 2 Signal Name 1 VCC3V3 JTAG_TDO 3 JTAG_TDI 4 JTAG_PROG 5 JTAG_TRST 6 JTAG_TMS 7 GND 8 JTAG_TCK 9 JTAG_DONE 10 JTAG_INIT LCD Connector (Optional) The LCD connector is a 16-pin header with a standard pinning for LCD modules with back-light (e.g. Truly MTCC202DPRN-1N). In order to use an LCD module, attach it to the connector via a 16-pin ribbon cable. Note: The LCD module is tied to a 5V supply. The LatticeECP2-50 to LCD interface is 3.3V. Put a jumper on connector X6 to turn on the backlight of the LCD. The contrast of the LCD module is adjustable with the potentiometer R0526, because different LCD modules need different voltages for the best contrast. Figure 3. LCD Panel (Not Included) Table 10. LCD Connector X6 Pin Definition Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 1 GND — 2 VCC5V — 3 CONTRAST — 4 LCD_REGSEL K24 5 LCD_RW J24 6 LCD_ENABLE J22 7 SEG_A# M24 8 SEG_B# N23 9 SEG_C# M22 10 SEG_D# M21 11 SEG_E# M20 12 SEG_F# L22 13 SEG_G# L21 14 SEG_DP# K22 15 BACKLIGHT — 16 GND — SATA Interfaces Find the jacks X15 and X16 for connecting SATA cables on the right side of the board. This provides a convenient method for evaluating or using LVDS signals with the FPGA. This board does not support implementation of a full SATA solution. These SATA jacks have differential nets with high-speed signals connected to them. See Table 11 for SATA pinning information. The positive signal is connected with a plus (+), the negative with a minus (-). Every differential signal pair can act as receiver or transmitter depending on the configuration of the FPGA. 10 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 11. SATA Jacks X15 (Left Column) and X16 (Right Column) Pin Definition Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 2 SATA_X1D0+ M4 2 SATA_X2D0+ U3 3 SATA_X1D0- M5 3 SATA_X2D0- U4 5 SATA_X1D1+ P3 5 SATA_X2D1+ V2 6 SATA_X1D1- R3 6 SATA_X2D1- W2 Serial Interface The board includes an RS232 serial interface port. The interface provides transmit (TX), receive (RX), and hardware handshaking. The Maxim MAX3232 data sheet provides detailed information on the interface circuit. A 9-pin female to 9-pin female null modem cable is required. Table 12. Serial Interface X9 Pin Definition Signal Sub-D Pin FPGA Pin Direction RS232 Function 3 RS_TXD_LVTTL K26 Out Transmit Data 7 RS_RTS_LVTTL K25 Out Request to Send 2 RS_RXD_LVTTL J25 In Receive Data 8 RS_CTS_LVTTL J26 In Clear to Send Sigma Delta D/A Converter The board includes a low-pass filter connected to a dedicated pin (C14) of the FPGA. With this, a sigma delta converter can be realized. Great results can be achieved by using a resolution of 8 to 10 bits. Example VHDL code is provided. Power Supply Four different voltages are needed: 3.3V I/O voltage, 2.5V DDR and LVDS voltages as well as 1.2V core voltage. The 3.3V supply draws up to 1A, the 2.5V and 1.2V supplies up to 2A of current. For more information, see the power supply information in the Components section of this document. Test Points In order to check the various voltage levels used, several test points are provided. There is one test point for 1.2V, 2.5V, 3.3V, one for ground, and one for accessing the 25MHz oscillator. The 25MHz clock signal can be checked with another test point. USB Host/Peripheral Interface There are one mini USB OTG and two USB host connectors on board. These are connected to the Cypress CY7C67300 USB Host/Peripheral Controller U0702. This controller is compliant with the Universal Serial Bus Specification 2.0. You can transmit and receive serial data at both full-speed (12 Mbps) and low-speed (1.5 Mbps) data rates. For more information, please refer to the data sheet of the USB controller. U0703 and U0704 are USB power control switches, which must be enabled by the user via the USB PWEN signals. The USB OC signal pulls low to indicate voltage, current and thermal issues. Table 13. USB GPIO Connections (U0702) Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 94 USB_GPIO0 AE20 93 USB_GPIO1 AC18 92 USB_GPIO2 AE13 91 USB_GPIO3 AB20 90 USB_GPIO4 AA20 89 USB_GPIO5 AF19 87 USB_GPIO6 AE19 86 USB_GPIO7 AD19 11 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 13. USB GPIO Connections (U0702) (Continued) Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 66 USB_GPIO8 AC19 65 USB_GPIO9 AB19 61 USB_GPIO10 AA19 60 USB_GPIO11 AF18 59 USB_GPIO12 AE18 58 USB_GPIO13 AD18 57 USB_GPIO14 AC18 56 USB_GPIO15 AB18 55 USB_GPIO16 AF17 54 USB_GPIO17 AE17 53 USB_GPIO18 AD17 52 USB_GPIO19 AC17 50 USB_GPIO20 AB17 49 USB_GPIO21 AF16 48 USB_GPIO22 AE16 47 USB_GPIO23 AF15 46 USB_GPIO24 AE15 45 USB_GPIO25 AF14 44 USB_GPIO26 AE14 43 USB_GPIO27 AF13 42 USB_GPIO28 AE13 41 USB_GPIO29 - Table 14. Additional USB GPIO Connections (U0702, U0704, and U0704) Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin U0703:1 USB_PWEN0 Y17 U0703:2 USB_OC0# AA16 U0703:4 USB_PWEN1 Y16 U0703:3 USB_OC1# Y20 U0704:1 USB_PWEN2 AA21 U0704:2 USB_OC2# Y19 U0702:85 HPE_RESOUT# AE24 USB Configuration Connector In addition to the ispDOWNLOAD connector, the FPGA and the MachXO can also be configured by a standard USB connection. The USB target connector is wired to the Cypress CY7C68013A device (U0301). This programming method requires the use of the ispVM System software. This can be downloaded from the Lattice web site at: www.latticesemi.com/ispvm. This connection will appear to the ispVM System software as if a regular USB-based ispDOWNLOAD cable is connected to the PC. The CY7C68013A in combination with the MachXO CPLD acts as a built-in ispDOWNLOAD cable. The MachXO is connected to the ispDOWNLOAD Connector X3, and can program the LatticeECP2-50. The LatticeECP2-50 can be programmed when DIP switch SW0302 is ‘off’ (pushed down). Note: Like the ispDOWNLOAD connector, the MachXO drives the JTAG signals when it is programmed for USB configuration. Only use the built-in ispDOWNLOAD cable or an external ispDOWNLOAD cable exclusively. It is not recommended to switch between cables without first power cycling the board. Failure to follow this recommendation may cause unpredictable results and may possibly damage the board. Table 15. Connections Between the USB Controller (CY7C68013A) and the MachXO Cypress Pin Signal Name MachXO Pin Cypress Pin Signal Name MachXO Pin 34 GP_D0 G14 35 GP_D1 N14 36 GP_D2 H14 37 GP_D3 H13 44 GP_D4 H12 45 GP_D5 J13 46 GP_D6 J12 47 GP_D7 K14 80 GP_D8 K13 81 GP_D9 K12 82 GP_D10 L14 83 GP_D11 M13 95 GP_D12 M14 96 GP_D13 M12 12 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 15. Connections Between the USB Controller (CY7C68013A) and the MachXO (Continued) Cypress Pin Signal Name MachXO Pin Cypress Pin Signal Name MachXO Pin 97 GP_D14 N14 98 GP_D15 N13 57 GP_ADR0 H1 58 GP_ADR1 H2 59 GP_ADR2 J1 60 GP_ADR3 J3 61 GP_ADR4 K1 62 GP_ADR5 K2 63 GP_ADR6 L1 64 GP_ADR7 L3 93 GP_ADR8 M1 69 GP_SLOE M3 67 GP_INT0 N7 68 GP_INT1 M6 71 GP_FIFOADR0 M4 72 GP_FIFOADR1 N4 70 GP_WU2 N3 73 GP_PKTEND P5 74 GP_SLCS# G3 79 USBCF_WAKE N9 3 GP_RDY0 D3 4 GP_RDY1 E2 5 GP_RDY2 F2 6 GP_RDY3 F3 7 GP_RDY4 G1 8 GP_RDY5 G2 54 GP_CTL0 D1 55 GP_CTL1 C3 56 GP_CTL2 C2 51 GP_CTL3 C1 52 GP_CTL4 B2 76 GP_CTL5 B1 23 GP_T0 M2 24 GP_T1 N1 25 GP_T2 P1 28 GP_BKPT F12 100 USB_CLK_O M7 26 GP_IFCLK M8 41 GP_RXD0 E13 40 GP_TXD0 E14 43 GP_RXD1 F13 42 GP_TXD1 F14 VGA Interface The board includes a VGA connector for driving a VGA monitor. The VGA interface is connected to a 15-pin plug socket. The pin definitions are listed in Table 16. VGA RD0 and VGA RD1 are both connected to pin 1, but have different series resistors (see Figure 4). Thus, a 6bit VGA interface is realized. Figure 4 shows the connection of the RGB signals. The FPGA is responsible for generating correct HSYNC and VSYNC sweep frequencies. Understand the SYNC frequencies of the VGA monitor being connected to the VGA plug and adjust the FPGA frequencies as required. Table 16. VGA Connector X1B Pin Definition, n.c. ... Not Connected Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 1 VGA_RD0 AF24 1 VGA_RD1 AE23 2 VGA_GR0 AF23 2 VGA_GR1 AE22 3 VGA_BL0 AF22 3 VGA_BL1 AE21 4 n.c. — 5 n.c. — 6 GND — 7 GND — 8 GND — 9 n.c. — 10 GND — 11 n.c. — 12 n.c. — 13 VGA_HSYNC AF20 14 VGA_VSYNC AF21 15 n.c. — 13 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Figure 4. VGA Connector 14 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor User Interface Figure 5 shows the position of the user interface elements. Figure 5. User Interface Features (Version 1 Board Shown in this Figure) Power Plug RS232 Connector Audio Line In Line Out Ethernet 10/100M VGA Connector Mini USB OTG Connector USB Host Connector 2.5 V Testpoint 3.3 V Testpoint DDR SDRAM Sockel GND Testpoint 1.2 V Testpoint SATA LVDS Connectors CLK Testpoint Flywire Connector High-Speed USB for Configuration Expansion Connector Sigma Delta DAC Connector LCD Connector 15 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor 7-Segment Display The 7-segment display is wired as follows: Table 17. 7-Segment Display U0502 Pin Definition A F G E B C D Pin Signal Name A SEG_A# FPGA Pin Pin M24 E Signal Name SEG_E# FPGA Pin M20 B SEG_B# N23 F SEG_F# L22 C SEG_C# M22 G SEG_G# L21 D SEG_D# M21 DP SEG_DP# K22 SEG_CA0# K21 left SEG_CA1# K20 right The signals of the 7-segment display are low-active, which means that with a logic ‘0’, the segment is lit. SEG A# ... SEG F# and SEG DP# drive not only the two 7-segment displays, but also the LCD. To write different data to these three components, the user must drive the signals alternately to the components. This can be realized with the signals SEG CA0#, SEG CA1# and LCD ENABLE. They serve to activate the two 7-segment displays and the LCD, respectively. DIP Switches There is a 4-bit DIP switch on the board. When the switch is turned to the on position, a logic ‘1’ will be seen. The connections are in Table 18. Table 18. DIP Switches SW0514 Connection Signal Name FPGA Pin 1 DSW0 F26 3 DSW2 E26 Switch SW315 Switch Signal Name FPGA Pin 2 DSW1 F25 4 DSW3 E25 SW316 LEDs Eight LEDs can be used for custom status signaling. They are low-active; with a logic ‘0’ the LED is on. You can control the LEDs via the signals below. Table 19. LED LD0501 ... LD0508 Connection Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 1 LED0# R24 5 LED4# P23 2 LED1# R23 6 LED5# P22 3 LED2# R22 7 LED6# P21 4 LED3# R21 8 LED7# N22 Key Matrix The board also features a key matrix with 12 push-buttons, which are not debounced. They must be driven with three column lines and can be read with four rows. The following table shows the connections. 16 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 20. Key Matrix with the Keys SW302 ... SW313 Definition Signal Name TST_COL0 TST_COL1 TST_COL2 TST_ROW0 1 2 3 TST_ROW1 4 5 6 TST_ROW2 7 8 9 TST_ROW3 C 0 E Table 21. Key Matrix with the Keys SW302 ... SW313 Connection Signal Name FPGA Pin Signal Name FPGA Pin TST_ROW0 H26 TST_COL0 G26 TST_ROW1 H25 TST_COL1 G25 TST_ROW2 H24 TST_COL2 G24 TST_ROW3 H23 To query all keys of the matrix, you must poll the column driver signals (TST COL0, TST COL1, and TST COL2). If you press a key, a logic ‘1’ appears in the corresponding row. The following diagram explains the functionality: Figure 6. Polling of the Key Matrix Col0 Col1 Col2 1 pressed 3 pressed Row0 6 pressed 6 pressed Row1 You do not need the polling method if only four keys are used. Connect the column driver signals of one column to VCC, the other two to GND and query the row data signals. CPU Reset Key The CPU reset key is a global reset. Please refer to the Reset Chip section of this document for detailed information. Single Step Key The single step key is connected to a normal input of the FPGA and can be used by the application as required. This key is connected to a Schmitt trigger, meaning it is debounced. This key can be used as a single clock for testing your design. 17 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Components Figure 7 illustrates the position of major components. Figure 7. Components (Version 1 board Shown in this Figure) USB Host/ Target/OTG Controller AC‘97 Audio Codec Ethernet PHY CPLD MachXO FPGA LFEC250 USB Configuration Controller Prototyping Area SPI Flash Reset Controller 18 Asynchronous SRAM Parallel Flash LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor 12 x 12 FPGA Prototyping Area of The FPGA A 12x12 prototyping area is available. The lead-wire spacing of the prototyping area is 100mil (2.54 mm). Figure 8 shows the prototyping area in top view. 14 plated-through-holes on its left side are connected to the FPGA. Eight through-holes on the right side are wired to a 2.5V I/O bank. In the top row of the prototyping area there are six connections to the 3.3V power supply as well as three to 2.5V. The bottom row has ten plated-through-holes connected to GND. Table 22. FPGA Connections for the 12x12 Prototyping Area LRF Pin Signal Name FPGA Pin LRF Pin Signal Name FPGA Pin TP0901 BB3V3_IO0 A15 TP0902 BB3V3_IO1 B15 TP0903 BB3V3_IO2 C15 TP0904 BB3V3_IO3 D15 TP0905 BB3V3_IO4 A16 TP0906 BB3V3_IO5 B16 TP0907 BB3V3_IO6 E16 TP0908 BB3V3_IO7 A17 TP0909 BB3V3_IO8 B17 TP0910 BB3V3_IO9 C17 TP0911 BB3V3_IO10 D17 TP0912 BB3V3_IO11 E17 TP09133 BB3V3_IO12 A18 TP09134 BB3V3_IO13 B18 TP09135 BB3V3_IO14 C18 TP09136 BB3V3_IO15 D18 TP09137 BB3V3_IO16 E18 TP09138 BB3V3_IO17 A19 TP09139 BB3V3_IO18 B19 TP09140 BB3V3_IO19 C19 TP09141 BB3V3_IO20 D19 TP09142 BB3V3_IO21 E19 TP09143 BB3V3_CLK0+ D14 TP09144 BB3V3_CLK0- F14 TP0913 VCC3V3 — TP0925 VCC3V3 — TP0937 VCC3V3 — TP0949 VCC3V3 — TP0961 VCC3V3 — TP0973 VCC3V3 — TP0985 VCC3V3 — TP0997 VCC3V3 — TP09109 VCC3V3 — TP09121 VCC3V3 — TP0924 GND — TP0936 GND — TP0948 GND — TP0960 GND — TP0972 GND — TP0984 GND — TP0996 GND — TP09108 GND — TP09120 GND — TP09132 GND — 19 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Figure 8. Schematic Illustration of the Prototyping Area VCC3V3 BB3V3_IO[21:0] BB3V3_IO[21:0] TP0901 TP0913 TP0925 TP0937 TP0949 TP0961 TP0973 TP0985 TP0997 TP09109 TP09121 TP09133 BB3V3_IO0 BB3V3_IO12 TP0902 TP0914 TP0926 TP0938 TP0950 TP0962 TP0974 TP0986 TP0998 TP09110 TP09122 TP09134 BB3V3_IO1 BB3V3_IO13 TP0903 TP0915 TP0927 TP0939 TP0951 TP0963 TP0975 TP0987 TP0999 TP09111 TP09123 TP09135 BB3V3_IO2 BB3V3_IO14 TP0904 TP0916 TP0928 TP0940 TP0952 TP0964 TP0976 TP0988 TP09100 TP09112 TP09124 TP09136 BB3V3_IO3 BB3V3_IO15 TP0905 TP0917 TP0929 TP0941 TP0953 TP0965 TP0977 TP0989 TP09101 TP09113 TP09125 TP09137 BB3V3_IO4 BB3V3_IO16 TP0906 TP0918 TP0930 TP0942 TP0954 TP0966 TP0978 TP0990 TP09102 TP09114 TP09126 TP09138 TP0907 TP0919 TP0931 TP0943 TP0955 TP0967 TP0979 TP0991 TP09103 TP09115 TP09127 TP09139 BB3V3_IO5 BB3V3_IO17 BB3V3_IO6 BB3V3_IO18 TP0908 TP0920 TP0932 TP0944 TP0956 TP0968 TP0980 TP0992 TP09104 TP09116 TP09128 TP09140 BB3V3_IO7 BB3V3_IO19 TP0909 TP0921 TP0933 TP0945 TP0957 TP0969 TP0981 TP0993 TP09105 TP09117 TP09129 TP09141 BB3V3_IO8 BB3V3_IO20 TP0910 TP0922 TP0934 TP0946 TP0958 TP0970 TP0982 TP0994 TP09106 TP09118 TP09130 TP09142 BB3V3_IO9 BB3V3_IO21 TP0911 TP0923 TP0935 TP0947 TP0959 TP0971 TP0983 TP0995 TP09107 TP09119 TP09131 TP09143 BB3V3_IO10 BB3V3_CLK0+ DIFF TP0912 TP0924 TP0936 TP0948 TP0960 TP0972 TP0984 TP0996 TP09108 TP09120 TP09132 TP09144 BB3V3_IO11 BB3V3_CLK0- GND Asynchronous SRAM The board is populated with two asynchronous K6R4016V1D SRAMs from Samsung. Each is 4 Mbit in size with a data bus width of 16 bits. They are wired as one memory with a 32-bit data bus and a depth of 256 k. The 18-bit address bus, the data bus and the control signals are connected directly to the FPGA. The 18-bit address bus, named MEMORY_A0 through MEMORY_A17, addresses word (4 bytes) locations. Table 23. Address Signals of the Asynchronous SRAM Chips U0404 and U0405 SRAM Pin Signal Name FPGA Pin SRAM Pin Signal Name FPGA Pin 1 MEMORY_A0 C1 2 MEMORY_A1 B2 3 MEMORY_A2 C2 4 MEMORY_A3 A3 5 MEMORY_A4 B3 18 MEMORY_A5 C3 19 MEMORY_A6 D3 20 MEMORY_A7 A4 21 MEMORY_A8 B4 22 MEMORY_A9 C4 23 MEMORY_A10 D4 24 MEMORY_A11 A5 25 MEMORY_A12 B5 26 MEMORY_A13 C5 27 MEMORY_A14 D5 42 MEMORY_A15 E5 43 MEMORY_A16 A6 44 MEMORY_A17 B6 20 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 24. Data Signals of the Asynchronous SRAM Chip U0404 SRAM Pin Signal Name 7 MEMORY_DQ0 9 MEMORY_DQ2 13 MEMORY_DQ4 15 MEMORY_DQ6 FPGA Pin SRAM Pin Signal Name FPGA Pin E7 8 MEMORY_DQ1 F7 G7 10 MEMORY_DQ3 A8 B8 14 MEMORY_DQ5 C8 D8 16 MEMORY_DQ7 E8 29 MEMORY_DQ8 F8 30 MEMORY_DQ9 G8 31 MEMORY_DQ10 A9 32 MEMORY_DQ11 B9 35 MEMORY_DQ12 C9 36 MEMORY_DQ13 D9 37 MEMORY_DQ14 E9 38 MEMORY_DQ15 A10 Table 25. Data Signals of the Asynchronous SRAM Chip U0405 SRAM Pin Signal Name FPGA Pin SRAM Pin Signal Name FPGA Pin 7 MEMORY_DQ16 B10 8 MEMORY_DQ17 C10 9 MEMORY_DQ18 D10 10 MEMORY_DQ19 E10 13 MEMORY_DQ20 F10 14 MEMORY_DQ21 G10 15 MEMORY_DQ22 A11 16 MEMORY_DQ23 B11 29 MEMORY_DQ24 E11 30 MEMORY_DQ25 F11 31 MEMORY_DQ26 G11 32 MEMORY_DQ27 C12 35 MEMORY_DQ28 D12 36 MEMORY_DQ29 E12 37 MEMORY_DQ30 F12 38 MEMORY_DQ31 G12 Table 26. Control Signals of the Asynchronous SRAM Chips U0404 and U0405 SRAM Pin Signal Name FPGA Pin SRAM Pin Signal Name FPGA Pin SRAM Pin Signal Name FPGA Pin 17 MEMORY_WE# C13 41 MEMORY_OE# D13 39 SRAM_BE0# F13 40 SRAM_BE1# G13 6 SRAM_CE# E13 MachXO The LCMXO640 is a non-volatile, instant-on, reprogrammable logic device. It supports “background programming” called TransFR™ (i.e., the device can be programmed while in operation). The MachXO comes preprogrammed from the factory. The factory program permits the CY7C68013A/MachXO combination to work as a built-in USB ispDOWNLOAD cable. Using ispVM software the built-in download cable permits the FPGA, and SPI PROM, to be programmed. It is not recommended for the MachXO to be reprogrammed. However, the MachXO does provide some connections to the LatticeECP2-50 FPGA, and to an 8x6 prototyping area. For further information, please consult the MachXO Family Data Sheet. 21 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 27. Interface Between the MachXO and the FPGA CPLD Pin Signal Name FPGA Pin CPLD Pin Signal Name A1 A3 FPGA Pin MACHXO_IO0 A20 A2 MACHXO_IO1 A23 MACHXO_IO2 C20 B3 MACHXO_IO3 D20 A4 MACHXO_IO4 E20 C4 MACHXO_IO5 A21 A5 MACHXO_IO6 B21 B5 MACHXO_IO7 E21 A6 MACHXO_IO8 A22 B6 MACHXO_IO9 B22 B10 MACHXO_IO10 C22 A11 MACHXO_IO11 D22 A12 MACHXO_IO12 A23 B12 MACHXO_IO13 B23 A13 MACHXO_IO14 E23 A14 MACHXO_IO15 A24 C8 MACHXO_CLK0 H13 B8 MACHXO_CLK0 H13 FPGA The LatticeECP2-50 FPGA represents the heart of the board. It has the following features: • 48 k Look-Up Tables (LUTs) • 96 kbit of distributed RAM • 387 kbit of EBR SRAM • 21 EBR SRAM blocks • 18 sysDSP blocks • 72 18 x 18 multipliers • 6 PLLs: 2 GPLLs, 2 SPLLs, 2 GDLLs • 500 user I/Os • DDR memory support (DDR1-400, DDR2-400) • Supported I/O standards: LVCMOS, LVTTL, SSTL, HSTL, LVDS, PCI, differential • HSTL, differential SSTL, RSDS, Bus LVDS, MLVDS, LVPECL The ispLEVER design software can be used to develop/modify programs for the FPGA using Verilog or VHDL design entry methods. For more information on the ispLEVER software, see www.latticesemi.com/software. Sample programs for the FPGA are available on-line as well. These can be found at www.latticesemi.com/boards. Select FPGA/FPSC Boards -> LatticeMico32/DSP Development board for LatticeECP2 and click on the Design Files link. For further information please consult the LatticeECP2/M Family Data Sheet. Parallel Flash Two parallel MX29LV128MBTI-90Q Flash components from Macronics (or equivalents) are provided on the board for program code and data. As with the SRAM, a 32-bit data bus is realized with these two devices. Thus, Flash can be accessed as a 8Mx32 memory. The 23-bit address bus, the data bus and the control signals are connected directly to the FPGA. The 23-bit address bus, named MEMORY_A0 through MEMORY_A22, addresses word (4 bytes) locations. 22 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Note: The LatticeMico32/DSD Development Board generates byte enable outputs at the top-level HDL module. The board does not use these outputs, which causes ispLEVER to generate some warning messages. The warnings correctly tell the user that these pins are not connected or assigned to any location. The warnings can be avoided by either commenting out these byte enable outputs, or assigning them to unused I/O. Table 28. Address Signals of the Flash Chips U0402 and U0403 Flash Pin Signal Name FPGA Pin Flash Pin Signal Name FPGA Pin 31 MEMORY_A0 C1 26 MEMORY_A1 B2 25 MEMORY_A2 C2 24 MEMORY_A3 A3 23 MEMORY_A4 B3 22 MEMORY_A5 C3 21 MEMORY_A6 D3 20 MEMORY_A7 A4 10 MEMORY_A8 B4 9 MEMORY_A9 C4 8 MEMORY_A10 D4 7 MEMORY_A11 A5 6 MEMORY_A12 B5 5 MEMORY_A13 C5 4 MEMORY_A14 D5 3 MEMORY_A15 E5 54 MEMORY_A16 A6 19 MEMORY_A17 B6 18 MEMORY_A18 E6 11 MEMORY_A19 A7 12 MEMORY_A20 B7 15 MEMORY_A21 C7 2 MEMORY_A22 D7 Table 29. Data Signals of the Flash Chip U0402 Flash Pin Signal Name FPGA Pin Flash Pin Signal Name FPGA Pin 35 MEMORY_DQ0 E7 37 MEMORY_DQ1 C9 39 MEMORY_DQ2 A11 41 MEMORY_DQ3 F12 44 MEMORY_DQ4 B8 46 MEMORY_DQ5 C8 48 MEMORY_DQ6 D8 50 MEMORY_DQ7 E8 36 MEMORY_DQ8 F8 38 MEMORY_DQ9 G8 40 MEMORY_DQ10 A9 42 MEMORY_DQ11 B9 45 MEMORY_DQ12 C9 47 MEMORY_DQ13 D9 49 MEMORY_DQ14 E9 51 MEMORY_DQ15 A10 FPGA Pin Flash Pin Signal Name FPGA Pin Table 30. Data Signals of the Flash Chip U0403 Flash Pin Signal Name 35 MEMORY_DQ16 B10 37 MEMORY_DQ17 C10 39 MEMORY_DQ18 D10 41 MEMORY_DQ19 E10 44 MEMORY_DQ20 F10 46 MEMORY_DQ21 G10 48 MEMORY_DQ22 A11 50 MEMORY_DQ23 B11 36 MEMORY_DQ24 E11 38 MEMORY_DQ25 F11 40 MEMORY_DQ26 G11 42 MEMORY_DQ27 C12 45 MEMORY_DQ28 D12 47 MEMORY_DQ29 E12 49 MEMORY_DQ30 F12 51 MEMORY_DQ31 G12 23 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 31. Control Signals of the Flash Chips U0402 and U0403 Flash Pin Signal Name FPGA Pin Flash Pin Signal Name FPGA Pin 34 MEMORY_OE# D13 32 FLASH_CE# A13 13 MEMORY_WE# C13 16 FLASH_WP#/ACC A12 14 FLASH_RESET B14 17 53 FLASH_BYTE# B12 FLASH_RY/BY#_A A14 SPI Flash The LatticeECP2-50 FPGA is an SRAM-based programmable device, and is therefore volatile. In order for it to be automatically configured upon power-up, a non-volatile 16 Mbit SPI Flash device is provided. The SPI Flash can be programmed with configuration bitstream data. The SPI Flash can be configured either through the ispDOWNLOAD connector or via the integrated USB configuration interface. Table 32. FPGA to SPI Flash Connections SPI Pin Signal Name FPGA Port Name FPGA Direction FPGA Pin CS CSSPIN CEJ Output V22 CLK CCLK SCK Output NC/E191 Q SPIDO SO Input W23 DI SISPI SI Output Y25 WPn WP# WPJ Output AA25 (FPGA NC) HOLDn HOLD# HOLDJ Output AB26 (FPGA NC) Note: The SPI CLK pin can be connected to FPGA E19. This allows the LatticeMico32 to access the SPI PROM for data retrieval/storage purposes. On revision B boards, CLK is E17. To program the SPI Flash configuration device, use the FPGA Loader function of the ispVM System software. The FPGA Loader programming scheme provides an in-system JTAG programming method for configuration devices. The FPGA acts as a bridge between the JTAG interface and the SPI interface of the serial configuration device. Configure the SPI Flash as follows: 1. In the ispVM System software, choose Edit -> Add Device to open the Device Information dialog box. 2. Click Select to open the Select Device dialog box. Select device family LatticeECP2, device LFE2-50E, and package 672 fpBGA from the drop-down lists. 3. Change the Device Access Options to SPI Flash Programming. 4. Select Flash Device : STMicro SPI-M25P16 and click OK. 5. Browse Data File: Select the ECP2-50 bitstream to program into the SPI PROM, click OK. 6. Click OK to close the SPI Serial Flash Device dialog. 7. Click OK to close the Device Information dialog 8. Click GO. The ispVM System software programs the SPI Flash via the FPGA. 9. Disconnect and then reconnect the power supply. The FPGA will take about three seconds to be programmed by the SPI Flash. Power Supply Power is supplied via a 2.1 mm DC power jack in the top left corner of the board. The board is protected against reversed power supply. The input supply is 5V DC. 24 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor A two-phase synchronous step-down switching regulator generates the 3.3V (1A max.) I/O voltage and the 1.2V (2A max.) core voltage. Note: If you use a power supply other than the one included in the shipment, make sure it supplies regulated 5V. Reset Chip After power-up, a power surveillance chip (U0601) waits until the 5V supply and the 3.3V I/O voltage are stable. Then, after 200 ms, it drives the signal HPE RESET# (pin M25 of the FPGA) high. If you press the reset button, the supervisory circuit will generate a low on the HPE RESET# signal. The surveillance chip has an I2C serial 2 kbit CMOS EEPROM. The four most significant bits of the 8-bit slave address are programmable; the default being 1010. Detailed information on the reset circuit and the I2C interface can be found in the data sheet of the Catalyst Semiconductor CAT1026. Troubleshooting If your board is not working properly, please follow these steps for diagnosis. 1. Check the 3.3V and 2.5V LEDs to ensure that the power supply is working correctly. 2. Make sure that the INIT LED is lit. 3. Load test program. 4. Make sure the FPGA has been configured properly (DONE LED must be lit). 5. Start test program 1. Circuit diagrams for the localization of errors can be found in the appendix. Electrical Specifications Power requirement: Input current: regulated 5V DC 2000 mA Mechanical Specifications Dimensions: Net weight: Temperature range: 160 mm [L] x 160 mm [W] x 31 mm [H] 160 g 0 to 50oC 25 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor FPGA Pin Information Table 33. Pin Table Pin Name Signal Name Area M24 SEG_A# 7-Segment Display N23 SEG_B# 7-Segment Display M22 SEG_B# 7-Segment Display K21 SEG_CA0# 7-Segment Display K20 SEG_CA0# 7-Segment Display M21 SEG_D# 7-Segment Display K22 SEG_DP# 7-Segment Display M20 SEG_E# 7-Segment Display L22 SEG_F# 7-Segment Display L21 SEG_G# 7-Segment Display B24 AC97_BITCLK AC97 Audio Codec C23 AC97_EAPD AC97 Audio Codec D25 AC97_EXT CLK AC97 Audio Codec B25 AC97_RESET# AC97 Audio Codec C26 AC97_SDATA_IN AC97 Audio Codec C25 AC97_SDATA_OUT AC97 Audio Codec D24 AC97_SYNC AC97 Audio Codec W4 ADC- Analog Digital Converter W3 ADC+ Analog Digital Converter Y3 ADCS Analog Digital Converter AA22 CCLK Configuration AC24 CFG0 Configuration W20 CFG1 Configuration AD24 CFG2 Configuration V22 CSSPIN Configuration Y24 DOUT Configuration AC3 EC_TCK Configuration AA8 EC_TDI Configuration AA5 EC_TDO Configuration AB4 EC_TMS Configuration AD25 JTAG_DONE Configuration AB24 JTAG_INIT Configuration V19 PROGRAM# Configuration Y25 SISPI Configuration W23 SPIDO Configuration AB25 SPIFASTN# Configuration AD10 DDR_A0 DDR SDRAM AB11 DDR_A1 DDR SDRAM AC10 DDR_A10 DDR SDRAM AC14 DDR_A11 DDR SDRAM AD14 DDR_A12 DDR SDRAM AB10 DDR_A13 DDR SDRAM AB12 DDR_A2 DDR SDRAM 26 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 33. Pin Table (Continued) Pin Name AC12 Signal Name DDR_A3 Area DDR SDRAM AD12 DDR_A4 DDR SDRAM AB13 DDR_A5 DDR SDRAM AC13 DDR_A6 DDR SDRAM AD13 DDR_A7 DDR SDRAM AB15 DDR_A8 DDR SDRAM AB14 DDR_A9 DDR SDRAM AD7 DDR_BA0 DDR SDRAM AC7 DDR_BA1 DDR SDRAM AF9 DDR_CAS# DDR SDRAM AF12 DDR_CK0- DDR SDRAM AE12 DDR_CK0+ DDR SDRAM AA2 DDR_CK1- DDR SDRAM Y1 DDR_CK1+ DDR SDRAM AF11 DDR_CKE0 DDR SDRAM AF10 DDR_CKE1 DDR SDRAM AF6 DDR_DM0 DDR SDRAM AB6 DDR_DM1 DDR SDRAM AB2 DDR_DM2 DDR SDRAM T2 DDR_DM3 DDR SDRAM AD9 DDR_DQ0 DDR SDRAM AC9 DDR_DQ1 DDR SDRAM AD5 DDR_DQ10 DDR SDRAM AC5 DDR_DQ11 DDR SDRAM AF4 DDR_DQ12 DDR SDRAM AE4 DDR_DQ13 DDR SDRAM AD4 DDR_DQ14 DDR SDRAM AC4 DDR_DQ15 DDR SDRAM AE2 DDR_DQ16 DDR SDRAM AD1 DDR_DQ17 DDR SDRAM AD2 DDR_DQ18 DDR SDRAM AD3 DDR_DQ19 DDR SDRAM AB9 DDR_DQ2 DDR SDRAM AC1 DDR_DQ20 DDR SDRAM AC2 DDR_DQ21 DDR SDRAM Y5 DDR_DQ22 DDR SDRAM Y6 DDR_DQ23 DDR SDRAM V1 DDR_DQ24 DDR SDRAM U1 DDR_DQ25 DDR SDRAM P4 DDR_DQ26 DDR SDRAM P5 DDR_DQ27 DDR SDRAM P6 DDR_DQ28 DDR SDRAM N3 DDR_DQ29 DDR SDRAM AD8 DDR_DQ3 DDR SDRAM 27 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 33. Pin Table (Continued) Pin Name N4 Signal Name DDR_DQ30 Area DDR SDRAM N5 DDR_DQ31 DDR SDRAM AC8 DDR_DQ4 DDR SDRAM AB8 DDR_DQ5 DDR SDRAM AF7 DDR_DQ7 DDR SDRAM AE7 DDR_DQ7 DDR SDRAM AF5 DDR_DQ8 DDR SDRAM AE5 DDR_DQ9 DDR SDRAM AE6 DDR_DQS0 DDR SDRAM AA6 DDR_DQS1 DDR SDRAM AB3 DDR_DQS2 DDR SDRAM T1 DDR_DQS3 DDR SDRAM AE9 DDR_RAS# DDR SDRAM AF8 DDR_S0# DDR SDRAM AE8 DDR_S1# DDR SDRAM AF3 DDR_VREF DDR SDRAM P9 DDR_VREF DDR SDRAM AE10 DDR_WE# DDR SDRAM C14 DAC_DIG Digital Analog Converter F26 DSW0 DIP Switch F25 DSW1 DIP Switch E26 DSW2 DIP Switch E25 DSW3 DIP Switch P25 ETH_COL Ethernet N26 ETH_CRS Ethernet M26 ETH_MDC Ethernet W24 ETH_MDINTR# Ethernet N25 ETH_MDIO Ethernet L26 ETH_RXCLK Ethernet AA26 ETH_RXD0 Ethernet Y26 ETH_RXD1 Ethernet W26 ETH_RXD2 Ethernet W25 ETH_RXD3 Ethernet R25 ETH_RXDV Ethernet P26 ETH_RXER Ethernet L25 ETH_TXCLK Ethernet V26 ETH_TXD0 Ethernet V25 ETH_TXD1 Ethernet V24 ETH_TXD2 Ethernet V23 ETH_TXD3 Ethernet R26 ETH_TXEN Ethernet U26 ETH_TXER Ethernet D1 CARDSEL# Expansion Connector L1 EXPCON_CLKIN Expansion Connector 28 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 33. Pin Table (Continued) Pin Name Signal Name Area M1 EXPCON_CLKOUT Expansion Connector R1 EXPCON_IO0 Expansion Connector R2 EXPCON_IO1 Expansion Connector L8 EXPCON_IO10 Expansion Connector K1 EXPCON_IO11 Expansion Connector K2 EXPCON_IO12 Expansion Connector K3 EXPCON_IO13 Expansion Connector K4 EXPCON_IO14 Expansion Connector K5 EXPCON_IO15 Expansion Connector K6 EXPCON_IO16 Expansion Connector K7 EXPCON_IO17 Expansion Connector K8 EXPCON_IO18 Expansion Connector J1 EXPCON_IO19 Expansion Connector P1 EXPCON_IO2 Expansion Connector J2 EXPCON_IO20 Expansion Connector J3 EXPCON_IO21 Expansion Connector J4 EXPCON_IO22 Expansion Connector J5 EXPCON_IO23 Expansion Connector J8 EXPCON_IO24 Expansion Connector J9 EXPCON_IO25 Expansion Connector H1 EXPCON_IO26 Expansion Connector H2 EXPCON_IO27 Expansion Connector H3 EXPCON_IO28 Expansion Connector H4 EXPCON_IO29 Expansion Connector P2 EXPCON_IO3 Expansion Connector H5 EXPCON_IO30 Expansion Connector H6 EXPCON_IO31 Expansion Connector H7 EXPCON_IO32 Expansion Connector H8 EXPCON_IO33 Expansion Connector G1 EXPCON_IO34 Expansion Connector G2 EXPCON_IO35 Expansion Connector G3 EXPCON_IO36 Expansion Connector G4 EXPCON_IO37 Expansion Connector F1 EXPCON_IO38 Expansion Connector F2 EXPCON_IO39 Expansion Connector N1 EXPCON_IO4 Expansion Connector F5 EXPCON_IO40 Expansion Connector F6 EXPCON_IO41 Expansion Connector E1 EXPCON_IO42 Expansion Connector E2 EXPCON_IO43 Expansion Connector E3 EXPCON_IO44 Expansion Connector E4 EXPCON_IO45 Expansion Connector M6 EXPCON_IO5 Expansion Connector L2 EXPCON_IO6 Expansion Connector 29 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 33. Pin Table (Continued) Pin Name Signal Name Area L5 EXPCON_IO7 Expansion Connector L6 EXPCON_IO8 Expansion Connector L7 EXPCON_IO9 Expansion Connector B12 FLASH_BYTE# Flash/SRAM A13 FLASH_CE# Flash/SRAM B14 FLASH_RESET# Flash/SRAM A14 FLASH_RY/BY# A Flash/SRAM B13 FLASH_RY/BY# B Flash/SRAM A12 FLASH_WP#/ACC Flash/SRAM C1 MEMORY_A0 Flash/SRAM B2 MEMORY_A1 Flash/SRAM D4 MEMORY_A10 Flash/SRAM A5 MEMORY_A11 Flash/SRAM B5 MEMORY_A12 Flash/SRAM C5 MEMORY_A13 Flash/SRAM D5 MEMORY_A14 Flash/SRAM E5 MEMORY_A15 Flash/SRAM A6 MEMORY_A16 Flash/SRAM B6 MEMORY_A17 Flash/SRAM E6 MEMORY_A18 Flash/SRAM A7 MEMORY_A19 Flash/SRAM C2 MEMORY_A2 Flash/SRAM B7 MEMORY_A20 Flash/SRAM C7 MEMORY_A21 Flash/SRAM D7 MEMORY_A22 Flash/SRAM A3 MEMORY_A3 Flash/SRAM B3 MEMORY_A4 Flash/SRAM C3 MEMORY_A5 Flash/SRAM D3 MEMORY_A6 Flash/SRAM A4 MEMORY_A7 Flash/SRAM B4 MEMORY_A8 Flash/SRAM C4 MEMORY_A9 Flash/SRAM E7 MEMORY_DQ0 Flash/SRAM F7 MEMORY_DQ1 Flash/SRAM A9 MEMORY_DQ10 Flash/SRAM B9 MEMORY_DQ11 Flash/SRAM C9 MEMORY_DQ12 Flash/SRAM D9 MEMORY_DQ13 Flash/SRAM E9 MEMORY_DQ14 Flash/SRAM A10 MEMORY_DQ15 Flash/SRAM B10 MEMORY_DQ16 Flash/SRAM C10 MEMORY_DQ17 Flash/SRAM D10 MEMORY_DQ18 Flash/SRAM E10 MEMORY_DQ19 Flash/SRAM 30 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 33. Pin Table (Continued) Pin Name G7 Signal Name MEMORY_DQ2 Area Flash/SRAM F10 MEMORY_DQ20 Flash/SRAM G10 MEMORY_DQ21 Flash/SRAM A11 MEMORY_DQ22 Flash/SRAM B11 MEMORY_DQ23 Flash/SRAM E11 MEMORY_DQ24 Flash/SRAM F11 MEMORY_DQ25 Flash/SRAM G11 MEMORY_DQ26 Flash/SRAM C12 MEMORY_DQ27 Flash/SRAM D12 MEMORY_DQ28 Flash/SRAM E12 MEMORY_DQ29 Flash/SRAM A8 MEMORY_DQ3 Flash/SRAM F12 MEMORY_DQ30 Flash/SRAM G12 MEMORY_DQ31 Flash/SRAM B8 MEMORY_DQ4 Flash/SRAM C8 MEMORY_DQ5 Flash/SRAM D8 MEMORY_DQ6 Flash/SRAM E8 MEMORY_DQ7 Flash/SRAM F8 MEMORY_DQ8 Flash/SRAM G8 MEMORY_DQ9 Flash/SRAM D13 MEMORY_OE# Flash/SRAM C13 MEMORY_WE# Flash/SRAM F13 SRAM_BE0# Flash/SRAM G13 SRAM_BE1# Flash/SRAM E14 SRAM_BE2# Flash/SRAM E15 SRAM_BE3# Flash/SRAM E13 SRAM_CE# Flash/SRAM AD15 CLK_FPGA FPGA Clock U25 CLK_FPGA FPGA Clock F14 BB3V3_CLK0- FPGA Prototyping Area D14 BB3V3_CLK0+ FPGA Prototyping Area A15 BB3V3_IO0 FPGA Prototyping Area B15 BB3V3_IO1 FPGA Prototyping Area D17 BB3V3_IO10 FPGA Prototyping Area E17 BB3V3_IO11 FPGA Prototyping Area A18 BB3V3_IO12 FPGA Prototyping Area B18 BB3V3_IO13 FPGA Prototyping Area C18 BB3V3_IO14 FPGA Prototyping Area D18 BB3V3_IO15 FPGA Prototyping Area E18 BB3V3_IO16 FPGA Prototyping Area A19 BB3V3_IO17 FPGA Prototyping Area B19 BB3V3_IO18 FPGA Prototyping Area C19 BB3V3_IO19 FPGA Prototyping Area C15 BB3V3_IO2 FPGA Prototyping Area 31 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 33. Pin Table (Continued) Pin Name Signal Name Area D19 BB3V3_IO20 FPGA Prototyping Area E19 BB3V3_IO21 FPGA Prototyping Area D15 BB3V3_IO3 FPGA Prototyping Area A16 BB3V3_IO4 FPGA Prototyping Area B16 BB3V3_IO5 FPGA Prototyping Area E16 BB3V3_IO6 FPGA Prototyping Area A17 BB3V3_IO7 FPGA Prototyping Area B17 BB3V3_IO8 FPGA Prototyping Area C17 BB3V3_IO9 FPGA Prototyping Area T21 I2C_SCL1 I2C EEPROM T22 I2C_SDA1 I2C EEPROM G26 TST_COL0 Key Matrix G25 TST_COL1 Key Matrix G24 TST_COL2 Key Matrix H26 TST_ROW0 Key Matrix H25 TST_ROW1 Key Matrix H24 TST_ROW2 Key Matrix H23 TST_ROW3 Key Matrix J22 LCD_ENABLE LCD K24 LCD_REGSEL LCD J24 LCD_RW LCD R24 LED0# LED R23 LED1# LED R22 LED2# LED R21 LED3# LED P23 LED4# LED P22 LED5# LED P21 LED6# LED N22 LED7# LED H13 MACHXO_CLK0 MachXO H14 MACHXO_CLK1 MachXO A20 MACHXO_IO0 MachXO B20 MACHXO_IO1 MachXO C22 MACHXO_IO10 MachXO D22 MACHXO_IO11 MachXO A23 MACHXO_IO12 MachXO B23 MACHXO_IO13 MachXO E23 MACHXO_IO14 MachXO A24 MACHXO_IO15 MachXO C20 MACHXO_IO2 MachXO D20 MACHXO_IO3 MachXO E20 MACHXO_IO4 MachXO A21 MACHXO_IO5 MachXO B21 MACHXO_IO6 MachXO 32 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 33. Pin Table (Continued) Pin Name Signal Name Area E21 MACHXO_IO7 MachXO A22 MACHXO_IO8 MachXO B22 MACHXO_IO9 MachXO M25 HPE_RESET# Reset AE24 HPE_RESOUT# Reset J26 RS CTS_LVTTL RS232 K25 RS RTS_LVTTL RS232 J25 RS RXD_LVTTL RS232 K26 RS TXD_LVTTL RS232 M5 SATA_X1D0- SATA M4 SATA_X1D0+ SATA R3 SATA_X1D1- SATA P3 SATA_X1D1+ SATA U4 SATA_X2D0- SATA U3 SATA_X2D0+ SATA W2 SATA_X2D1- SATA V2 SATA_X2D1+ SATA E24 TST_STEP Single Step Key AB21 USB_CTS USB Interface AE20 USB_GPIO0 USB Interface AD20 USB_GPIO1 USB Interface AA19 USB_GPIO10 USB Interface AF18 USB_GPIO11 USB Interface AE18 USB_GPIO12 USB Interface AD18 USB_GPIO13 USB Interface AC18 USB_GPIO14 USB Interface AB18 USB_GPIO15 USB Interface AF17 USB_GPIO16 USB Interface AE17 USB_GPIO17 USB Interface AD17 USB_GPIO18 USB Interface AC17 USB_GPIO19 USB Interface AC20 USB_GPIO2 USB Interface AB17 USB_GPIO20 USB Interface AF16 USB_GPIO21 USB Interface AE16 USB_GPIO22 USB Interface AF15 USB_GPIO23 USB Interface AE15 USB_GPIO24 USB Interface AF14 USB_GPIO25 USB Interface AE14 USB_GPIO26 USB Interface AF13 USB_GPIO27 USB Interface AE13 USB_GPIO28 USB Interface AB20 USB_GPIO3 USB Interface AA20 USB_GPIO4 USB Interface AF19 USB_GPIO5 USB Interface 33 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Table 33. Pin Table (Continued) Pin Name Signal Name Area AE19 USB_GPIO6 USB Interface AD19 USB_GPIO7 USB Interface AC19 USB_GPIO8 USB Interface AB19 USB_GPIO9 USB Interface AD23 USB_MISO USB Interface AB16 USB_MOSI USB Interface AA16 USB_OC0# USB Interface Y20 USB_OC1# USB Interface Y19 USB_OC2# USB Interface Y17 USB_PWEN0 USB Interface Y16 USB_PWEN1 USB Interface AA21 USB_PWEN2 USB Interface AB22 USB_RTS USB Interface AC23 USB_RXD USB Interface AC22 USB_SCK USB Interface AD22 USB_SSI# USB Interface AA17 USB_TXD USB Interface AF22 VGA_BL0 VGA Interface AE21 VGA_BL1 VGA Interface AF23 VGA_GR0 VGA Interface AE22 VGA_GR1 VGA Interface AF20 VGA_HSYNC VGA Interface AF24 VGA_RD0 VGA Interface AE23 VGA_RD1 VGA Interface AF21 VGA_VSYNC VGA Interface Ordering Information Ordering Part Number Description LatticeMico32/DSP Development Board for LatticeECP2 LFE2-50E-D-EV Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com 34 China RoHS EnvironmentFriendly Use Period (EFUP) 10 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Lattice Semiconductor Revision History Date Version February 2007 01.0 Initial release. Change Summary March 2007 01.1 Added Ordering Information section. April 2007 01.2 Updated SATA Interfaces information. Reset Chip section - updated FPGA pin number for the the HPE RESET signal. April 2007 01.3 Ordering information (EFUP) updated. April 2007 01.4 Added important information for proper connection of ispDOWNLOAD (Programming) Cables. July 2007 01.5 Various minor updates to improve readability, and correct typographical errors. August 2007 01.6 Updated information for pins 4-7 in the Expansion Connector X14 table. Updated information for LRF pin TP0902 in the FPGA Connections for the 12x12 Prototyping Area table. September 2007 01.7 Updated Ascynchronous SRAM text section and corresponding table. Updated Parallel Flash text section. February 2008 01.8 Updated Ordering Information. March 2008 01.9 Corrected Schematic Illustration of the Prototyping Area diagram. April 2008 02.0 Updated 7-Segment Display U0502 Pin Definition table. June 2008 02.1 Updated Schematic Illustration of the Prototyping Area. October 2008 02.2 Updated Peripheral Interfaces diagram with Board Version 2 information. Updated Data Signal of the Asynchronous SRAM Chip U0404 table. SPI Flash text section - Updated SPI Flash density to 16 bits. Added table. Updated steps for programing the SPI Flash memory. Added note to Parallel Flash text section. Added Appendix B. Board Version 2 Schematics. October 2008 02.3 Address Signals of the Asynchronous SRAM Chips U0404 and U0405 table - updated FPGA Pin information for MEMORY_A1 and MEMORY_A2. Address Signals of the Flash Chips U0402 and U0403 table updated FPGA Pin information for MEMORY_A1 and MEMORY_A2. October 2008 02.4 Updated photo used in User Interface Features figure. Updated photo used in Components figure. February 2009 02.5 Updated Audio Interface text section. June 2009 02.6 Updated FPGA to SPI Flash Connections table. © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Portions copyright 2005 - 2008 Gleichmann and Company Electronics GmbH. 35 A B C D LED0# LED1# LED2# LED3# LED4# LED5# LED6# LED7# 5 5 5 5 5 5 5 5 ETH_TXER ETH_TXD3 ETH_TXD2 ETH_TXD1 ETH_TXD0 8 8 8 8 8 3 MACHXO_IO[15:0] 4 DDR_WE# 4 DDR_RAS# 4 DDR_CAS# 4 DDR_CK0+ 4 DDR_CK04 DDR_CKE0 4 DDR_BA0 4 DDR_DM[3:0] 4 DDR_DQ[31:0] SRAM_BE0# SRAM_BE1# SRAM_BE2# SRAM_BE3# SRAM_CE# 4 MEMORY_OE# 4 MEMORY_WE# 4 MEMORY_A[22:0] 10 VGA_RD0 10 VGA_RD1 10 VGA_GR0 10 VGA_GR1 10 AC97_BITCLK 10 AC97_SDATA_OUT 10 AC97_SDATA_IN 10 AC97_SYNC 9 SATA_X1D0+ 9 SATA_X1D09 SATA_X1D1+ 9 SATA_X1D1- 9 CARDSEL# 9 EXPCON_CLKIN 9 EXPCON_CLKOUT 9 EXPCON_IO[45:0] 4 4 4 4 4 TST_ROW0 TST_ROW1 TST_ROW2 TST_ROW3 TST_COL0 TST_COL1 TST_COL2 5 LCD_REGSEL 5 LCD_RW 5 LCD_ENABLE 5 DSW0 5 DSW1 5 DSW2 5 DSW3 5 TST_STEP 5 5 5 5 5 5 5 USB ETH_CRS ETH_COL ETH_RXCLK ETH_RXDV ETH_TXEN ETH_TXCLK ETH_TXER ETH_TXD3 ETH_TXD2 ETH_TXD1 ETH_TXD0 USB_MISO USB_SSI# USB_SCK USB_MOSI USB_TXD USB_RXD USB_RTS USB_CTS 7 7 7 7 7 7 ETH_RXER ETH_RXD3 ETH_RXD2 ETH_RXD1 ETH_RXD0 8 ETH_MDC 8 ETH_MDIO 8 ETH_MDINTR# 8 8 8 8 8 USB_PWEN0 USB_OC0# USB_PWEN1 USB_OC1# USB_PWEN2 USB_OC2# 7 RS_RXD_LVTTL 7 RS_CTS_LVTTL Ethernet USB_GPIO[28:0] RS_TXD_LVTTL RS_RTS_LVTTL RS232 HPE_RESOUT# 6 I2C_SDA1 6 I2C_SCL1 6 CLK_FPGA Clock / Reset HPE_RESET# LED0# LED1# LED2# LED3# LED4# LED5# LED6# LED7# SEG_CA0# SEG_CA1# SEG_A# SEG_B# SEG_C# SEG_D# SEG_E# SEG_F# SEG_G# SEG_DP# ETH_MDC ETH_MDIO ETH_MDINTR# ETH_RXER ETH_RXD3 ETH_RXD2 ETH_RXD1 ETH_RXD0 USB_PWEN0 USB_OC0# USB_PWEN1 USB_OC1# USB_PWEN2 USB_OC2# RS_RXD_LVTTL RS_CTS_LVTTL I2C_SDA1 I2C_SCL1 CLK_FPGA LCD_REGSEL LCD_RW LCD_ENABLE DSW0 DSW1 DSW2 DSW3 TST_STEP TST_ROW0 TST_ROW1 TST_ROW2 TST_ROW3 TST_COL0 TST_COL1 TST_COL2 9 SATA_X2D0+ 9 SATA_X2D09 SATA_X2D1+ 9 SATA_X2D1- 9 BB3V3_CLK0+ 9 BB3V3_CLK0- 9 BB3V3_IO[21:0] 5 MACHXO_IO[15:0] FLASH_CE# FLASH_RESET# FLASH_RY/BY#_A FLASH_RY/BY#_B FLASH_WP#/ACC FLASH_BYTE# 4 DDR_S0# 4 DDR_S1# 4 DDR_VREF 4 DDR_CK1+ 4 DDR_CK14 DDR_CKE1 4 DDR_BA1 4 DDR_A[13:0] 4 DDR_DQS[3:0] 4 4 4 4 4 4 3 MACHXO_CLK0 3 MACHXO_CLK1 MachXO DDR_WE# DDR_RAS# DDR_CAS# DDR_CK0+ DDR_CK0DDR_CKE0 DDR_BA0 DDR_DM[3:0] DDR_DQ[31:0] SRAM_BE0# SRAM_BE1# SRAM_BE2# SRAM_BE3# SRAM_CE# MEMORY_OE# MEMORY_WE# 4 MEMORY_DQ[31:0] 10 VGA_BL0 10 VGA_BL1 10 VGA_HSYNC 10 VGA_VSYNC 10 AC97_RESET# 10 AC97_EXT_CLK 10 AC97_EAPD Memory MEMORY_A[22:0] VGA_RD0 VGA_RD1 VGA_GR0 VGA_GR1 VGA AC97_BITCLK AC97_SDATA_OUT AC97_SDATA_IN AC97_SYNC Audio Codec SATA_X1D0+ SATA_X1D0SATA_X1D1+ SATA_X1D1- CARDSEL# EXPCON_CLKIN EXPCON_CLKOUT EXPCON_IO[45:0] MACHXO_CLK0 MACHXO_CLK1 DDR_S0# DDR_S1# DDR_VREF DDR_CK1+ DDR_CK1DDR_CKE1 DDR_BA1 DDR_A[13:0] DDR_DQS[3:0] FLASH_CE# FLASH_RESET# FLASH_RY/BY#_A FLASH_RY/BY#_B FLASH_WP#/ACC FLASH_BYTE# MEMORY_DQ[31:0] VGA_BL0 VGA_BL1 VGA_HSYNC VGA_VSYNC AC97_RESET# AC97_EXT_CLK AC97_EAPD SATA_X2D0+ SATA_X2D0SATA_X2D1+ SATA_X2D1- BB3V3_CLK0+ BB3V3_CLK0- BB3V3_IO[21:0] Expansion Connectors and Prototyping Area 8 ETH_CRS 8 ETH_COL 8 ETH_RXCLK 8 ETH_RXDV 8 ETH_TXEN 8 ETH_TXCLK USB_MISO USB_SSI# USB_SCK USB_MOSI USB_TXD USB_RXD USB_RTS USB_CTS 7 7 7 7 7 7 7 7 7 USB_GPIO[28:0] 7 RS_TXD_LVTTL 7 RS_RTS_LVTTL 6,7,8,9 HPE_RESOUT# 3,6 HPE_RESET# SEG_CA0# SEG_CA1# SEG_A# SEG_B# SEG_C# SEG_D# SEG_E# SEG_F# SEG_G# SEG_DP# 5 5 5 5 5 5 5 5 5 5 R0201 0R00 GND USB_PWEN2 VGA_RD0 HPE_RESOUT# USB_OC1# USB_RTS USB_GPIO1 VGA_BL1 VGA_VSYNC VGA_BL0 VGA_GR1 USB_SSI# VGA_GR0 VGA_RD1 USB_MISO USB_RXD USB_GPIO3 USB_GPIO2 USB_CTS USB_SCK USB_OC2# USB_PWEN0 VGA_HSYNC USB_GPIO0 USB_GPIO4 USB_TXD USB_GPIO11 USB_GPIO5 USB_GPIO10 USB_GPIO19 USB_MOSI USB_GPIO24 USB_GPIO23 USB_GPIO22 USB_GPIO21 USB_PWEN1 USB_GPIO15 USB_GPIO18 USB_GPIO13 USB_GPIO14 USB_GPIO7 USB_GPIO8 USB_GPIO17 USB_GPIO9 USB_GPIO6 USB_GPIO16 USB_GPIO12 USB_GPIO26 USB_GPIO25 USB_OC0# USB_GPIO28 USB_GPIO27 USB_GPIO20 CLK_FPGA 4 SRAM_BE1# MEMORY_DQ17 MEMORY_DQ27 MEMORY_DQ16 MEMORY_DQ15 SRAM_BE0# MEMORY_DQ28 SRAM_CE# MEMORY_WE# MEMORY_DQ23 MEMORY_DQ22 MACHXO_CLK0 MACHXO_CLK1 MEMORY_DQ18 MEMORY_DQ30 MEMORY_A20 MEMORY_A19 MEMORY_DQ12 MEMORY_DQ24 MEMORY_DQ4 MEMORY_DQ3 MEMORY_DQ31 MEMORY_DQ29 MEMORY_DQ11 MEMORY_DQ10 MEMORY_DQ21 MEMORY_DQ13 MEMORY_DQ14 MEMORY_DQ19 MEMORY_DQ25 MEMORY_DQ5 MEMORY_DQ6 MEMORY_A17 MEMORY_A16 MEMORY_DQ26 MEMORY_DQ8 MEMORY_DQ20 MEMORY_DQ7 MEMORY_A22 MEMORY_A21 MEMORY_A12 MEMORY_A11 MEMORY_A15 MEMORY_A18 MEMORY_DQ1 MEMORY_DQ0 MEMORY_DQ2 MEMORY_DQ9 MEMORY_A0 MEMORY_A2 MEMORY_A6 MEMORY_A10 MEMORY_A1 MEMORY_A4 MEMORY_A3 MEMORY_A7 MEMORY_A5 MEMORY_A9 MEMORY_A8 MEMORY_A14 MEMORY_A13 AD15 AC15 AE13 AF13 AB17 Y15 AE14 AF14 AA16 W15 AC17 AB16 AE15 AF15 AE16 AF16 Y16 AB18 AD17 AD18 AC18 AD19 AC19 AE17 AB19 AE19 AF17 AE18 W16 AA17 AF18 AF19 AA19 W17 Y19 Y17 AF20 AE20 AA20 W18 AD20 AE21 AF21 AF22 AE22 AD22 AF23 AE23 AD23 AC23 AB20 AC20 AB21 AC22 W19 AA21 AF24 AE24 Y20 AB22 Y21 AB23 G5 G6 E5 E6 F7 E7 G7 G8 C1 C2 D3 D4 B2 B3 A3 A4 C3 C4 B4 D5 C5 H9 F8 F10 E8 D7 C7 B5 A5 H10 G10 D9 E9 E10 F11 C8 D8 B6 A6 G11 H11 D10 F12 B7 A7 C9 E11 B8 A8 G12 E12 B9 A9 H12 G13 C10 C12 B10 A10 F13 D12 E13 C13 B11 A11 H13 H14 BANK 0 BANK 4 ECP2-50-672BGA PB49A/PCLKT4_0 PB49B/PCLKC4_0 PB50A PB50B PB51A/BDQS51 PB51B PB52A PB52B PB53A PB53B PB54A PB54B PB55A PB55B PB56A PB56B PB57A PB57B PB58A PB58B PB59A PB59B PB60A/BDQS60 PB60B PB61A PB61B PB62A PB62B PB63A PB63B PB64A PB64B PB65A PB65B PB66A PB66B PB67A PB67B PB68A PB68B PB69A/BDQS69 PB69B PB70A PB70B PB74A PB74B PB75A PB75B PB76A PB76B PB77A PB77B PB78A/BDQS78 PB78B PB79A PB79B PB80A PB80B PB81A PB81B PB82A/VREF2_4 PB82B/VREF1_4 U0201C ECP2-50-672BGA PT2A/VREF1_0 PT2B/VREF2_0 PT3A PT3B PT4A PT4B PT5A PT5B PT6A PT6B PT7A PT7B PT8A PT8B PT9A PT9B PT10A PT10B PT22B PT23A PT23B PT24A PT24B PT25A PT25B PT26A PT26B PT27A PT27B PT28A PT28B PT29A PT29B PT30A PT30B PT31A PT31B PT32A PT32B PT33A PT33B PT34A PT34B PT35A PT35B PT36A PT36B PT37A PT37B PT38A PT38B PT39A PT39B PT40A PT40B PT41A PT41B PT42A PT42B PT43A PT43B PT44A PT44B PT45A PT45B PT46A/PCLKT0_0 PT46B/PCLKC0_0 U0201A Lattice ECP2-50 FPGA BANK 1 VREF2_5/PB2A VREF1_5/PB2B PB3A PB3B PB4A PB4B PB5A PB5B BDQS6/PB6A PB6B PB7A PB7B PB8A PB8B PB9A PB9B PB10A PB10B PB20A PB20B PB21A PB21B PB22A PB22B PB23A PB23B BDQS24/PB24A PB24B PB25A PB25B PB26A PB26B PB27A PB27B PB28A PB28B PB29A PB29B PB30A PB30B PB31A PB31B PB32A PB32B BDQS33/PB33A PB33B PB34A PB34B PB35A PB35B PB36A PB36B PB37A PB37B PB38A PB38B PB39A PB39B PB40A PB40B PB41A PB41B BDQS42/PB42A PB42B PB43A PB43B PCLKT5_0/PB44A PCLKC5_0/PB44B BANK 5 XRES PCLKT1_0/PT48A PCLKC1_0/PT48B PT49A PT49B PT50A PT50B PT51A PT51B PT52A PT52B PT53A PT53B PT54A PT54B PT55A PT55B PT56A PT56B PT57A PT57B PT58A PT58B PT59A PT59B PT60A PT60B PT61A PT61B PT62A PT62B PT63A PT63B PT64A PT64B PT65A PT65B PT66A PT66B PT67A PT67B PT68A PT68B PT69A PT69B PT70A PT70B PT71A PT71B PT74A PT74B PT75A PT75B PT76A PT76B PT77A PT77B PT78A PT78B PT79A PT79B PT80A PT80B PT81A PT81B VREF1_1/PT82A VREF2_1/PT82B AE3 AF3 AC4 AD4 AE4 AF4 V9 W9 AA6 AB6 AC5 AD5 AA7 AB7 AE5 AF5 AC7 AD7 W10 Y10 W11 AA10 AC8 AD8 AB8 AB10 AE6 AF6 AA11 AC9 AB9 AD9 Y11 AB11 AE7 AF7 AC10 AD10 AA12 W12 AB12 Y12 AD12 AC12 AC13 AA13 AD13 AC14 AE8 AF8 AB15 Y13 AE9 AF9 W13 AA14 AE10 AF10 W14 AB13 Y14 AB14 AE11 AF11 AD14 AA15 AE12 AF12 XRES H16 GND DDR_CK0+ DDR_CK0- DDR_CKE0 DDR_A12 DDR_A9 DDR_A5 DDR_WE# DDR_CKE1 DDR_RAS# DDR_CAS# DDR_A7 DDR_A11 DDR_S1# DDR_S0# DDR_A8 DDR_A4 DDR_A3 DDR_A6 DDR_A2 DDR_A1 DDR_DQ7 DDR_DQ6 DDR_A10 DDR_A0 DDR_DQ1 DDR_DQ2 DDR_DQ0 DDR_DQ4 DDR_DQ3 DDR_DQ5 DDR_A13 DDR_DQS0 DDR_DM0 DDR_DQ9 DDR_DQ8 DDR_BA1 DDR_BA0 DDR_DQS1 DDR_DM1 DDR_DQ11 DDR_DQ10 DDR_VREF DDR_DQ15 DDR_DQ14 DDR_DQ13 DDR_DQ12 1% R0202 10K0 MACHXO_IO7 MACHXO_IO12 MACHXO_IO15 BB3V3_IO18 BB3V3_IO20 MACHXO_IO1 MACHXO_IO6 BB3V3_IO19 BB3V3_IO21 MACHXO_IO5 MACHXO_IO8 MACHXO_IO3 MACHXO_IO2 MACHXO_IO13 MACHXO_IO9 MACHXO_IO4 MACHXO_IO10 BB3V3_IO16 BB3V3_IO6 BB3V3_IO12 BB3V3_IO13 BB3V3_IO15 BB3V3_IO11 BB3V3_IO17 MACHXO_IO0 SRAM_BE3# BB3V3_IO10 BB3V3_IO9 BB3V3_IO5 BB3V3_IO14 BB3V3_IO8 BB3V3_IO7 BB3V3_IO3 BB3V3_IO1 BB3V3_IO4 FLASH_RY/BY#_B FLASH_CE# BB3V3_IO0 BB3V3_IO2 FLASH_RESET# FLASH_RY/BY#_A MACHXO_IO11 MACHXO_IO14 GND LVDS 3 LVDS LVDS LVDS LVDS GND C0201 100n C0202 100n AC97_BITCLK DAC_DIG MEMORY_OE# DDR_DQ21 DDR_DQ19 DDR_DQ20 DDR_DQ17 DDR_DQ23 DDR_DQ22 DDR_DQ16 DDR_DQ18 DDR_DQS2 DDR_DM2 ADC+ ADC- ADCS SATA_X2D0+ SATA_X2D0- DDR_CK1+ DDR_CK1- SATA_X2D1+ SATA_X2D1- DDR_DQ28 DDR_DQ27 DDR_DQ26 DDR_DQ25 DDR_DQ24 SATA_X1D1+ SATA_X1D1- DDR_DQS3 DDR_DM3 DDR_VREF DDR_DQ29 DDR_DQ30 DDR_DQ31 SATA_X1D0+ SATA_X1D0- F21 E22 H20 G21 C23 D23 C24 B24 G22 H21 B25 D24 C25 D25 E24 F22 C26 D26 J19 K19 G23 G24 H22 J22 E25 E26 L19 K20 F25 F26 G25 G26 H23 H24 H25 H26 K23 J23 J25 J26 J24 K24 M21 K21 M22 L22 M19 M20 K25 K26 N23 M24 K22 L21 M23 N24 GND M4 M5 N7 P9 N3 N4 N5 P7 T1 T2 P8 P6 P5 P4 U1 V1 P3 R3 R4 U2 V2 W2 T6 R5 R6 R7 W1 Y2 Y1 AA2 T5 T7 U3 U4 V3 U5 V4 V5 Y3 Y4 W3 W4 AA1 AB1 U8 U7 V8 U6 W6 W5 AC1 AD1 Y6 Y5 AE2 AD2 AB3 AB2 W7 W8 Y7 Y8 AC2 AD3 + C0238 4u70 VCC1V2 SEG_E# RS_RTS_LVTTL RS_TXD_LVTTL SEG_B# SEG_A# SEG_DP# SEG_G# RS_RXD_LVTTL RS_CTS_LVTTL LCD_RW LCD_REGSEL SEG_D# SEG_CA0# SEG_C# SEG_F# SEG_CA1# DSW1 DSW0 TST_COL1 TST_COL0 TST_ROW3 TST_ROW2 TST_ROW1 TST_ROW0 LCD_ENABLE DSW3 DSW2 TST_COL2 AC97_SDATA_IN AC97_RESET# AC97_SYNC AC97_SDATA_OUT AC97_EXT_CLK TST_STEP AC97_EAPD DIFF BB3V3_CLK0+ BB3V3_CLK0FLASH_BYTE# FLASH_WP#/ACC SRAM_BE2# D14 F14 B12 A12 E14 G14 C14 D13 H15 H17 B13 A13 A15 C15 B14 A14 F15 D15 B15 A16 G15 E15 D17 C17 B16 C18 B17 A17 H18 F16 G16 E16 A18 B18 D18 E17 A19 A20 F17 G19 E18 G17 B19 D19 B20 B21 C19 E19 A21 A22 D20 C20 B23 B22 E20 C22 F19 E21 A23 A24 H19 F20 J18 G20 D22 E23 1 2 Human Interface 3 BANK 6 GND + C0240 4u70 ECP2-50-672BGA PL46A/PCLKT6_0 PL46B/PCLKC6_0 PL47A/VREF2_6 PL47B/VREF1_6 PL48A PL48B PL49A PL49B PL50A/LDQS50 PL50B PL51A PL51B PL52A PL52B PL53A PL53B PL54A PL54B PL55A PL55B PL56A PL56B PL57A PL57B PL58A/LDQS58 PL58B PL59A PL59B PL60A/LLM0_GDLLT_IN_A PL60B/LLM0_GDLLC_IN_A PL61A/LLM0_GDLLT_FB_A PL61B/LLM0_GDLLC_FB_D PL63A/LLM0_GPLLT_IN_A PL63B/LLM0_GPLLC_IN_A PL64A/LLM0_GPLLT_FB_A PL64B/LLM0_GPLLC_FB_A PL65A PL65B PL66A PL66B PL67A/LDQS67 PL67B PL68A PL68B PL69A PL69B PL70A PL70B PL71A PL71B PL72A PL72B PL73A PL73B PL74A PL74B PL75A/LDQS75 PL75B PL76A PL76B PL77A PL77B PL78A PL78B U0201D C0239 1n00 VCC2V5 ECP2-50-672BGA BANK 7 GND + C0242 4u70 + C0243 4u70 VREF2_7/PL2A VREF1_7/PL2B PL5A PL5B PL6A PL6B PL7A PL7B LDQS8/PL8A PL8B PL9A PL9B PL10A PL10B PL11A PL11B PL12A PL12B PL13A PL13B PL14A PL14B PL15A PL15B LDQS16/PL16A PL16B PL17A PL17B PL18A PL18B PL19A PL19B PL23A PL23B LDQS24/PL24A PL24B LUM0_SPLLT_IN_A/PL25A LUM0_SPLLC_IN_A/PL25B LUM0_SPLLT_FB_A/PL26A LUM0_SPLLC_FB_A/PL26B PL37A PL38A PL38B PL39A PL39B PL40A PL40B LDQS41/PL41A PL41B PL42A PL42B PL43A PL43B PCLKT7_0/PL44A PCLKC7_0/PL44B C0241 1n00 VCC3V3 BANK 3 PCLKT3_0/PR46A PCLKC3_0/PR46B VREF1_3/PR47A VREF2_3/PR47B PR48A PR48B PR49A PR49B RDQS50/PR50A PR50B PR51A PR51B PR52A PR52B PR53A PR53B PR54A PR54B PR55A PR55B PR56A PR56B PR57A PR57B RDQS58/PR58A PR58B PR59A PR59B RLM0_GDLLC_IN_A/PR60A RLM0_GDLLC_IN_A/PR60B RLM0_GDLLT_FB_A/PR61A RLM0_GDLLC_FB_A/PR61B RLM0_GPLLT_IN_A/PR63A RLM0_GPLLC_IN_A/PR63B RLM0_GPLLT_FB_A/PR64A RLM0_GPLLC_FB_A/PR64B PR65A PR65B PR66A PR66B RDQS67/PR67A PR67B PR68A PR68B PR69A PR69B PR70A PR70B BANK 2 PR2A/VREF1_2 PR2B/VREF2_2 PR5A PR5B PR6A PR6B PR7A PR7B PR8A/RDQS8 PR8B PR9A PR9B PR10A PR10B PR11A PR11B PR12A PR12B PR13A PR13B PR14A PR14B PR15A PR15B PR16A/RDQS16 PR16B PR17A PR17B PR18A PR18B PR19A PR19B PR23A PR23B PR24A/RDQS24 PR24B PR25A/RUM0_SPLLT_IN_A PR25B/RUM0_SPLLC_IN_A PR26A/RUM0_SPLLT_FB_A PR26B/RUM0_SPLLC_FB_A PR37A PR37B PR38A PR38B PR39A PR39B PR40A PR40B PR41A/RDQS41 PR41B PR42A PR42B PR43A PR43B PR44A/PCLKT2_0 PR44B/PCLKC2_0 U0201B 1 2 4 1 2 Offpage 1 2 2 1 1 2 5 D2 D1 F6 F5 E4 E3 E2 E1 H6 H5 F2 F1 H8 J9 G4 G3 H7 J8 G2 G1 H3 H4 J5 J4 J3 K4 H1 H2 K6 K7 J1 J2 K3 K2 K1 L2 L1 M2 M1 N2 N1 L8 K8 L6 K5 L7 L5 P1 P2 M6 N8 R1 R2 M7 N9 EXPCON_IO0 EXPCON_IO1 EXPCON_IO4 EXPCON_IO10 EXPCON_IO18 EXPCON_IO8 EXPCON_IO15 EXPCON_IO9 EXPCON_IO7 EXPCON_IO2 EXPCON_IO3 EXPCON_IO5 EXPCON_CLKOUT CARDSEL# EXPCON_IO41 EXPCON_IO40 EXPCON_IO45 EXPCON_IO44 EXPCON_IO43 EXPCON_IO42 EXPCON_IO31 EXPCON_IO30 EXPCON_IO39 EXPCON_IO38 EXPCON_IO33 EXPCON_IO25 EXPCON_IO37 EXPCON_IO36 EXPCON_IO32 EXPCON_IO24 EXPCON_IO35 EXPCON_IO34 EXPCON_IO28 EXPCON_IO29 EXPCON_IO23 EXPCON_IO22 EXPCON_IO21 EXPCON_IO14 EXPCON_IO26 EXPCON_IO27 EXPCON_IO16 EXPCON_IO17 EXPCON_IO19 EXPCON_IO20 EXPCON_IO13 EXPCON_IO12 EXPCON_IO11 EXPCON_IO6 EXPCON_CLKIN C0245 1n00 ETH_RXD1 ETH_RXD0 ETH_TXD3 ETH_MDINTR# ETH_TXER ETH_TXD0 ETH_TXD1 ETH_TXD2 ETH_RXD2 ETH_RXD3 CLK_FPGA LED1# LED0# ETH_COL ETH_RXER I2C_SCL1 LED2# ETH_RXDV ETH_TXEN I2C_SDA1 LED6# ETH_MDIO ETH_CRS LED3# LED7# LED5# LED4# HPE_RESET# ETH_MDC ETH_TXCLK ETH_RXCLK C0244 1n00 2 L25 L26 N21 N18 M25 M26 N20 N19 N25 N26 R21 N22 P22 P23 P19 P21 R19 P20 R23 R24 P25 P26 T21 R22 R25 R26 T22 T20 T26 T25 U20 T19 U25 U24 U23 U22 U26 V26 V25 V24 W26 W25 U19 U21 Y26 AA26 V23 W24 2 GND GND GND GND GND GND GND GND GND GND GND C0234 100n C0231 100n C0228 100n C0225 100n C0222 100n C0219 100n C0216 100n C0213 100n C0211 100n C0207 100n C0203 100n C0210 100n ADCS ADC+ ADC- 1 VCC1V2 X22 optional A0201 Jumper AE25 V18 F4 J7 L4 M10 M9 AA4 R10 R9 T4 V7 AC11 AC6 U12 V12 Y9 AC16 AC21 U15 V15 Y18 AA23 R17 R18 T23 V20 F23 J20 L23 M17 M18 D16 D21 G18 J15 K15 D11 D6 G9 J12 K12 L12 L13 L14 L15 M11 M12 M15 M16 N11 N16 P11 P16 R11 R12 R15 R16 T12 T13 T14 T15 1 POWER SUPPLY 0,1% R0204 10k0 1 0,1% 2 2 10k0 R0203 C0246 C0247 DAC_DIG DAC 1 2 P r o j e c t: Revision: Authors: IF W : GND_DAC 2 1 A2 A25 AA18 AA24 AA3 AA9 AD11 AD16 AD21 AD6 AE1 AE26 AF2 AF25 B1 B26 C11 C16 C21 C6 F18 F24 F3 F9 J13 J14 J21 J6 K10 K11 K13 K14 K16 K17 L10 L11 L16 L17 L24 L3 M13 M14 N10 N12 N13 N14 N15 N17 P10 P12 P13 P14 P15 P17 R13 R14 T10 T11 T16 T17 T24 T3 U10 U11 U13 U14 U16 U17 V13 V14 V21 V6 1 GND 10:35:32 S h e et: 02_FPGA Last modified: Monday, September 04, 2006 17:15:04 GND_DAC GND GND Sternpunkt an X2 GND_ADC Sternpunkt an X1 0 X1 4 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Created: Saturday, April 29, 2006 Page 2 o f 12 HDR2 X2 Hpe_mini LEC2 R01 csam C0251 nb_4p70 DAC_ANALOG C0250 4p70 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 A-4232 Hagenberg R0205 33k2 2 1 GND_ADC 2 3n30 nb nb nb C0249 C0248 ECP2-50-672BGA VCCIO8 VCCIO8 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC U0201F FB0201 BLM18BD601SN1 3 C0237 100n C0236 100n VCC3V3 C0233 100n VCC3V3 C0230 100n VCC2V5 C0227 100n VCC2V5 C0224 100n VCC3V3 C0221 100n VCC3V3 C0218 100n VCC3V3 C0215 100n VCC3V3 GND VCC1V2 C0206 100n VCC3V3 C0209 100n C0205 100n 1 Place pins 0..4 near the balls of the FPGA. These pins must also be accessible for measurements instruments. LVDS ADC C0235 100n C0232 100n C0229 100n C0226 100n C0223 100n C0220 100n C0217 100n C0214 100n C0212 100n C0208 100n C0204 100n 2 1 2 36 1 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Appendix A. Board Version 1 Schematic Figure 9. A B C D USB_SCL USB_SDA HPE_RESET# EXPCON_IO[45:0] CLK_MACHXO MACHXO_CLK0 MACHXO_CLK1 GND TP0303 1 2 3 4 SHIELD SHIELD USB Peripheral VCC DATADATA+ GND X3 6 5 1 2 3 4 5 6 7 8 9 10 GPIO_TDO GPIO_TDI GPIO_TCK JTAG_TDI JTAG_TDO JTAG_TCK 5 GPIO_TMS GND B A CAS-120A C SW0302 MACHXO_TCK MACHXO_TDO MACHXO_TDI 2 JTAG_TCK JTAG_DONE JTAG_INIT JTAG_TDO JTAG_TDI JTAG_PROG JTAG_TRST JTAG_TMS VCC3V3 JTAG_TMS CON10 X4 GNDP GND 3 1 E C _ T CK E C _ T DO E C _ TDI R0316 10K0 VCC3V3 GNDA_CONF MACHXO_TMS EC_TMS TP0307 TP0305 TP0304 JTAG Connector for Configuration GNDA_CONF PWR_IN USBCF_M USBCF_P USB Peripheral for Configuration VCC3V3 SPIDO SPIFASTN# JTAG_DONE JTAG_INIT CCLK PROGRAM# CFG0 CFG1 CFG2 SISPI DOUT CSSPIN R0317 10K0 VCC3V3 DOUT TP0302 R0301 4k70 CCLK USB-JTAG Programmer Connector 7 USB_SCL 7 USB_SDA 2,6 HPE_RESET# 2,9 EXPCON_IO[45:0] 6 CLK_MACHXO 2 MACHXO_CLK0 2 MACHXO_CLK1 1 2 J10 J11 J16 J17 K18 L18 T18 U18 V16 V17 V10 V11 T9 U9 K9 L9 AD25 AB24 AA22 V19 AC24 W20 AD24 Y25 Y24 V22 W21 Y22 AC25 AB25 AD26 AC26 Y23 W22 AA25 AB26 W23 + C0307 2u20 GND 29 30 USBCF_I2C_SCL USBCF_I2C_SDA 4 C0308 100n C0309 100n 43 42 GP_RXD1 GP_TXD1 77 41 40 GP_RXD0 GP_TXD0 HPE_RESET# 23 24 25 GP_T0 GP_T1 GP_T2 28 100 26 31 32 22 84 79 USBCF_WAKE GP_BKPT USB_CLK_O GP_IFCLK 54 55 56 51 52 76 GP_CTL0 GP_CTL1 GP_CTL2 GP_CTL3 GP_CTL4 GP_CTL5 13 14 15 27 3 4 5 6 7 8 10 11 17 18 GND C0340 12p0 C0310 100n GND C0311 100n VCC3V3 PD0/FD8 PD1/FD9 PD2/FD10 PD3/FD11 PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 PB0/FD0 PB1/FD1 PB2/FD2 PB3/FD3 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 C0312 100n GP_ADR0 GP_ADR1 GP_ADR2 GP_ADR3 GP_ADR4 GP_ADR5 GP_ADR6 GP_ADR7 57 58 59 60 61 62 63 64 9 16 2 21 39 48 50 65 75 94 99 1 20 33 38 49 53 66 78 85 12 19 C0313 100n GND GND 1 C0326 5n60 C0315 1n00 GNDA_CONF C0314 100n VCC3V3_CONF VCC3V3 GNDA_CONF R0315 4k70 R0314 10K0 GND VCC3V3 FB0301 BLM18BD601SN1 2 VCC1V2 C0302 100n VCC3V3_CONF GP_ADR8 GP_D8 GP_D9 GP_D10 GP_D11 GP_D12 GP_D13 GP_D14 GP_D15 80 81 82 83 95 96 97 98 86 87 88 89 90 91 92 93 GP_D0 GP_D1 GP_D2 GP_D3 GP_D4 GP_D5 GP_D6 GP_D7 FB0302 BLM18PG600SN1 1 2 GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC AGND AGND AVCC AVCC PE0/T0OUT PE1/T1OUT PE2/T2OUT PE3/RXD0OUT PE4/RXD1OUT PE5/INT6 PE6/T2EX PE7/GPIFADR8 C0325 5n60 GND GP_INT0 GP_INT1 GP_SLOE GP_WU2 GP_FIFOADR0 GP_FIFOADR1 GP_PKTEND GP_SLCS# GND GND C0301 1n00 GND Place the 4k7 resistors close to their clock line to keep the stub length as short as possible. VCC3V3 34 35 36 37 44 45 46 47 67 68 69 70 71 72 73 74 VCCPLL R0303 4k70 EC_TDO EC_TMS EC_TDI EC_TCK PC0/GPIFADR0 PC1/GPIFADR1 PC2/GPIFADR2 PC3/GPIFADR3 PC4/GPIFADR4 PC5/GPIFADR5 PC6/GPIFADR6 PC7/GPIFADR7 CY7C68013A_TQFP100 RESET BKPT CLKOUT IFCLK RD WR SCL SDA RXD1 TXD1 RXD0 TXD0 T0 T1 T2 INT4 INT5 WAKEUP CTL0/FLAGA CTL1/FLAGB CTL2/FLAGC CTL3 CTL4 CTL5 DPLUS DMINUS NC NC NC RESERVED RDY0/SLRD RDY1/SLWR RDY2 RDY3 RDY4 RDY5 N6 P24 M3 T8 R20 M8 R8 P18 L20 AB5 AA5 AB4 AA8 AC3 PA0/INT0 PA1/INT1 PA2/SLOE PA3/WU2 PA4/FIFOADR0 PA5/FIFOADR1 PA6/PKTEND PA7/FLAGD/SLCS NC1 NC2 NC3 LLM0_PLLCAP RLM0_PLLCAP XTALOUT XTALIN U0301 VCCJ TDO TMS TDI TCK LUM0_VCCPLL LLM0_VCCPLL RLM0_VCCPLL RUM0_VCCPLL BANK 9 AUX & PLL POWER USBCF_P USBCF_M GP_RDY0 GP_RDY1 GP_RDY2 GP_RDY3 GP_RDY4 GP_RDY5 GND Q0301 24MHz 1 C0339 12p0 2 ECP2-50-672BGA VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX DONE INITN CCLK PROGRAMN CFG0 CFG1 CFG2 BUSY/PR71A DOUT/CSON/PR71B DI/PR72A WRITEN/PR77B CS1N/PR77A CSN/PR76B PR76A/D0 PR75B/D1 PR75A/D2 PR74B/D3 PR74A/D4 PR73B/D5 PR73A/D6 PR72B/D7 BANK 8 3 GND GND C0316 100n VCC3V3 GND N12 P7 P6 N2 M10 P2 N11 P9 MACHXO_SLEEPN VCC3V3 P3 P4 N5 M5 M3 N3 M4 N4 P5 N6 M6 N7 M7 N8 P8 M8 N9 M9 N10 P10 P11 M11 P12 P13 P14 C7 B11 C5 A10 B4 C9 A7 A1 B3 A2 A3 C4 A4 A5 B5 C6 B6 A6 B7 C8 B8 A8 A9 B9 C10 B10 C11 A11 C12 B12 B13 A12 A13 MACHXO_TMS MACHXO_TCK MACHXO_TDO MACHXO_TDI GP_INT1 GP_INT0 USB_CLK_O USBCF_I2C_SDA USBCF_I2C_SCL GP_IFCLK USBCF_WAKE JTAG_INIT JTAG_TRST JTAG_DONE GPIO_TDI JTAG_PROG GPIO_TDO GPIO_TMS GPIO_TCK GP_SLOE GP_WU2 GP_FIFOADR0 GP_FIFOADR1 GP_PKTEND VCC3V3 MACHXO_IO12 MACHXO_IO14 MACHXO_IO13 MACHXO_IO11 MACHXO_IO10 MACHXO_CLK0 MACHXO_CLK1 CLK_MACHXO USB_SDA USB_SCL MACHXO_IO9 MACHXO_IO8 MACHXO_IO0 MACHXO_IO3 MACHXO_IO1 MACHXO_IO2 MACHXO_IO5 MACHXO_IO4 MACHXO_IO6 MACHXO_IO7 WP# GND C0304 100n BANK 3/6,7 VCC VCCIO1/VCCIO3 VCCIO1/VCCIO2 GNDIO1/GNDIO3 GNDIO1/GNDIO2 GND PR2A/PR2A PR2B/PR3C PR2C/PR2B PR2D/PR3D PR3C/PR4A PR3D/PR4B PR4B/PR5A PR4C/PR5B PR4D/PR6A PR5C/PR6B PR5D/PR6C PR6B/PR8A PR6C/PR8B PR6D/PR9A PR7A/PR9B PR7B/PR10A PR7C/PR10B PR8A/PR11A PR8B/PR11B PR8C/PR12A PR8D/PR12B PR10A/PR14A PR10B/PR14B PR11A/PR15A PR11B/PR16A PR11C/PR15B PR11D/PR16B C0317 100n C0318 100n C0319 100n C0320 100n VCC VCCIO3/VCCIO7 VCCIO3/VCCIO6 GNDIO3/GNDIO7 GNDIO3/GNDIO6 GND MACHXO-640/1200-132csBGA VCC VCCIO2/VCCIO5 VCCIO2/VCCIO4 GNDIO2/GNDIO5 GNDIO2/GNDIO4 GND PB2C PL2A PB2D PL2B/PL3C PL2C/PL2B PB3B PB3C/PB4A PL2D/PL4A PB3D/PB4B PL3A/PL3D PB4E/PB5C PL3B/PL4B PB4F/PB6A PL3D/PL4C PB5A/PB6F PL5A/PL6A PB5B/PB7B (PCLKT)(GSRN) PL5B/PL6B PB5D/PB7C PL5D/PL6D PB6A/PB7D PL6B/PL7C PB6B/PB7F (PCLKT) PL6C/PL7D PB7A/PB9A PL6D/PL8C PB7B/PB9B PL7A/PL8D PB7E/PB9C PL7B/PL10A PB7F/PB9D PL7C/PL10B PB8C/PB10A PL8A/PL11B PB8D/PB10B (TSALL) PL8C/PL11C PB9C/PB10C PL9A/PL11D PB9D/PB11C PL9B/PL12A PB9F/PB11D PL9C/PL12B PL10A/PL14A TMS PL10B/PL14B TCK PL11A/PL15A TDO PL11B/PL16A TDI PL11C/PL15B PL11D/PL16B SLEEPN VCCAUX BANK 2/4,5 VCC VCCIO0/VCCIO1 VCCIO0/VCCIO0 GNDIO0/GNDIO1 GNDIO0/GNDIO0 GND 16 15 14 13 12 11 10 9 BANK 1/2,3 C0303 100n PT2A PT2B/PT3A PT2C/PT2B PT2D/PT3B PT2F/PT3C PT3B/PT3D PT3D/PT4B PT3E/PT5A PT3F/PT5B PT4C/PT5C PT4D/PT5D PT5A/PT6D PT5B/PT6F (PCLKT) PT6A/PT7B PT6B/PT7D (PCLKT) PT7A/PT9A PT7B/PT9B PT7E/PT9E PT7F/PT9F PT8C/PT10C PT9A/PT10D PT9B/PT11A PT9C/PT10F PT9D/PT11C PT9E/PT11B PT9F/PT11D VCCAUX CLK DI NC NC NC NC GND WP H3 D2 K3 E1 L2 F1 B1 C1 B2 C2 C3 D1 D3 E2 E3 F2 F3 G1 G2 G3 H2 H1 J1 J2 J3 K2 K1 L1 L3 M1 N1 M2 P1 GND C0322 100n VCC3V3 2 GP_CTL5 GP_CTL3 GP_CTL4 GP_CTL2 GP_CTL1 GP_CTL0 GP_RDY0 GP_RDY1 HPE_RESET# GP_RDY2 GP_RDY3 GP_RDY4 GP_RDY5 GP_SLCS# GP_ADR1 GP_ADR0 GP_ADR2 MACHXO_TSALL GP_ADR3 GP_ADR5 GP_ADR4 GP_ADR6 GP_ADR7 GP_ADR8 GP_T1 GP_T0 GP_T2 VCC3V3 GP_TXD0 GP_RXD0 GP_BKPT GP_RXD1 GP_TXD1 GP_D0 GP_D1 GP_D4 GP_D3 GP_D2 GP_D6 GP_D5 GP_D9 GP_D8 GP_D7 GP_D10 GP_D11 GP_D13 GP_D15 GP_D12 GP_D14 MACHXO_IO15 C0321 100n G12 L12 E12 L13 D13 J14 A14 C13 B14 C14 D12 D14 E14 E13 F12 F13 F14 G14 G13 H12 H13 H14 J12 J13 K12 K13 K14 L14 M13 M12 N13 M14 N14 GND WP# CCLK SISPI GND M25P16-VMF6P 16Mb M25P16 HOLD VCC NC NC NC NC CS Q U0305 VCC3V3 1 2 3 4 5 6 7 8 U0302 BANK 0/0,1 CSSPIN SPIDO HOLD# R0304 10K0 VCC3V3 SPI Flash for Configuration C0323 1n00 GND + TSALL TP0311 C0324 4u70 RJ0310 10K0 RJ0309 nb_10K0 VCC3V3 Source GND T0302 BSS138/SOT 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 Pull-Up Pull-Down X Pull-Up Pull-Down X X X X TP0308 JTAG_TCK JTAG_TDO JTAG_TMS JTAG_TDI TVi0 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 A-4232 Hagenberg RJ0308 nb_0R00 RJ0307 10K0 1 Created: Saturday, April 29, 2006 Page 3 o f 12 10:35:54 S h e e t: 0 3 _ F P G A _ C o n f Last modified: Monday, September 04, 2006 17:15:09 VCC1V2_T H p e _ mini LEC2 R01 csam VCC3V3_T RJ0306 0R00 VCC2V5_T VCC5V0 RJ0304 0R00 RJ0305 nb_10K0 TVo2 TVo3 TP0310 PROGRAM# SW0301 B3FS-1012 RJ0303 nb_10K0 GND 4 3 TVo1 GND RJ0302 0R00 RJ0301 nb_10K0 2 1 LD0303 LED yellow R0308 270R TVo0 TVi3 TVi2 TVi1 P r o j e c t: Revision: Authors: IF W : TestContact TP0 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 X23 GND 1 VCC3V3 VCC3V3 GND SPIFASTN# CFG0 CFG1 CFG2 INIT# TP0309 DONE R0307 4k70 VCC3V3 PROGRAM# Test Adapter rev 1.1 0 0 0 1 1 1 0 0 1 CFG2 CFG1 CFG0 SPIFAST# SOT-23 Drain GND Gate SPI Normal SPI Fast Reserved SPIm Normal SPIm Fast Reserved Reserved Slave Serial Reserved Mode JTAG_INIT JTAG_DONE LD0302 LED red R0306 270R VCC3V3 T0301 BSS138/SOT LD0301 LED blue R0305 270R VCC3V3 Configuration Settings 2 1 U0201E 2 1 TP0301 1 2 1 2 Lattice ECP2-50 FPGA (Configuration) 1 2 2 1 MACHXO_IO[15:0] 2 1 2 MACHXO_IO[15:0] 1 2 1 Offpage 1 2 3 1 2 1 4 1 2 1 2 1 2 1 2 1 2 2 1 2 2 1 2 2 1 2 5 1 2 1 37 2 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 10. A B C D SRAM_BE0# SRAM_BE1# SRAM_BE2# SRAM_BE3# SRAM_CE# 2 2 2 2 2 SRAM_BE0# SRAM_BE1# SRAM_BE2# SRAM_BE3# SRAM_CE# FLASH_CE# FLASH_RESET# FLASH_RY/BY#_A FLASH_RY/BY#_B FLASH_WP#/ACC FLASH_BYTE# MEMORY_OE# MEMORY_WE# MEMORY_DQ[31:0] MEMORY_A[22:0] DDR_VREF DDR_S0# DDR_S1# DDR_WE# DDR_RAS# DDR_CAS# DDR_BA0 DDR_BA1 DDR_CKE0 DDR_CKE1 DDR_CK1+ DDR_CK1- DDR_CK0+ DDR_CK0- DDR_A[13:0] DDR_DM[3:0] DDR_DQS[3:0] 33R0 2 R0416 1 33R0 2 RN0413 CND1J 10K JTA 33R DDR_VTT 1 10 SODIMM_A4 2 9 SODIMM_A2 3 8 SODIMM_A0 4 7 SODIMM_BA1 5 6 RN0414 CND1J 10K JTA 33R DDR_VTT 1 10 SODIMM_RAS# 2 9 SODIMM_CAS# 8 3 SODIMM_S1# 4 7 5 6 SODIMM_A5 SODIMM_A3 SODIMM_A1 SODIMM_A10 DDR_VTT SODIMM_BA0 SODIMM_WE# SODIMM_S0# SODIMM_A13 DDR_VTT 5 RN0412 CND1J 10K JTA 33R DDR_VTT 1 10 SODIMM_CKE0 9 2 SODIMM_A11 3 8 SODIMM_A8 4 7 SODIMM_A6 5 6 SODIMM_CKE1 SODIMM_A12 SODIMM_A9 SODIMM_A7 DDR_VTT SODIMM_DM3 RN0411 CND1J 10K JTA 33R DDR_VTT 1 10 SODIMM_DQ28 2 9 SODIMM_DQ29 8 3 SODIMM_DQ30 4 7 SODIMM_DQ31 5 6 33R0 2 R0420 1 SODIMM_DQ24 SODIMM_DQ25 SODIMM_DQ26 SODIMM_DQ27 DDR_VTT 33R0 2 R0419 1 SODIMM_DQS3 RN0410 CND1J 10K JTA 33R DDR_VTT 1 10 SODIMM_DQ20 2 9 SODIMM_DQ21 3 8 SODIMM_DQ22 4 7 SODIMM_DQ23 5 6 R0418 1 SODIMM_DQ16 SODIMM_DQ17 SODIMM_DQ18 SODIMM_DQ19 DDR_VTT 33R0 2 R0417 1 SODIMM_DM2 RN0409 CND1J 10K JTA 33R DDR_VTT 1 10 SODIMM_DQ12 2 9 SODIMM_DQ13 3 8 SODIMM_DQ14 4 7 SODIMM_DQ15 5 6 SODIMM_DQS2 SODIMM_DQ8 SODIMM_DQ9 SODIMM_DQ10 SODIMM_DQ11 DDR_VTT SODIMM_DM1 SODIMM_DQS1 33R0 2 R0415 1 RN0408 CND1J 10K JTA 33R DDR_VTT 1 10 SODIMM_DQ4 2 9 SODIMM_DQ5 3 8 SODIMM_DQ6 4 7 SODIMM_DQ7 5 6 33R0 2 R0414 1 SODIMM_DM0 SODIMM_DQ0 SODIMM_DQ1 SODIMM_DQ2 SODIMM_DQ3 DDR_VTT 33R0 2 R0413 1 SODIMM_DQS0 Parallel Termination Resistors - Place C0401 as close as possible to the PVIN pin - Place C0403 as close as possible to the VREF pin - Place a bulk cap (100-220 µF) capacitor at each end of the VTT island. (C04??, C04??) FLASH_CE# FLASH_RESET# FLASH_RY/BY#_A FLASH_RY/BY#_B FLASH_WP#/ACC FLASH_BYTE# 2 2 2 2 2 2 2 MEMORY_OE# 2 MEMORY_WE# 2 MEMORY_DQ[31:0] 2 MEMORY_A[22:0] 2 DDR_VREF 2 DDR_S0# 2 DDR_S1# 2 DDR_WE# 2 DDR_RAS# 2 DDR_CAS# 2 DDR_BA0 2 DDR_BA1 2 DDR_CKE0 2 DDR_CKE1 2 DDR_CK1+ 2 DDR_CK1- 2 DDR_CK0+ 2 DDR_CK0- 2 DDR_A[13:0] 2 DDR_DM[3:0] 2 DDR_DQS[3:0] GND C0416 220u DDR_VTT SODIMM_A10 SODIMM_BA0 SODIMM_WE# SODIMM_S0# SODIMM_A13 SODIMM_A7 SODIMM_A5 SODIMM_A3 SODIMM_A1 SODIMM_A12 SODIMM_A9 SODIMM_CKE1 SODIMM_DQ26 SODIMM_DQ27 SODIMM_DQ25 SODIMM_DQS3 SODIMM_DQ19 SODIMM_DQ24 SODIMM_DQS2 SODIMM_DQ18 SODIMM_DQ16 SODIMM_DQ17 SODIMM_CK0+ SODIMM_CK0- SODIMM_DQ10 SODIMM_DQ11 SODIMM_DQ9 SODIMM_DQS1 SODIMM_DQ3 SODIMM_DQ8 SODIMM_DQS0 SODIMM_DQ2 C0417 100n GND VCC2V5 SODIMM_DQ0 SODIMM_DQ1 DDR_VREF GND C0401 47u 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 5 6 7 2 DQ20 DQ21 Vdd DM2 DQ22 Vss DQ23 DQ28 Vdd DQ29 DM3 Vss DQ30 DQ31 Vdd CB4/NC CB5/NC Vss DM8/NC CB6/NC Vdd CB7/NC NC Vss Vss Vdd Vdd CKE0 NC A11 A8 Vss A6 A4 A2 A0 Vdd BA1 RAS# CAS# S1#/NC NC Vss DQ36 DQ37 Vdd DM4 DQ38 Vss DQ39 DQ44 Vdd DQ45 DM5 Vss DQ46 DQ47 Vdd CK1CK1+ Vss DQ52 DQ53 Vdd DM6 DQ54 Vss DQ55 DQ60 Vdd DQ61 DM7 Vss DQ62 DQ63 Vdd SA0 SA1 SA2 NC C0418 100n C0419 100n DDR_SODIMM200 DQ16 DQ17 Vdd DQS2 DQ18 Vss DQ19 DQ24 Vdd DQ25 DQS3 Vss DQ26 DQ27 Vdd CB0/NC CB1/NC Vss DQS8/NC CB2/NC Vdd CB3/NC NC Vss CK2+/NC CK2-/NC Vdd CKE1/NC NC A12/NC A9 Vss A7 A5 A3 A1 Vdd A10/AP BA0 WE# S0# A13/NC Vss DQ32 DQ33 Vdd DQS4 DQ34 Vss DQ35 DQ40 Vdd DQ41 DQS5 Vss DQ42 DQ43 Vdd Vdd Vss Vss DQ48 DQ49 Vdd DQS6 DQ50 Vss DQ51 DQ56 Vdd DQ57 DQS7 Vss DQ58 DQ59 Vdd SDA SCL Vddspd Vddid X5B 4 3 8 1 Vref Vss DQ4 DQ5 Vdd DM0 DQ6 Vss DQ7 DQ12 Vdd DQ13 DM1 Vss DQ14 DQ15 Vdd Vdd Vss Vss DDR_SODIMM200 Vref Vss DQ0 DQ1 Vdd DQS0 DQ2 Vss DQ3 DQ8 Vdd DQ9 DQS1 Vss DQ10 DQ11 Vdd CK0+ CK0Vss X5A LP2995MR VDDQ VREF AVIN VSENSE PVIN VTT GND NC C0420 100n 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND C0402 220u C0403 100n 4 C0421 100n C0422 100n SODIMM_CK1SODIMM_CK1+ SODIMM_BA1 SODIMM_RAS# SODIMM_CAS# SODIMM_S1# SODIMM_A6 SODIMM_A4 SODIMM_A2 SODIMM_A0 SODIMM_A11 SODIMM_A8 SODIMM_CKE0 SODIMM_DQ30 SODIMM_DQ31 SODIMM_DQ29 SODIMM_DM3 SODIMM_DQ23 SODIMM_DQ28 SODIMM_DM2 SODIMM_DQ22 SODIMM_DQ20 SODIMM_DQ21 SODIMM_DQ14 SODIMM_DQ15 SODIMM_DQ13 SODIMM_DM1 SODIMM_DQ7 SODIMM_DQ12 SODIMM_DM0 SODIMM_DQ6 SODIMM_DQ4 SODIMM_DQ5 DDR_VREF VCC2V5 GND DDR_VREF DDR_VTT 22R0 2 SODIMM_DQS2 RN04061 5 6 7 8 RN04052 5 6 7 8 GND C0414 100n DDR_VTT GND C0413 100n DDR_CK1+ DDR_CK1- C0412 100n DDR_VREF 22R0 2 R0412 1 C0415 100n SODIMM_CK1+ 22R0 2 CN1j 4 JTA 22R DDR_S0# 4 DDR_S1# 3 DDR_A13 2 1 CN1j 4 JTA 22R DDR_BA0 4 DDR_RAS# 3 DDR_WE# 2 DDR_CAS# 1 CN1j 4 JTA 22R DDR_A1 4 DDR_A0 3 DDR_A10 2 DDR_BA1 1 CN1j 4 JTA 22R DDR_A5 4 DDR_A4 3 DDR_A3 2 DDR_A2 1 CN1j 4 JTA 22R DDR_A9 4 DDR_A8 3 DDR_A7 2 DDR_A6 1 R0411 1 RN04072 5 6 7 8 SODIMM_CK1- SODIMM_S0# SODIMM_S1# SODIMM_A13 RN04071 SODIMM_BA0 5 SODIMM_RAS# 6 SODIMM_WE# 7 SODIMM_CAS# 8 RN04062 SODIMM_A1 5 SODIMM_A0 6 SODIMM_A10 7 SODIMM_BA1 8 SODIMM_A5 SODIMM_A4 SODIMM_A3 SODIMM_A2 SODIMM_A9 SODIMM_A8 SODIMM_A7 SODIMM_A6 DDR_DM3 DDR_DQS3 CN1j 4 JTA 22R DDR_CKE1 4 DDR_CKE0 3 DDR_A12 2 DDR_A11 1 22R0 2 22R0 2 R0409 1 R0410 1 RN04051 SODIMM_CKE1 5 SODIMM_CKE0 6 SODIMM_A12 7 SODIMM_A11 8 SODIMM_DM3 SODIMM_DQS3 CN1j 4 JTA 22R DDR_DQ26 4 DDR_DQ30 3 DDR_DQ27 2 DDR_DQ31 1 DDR_DM2 DDR_DQS2 RN04042 SODIMM_DQ26 5 SODIMM_DQ30 6 SODIMM_DQ27 7 SODIMM_DQ31 8 22R0 2 CN1j 4 JTA 22R DDR_DQ24 4 DDR_DQ28 3 DDR_DQ25 2 DDR_DQ29 1 R0408 1 22R0 2 CN1j 4 JTA 22R DDR_DQ18 4 DDR_DQ22 3 DDR_DQ19 2 DDR_DQ23 1 RN04041 SODIMM_DQ24 5 SODIMM_DQ28 6 SODIMM_DQ25 7 SODIMM_DQ29 8 SODIMM_DM2 R0407 1 RN04032 SODIMM_DQ18 5 SODIMM_DQ22 6 SODIMM_DQ19 7 SODIMM_DQ23 8 DDR_CK0- DDR_CK0+ DDR_DM1 DDR_DQS1 CN1j 4 JTA 22R DDR_DQ16 4 DDR_DQ20 3 DDR_DQ17 2 DDR_DQ21 1 22R0 2 R0406 1 RN04031 SODIMM_DQ16 5 SODIMM_DQ20 6 SODIMM_DQ17 7 SODIMM_DQ21 8 SODIMM_CK0- R0405 1 22R0 2 R0404 1 SODIMM_DM1 SODIMM_CK0+ 22R0 2 R0403 1 7 8 SODIMM_DQS1 SODIMM_DQ11 SODIMM_DQ15 CN1j 4 JTA 22R DDR_DQ10 4 DDR_DQ14 3 DDR_DQ11 2 DDR_DQ15 1 DDR_DM0 DDR_DQS0 RN04022 SODIMM_DQ10 5 SODIMM_DQ14 6 22R0 2 22R0 2 CN1j 4 JTA 22R DDR_DQ8 4 DDR_DQ12 3 DDR_DQ9 2 DDR_DQ13 1 R0402 1 R0401 1 CN1j 4 JTA 22R DDR_DQ2 4 DDR_DQ6 3 DDR_DQ3 2 DDR_DQ7 1 CN1j 4 JTA 22R DDR_DQ0 4 DDR_DQ4 3 DDR_DQ1 2 DDR_DQ5 1 RN04021 SODIMM_DQ8 5 SODIMM_DQ12 6 SODIMM_DQ9 7 SODIMM_DQ13 8 SODIMM_DM0 SODIMM_DQS0 RN04012 SODIMM_DQ2 5 SODIMM_DQ6 6 SODIMM_DQ3 7 SODIMM_DQ7 8 RN04011 SODIMM_DQ0 5 SODIMM_DQ4 6 SODIMM_DQ1 7 SODIMM_DQ5 8 Series Resistors 3 MEMORY_A[22:0] 32 34 13 16 14 FLASH_CE# MEMORY_OE# MEMORY_WE# FLASH_WP#/ACC FLASH_RESET# CE# OE# WE# WP#/ACC RESET# GND C0404 4u70 C0405 100n GND 30 1 27 28 55 56 FLASH_RY/BY#_A FLASH_BYTE# 17 53 C0406 4u70 NC NC NC NC NC NC 30 1 27 28 55 56 17 53 35 37 39 41 44 46 48 50 36 38 40 42 45 47 49 51 C0407 100n FLASH_RY/BY#_B FLASH_BYTE# MEMORY_DQ16 MEMORY_DQ17 MEMORY_DQ18 MEMORY_DQ19 MEMORY_DQ20 MEMORY_DQ21 MEMORY_DQ22 MEMORY_DQ23 MEMORY_DQ24 MEMORY_DQ25 MEMORY_DQ26 MEMORY_DQ27 MEMORY_DQ28 MEMORY_DQ29 MEMORY_DQ30 MEMORY_DQ31 Flash HIGH NC NC NC NC NC NC A0 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 128 Megabit DQ6 A7 DQ7 (x16) A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 A12 DQ12 A13 DQ13 A14 DQ14 A15 DQ15/A-1 A16 A17 MACRONIX A18 MX29LV128MBTI-90Q A19 A20 A21 RY/BY# A22 BYTE# U0403 GND VCC3V3 CE# OE# WE# WP#/ACC RESET# MEMORY_DQ0 MEMORY_DQ1 MEMORY_DQ2 MEMORY_DQ3 MEMORY_DQ4 MEMORY_DQ5 MEMORY_DQ6 MEMORY_DQ7 MEMORY_DQ8 MEMORY_DQ9 MEMORY_DQ10 MEMORY_DQ11 MEMORY_DQ12 MEMORY_DQ13 MEMORY_DQ14 MEMORY_DQ15 35 37 39 41 44 46 48 50 36 38 40 42 45 47 49 51 Flash LOW A0 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 DQ4 A4 DQ5 A5 A6 128 Megabit DQ6 A7 DQ7 (x16) A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 A12 DQ12 A13 DQ13 A14 DQ14 A15 DQ15/A-1 A16 A17 MACRONIX A18 MX29LV128MBTI-90Q A19 A20 RY/BY# A21 A22 BYTE# U0402 VCC3V3 31 26 25 24 23 22 21 20 10 9 8 7 6 5 4 3 54 19 18 11 12 15 2 32 34 13 16 14 31 26 25 24 23 22 21 20 10 9 8 7 6 5 4 3 54 19 18 11 12 15 2 MEMORY_A0 MEMORY_A1 MEMORY_A2 MEMORY_A3 MEMORY_A4 MEMORY_A5 MEMORY_A6 MEMORY_A7 MEMORY_A8 MEMORY_A9 MEMORY_A10 MEMORY_A11 MEMORY_A12 MEMORY_A13 MEMORY_A14 MEMORY_A15 MEMORY_A16 MEMORY_A17 MEMORY_A18 MEMORY_A19 MEMORY_A20 MEMORY_A21 MEMORY_A22 FLASH_CE# MEMORY_OE# MEMORY_WE# FLASH_WP#/ACC FLASH_RESET# MEMORY_A0 MEMORY_A1 MEMORY_A2 MEMORY_A3 MEMORY_A4 MEMORY_A5 MEMORY_A6 MEMORY_A7 MEMORY_A8 MEMORY_A9 MEMORY_A10 MEMORY_A11 MEMORY_A12 MEMORY_A13 MEMORY_A14 MEMORY_A15 MEMORY_A16 MEMORY_A17 MEMORY_A18 MEMORY_A19 MEMORY_A20 MEMORY_A21 MEMORY_A22 VCC3V3 MEMORY_DQ[15:0] 2 R0422 10K0 VCC3V3 MEMORY_DQ[31:16] R0421 10K0 VCC3V3 VCC3V3 MEMORY_A[17:0] VCC3V3 MEMORY_A[17:0] 17 SAMSUNG 11 33 17 41 6 40 39 1 2 3 4 5 18 19 20 21 22 23 24 25 26 27 42 43 44 12 34 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38 GND GND IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 IO16 C0408 4u70 P r o j e c t: Revision: Authors: IF W : C0409 100n SAMSUNG GND 1 12:36:34 S h e e t: 0 4 _ M e m o ry Last modified: Monday, September 04, 2006 17:15:10 MEMORY_DQ[31:16] MEMORY_DQ[15:0] Created: Friday, September 24, 2004 Page o f 12 4 H p e _ m in i L E C 2 R01 csam C0411 100n MEMORY_DQ16 MEMORY_DQ17 MEMORY_DQ18 MEMORY_DQ19 MEMORY_DQ20 MEMORY_DQ21 MEMORY_DQ22 MEMORY_DQ23 MEMORY_DQ24 MEMORY_DQ25 MEMORY_DQ26 MEMORY_DQ27 MEMORY_DQ28 MEMORY_DQ29 MEMORY_DQ30 MEMORY_DQ31 GND MEMORY_DQ0 MEMORY_DQ1 MEMORY_DQ2 MEMORY_DQ3 MEMORY_DQ4 MEMORY_DQ5 MEMORY_DQ6 MEMORY_DQ7 MEMORY_DQ8 MEMORY_DQ9 MEMORY_DQ10 MEMORY_DQ11 MEMORY_DQ12 MEMORY_DQ13 MEMORY_DQ14 MEMORY_DQ15 C0410 4u70 12 34 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38 K6R4016V1D-UI10 VCC VCC WE# OE# CS# UB# LB# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 U0405 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 A-4232 Hagenberg GND GND GND IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 IO16 K6R4016V1D-UI10 VCC VCC WE# OE# CS# UB# LB# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 U0404 Async. SRAM HIGH 11 33 VCC3V3 MEMORY_WE# MEMORY_OE# SRAM_CE# SRAM_BE3# SRAM_BE2# MEMORY_A0 MEMORY_A1 MEMORY_A2 MEMORY_A3 MEMORY_A4 MEMORY_A5 MEMORY_A6 MEMORY_A7 MEMORY_A8 MEMORY_A9 MEMORY_A10 MEMORY_A11 MEMORY_A12 MEMORY_A13 MEMORY_A14 MEMORY_A15 MEMORY_A16 MEMORY_A17 MEMORY_WE# 41 6 40 39 SRAM_CE# SRAM_BE1# SRAM_BE0# MEMORY_OE# 1 2 3 4 5 18 19 20 21 22 23 24 25 26 27 42 43 44 MEMORY_A0 MEMORY_A1 MEMORY_A2 MEMORY_A3 MEMORY_A4 MEMORY_A5 MEMORY_A6 MEMORY_A7 MEMORY_A8 MEMORY_A9 MEMORY_A10 MEMORY_A11 MEMORY_A12 MEMORY_A13 MEMORY_A14 MEMORY_A15 MEMORY_A16 MEMORY_A17 Async. SRAM LOW (2 x 4 Mbit organized as 256k words of 32 bits) MEMORY_A[22:0] SRAM (2 x 128 Mbit organized as 8M words of 32 bits) 1 Parallel Flash 29 Vio Vss 33 U0401 1 2 43 Vcc 29 Vio Vss 33 Vss 52 43 Vcc Vss 52 VCC2V5 1 2 DDR SDRAM socket (32 bit data bus) 1 2 DDR_DQ[31:0] 1 2 2 DDR_DQ[31:0] 2 1 2 Offpage 3 1 2 4 1 5 1 2 38 2 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 11. A B C D LED0# LED1# LED2# LED3# LED4# LED5# LED6# LED7# TST_ROW0 TST_ROW1 TST_ROW2 TST_ROW3 TST_COL0 TST_COL1 TST_COL2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 LCD_REGSEL 2 LCD_RW 2 LCD_ENABLE 2 DSW0 2 DSW1 2 DSW2 2 DSW3 2 TST_STEP SEG_CA0# SEG_CA1# SEG_A# SEG_B# SEG_C# SEG_D# SEG_E# SEG_F# SEG_G# SEG_DP# 2 2 2 2 2 2 2 2 2 2 5 LCD_REGSEL LCD_RW LCD_ENABLE DSW0 DSW1 DSW2 DSW3 TST_STEP TST_ROW0 TST_ROW1 TST_ROW2 TST_ROW3 TST_COL0 TST_COL1 TST_COL2 LED0# LED1# LED2# LED3# LED4# LED5# LED6# LED7# SEG_CA0# SEG_CA1# SEG_A# SEG_B# SEG_C# SEG_D# SEG_E# SEG_F# SEG_G# SEG_DP# TP0501 nb_TEST POINT 8x LED LED0# LCD Connector SEG_DP# SEG_G# SEG_F# SEG_E# SEG_D# SEG_C# SEG_B# 2 2 2 2 1 2 2 2 R0526 5K Display Contrast 4 GND VCC5V0 GND LCD_RW SEG_A# SEG_C# SEG_E# SEG_G# SEG_DP#_X SEG_G#_X SEG_F#_X SEG_E#_X SEG_D#_X SEG_C#_X SEG_B#_X SEG_A#_X LCD_CONT 1 1 1 1 1 1 TP0504 nb_TEST POINT LED3# LD0503 LED red 330R R0503 X6 HDR2 LCD Backlight on/off 120R R0521 120R R0519 120R R0516 120R R0514 1K00 R0513 1K00 R0511 VCC5V0 1 1 1 R0524 10K0 120R R0522 120R R0520 120R R0518 120R 2 SEG_CA1# 2 2 SEG_A# LED2# LD0502 LED red 330R R0502 TP0503 nb_TEST POINT SEG_CA0# R0515 TP0502 nb_TEST POINT LED1# LD0501 LED red 330R R0501 VCC3V3 7-Segment Display GND 1 2 1 1 2 1 1 1 2 2 1 1 Offpage 1 2 2 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 R0507 E F 1 D G A D1 DP C B VCC5V0 LCD_REGSEL LCD_ENABLE SEG_B# SEG_D# SEG_F# SEG_DP# GND D2 BC807-25 Q0502 1 BC807-25 Q0501 VCC3V3 3 TP0508 nb_TEST POINT LED7# LD0507 LED red 330R TP0507 nb_TEST POINT LED6# LD0506 LED red 330R R0506 TP0506 nb_TEST POINT LED5# LD0505 LED red 330R R0505 ELD-426SYGWA/S530-E2 A B C D E F G DP U0502 CON16A X7 7 6 4 1 3 8 9 2 SEG_CA1#_B SEG_CA0#_B TP0505 nb_TEST POINT LED4# LD0504 LED red 330R R0504 2 1 1 1 1 2 1 1 2 10 C.A. D1 SEG_CA1#_X 3 2 3 SEG_CA0#_X 5 2 1 LD0508 LED red 330R R0508 TP0509 nb_TEST POINT 1 3 TST_ROW0 2 GND R0525 1K00 TST_ROW3 GND R0523 1K00 TST_ROW2 GND R0517 1K00 TST_ROW1 GND 4 SW0501 B3FS-1012 1 3 R0512 1K00 4x DIP Switch Key Matrix GND Single Step Key TST_COL0 4 D0504 MMBD4148 4 4 D0507 MMBD4148 2 2 1 2 3 4 10K0 RP0502 8 7 6 5 D0510 MMBD4148 4 SW0511 B3FS-1012 1 3 2 SW0508 B3FS-1012 1 3 2 DSW0 DSW1 DSW2 DSW3 GND 4 D0501 MMBD4148 SW0505 B3FS-1012 1 3 2 SW0502 B3FS-1012 1 3 R0510 100K R0509 100K VCC3V3 2 GND C0501 100n TST_COL1 4 D0502 MMBD4148 D0505 MMBD4148 4 4 D0508 MMBD4148 2 SW DIP-4 D0511 MMBD4148 4 SW0512 B3FS-1012 1 3 2 SW0509 B3FS-1012 1 3 2 SW0506 B3FS-1012 1 3 2 SW0503 B3FS-1012 1 3 GND TST_STEP 1 2 3 4 1K0 RP0501 8 7 6 5 74AHC1G14_SOT353 4 U0501 VCC3V3 nc SW0514 1 2 5 3 5 TST_COL2 2 1 1 C.A. D2 1 2 1 2 1 2 1 39 2 D0506 MMBD4148 4 4 D0509 MMBD4148 2 P r o j e c t: Revision: Authors: IF W : D0512 MMBD4148 4 SW0513 B3FS-1012 1 3 2 SW0510 B3FS-1012 1 3 2 1 12:31:55 S h e e t: 0 5 _ L E D _ K E Y Last modified: Monday, September 04, 2006 17:15:09 Created: Friday, September 24, 2004 Page o f 12 5 H p e _ mini LEC2 R01 csam Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 A-4232 Hagenberg VCC3V3 4 D0503 MMBD4148 SW0507 B3FS-1012 1 3 2 SW0504 B3FS-1012 1 3 1 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 12. 40 A B C D 2 I2C_SDA1 2 I2C_SCL1 2,7,8,9 HPE_RESOUT# 2,3 HPE_RESET# 3 CLK_MACHXO 9 EXPCON_OSC 8 CLK_ETH 2 CLK_FPGA 5 I2C_SDA1 I2C_SCL1 HPE_RESOUT# HPE_RESET# CLK_MACHXO EXPCON_OSC CLK_ETH CLK_FPGA 2 4 SW0601 B3FS-1012 1 3 GND HPE_RESOUT# GND 1 2 nb_HDR2 X8 2 1 BAT54A D0601 3 GND 4 C0602 1n00 FB0601 BLM21PG331SN1D 1 2 R0605 10K0 VCC3V3 VCC3V3 Clock Sources Reset Button Ext. Reset Reset Control GND C0603 100n GND C0601 100n VCC3V3 8 RESET CAT1026SI-30 GND RESET SCL SDA VSENSE VLOW VCC U0601 2 1 CLK VCC 3 4 CLK GND C0604 100n VCC3V3_OSC VCC3V3_OSC OSC_SMT4_25MHz GND EN U0603 2 7 1 CAT_RESET GND 6 2 1 4 TP0601 TEST POINT CLK R0604 100K 3 5 7 8 1 3 R0607 nb_10K0 CY2304NZ_TSSOP8 VDD OUT1 OE OUT2 BUF_IN OUT3 GND OUT4 U0604 VCC3V3_OSC CAT_I2C_SDA 3 GND R0603 10K0 VCC3V3 R0606 nb_10K0 VCC3V3 CAT_RESET# CAT_I2C_SCL Vth = 1.25V x (R0601+R0602)/R0602 = 4.4V R0602 10K7 CAT_I2C_SCL 6 CAT_I2C_SDA 5 CAT_VSENSE 3 1.25 V 4 R0601 27K0 VCC5V0 1 2 Offpage 4 1 2 33R0 R0615 33R0 R0614 33R0 R0613 33R0 R0612 Rs of the I2C bus R0611 22R0 R0610 22R0 2 GND nc EXPCON_OSC CLK_MACHXO CLK_ETH CLK_FPGA I2C_SDA1 R0608 2K7 VCC3V3 R0609 2K7 Rp of the I2C bus HPE_RESET# 74AHC1G14_SOT353 4 U0602 I2C_SCL1 1 VCC3V3 5 3 5 2 2 1 12:38:11 S h e e t: 0 6 _ C l o c k _ R e s e t Last modified: Monday, September 04, 2006 17:15:09 Created: Friday, September 24, 2004 Page o f 12 6 H p e _ mini LEC2 R01 csam Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 A-4232 Hagenberg P r o j e c t: Revision: Authors: IF W : 1 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 13. A B C D USB_PWEN0 USB_OC0# USB_PWEN1 USB_OC1# USB_PWEN2 USB_OC2# 2 2 2 2 2 2 2,6,8,9 HPE_RESOUT# 3 USB_SCL 3 USB_SDA USB_MISO USB_SSI# USB_SCK USB_MOSI USB_TXD USB_RXD USB_RTS USB_CTS 2 USB_GPIO[28:0] 2 2 2 2 2 2 2 2 5 HPE_RESOUT# USB_SCL USB_SDA USB_PWEN0 USB_OC0# USB_PWEN1 USB_OC1# USB_PWEN2 USB_OC2# USB_MISO USB_SSI# USB_SCK USB_MOSI USB_TXD USB_RXD USB_RTS USB_CTS USB_GPIO[28:0] RS_TXD_LVTTL RS_RTS_LVTTL RS_RXD_LVTTL RS_CTS_LVTTL C0704 100n 4 5 GNDA_USB C0725 D0701 BAT54S C0724 100n 2 1 C0705 100n 2 15 6 16 13 8 14 7 GND VCC3V3 C0718 100n GND HPE_RESOUT# C0717 10u0 VCC3V3 100n USB_OTG_VBUS VCC3V3_USB 4 USB_OTG_DM1A USB_OTG_DP1A USB_DM1B USB_DP1B USB_MISO USB_SSI# USB_SCK USB_MOSI USB_TXD USB_RXD USB_RTS USB_CTS C0706 100n 0R00 2 R0701 1 CHARGE PUMP USB PORTS AGND DM2A DP2A DM2B DP2B MEMSEL ROMSEL RAMSEL POWER C0720 100n C0721 100n CY7C67300_TQFP100 VCC VCC VCC RESET RESERVED 1 26 51 75 100 29 28 16 15 14 6 9 10 4 5 34 35 36 GND GND VCC3V3 C0723 1n00 GNDA_USB C0722 100n VCC3V3_USB USB_XTALIN USB_XTALOUT GND GNDA_USB USB_DM2A USB_DP2A USB_DM2B USB_DP2B USB_GPIO0 USB_GPIO1 USB_GPIO2 USB_GPIO3 USB_GPIO4 USB_GPIO5 USB_GPIO6 USB_GPIO7 USB_GPIO8 USB_GPIO9 USB_GPIO10 USB_GPIO11 USB_GPIO12 USB_GPIO13 USB_GPIO14 USB_GPIO15 USB_GPIO16 USB_GPIO17 USB_GPIO18 USB_GPIO19 USB_GPIO20 USB_GPIO21 USB_GPIO22 USB_GPIO23 USB_GPIO24 USB_GPIO25 USB_GPIO26 USB_GPIO27 USB_GPIO28 USB_OTG_ID USB_SCL USB_SDA FB0704 BLM18PG600SN1 2 GND GND GND GND XTALIN XTALOUT OTGVBUS BOOSTVCC CSWITCHA BOOSTGND CSWITCHB VSWITCH RESET / CLOCK AVCC DM1A DP1A DM1B DP1B BEH WR RD 94 93 92 91 90 89 87 86 66 65 61 60 59 58 57 56 55 54 53 52 50 49 48 47 46 45 44 43 42 41 40 39 RS_DCD_LVTTL_X RS_DSP_LVTTL_X RS_DTP_LVTTL_X RS_CTS_LVTTL_X RS_TXD_LVTTL_X RS_RTS_LVTTL_X RS_RXD_LVTTL_X GPIO0/D0 GPIO1/D1 GPIO2/D2 GPIO3/D3 GPIO4/D4 GPIO5/D5 GPIO6/D6 GPIO7/D7 GPIO8/MISO/D8 GPIO9/SSI/D9 GPIO10/SCK/D10 GPIO11/MOSI/D11 GPIO12/D12 GPIO13/D13 GPIO14/D14 GPIO15/SSI/D15 GPIO16/TXD/I_A0 GPIO17/RXD/I_A1 GPIO18/RTS/I_A2 GPIO19/CS0/H_A0 GPIO20/CS1/H_A1 GPIO21/nCS GPIO22/WR/IOW GPIO23/RD/IOR GPIO24/INT/IORDY GPIO25 GPIO26/CTS/PWM3 GPIO27/RX GPIO28/TX GPIO29/OTGID GPIO30/SCL GPIO31/SDA GPIO 0R00 2 R0702 1 D0 D1 D2 D3 D4 D5 D6 D7 D8/MISO D9/SSI D10/SCK D11/MOSI D12/TXD D13/RXD D14/RTS D15/CTS EXT MEMORY CONTROL A0/BEL A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15/CLKSEL A16 A17 A18 U0702 EXT MEMORY C0719 100n 37 63 88 85 84 11 13 12 21 22 23 18 19 98 64 62 83 82 81 80 79 78 77 76 74 73 72 71 70 69 68 67 99 1 2 3 7 8 17 20 24 25 27 30 31 32 33 38 97 95 96 VCC3V3 GND USB_A15 R0703 47K0 VCC3V3 V+ GND V- VCC R1IN R2IN T1OUT T2OUT MAX3232/TSSOP C2+ C2- C1+ C1- R1OUT R2OUT T1IN T2IN U0701 USB Controller C0703 100n 12 9 RS_RXD_LVTTL RS_CTS_LVTTL 1 3 11 10 RS_TXD_LVTTL RS_RTS_LVTTL RS232 Interface 2 1 2 RS_TXD_LVTTL 2 RS_RTS_LVTTL 2 RS_RXD_LVTTL 2 RS_CTS_LVTTL 3 CON_DSUB_9M X9 Q0701 CRYSTAL_12MHz R0706 15K0 VCC3V3 USB_GPIO[28:0] 5 9 4 8 3 7 2 6 1 1 2 Offpage 2 1 1 3 GND C0715 22p0 C0702 10u0 GNDA_USB 1 2 USB_PWEN2 USB_OC2# 6 3 4 7 GNDA_USB C0712 1u00 GNDA_USB 3 4 USB_OC1# USB_PWEN1 VCC5V0 1 2 USB_PWEN0 USB_OC0# 6 7 GNDA_USB C0707 1u00 VCC5V0 VCC3V3 C0716 22p0 R0707 10K0 VCC3V3 R0705 10K0 GND C0701 100n VCC3V3 R0704 10K0 3 R0708 nb_1M00 2 4 2 1 1 2 1 2 OUTB OUTA OUTB OUTA SP2526-1EN GND FLGB ENB ENA FLGA IN U0704 SP2526-1EN GND FLGB ENB ENA FLGA IN U0703 USB_SCL USB_SDA GNDA_USB + C0713 100u USB_VBUS2 GNDA_USB + C0710 100u USB_VBUS1 GNDA_USB C0714 100n C0711 100n C0709 100n USB_VBUS0_X USB_VBUS1_X USB_VBUS2_X 2 GND GPIO31 SDA 0 0 1 1 RJ0702 0R00 Host Port Interface (HPI) High-Speed Serial (HSS) Serial Peripheral Interface (SPI) I2C EEPROM (Standalone Mode) GND RJ0701 nb_10K0 GPIO30 SCL 0 1 0 1 RJ0704 0R00 RJ0703 nb_10K0 VCC3V3 BLM21PG331SN1D 2 FB0703 BLM21PG331SN1D 2 FB0702 BLM21PG331SN1D 2 FB0701 VCC3V3 1 1 1 Boot Configuration Interface 5 8 5 8 + C0708 100u USB_VBUS0 2 GND USB_OTG_VBUS_X FB0705 1500mA BLM21PG331SN1D 330 Ohm @ 100 MHz 1C 2C 3C 4C USB_VBUS2_X USB_DM2B USB_DP2B 6 7 8 9 1 SHIELD SHIELD SHIELD P r o j e c t: Revision: Authors: IF W : 16 15 14 13 GNDP 1 12:34:50 S h e et: 07_Serial_USB Last modified: Monday, September 04, 2006 17:15:10 USB HOST USB HOST USB HOST USB OTG Created: Friday, September 24, 2004 Page 7 o f 12 Hpe_mini LEC2 R01 csam GNDA_USB USB_TypeA/Host VCC DATADATA+ GND X11C USB_TypeA/Host VCC DATADATA+ GND X11B USB_TypeA/Host VCC DATADATA+ GND SHIELD USB miniAB 440479-1 VBUS SH1 DSH2 D+ ID SH3 GND SH4 X10 X11A 1 2 3 4 5 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 A-4232 Hagenberg GND GNDA_USB 1B 2B 3B 4B 1A 2A 3A 4A USB_VBUS1_X USB_DM2A USB_DP2A USB_VBUS0_X USB_DM1B USB_DP1B C0727 nb_100n GND USB_OTG_DM1A USB_OTG_DP1A USB_OTG_ID C0726 4u70 USB_OTG_VBUS 1 2 5 1 2 1 2 1 2 1 41 2 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 14. ETH_RXER ETH_RXD3 ETH_RXD2 ETH_RXD1 ETH_RXD0 RJ0804 10K0 ETH_RXCLK0 1 RJ0806 10K0 C0810 220n RP0802 10k0 RJ0805 VCC3V3 nb_10K0 ETH_TXCLK0 1 FB0802 BLM18PG600SN1 1 2 VCC3V3 22R0 R0806 22R0 R0802 RJ0803 nb_10K0 2 2 C0813 10n0 52 49 63 62 1 ETH_RXDV ETH_CRS ETH_COL CLK_ETH GND_LAN 21 22 8 40 51 VCC3V3 9 10 44 32 33 39 4 43 42 3 ETH_MDC ETH_MDIO HPE_RESOUT# 64 ETH_MDINTR# VCC3V3_LAN VCC3V3_LAN GND 53 45 46 47 48 ETH_RXER ETH_RXD3 ETH_RXD2 ETH_RXD1 ETH_RXD0 2 56 55 ETH_TXEN LXT971A VCCA VCCA VCCIO VCCIO VCCD nc nc nc SLEEP PAUSE PWRDWN RESET# MDC MDIO MDDIS MDINT# XO REFCLK/XI CRS COL RX_CLK RX_DV RX_ER RXD3 RXD2 RXD1 RXD0 TX_EN TX_CLK TPFOP DGND DGND DGND DGND DGND DGND DGND TEST0 TEST1 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 TDI TDO TMS TCK TRST LED/CFG1 LED/CFG2 LED/CFG3 RBIAS TxSLEW0 TxSLEW1 SD/TP TPFIN TPFIP TPFON 24 61 50 41 25 18 11 7 34 35 16 15 14 13 12 27 28 29 30 31 38 37 36 17 5 6 26 1 23 GND ETH_CFG1 ETH_CFG2 ETH_CFG3 0 0 1 1 GND 0 1 0 1 TxSLEW1 R0817 10K0 R0804 nb_10K0 VCC3V3 TxSLEW0 GND 3 R0816 22K1 2 1 GND C0802 270p 2 C0801 270p 2 1 20 19 2.5ns 3.1ns 3.7ns 4.3ns C0805 10n0 R0807 49R9 GND_LAN Slew Rate R0818 10K0 R0805 nb_10K0 C0803 100n R0808 49R9 LAN_RX- LAN_RX+ LAN_TX- LAN_TX+ C0804 100n 5 4 6 1 3 2 FB0801 BLM11B750S VCC3V3_LAN RX+ CT_RX RX- TX+ CT_TX TX- 2 220n 1 C0809 PULSE H1112 RD+ CT_RD RD- TD+ CT_TD TD- U0802 8 9 7 2 12 10 11 C0806 1n00 2kV R0809 49R9 C0807 1n00 2kV R0810 49R9 GNDP C0808 1n00 2kV R0814 49R9 R0811 49R9 R0815 49R9 R0812 49R9 GNDP ETH_RX- ETH_TX+ ETH_TXETH_RX+ 13 1 2 3 4 5 6 7 8 14 RJ-45-LED SHIELD TX+ TXLED2+ RX+ LED2nc nc RXLED1+ nc LED1nc SHIELD X12 R0801 220R P r o j e c t: Revision: Authors: IF W : R0803 220R Hpe_mini LEC2 R01 csam LED0801 LED red R0813 220R VCC3V3 ETH_CFG3 ETH_CFG1 ETH_CFG2 11 12 9 10 VCC3V3 1 S h e et: 08_Ethernet Last modified: Monday, September 04, 2006 17:15:10 C D 5 4 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 A-4232 Hagenberg 1 Created: Tuesday, December 14, 2004 14:10:51 Page o f 12 8 A GND_LAN GND RJ0802 10K0 RJ0801 nb_10K0 VCC3V3 ETH_RXCLK ETH_TXCLK TX_ER TXD3 TXD2 TXD1 TXD0 U0801 2 A GND CLK_ETH HPE_RESOUT# ETH_MDC ETH_MDIO ETH_MDINTR# ETH_CRS ETH_COL ETH_RXCLK ETH_RXDV ETH_RXER ETH_RXD3 ETH_RXD2 ETH_RXD1 ETH_RXD0 54 60 59 58 57 ETH_TXER ETH_TXD3 ETH_TXD2 ETH_TXD1 ETH_TXD0 RP0801 10k0 3 B 6 CLK_ETH 2,6,7,9 HPE_RESOUT# 2 ETH_MDC 2 ETH_MDIO 2 ETH_MDINTR# 2 ETH_CRS 2 ETH_COL 2 ETH_RXCLK 2 ETH_RXDV 2 2 2 2 2 ETH_TXEN ETH_TXCLK GND 4 8 7 6 5 1 2 3 4 B C D 2 ETH_TXEN 2 ETH_TXCLK Ethernet 1 ETH_TXER ETH_TXD3 ETH_TXD2 ETH_TXD1 ETH_TXD0 1 2 2 1 2 2 1 2 2 1 1 2 2 1 1 2 2 1 2 1 1 2 2 1 2 1 1 1 2 2 ETH_TXER 2 ETH_TXD3 2 ETH_TXD2 2 ETH_TXD1 2 ETH_TXD0 1 1 2 2 1 2 2 Offpage 1 2 42 2 1 8 7 6 5 1 2 3 4 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 1 2 1 2 5 Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 15. A B C D 2 SATA_X2D0+ 2 SATA_X2D02 SATA_X2D1+ 2 SATA_X2D1- 2 SATA_X1D0+ 2 SATA_X1D02 SATA_X1D1+ 2 SATA_X1D1- 2 BB3V3_CLK0+ 2 BB3V3_CLK0- 2 BB3V3_IO[21:0] 2,6,7,8 HPE_RESOUT# 6 EXPCON_OSC 2 EXPCON_CLKIN 2 EXPCON_CLKOUT 2 CARDSEL# 2 EXPCON_IO[45:0] 5 SATA_X2D0+ SATA_X2D0SATA_X2D1+ SATA_X2D1- SATA_X1D0+ SATA_X1D0SATA_X1D1+ SATA_X1D1- BB3V3_CLK0+ BB3V3_CLK0- BB3V3_IO[21:0] HPE_RESOUT# EXPCON_OSC EXPCON_CLKIN EXPCON_CLKOUT CARDSEL# EXPCON_IO[45:0] GND EXPCON_IO16 EXPCON_IO17 EXPCON_IO18 EXPCON_IO19 EXPCON_IO21 EXPCON_IO22 EXPCON_IO24 EXPCON_IO25 EXPCON_IO27 EXPCON_IO28 HPE_RESOUT# EXPCON_IO0 EXPCON_IO2 EXPCON_IO4 EXPCON_IO6 EXPCON_IO8 EXPCON_IO10 EXPCON_IO12 EXPCON_IO14 4 SATA_XT2D0+ SATA_XT2D0- SATA_XT1D1+ SATA_XT1D1- SATA_XT1D0+ SATA_XT1D00R00 2 0R00 2 R0908 1 0R00 2 R0907 1 R0905 1 GND GND_HS 1 2 3 4 5 6 7 SATA_XT2D1SATA_XT2D1+ SATA_XT2D0+ SATA_XT2D0- GND_HS Sternpunkt X16 CON_SATA GND A+ AGND BB+ GND LVDS LVDS LVDS SATA_XT2D1+ SATA_XT2D10R00 2 0R00 2 R0914 1 R0916 1 0R00 2 R0913 1 R0915 nb_100R R0912 nb_100R R0909 nb_100R R0906 nb_100R 3 SATA_X2D1+ SATA_X2D1- SATA_X2D0+ SATA_X2D0- SATA_X1D1+ SATA_X1D1- SATA_X1D0+ SATA_X1D0- 3 LVDS LVDS LVDS LVDS BB3V3_IO[21:0] BB3V3_IO11 BB3V3_IO10 BB3V3_IO9 BB3V3_IO8 BB3V3_IO7 BB3V3_IO6 BB3V3_IO5 BB3V3_IO4 BB3V3_IO3 BB3V3_IO2 BB3V3_IO1 BB3V3_IO0 GND TP0912 TP0911 TP0910 TP0909 TP0908 TP0907 TP0906 TP0905 TP0904 TP0903 TP0902 TP0901 TP0924 TP0923 TP0922 TP0921 TP0920 TP0919 TP0918 TP0917 TP0916 TP0915 TP0914 TP0913 VCC3V3 TP0936 TP0935 TP0934 TP0933 TP0932 TP0931 TP0930 TP0929 TP0928 TP0927 TP0926 TP0925 TP0948 TP0947 TP0946 TP0945 TP0944 TP0943 TP0942 TP0941 TP0940 TP0939 TP0938 TP0937 TP0960 TP0959 TP0958 TP0957 TP0956 TP0955 TP0954 TP0953 TP0952 TP0951 TP0950 TP0949 TP0972 TP0971 TP0970 TP0969 TP0968 TP0967 TP0966 TP0965 TP0964 TP0963 TP0962 TP0961 Prototyping Area (RM2.54) of FPGA Place the 0402-resistors of the LVDS termination as close as possible to the FPGA. 0R00 2 LVDS LVDS LVDS R0911 1 GND R0904 10K0 VCC3V3 X16 LVDS EXPCON_IO26 CARDSEL# EXPCON_IO23 EXPCON_IO20 EXPCON_IO1 EXPCON_IO3 EXPCON_IO5 EXPCON_IO7 EXPCON_IO9 EXPCON_IO11 EXPCON_IO13 EXPCON_IO15 EXPCON_3V3 GND EXPCON_IO29 EXPCON_IO31 EXPCON_IO33 EXPCON_IO35 EXPCON_IO37 EXPCON_IO39 EXPCON_IO41 EXPCON_IO43 EXPCON_IO45 CON_SATA SATA_XT1D1SATA_XT1D1+ SATA_XT1D0+ SATA_XT1D0- LVDS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Pin 2 removed for coding of expansion board 0R00 2 GND A+ AGND BB+ GND 1 2 3 4 5 6 7 HDR40 X14 HDR40 X13 R0910 1 X15 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 13 15 17 19 21 EXPCON_2V5 23 25 27 EXPCON_OSC 29 EXPCON_CLKIN 31 EXPCON_CLKOUT 33 35 37 EXPCON_3V3 39 EXPCON_2V5 EXPCON_IO30 EXPCON_IO32 EXPCON_IO34 EXPCON_IO36 EXPCON_IO38 EXPCON_IO40 EXPCON_IO42 EXPCON_IO44 SATA-Connector R0902 0R00 VCC3V3 VCC5V0 GND R0901 0R00 VCC2V5 Expansion Connector 1 2 Offpage 1 2 4 1 2 5 2 1 2 1 2 1 2 43 1 TP0984 TP0983 TP0982 TP0981 TP0980 TP0979 TP0978 TP0977 TP0976 TP0975 TP0974 TP0973 TP0996 TP0995 TP0994 TP0993 TP0992 TP0991 TP0990 TP0989 TP0988 TP0987 TP0986 TP0985 TP09111 TP09123 TP09135 TP09110 TP09122 TP09134 TP09133 2 TP09108 TP09120 TP09132 TP09144 TP09107 TP09119 TP09131 TP09143 TP09106 TP09118 TP09130 TP09142 TP09105 TP09117 TP09129 TP09141 TP09104 TP09116 TP09128 TP09140 TP09103 TP09115 TP09127 TP09139 TP09102 TP09114 TP09126 TP09138 TP09101 TP09113 TP09125 TP09137 TP09100 TP09112 TP09124 TP09136 TP0999 TP0998 TP0997 TP09109 TP09121 2 BB3V3_CLK0- BB3V3_CLK0+ BB3V3_IO21 BB3V3_IO20 BB3V3_IO19 BB3V3_IO18 BB3V3_IO17 BB3V3_IO16 BB3V3_IO15 BB3V3_IO14 BB3V3_IO13 BB3V3_IO12 DIFF BB3V3_IO[21:0] S h e et: 09_ExpCon_ProtoArea Last modified: Monday, September 04, 2006 17:15:10 1 Created: Tuesday, December 14, 2004 14:28:58 Page o f 12 9 Hpe_mini LEC2 R01 csam Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 A-4232 Hagenberg P r o j e c t: Revision: Authors: IF W : 1 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 16. 44 A B C D 2 2 2 2 2 2 2 2 VGA_RD0 VGA_RD1 VGA_GR0 VGA_GR1 VGA_BL0 VGA_BL1 VGA_HSYNC VGA_VSYNC AC97_BITCLK AC97_SDATA_OUT AC97_SDATA_IN AC97_SYNC AC97_RESET# AC97_EXT_CLK AC97_EAPD 5 GNDA_AUD GND Locate under CODEC use 60 mil wide trace between digital and analog GND planes VGA_RD0 VGA_RD1 VGA_GR0 VGA_GR1 VGA_BL0 VGA_BL1 VGA_HSYNC VGA_VSYNC AC97_BITCLK AC97_SDATA_OUT AC97_SDATA_IN AC97_SYNC AC97_RESET# AC97_EXT_CLK AC97_EAPD GNDA_AC C1015 1u00 FB1002 BLM18PG600SN1 2 GND C1016 100n R1017 270R R1014 270R R1011 270R VGA_VSYNC VGA_HSYNC VGA_BL1 VGA_BL0 VGA_GR1 VGA_GR0 VGA_RD1 VGA_RD0 C1019 100n 2 LC1002 NFE31PT222Z1E9 2 GNDA_AC R1018 270R R1016 270R R1015 270R R1013 270R R1012 270R 4 VGA_BL_X GND VGA_GR_X VGA_RD_X GND GND PLL ---> AC97_AIN_R AC97_AIN_L Connect ANALOG GND to GND on Plane realized in CAMTASTIC R1010 270R VDDA5V0_AC97 C1018 100n VDD3V3_AC97 VGA Interface 1 VCC5V0 C1017 1u00 VCC3V3 FB1001 BLM18PG600SN1 1 2 Audio Codec 3 2 2 2 2 2 2 2 3 X19 1 5L 4L 1L 15 14 13 12 11 R1027 1M00 C1006 100p 1 NF_R C1008 1n00 2 Q1001 nb_24.576MHz 0R00 R1026 GNDA_AC R1006 1k00 GNDA_AC R1003 1k00 C1004 1n00 Shield ST-4235-3/3-N LINE-IN NF_L FB1004 BLM21PG331SN1D 1 2 C1007 100p CON_DSUB_15F 6 1 7 2 8 3 9 4 10 5 33p0 C1029 33p0 C1028 1 X17A FB1003 BLM21PG331SN1D 1 2 AC97_EXT_CLK R1005 0R00 R1002 0R00 GNDA_AC 1 LC1001 NFE31PT222Z1E9 2 2L C1003 VDDA5V0_AC97 VDD3V3_AC97 3 25 38 1 9 3 ANALOG AFILT1/NC AFILT2/NC AFILT3/NC REFFLT VREFOUT MONO_OUT AVDD NC/AVDD DVDD1 DVDD2 XTL_OUT XTL_IN RESET DVSS1 DVSS2 AVSS AVSS/NC POWER SPDIF/NC EAPD/NC ID1 ID0 HPP/NC NC CLOCK BIT_CLK SDATA_OUT SDATA_IN SYNC 3DFLT/NC 3DN PHONE 3DP DIGITAL INTERFACE PC_BEEP AUX_L AUX_R VIDEO_L VIDEO_R MIC1 MIC2 CD_L HP_OUT_L CD_GND HP_OUT_C/NC CD_R HP_OUT_R LINE_IN_L LINE_OUT_L LINE_IN_R LINE_OUT_R U1001 AC'97 CODEC C1020 PB-Free Part: nb_100n LM4549BVHX GNDA_AC R1023 nb_0R00 R1028 0R0 2 AC97_XTL_IN AC97_XTL_OUT 11 AC97_RESET# 6 5 8 10 13 12 14 15 16 17 21 22 18 19 20 23 24 ---> R1021 33R0 GNDA_AC C1014 100n AC97_LINEIN_L AC97_LINEIN_R AC97_BITCLK AC97_SDATA_OUT AC97_SDATA_IN AC97_SYNC 1 1 26 42 4 7 48 47 46 45 44 43 32 33 34 29 30 31 27 28 37 39 40 41 35 36 C1011 22n0 GNDA_AC R1022 nb_0R00 GND 3L NF_L NF_R 5U 4U 1U 1 1 C1002 1u00 R1020 nb_0R00 R1025 nb_0R00 2 2 2 1 1 LC1004 NFE31PT222Z1E9 2 AC97_SPDIF_OUT AC97_EAPD C0805 TP1003 C1023 nb_10u0 10u0 (VT1612A) 1u00 (AD1881) C1024 nb_1n00 1u00 (AD1881) C0805 GNDA_AC R1009 47k0 GNDA_AC FB1006 BLM21PG331SN1D 2 R1008 47k0 FB1005 BLM21PG331SN1D 1 2 GNDA_AC 2 LC1003 NFE31PT222Z1E9 2 C1022 nb_100n 100n (VT1612A) 10n0 (CS4299) C0603 TP1002 TP1001 1u00 C1021 nb_22n0 47n0 (AD1881) C0603 C1005 Shield 4 ST-4235-3/3-N Headphone / Line-out X17B GNDA_AC R1024 nb_0R00 100n (AD1881) 1n00 (CS4299) AC97_PIN48 AC97_PIN47 AC97_3DFLT AC97_3DN AC97_3DP AC97_AFILT1 AC97_AFILT2 AC97_AFILT3 AC97_VREF AC97_VREFOUT AC97_HP_OUT_L AC97_HP_OUT_C AC97_HP_OUT_R AC97_LINEOUT_L AC97_LINEOUT_R LOCATE SEPERATE ANALOG POWER AND ANALOG GROUND PLANES DIRECTLY ON TOP OF ONE ANOTHER WITHOUT OVERLAPPING DIGITAL POWER OR GROUND PLANES. A SINGLE ZERO OHM RESISTOR SHOULD LINK THE DIGITAL AND ANALOG GROUND PLANES AS CLOSE TO THE CODEC AS POSSIBLE. <-----> <-----> R1007 1u00 47k0 2 C1001 R1004 1u00 47k0 2 3 3 Offpage 4 2 + 1 + 1 + + 1 C1025 nb_1n00 270p (VT1612A) C0603 C1010 1n00 AC97_AOUT_R C1009 1n00 AC97_AOUT_L 3 5 C1026 nb_1n00 270p (VT1612A) C0603 C0603 C1027 nb_1u00 270p (VT1612A) P r o j e c t: Revision: Authors: IF W : GNDA_AC S h e et: 10_Audio_VGA Last modified: Monday, September 04, 2006 17:15:09 1 Created: Tuesday, December 14, 2004 14:11:30 Page o f 12 10 Hpe_mini LEC2 R01 csam C1013 10u0 10u0 (VT1612A) 3u30 (LM4480) 1u00 (CS4299) C1206 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 A-4232 Hagenberg C1012 100n C0603 R1019 10k0 nb_10k0 (VT1612A) VDDA5V0_AC97 1 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 17. A B C D GND_PWR GND Connect ANALOG GND to GND on Plane 5 extra ANALOG GND plane connected with 6Vias to GND on plane CENTER C1120 100n 1 2 3 C1121 100n GND GND C1131 10u0 VCC5V0 1 2 3 D1102 2 TPS64203DBVT 6 5 4 4 R1107 15K0 C1117 220p 10MQ040N 1 EN SW GND VIN FB ISENSE U1102 C1122 33p0 VCC_KLD 2.5V/2.6V (2A) C1119 10n0 KLD-0202-A OUTSIDE OPENER 2 1 X20 R1116 1 R1115 1 C1123 33p0 + C1107 47u0 20V C7343 GND 10R0 2 3 G GND R1108 15K0 C1118 220p C1114 10u0 GND_PWR 0R033 2 GND_PWR + C1106 47u0 20V C7343 VCC5V0 T1103 S Si3445DV D D1106 10MQ040N GND 5 20 9 11 8 15 1 6 10 7 28 R1118 36k0 1% 10u0 L1103 R1117 42K2 1% optional A1101 Jumper X21 HDR3 max 2.4A GND C1134 1u00 VCC2V5_T PW_BOOST2 PW_BOOST1 + C1133 100u GND 12 13 14 19 17 16 18 4 3 2 23 26 27 25 R1119 39k0 1% C1132 4p70 Vos2 SENSE2- SENSE2+ BG2 SW2 TG2 BOOST2 Vos1 SENSE1- SENSE1+ BG1 SW1 TG1 BOOST1 C1105 100n LTC1628-SSOP28 PGND SGND ITH2 ITH1 RUN/SS2 RUN/SS1 STBYMD 3V3Out FCB FLTCPL FREQSET INTVcc Ext_Vcc VIN U1101 GND C1104 10u0 3 3 2 PH1103 PlaceHolder 1 GND 1 LD1102 LED green 2.5V PG R1120 100R VCC2V5 Place the parts C1103, C1105 and C1124 as close as possible to the pins of the U1101 Set the jumper to 1-2 for 2.5V and to 3-2 for 2.6V (This is important for the DDR SDRAM module) GND 22 24 21 GND_PWR GND_PWR R1103 4k70 3.3V (1A) / 1.2V (2A) DC/DC-Converter 4 2 1 2 1 1 PW_T1B_GATE C1113 nb_10n0 GND_PWR C1103 100n TP1104 TEST POINT 2.5V C1125 nb_10n0 5 VCC5V0 R1105 5R10 C1108 1n00 PW_SW1 GND_PWR R1110 5R10 C1126 1n00 GNDP optional Label01 LABEL optional Pad1101 ArtNr05281 optional Pad1102 ArtNr05281 2 optional Pad1103 ArtNr05281 GND max 2A C1127 1n00 R1111 0R05 max 1A C1112 1n00 R1102 0R025 GNDP 1 1 optional Pad1105 ArtNr05281 PW_SW2_L D1105 10MQ040N 100u0 L1102 C1116 100n PW_SW1_L D1103 10MQ040N 33u0 L1101 C1102 100n optional Pad1104 ArtNr05281 PW_SW2 GND_PWR C1115 10u0 Miscellaneous DRILL1103 DRILL DRILL1101 DRILL 2 C1101 10u0 GND_PWR T1102B SI6966DQ T1102A SI6966DQ PW_VOS2 2 GND_PWR T1101B SI6966DQ T1101A SI6966DQ VOS1 VCC5V0 Drill PW_T2B_GATE GND_PWR C1124 100n 4 5 PW_T1A_GATE 4 D1101 MBR0540LT1 D1104 MBR0540LT1 PW_T2A_GATE 2 5 4 1 2 5 6 2 1 1 2 3 2 1 1 8 1 2 1 2 3 8 7 6 2 3 7 6 1 2 1 2 1 2 1 DRILL1104 DRILL DRILL1102 DRILL 2 2 C1128 180p C1109 180p 1 2 1 R1106 10K0 1% R1104 5K10 1% GND_PWR + C1111 220u 10V C7343H LESR40 P r o j e c t: Revision: Authors: IF W : VCC1V2 TEST POINT 1.2V TP1101 1 1 09:11:59 S h e et: 11_PowerSupply Last modified: Monday, September 04, 2006 17:14:07 LD1101 LED green 3.3V PG TEST POINT 3.3V TP1103 1 Created: Friday, September 10, 2004 Page 11 o f 12 GND R1114 330R VCC3V3 TEST POINT GND TP1102 1 PH1102 PlaceHolder 1 2 GND PH1101 PlaceHolder 1 2 1 Hpe_mini LEC2 R01 csam + C1130 220u 10V C7343H LESR40 GND_PWR C1129 10u0 VCC3V3_T GND_PWR C1110 10u0 10V VCC1V2_T Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 A-4232 Hagenberg R1113 15K0 1% R1112 47K0 1% GND_PWR 2 2 1 2 1 2 1 Offpage 1 2 1 2 2 45 1 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 18. 46 3 2 1 EXPANSION CONNECTOR & SATA 5 4 3 position of U0601 must be changed away from the DDR test adapter added (X23) final version new release CHANGE DESCRIPTION ... DATE REVISIONS ... VERSION 2 ... AUTHOR ... CHANGE DESCRIPTION Pr o je ct: Revision: Hp e _ min i L EC2 R01 csam 0 1 _ O ve r vie w Sh e e t: Last modified: Monday, September 04, 2006 10:13:29 C 1 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 Created: Monday, September 13, 2004 A-4232 Hagenberg Page 1 of 12 Authors: IFW: 05:56:22 A CSAM CSAM CSAM AUTHOR A 1.2 1.1 1.0 VERSION D B 12/12 DESIGN NOTES 11/12 POWER SUPPLY 10/12 AUDIO & VGA 9/12 6/12 USB & RS232 HUMAN INTERFACE CLOCK & RESET 5/12 ETHERNET MEMORY 4/12 8/12 FPGA CONFIGURATION 3/12 7/12 19-07-2006 FPGA I/O & POWER 2/12 04-09-2006 05-05-2006 PROJECT OVERVIEW DATE REVISIONS 1/12 SHEET PAGE DESCRIPTION PAGE LOCATOR Copying of this document, and giving it to others and the use or communication of the contents thereof, are forbidden without express authority. Offenders are liable to the payment of damages. All rights are reserved in the event of the grant of a patent or the registration of a utility model or design. Copyright © Gleichmann Electronics Research (Austria) GmbH & Co KG 2005, All Rights Reserved Gleichmann Electronics Hpe_mini_LEC2 V1.2 4 B C D 5 Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Appendix B. Board Version 2 Schematic Figure 19. A B C D LED0# LED1# LED2# LED3# LED4# LED5# LED6# LED7# 5 5 5 5 5 5 5 5 USB_MISO USB_SSI# USB_SCK USB_MOSI USB_TXD USB_RXD USB_RTS USB_CTS 9 EXPCON_IO[45:0] 3 MACHXO_IO[15:0] 4 DDR_WE# 4 DDR_RAS# 4 DDR_CAS# 4 DDR_CK0+ 4 DDR_CK04 DDR_CKE0 4 DDR_BA0 4 DDR_DM[3:0] 4 DDR_DQ[31:0] SRAM_BE0# SRAM_BE1# SRAM_BE2# SRAM_BE3# SRAM_CE# 4 MEMORY_OE# 4 MEMORY_WE# 4 MEMORY_A[22:0] 10 VGA_RD0 10 VGA_RD1 10 VGA_GR0 10 VGA_GR1 10 AC97_BITCLK 10 AC97_SDATA_OUT 10 AC97_SDATA_IN 10 AC97_SYNC 9 SATA_X1D0+ 9 SATA_X1D09 SATA_X1D1+ 9 SATA_X1D1- 9 CARDSEL# 9 EXPCON_CLKIN 9 EXPCON_CLKOUT 4 4 4 4 4 5 LCD_REGSEL 5 LCD_RW 5 LCD_ENABLE 5 DSW0 5 DSW1 5 DSW2 5 DSW3 ETH_CRS ETH_COL ETH_RXCLK ETH_RXDV ETH_TXEN ETH_TXCLK ETH_TXER ETH_TXD3 ETH_TXD2 ETH_TXD1 ETH_TXD0 USB_MISO USB_SSI# USB_SCK USB_MOSI USB_TXD USB_RXD USB_RTS USB_CTS USB 7 7 7 7 7 7 8 ETH_MDC 8 ETH_MDIO 8 ETH_MDINTR# 8 ETH_RXER 8 ETH_RXD3 8 ETH_RXD2 8 ETH_RXD1 8 ETH_RXD0 USB_PWEN0 USB_OC0# USB_PWEN1 USB_OC1# USB_PWEN2 USB_OC2# 7 RS_RXD_LVTTL 7 RS_CTS_LVTTL Ethernet USB_GPIO[28:0] RS_TXD_LVTTL RS_RTS_LVTTL RS232 HPE_RESOUT# 6 I2C_SDA1 6 I2C_SCL1 6 CLK_FPGA Clock / Reset HPE_RESET# LED0# LED1# LED2# LED3# LED4# LED5# LED6# LED7# TST_ROW0 TST_ROW1 TST_ROW2 TST_ROW3 TST_COL0 TST_COL1 TST_COL2 5 TST_STEP 5 5 5 5 5 5 5 ETH_MDC ETH_MDIO ETH_MDINTR# ETH_RXER ETH_RXD3 ETH_RXD2 ETH_RXD1 ETH_RXD0 USB_PWEN0 USB_OC0# USB_PWEN1 USB_OC1# USB_PWEN2 USB_OC2# RS_RXD_LVTTL RS_CTS_LVTTL I2C_SDA1 I2C_SCL1 CLK_FPGA LCD_REGSEL LCD_RW LCD_ENABLE DSW0 DSW1 DSW2 DSW3 TST_STEP TST_ROW0 TST_ROW1 TST_ROW2 TST_ROW3 TST_COL0 TST_COL1 TST_COL2 9 BB3V3_IO[21:0] 9 SATA_X2D0+ 9 SATA_X2D09 SATA_X2D1+ 9 SATA_X2D1- 9 BB3V3_CLK0+ 9 BB3V3_CLK0- 5 FLASH_CE# FLASH_RESET# FLASH_RY/BY#_A FLASH_RY/BY#_B FLASH_WP#/ACC FLASH_BYTE# 4 DDR_S0# 4 DDR_S1# 4 DDR_VREF 4 DDR_CK1+ 4 DDR_CK14 DDR_CKE1 4 DDR_BA1 4 DDR_A[13:0] 4 DDR_DQS[3:0] 4 4 4 4 4 4 3 MACHXO_CLK0 3 MACHXO_CLK1 MachXO MACHXO_IO[15:0] DDR_WE# DDR_RAS# DDR_CAS# DDR_CK0+ DDR_CK0DDR_CKE0 DDR_BA0 DDR_DM[3:0] DDR_DQ[31:0] SRAM_BE0# SRAM_BE1# SRAM_BE2# SRAM_BE3# SRAM_CE# MEMORY_OE# MEMORY_WE# 4 MEMORY_DQ[31:0] 10 VGA_BL0 10 VGA_BL1 10 VGA_HSYNC 10 VGA_VSYNC 10 AC97_RESET# 10 AC97_EXT_CLK 10 AC97_EAPD Memory MEMORY_A[22:0] VGA_RD0 VGA_RD1 VGA_GR0 VGA_GR1 VGA AC97_BITCLK AC97_SDATA_OUT AC97_SDATA_IN AC97_SYNC Audio Codec SATA_X1D0+ SATA_X1D0SATA_X1D1+ SATA_X1D1- CARDSEL# EXPCON_CLKIN EXPCON_CLKOUT EXPCON_IO[45:0] MACHXO_CLK0 MACHXO_CLK1 DDR_S0# DDR_S1# DDR_VREF DDR_CK1+ DDR_CK1DDR_CKE1 DDR_BA1 DDR_A[13:0] DDR_DQS[3:0] FLASH_CE# FLASH_RESET# FLASH_RY/BY#_A FLASH_RY/BY#_B FLASH_WP#/ACC FLASH_BYTE# MEMORY_DQ[31:0] VGA_BL0 VGA_BL1 VGA_HSYNC VGA_VSYNC AC97_RESET# AC97_EXT_CLK AC97_EAPD SATA_X2D0+ SATA_X2D0SATA_X2D1+ SATA_X2D1- BB3V3_CLK0+ BB3V3_CLK0- BB3V3_IO[21:0] Expansion Connectors and Prototyping Area 8 ETH_CRS 8 ETH_COL 8 ETH_RXCLK 8 ETH_RXDV 8 ETH_TXEN 8 ETH_TXCLK 8 ETH_TXER 8 ETH_TXD3 8 ETH_TXD2 8 ETH_TXD1 8 ETH_TXD0 7 7 7 7 7 7 7 7 7 USB_GPIO[28:0] 7 RS_TXD_LVTTL 7 RS_RTS_LVTTL 6,7,8,9 HPE_RESOUT# 3,6 HPE_RESET# SEG_CA0# SEG_CA1# SEG_A# SEG_B# SEG_C# SEG_D# SEG_E# SEG_F# SEG_G# SEG_DP# 5 5 5 5 5 5 5 5 5 5 SEG_CA0# SEG_CA1# SEG_A# SEG_B# SEG_C# SEG_D# SEG_E# SEG_F# SEG_G# SEG_DP# R0201 0R00 GND USB_PWEN2 VGA_RD0 HPE_RESOUT# USB_OC1# USB_RTS USB_GPIO1 VGA_BL1 VGA_VSYNC VGA_BL0 VGA_GR1 USB_SSI# VGA_GR0 VGA_RD1 USB_MISO USB_RXD USB_GPIO3 USB_GPIO2 USB_CTS USB_SCK USB_OC2# USB_PWEN0 VGA_HSYNC USB_GPIO0 USB_GPIO4 USB_TXD USB_GPIO11 USB_GPIO5 USB_GPIO10 USB_GPIO19 USB_MOSI USB_GPIO24 USB_GPIO23 USB_GPIO22 USB_GPIO21 USB_PWEN1 USB_GPIO15 USB_GPIO18 USB_GPIO13 USB_GPIO14 USB_GPIO7 USB_GPIO8 USB_GPIO17 USB_GPIO9 USB_GPIO6 USB_GPIO16 USB_GPIO12 USB_GPIO26 USB_GPIO25 USB_OC0# USB_GPIO28 USB_GPIO27 USB_GPIO20 CLK_FPGA SRAM_BE1# MEMORY_DQ17 MEMORY_DQ27 MEMORY_DQ16 MEMORY_DQ15 SRAM_BE0# MEMORY_DQ28 SRAM_CE# MEMORY_WE# MEMORY_DQ23 MEMORY_DQ22 MACHXO_CLK0 MACHXO_CLK1 MEMORY_DQ18 MEMORY_DQ30 MEMORY_A20 MEMORY_A19 MEMORY_DQ12 MEMORY_DQ24 MEMORY_DQ4 MEMORY_DQ3 MEMORY_DQ31 MEMORY_DQ29 MEMORY_DQ11 MEMORY_DQ10 MEMORY_DQ21 MEMORY_DQ13 MEMORY_DQ14 MEMORY_DQ19 MEMORY_DQ25 MEMORY_DQ5 MEMORY_DQ6 MEMORY_A17 MEMORY_A16 MEMORY_DQ26 MEMORY_DQ8 MEMORY_DQ20 MEMORY_DQ7 MEMORY_A22 MEMORY_A21 MEMORY_A12 MEMORY_A11 MEMORY_A15 MEMORY_A18 MEMORY_DQ1 MEMORY_DQ0 MEMORY_DQ2 MEMORY_DQ9 MEMORY_A0 MEMORY_A2 MEMORY_A6 MEMORY_A10 MEMORY_A1 MEMORY_A4 MEMORY_A3 MEMORY_A7 MEMORY_A5 MEMORY_A9 MEMORY_A8 MEMORY_A14 MEMORY_A13 4 AD15 AC15 AE13 AF13 AB17 Y15 AE14 AF14 AA16 W15 AC17 AB16 AE15 AF15 AE16 AF16 Y16 AB18 AD17 AD18 AC18 AD19 AC19 AE17 AB19 AE19 AF17 AE18 W16 AA17 AF18 AF19 AA19 W17 Y19 Y17 AF20 AE20 AA20 W18 AD20 AE21 AF21 AF22 AE22 AD22 AF23 AE23 AD23 AC23 AB20 AC20 AB21 AC22 W19 AA21 AF24 AE24 Y20 AB22 Y21 AB23 G5 G6 E5 E6 F7 E7 G7 G8 C1 C2 D3 D4 B2 B3 A3 A4 C3 C4 B4 D5 C5 H9 F8 F10 E8 D7 C7 B5 A5 H10 G10 D9 E9 E10 F11 C8 D8 B6 A6 G11 H11 D10 F12 B7 A7 C9 E11 B8 A8 G12 E12 B9 A9 H12 G13 C10 C12 B10 A10 F13 D12 E13 C13 B11 A11 H13 H14 BANK 0 B AN K 4 ECP2-50-672BGA PB49A/PCLKT4_0 PB49B/PCLKC4_0 PB50A PB50B PB51A/BDQS51 PB51B PB52A PB52B PB53A PB53B PB54A PB54B PB55A PB55B PB56A PB56B PB57A PB57B PB58A PB58B PB59A PB59B PB60A/BDQS60 PB60B PB61A PB61B PB62A PB62B PB63A PB63B PB64A PB64B PB65A PB65B PB66A PB66B PB67A PB67B PB68A PB68B PB69A/BDQS69 PB69B PB70A PB70B PB74A PB74B PB75A PB75B PB76A PB76B PB77A PB77B PB78A/BDQS78 PB78B PB79A PB79B PB80A PB80B PB81A PB81B PB82A/VREF2_4 PB82B/VREF1_4 U0201C ECP2-50-672BGA PT2A/VREF1_0 PT2B/VREF2_0 PT3A PT3B PT4A PT4B PT5A PT5B PT6A PT6B PT7A PT7B PT8A PT8B PT9A PT9B PT10A PT10B PT22B PT23A PT23B PT24A PT24B PT25A PT25B PT26A PT26B PT27A PT27B PT28A PT28B PT29A PT29B PT30A PT30B PT31A PT31B PT32A PT32B PT33A PT33B PT34A PT34B PT35A PT35B PT36A PT36B PT37A PT37B PT38A PT38B PT39A PT39B PT40A PT40B PT41A PT41B PT42A PT42B PT43A PT43B PT44A PT44B PT45A PT45B PT46A/PCLKT0_0 PT46B/PCLKC0_0 U0201A Lattice ECP2-50 FPGA VREF2_5/PB2A VREF1_5/PB2B PB3A PB3B PB4A PB4B PB5A PB5B BDQS6/PB6A PB6B PB7A PB7B PB8A PB8B PB9A PB9B PB10A PB10B PB20A PB20B PB21A PB21B PB22A PB22B PB23A PB23B BDQS24/PB24A PB24B PB25A PB25B PB26A PB26B PB27A PB27B PB28A PB28B PB29A PB29B PB30A PB30B PB31A PB31B PB32A PB32B BDQS33/PB33A PB33B PB34A PB34B PB35A PB35B PB36A PB36B PB37A PB37B PB38A PB38B PB39A PB39B PB40A PB40B PB41A PB41B BDQS42/PB42A PB42B PB43A PB43B PCLKT5_0/PB44A PCLKC5_0/PB44B BANK 5 XRES PCLKT1_0/PT48A PCLKC1_0/PT48B PT49A PT49B PT50A PT50B PT51A PT51B PT52A PT52B PT53A PT53B PT54A PT54B PT55A PT55B PT56A PT56B PT57A PT57B PT58A PT58B PT59A PT59B PT60A PT60B PT61A PT61B PT62A PT62B PT63A PT63B PT64A PT64B PT65A PT65B PT66A PT66B PT67A PT67B PT68A PT68B PT69A PT69B PT70A PT70B PT71A PT71B PT74A PT74B PT75A PT75B PT76A PT76B PT77A PT77B PT78A PT78B PT79A PT79B PT80A PT80B PT81A PT81B VREF1_1/PT82A VREF2_1/PT82B BANK 1 AE3 AF3 AC4 AD4 AE4 AF4 V9 W9 AA6 AB6 AC5 AD5 AA7 AB7 AE5 AF5 AC7 AD7 W10 Y10 W11 AA10 AC8 AD8 AB8 AB10 AE6 AF6 AA11 AC9 AB9 AD9 Y11 AB11 AE7 AF7 AC10 AD10 AA12 W12 AB12 Y12 AD12 AC12 AC13 AA13 AD13 AC14 AE8 AF8 AB15 Y13 AE9 AF9 W13 AA14 AE10 AF10 W14 AB13 Y14 AB14 AE11 AF11 AD14 AA15 AE12 AF12 XRES H16 GND DDR_CK0+ DDR_CK0- DDR_CKE0 DDR_A12 DDR_A9 DDR_A5 DDR_WE# DDR_CKE1 DDR_RAS# DDR_CAS# DDR_A7 DDR_A11 DDR_S1# DDR_S0# DDR_A8 DDR_A4 DDR_A3 DDR_A6 DDR_A2 DDR_A1 DDR_DQ7 DDR_DQ6 DDR_A10 DDR_A0 DDR_DQ1 DDR_DQ2 DDR_DQ0 DDR_DQ4 DDR_DQ3 DDR_DQ5 DDR_A13 DDR_DQS0 DDR_DM0 DDR_DQ9 DDR_DQ8 DDR_BA1 DDR_BA0 DDR_DQS1 DDR_DM1 DDR_DQ11 DDR_DQ10 DDR_VREF DDR_DQ15 DDR_DQ14 DDR_DQ13 DDR_DQ12 1% R0202 10K0 MACHXO_IO7 MACHXO_IO12 MACHXO_IO15 BB3V3_IO18 BB3V3_IO20 MACHXO_IO1 MACHXO_IO6 BB3V3_IO19 BB3V3_IO21 MACHXO_IO5 MACHXO_IO8 MACHXO_IO3 MACHXO_IO2 MACHXO_IO13 MACHXO_IO9 MACHXO_IO4 MACHXO_IO10 BB3V3_IO16 BB3V3_IO6 BB3V3_IO12 BB3V3_IO13 BB3V3_IO15 BB3V3_IO11 BB3V3_IO17 MACHXO_IO0 SRAM_BE3# BB3V3_IO10 BB3V3_IO9 BB3V3_IO5 BB3V3_IO14 BB3V3_IO8 BB3V3_IO7 BB3V3_IO3 BB3V3_IO1 BB3V3_IO4 FLASH_RY/BY#_B FLASH_CE# BB3V3_IO0 BB3V3_IO2 FLASH_RESET# FLASH_RY/BY#_A MACHXO_IO11 MACHXO_IO14 GND LVDS 3 LVDS LVDS LVDS LVDS GND C0201 100n C0202 100n AC97_BITCLK DAC_DIG MEMORY_OE# DDR_DQ21 DDR_DQ19 DDR_DQ20 DDR_DQ17 DDR_DQ23 DDR_DQ22 DDR_DQ16 DDR_DQ18 DDR_DQS2 DDR_DM2 ADC+ ADC- ADCS SATA_X2D0+ SATA_X2D0- DDR_CK1+ DDR_CK1- SATA_X2D1+ SATA_X2D1- DDR_DQ28 DDR_DQ27 DDR_DQ26 DDR_DQ25 DDR_DQ24 SATA_X1D1+ SATA_X1D1- DDR_DQS3 DDR_DM3 DDR_VREF DDR_DQ29 DDR_DQ30 DDR_DQ31 SATA_X1D0+ SATA_X1D0- F21 E22 H20 G21 C23 D23 C24 B24 G22 H21 B25 D24 C25 D25 E24 F22 C26 D26 J19 K19 G23 G24 H22 J22 E25 E26 L19 K20 F25 F26 G25 G26 H23 H24 H25 H26 K23 J23 J25 J26 J24 K24 M21 K21 M22 L22 M19 M20 K25 K26 N23 M24 K22 L21 M23 N24 GND M4 M5 N7 P9 N3 N4 N5 P7 T1 T2 P8 P6 P5 P4 U1 V1 P3 R3 R4 U2 V2 W2 T6 R5 R6 R7 W1 Y2 Y1 AA2 T5 T7 U3 U4 V3 U5 V4 V5 Y3 Y4 W3 W4 AA1 AB1 U8 U7 V8 U6 W6 W5 AC1 AD1 Y6 Y5 AE2 AD2 AB3 AB2 W7 W8 Y7 Y8 AC2 AD3 + C0238 4u70 VCC1V2 SEG_E# RS_RTS_LVTTL RS_TXD_LVTTL SEG_B# SEG_A# SEG_DP# SEG_G# RS_RXD_LVTTL RS_CTS_LVTTL LCD_RW LCD_REGSEL SEG_D# SEG_CA0# SEG_C# SEG_F# SEG_CA1# DSW1 DSW0 TST_COL1 TST_COL0 TST_ROW3 TST_ROW2 TST_ROW1 TST_ROW0 LCD_ENABLE DSW3 DSW2 TST_COL2 AC97_SDATA_IN AC97_RESET# AC97_SYNC AC97_SDATA_OUT AC97_EXT_CLK TST_STEP AC97_EAPD DIFF BB3V3_CLK0+ BB3V3_CLK0FLASH_BYTE# FLASH_WP#/ACC SRAM_BE2# D14 F14 B12 A12 E14 G14 C14 D13 H15 H17 B13 A13 A15 C15 B14 A14 F15 D15 B15 A16 G15 E15 D17 C17 B16 C18 B17 A17 H18 F16 G16 E16 A18 B18 D18 E17 A19 A20 F17 G19 E18 G17 B19 D19 B20 B21 C19 E19 A21 A22 D20 C20 B23 B22 E20 C22 F19 E21 A23 A24 H19 F20 J18 G20 D22 E23 1 2 Human Interface 3 BANK 6 GND + C0240 4u70 ECP2-50-672BGA PL46A/PCLKT6_0 PL46B/PCLKC6_0 PL47A/VREF2_6 PL47B/VREF1_6 PL48A PL48B PL49A PL49B PL50A/LDQS50 PL50B PL51A PL51B PL52A PL52B PL53A PL53B PL54A PL54B PL55A PL55B PL56A PL56B PL57A PL57B PL58A/LDQS58 PL58B PL59A PL59B PL60A/LLM0_GDLLT_IN_A PL60B/LLM0_GDLLC_IN_A PL61A/LLM0_GDLLT_FB_A PL61B/LLM0_GDLLC_FB_D PL63A/LLM0_GPLLT_IN_A PL63B/LLM0_GPLLC_IN_A PL64A/LLM0_GPLLT_FB_A PL64B/LLM0_GPLLC_FB_A PL65A PL65B PL66A PL66B PL67A/LDQS67 PL67B PL68A PL68B PL69A PL69B PL70A PL70B PL71A PL71B PL72A PL72B PL73A PL73B PL74A PL74B PL75A/LDQS75 PL75B PL76A PL76B PL77A PL77B PL78A PL78B U0201D C0239 1n00 VCC2V5 BANK 7 GND + C0242 4u70 + C0243 4u70 VREF2_7/PL2A VREF1_7/PL2B PL5A PL5B PL6A PL6B PL7A PL7B LDQS8/PL8A PL8B PL9A PL9B PL10A PL10B PL11A PL11B PL12A PL12B PL13A PL13B PL14A PL14B PL15A PL15B LDQS16/PL16A PL16B PL17A PL17B PL18A PL18B PL19A PL19B PL23A PL23B LDQS24/PL24A PL24B LUM0_SPLLT_IN_A/PL25A LUM0_SPLLC_IN_A/PL25B LUM0_SPLLT_FB_A/PL26A LUM0_SPLLC_FB_A/PL26B PL37A PL38A PL38B PL39A PL39B PL40A PL40B LDQS41/PL41A PL41B PL42A PL42B PL43A PL43B PCLKT7_0/PL44A PCLKC7_0/PL44B C0241 1n00 VCC3V3 PCLKT3_0/PR46A PCLKC3_0/PR46B VREF1_3/PR47A VREF2_3/PR47B PR48A PR48B PR49A PR49B RDQS50/PR50A PR50B PR51A PR51B PR52A PR52B PR53A PR53B PR54A PR54B PR55A PR55B PR56A PR56B PR57A PR57B RDQS58/PR58A PR58B PR59A PR59B RLM0_GDLLC_IN_A/PR60A RLM0_GDLLC_IN_A/PR60B RLM0_GDLLT_FB_A/PR61A RLM0_GDLLC_FB_A/PR61B RLM0_GPLLT_IN_A/PR63A RLM0_GPLLC_IN_A/PR63B RLM0_GPLLT_FB_A/PR64A RLM0_GPLLC_FB_A/PR64B PR65A PR65B PR66A PR66B RDQS67/PR67A PR67B PR68A PR68B PR69A PR69B PR70A PR70B ECP2-50-672BGA BANK 3 BANK 2 PR2A/VREF1_2 PR2B/VREF2_2 PR5A PR5B PR6A PR6B PR7A PR7B PR8A/RDQS8 PR8B PR9A PR9B PR10A PR10B PR11A PR11B PR12A PR12B PR13A PR13B PR14A PR14B PR15A PR15B PR16A/RDQS16 PR16B PR17A PR17B PR18A PR18B PR19A PR19B PR23A PR23B PR24A/RDQS24 PR24B PR25A/RUM0_SPLLT_IN_A PR25B/RUM0_SPLLC_IN_A PR26A/RUM0_SPLLT_FB_A PR26B/RUM0_SPLLC_FB_A PR37A PR37B PR38A PR38B PR39A PR39B PR40A PR40B PR41A/RDQS41 PR41B PR42A PR42B PR43A PR43B PR44A/PCLKT2_0 PR44B/PCLKC2_0 U0201B 1 2 4 1 2 Offpage 1 2 2 1 1 2 5 D2 D1 F6 F5 E4 E3 E2 E1 H6 H5 F2 F1 H8 J9 G4 G3 H7 J8 G2 G1 H3 H4 J5 J4 J3 K4 H1 H2 K6 K7 J1 J2 K3 K2 K1 L2 L1 M2 M1 N2 N1 L8 K8 L6 K5 L7 L5 P1 P2 M6 N8 R1 R2 M7 N9 EXPCON_IO0 EXPCON_IO1 EXPCON_IO4 EXPCON_IO10 EXPCON_IO18 EXPCON_IO8 EXPCON_IO15 EXPCON_IO9 EXPCON_IO7 EXPCON_IO2 EXPCON_IO3 EXPCON_IO5 EXPCON_CLKOUT CARDSEL# EXPCON_IO41 EXPCON_IO40 EXPCON_IO45 EXPCON_IO44 EXPCON_IO43 EXPCON_IO42 EXPCON_IO31 EXPCON_IO30 EXPCON_IO39 EXPCON_IO38 EXPCON_IO33 EXPCON_IO25 EXPCON_IO37 EXPCON_IO36 EXPCON_IO32 EXPCON_IO24 EXPCON_IO35 EXPCON_IO34 EXPCON_IO28 EXPCON_IO29 EXPCON_IO23 EXPCON_IO22 EXPCON_IO21 EXPCON_IO14 EXPCON_IO26 EXPCON_IO27 EXPCON_IO16 EXPCON_IO17 EXPCON_IO19 EXPCON_IO20 EXPCON_IO13 EXPCON_IO12 EXPCON_IO11 EXPCON_IO6 EXPCON_CLKIN C0245 1n00 ETH_RXD1 ETH_RXD0 ETH_TXD3 ETH_MDINTR# ETH_TXER ETH_TXD0 ETH_TXD1 ETH_TXD2 ETH_RXD2 ETH_RXD3 CLK_FPGA LED1# LED0# ETH_COL ETH_RXER I2C_SCL1 LED2# ETH_RXDV ETH_TXEN I2C_SDA1 LED6# ETH_MDIO ETH_CRS LED3# LED7# LED5# LED4# HPE_RESET# ETH_MDC ETH_TXCLK ETH_RXCLK C0244 1n00 2 L25 L26 N21 N18 M25 M26 N20 N19 N25 N26 R21 N22 P22 P23 P19 P21 R19 P20 R23 R24 P25 P26 T21 R22 R25 R26 T22 T20 T26 T25 U20 T19 U25 U24 U23 U22 U26 V26 V25 V24 W26 W25 U19 U21 Y26 AA26 V23 W24 2 GND GND GND GND GND GND GND GND GND GND GND C0234 100n C0231 100n C0228 100n C0225 100n C0222 100n C0219 100n C0216 100n C0213 100n C0211 100n C0207 100n C0203 100n C0210 100n ADCS ADC+ ADC- 1 VCC1V2 X22 optional A0201 Jumper AE25 V18 F4 J7 L4 M10 M9 AA4 R10 R9 T4 V7 AC11 AC6 U12 V12 Y9 AC16 AC21 U15 V15 Y18 AA23 R17 R18 T23 V20 F23 J20 L23 M17 M18 D16 D21 G18 J15 K15 D11 D6 G9 J12 K12 L12 L13 L14 L15 M11 M12 M15 M16 N11 N16 P11 P16 R11 R12 R15 R16 T12 T13 T14 T15 1 R0203 0,1% 10k0 DAC_DIG DAC 1 33k2 2 2 1 0,1% 10k0 R0204 C0246 2 Authors: IFW: Pr o je ct: Revision: GND_DAC 2 1 Hp e _ min i L EC2 R01 csam C0251 nb_4p70 DAC_ANALOG C0250 4p70 2 1 HDR2 X2 4 A2 A25 AA18 AA24 AA3 AA9 AD11 AD16 AD21 AD6 AE1 AE26 AF2 AF25 B1 B26 C11 C16 C21 C6 F18 F24 F3 F9 J13 J14 J21 J6 K10 K11 K13 K14 K16 K17 L10 L11 L16 L17 L24 L3 M13 M14 N10 N12 N13 N14 N15 N17 P10 P12 P13 P14 P15 P17 R13 R14 T10 T11 T16 T17 T24 T3 U10 U11 U13 U14 U16 U17 V13 V14 V21 V6 1 03:35:32 Sh e e t: 0 2 _ F PG A Last modified: Monday, September 04, 2006 10:15:04 GND Sternpunkt an X2 GND_DAC GND GND Sternpunkt an X1 0 X1 GND_ADC GND_ADC 2 3n30 nb nb C0247 nb C0249 C0248 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 Created: Saturday, April 29, 2006 A-4232 Hagenberg Page of 12 2 R0205 POWER SUPPLY 1 ECP2-50-672BGA VCCIO8 VCCIO8 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC U0201F FB0201 BLM18BD601SN1 3 C0237 100n C0236 100n VCC3V3 C0233 100n VCC3V3 C0230 100n VCC2V5 C0227 100n VCC2V5 C0224 100n VCC3V3 C0221 100n VCC3V3 C0218 100n VCC3V3 C0215 100n VCC3V3 GND VCC1V2 C0206 100n VCC3V3 C0209 100n C0205 100n Place pins 0..4 near the balls of the FPGA. These pins must also be accessible for measurements instruments. LVDS ADC C0235 100n C0232 100n C0229 100n C0226 100n C0223 100n C0220 100n C0217 100n C0214 100n C0212 100n C0208 100n C0204 100n 2 1 2 47 1 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 20. A B C D BB3V3_IO[21:0] USB_SCL USB_SDA HPE_RESET# EXPCON_IO[45:0] CLK_MACHXO MACHXO_CLK0 MACHXO_CLK1 GND TP0303 1 2 3 4 USB Peripheral VCC DATADATA+ GND X3 SHIELD SHIELD 1 2 3 4 5 6 7 8 9 10 GPIO_TDI GPIO_TCK JT AG _ T DO JT AG _ T CK 5 2 B A CAS-120A C SW0302 MACHXO _ T CK 4 GNDP 3 1 EC_ T CK EC_ T DO EC_ T DI GND C340 1uF R318 300K SPIDO SPIFASTN# JTAG_DONE JTAG_INIT CCLK PROGRAM# CFG0 CFG1 CFG2 SISPI DOUT CSSPIN R0317 10K0 VCC3V3 VCC3V3 R0316 10K0 VCC3V3 GNDA_CONF MACHXO_TMS EC_TMS TP0307 TP0305 TP0304 6 5 VCC3V3 MACHXO _ T DO MACHXO _ T DI 2 JTAG_TCK JTAG_DONE JTAG_INIT JTAG_TDO JTAG_TDI JTAG_PROG JTAG_TRST JTAG_TMS SW602 B3FS-1012 1 3 GPIO_TDO JT AG _ T DI GND GPIO_TMS JTAG_TMS CON10 X4 VCC3V3 JTAG Connector for Configuration GNDA_CONF PWR_IN USBCF_M USBCF_P USB Peripheral for Configuration DOUT TP0302 R0301 4k70 CCLK USB-JTAG Programmer Connector 2 BB3V3_IO[21:0] 7 USB_SCL 7 USB_SDA 2,6 HPE_RESET# 2,9 EXPCON_IO[45:0] 6 CLK_MACHXO 2 MACHXO_CLK0 2 MACHXO_CLK1 BANK 8 GND + C0307 2u20 Q0301 24MHz 4 C0308 100n C0309 100n 77 28 100 26 31 32 29 30 USBCF_I2C_SCL USBCF_I2C_SDA GP_BKPT USB_CLK_O GP_IFCLK 41 40 GP_T0 GP_T1 GP_T2 43 42 23 24 25 USBCF_WAKE GP_RXD1 GP_TXD1 22 84 79 GP_RXD0 GP_TXD0 54 55 56 51 52 76 13 14 15 27 3 4 5 6 7 8 10 11 GP_CTL0 GP_CTL1 GP_CTL2 GP_CTL3 GP_CTL4 GP_CTL5 GND C0340 12p0 17 18 GND 1 C0310 100n GND C0311 100n VCC3V3 PD0/FD8 PD1/FD9 PD2/FD10 PD3/FD11 PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 PB0/FD0 PB1/FD1 PB2/FD2 PB3/FD3 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 C0312 100n GP_ADR0 GP_ADR1 GP_ADR2 GP_ADR3 GP_ADR4 GP_ADR5 GP_ADR6 GP_ADR7 57 58 59 60 61 62 63 64 2 21 39 48 50 65 75 94 99 1 20 33 38 49 53 66 78 85 12 19 9 16 C0313 100n GND GND GND C0326 5n60 C0315 1n00 GNDA_CONF C0314 100n VCC3V3_CONF VCC3V3 GNDA_CONF R0315 4k70 R0314 10K0 GND VCC3V3 FB0301 BLM18BD601SN1 2 VCC1V2 C0302 100n 1 VCC3V3_CONF GP_ADR8 GP_D8 GP_D9 GP_D10 GP_D11 GP_D12 GP_D13 GP_D14 GP_D15 80 81 82 83 95 96 97 98 86 87 88 89 90 91 92 93 GP_D0 GP_D1 GP_D2 GP_D3 GP_D4 GP_D5 GP_D6 GP_D7 FB0302 BLM18PG600SN1 1 2 GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC AGND AGND AVCC AVCC PE0/T0OUT PE1/T1OUT PE2/T2OUT PE3/RXD0OUT PE4/RXD1OUT PE5/INT6 PE6/T2EX PE7/GPIFADR8 C0325 5n60 C0301 1n00 GP_INT0 GP_INT1 GP_SLOE GP_WU2 GP_FIFOADR0 GP_FIFOADR1 GP_PKTEND GP_SLCS# GND GND GND Place the 4k7 resistors close to their clock line to keep the stub length as short as possible. VCC3V3 34 35 36 37 44 45 46 47 67 68 69 70 71 72 73 74 VCCPLL R0303 4k70 EC_TDO EC_TMS EC_TDI EC_TCK PC0/GPIFADR0 PC1/GPIFADR1 PC2/GPIFADR2 PC3/GPIFADR3 PC4/GPIFADR4 PC5/GPIFADR5 PC6/GPIFADR6 PC7/GPIFADR7 CY7C68013A_TQFP100 RESET BKPT CLKOUT IFCLK RD WR SCL SDA RXD1 TXD1 RXD0 TXD0 T0 T1 T2 INT4 INT5 WAKEUP CTL0/FLAGA CTL1/FLAGB CTL2/FLAGC CTL3 CTL4 CTL5 DPLUS DMINUS NC NC NC RESERVED RDY0/SLRD RDY1/SLWR RDY2 RDY3 RDY4 RDY5 N6 P24 M3 T8 R20 M8 R8 P18 L20 AB5 AA5 AB4 AA8 AC3 PA0/INT0 PA1/INT1 PA2/SLOE PA3/WU2 PA4/FIFOADR0 PA5/FIFOADR1 PA6/PKTEND PA7/FLAGD/SLCS NC1 NC2 NC3 LLM0_PLLCAP RLM0_PLLCAP XTALOUT XTALIN VCCJ TDO TMS TDI TCK LUM0_VCCPLL LLM0_VCCPLL RLM0_VCCPLL RUM0_VCCPLL BANK 9 U0301 AUX & PLL POWER USBCF_P USBCF_M GP_RDY0 GP_RDY1 GP_RDY2 GP_RDY3 GP_RDY4 GP_RDY5 C0339 12p0 2 ECP2-50-672BGA VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX DONE INITN CCLK PROGRAMN CFG0 CFG1 CFG2 BUSY/PR71A DOUT/CSON/PR71B DI/PR72A WRITEN/PR77B CS1N/PR77A CSN/PR76B PR76A/D0 PR75B/D1 PR75A/D2 PR74B/D3 PR74A/D4 PR73B/D5 PR73A/D6 PR72B/D7 USB_RESET_n J10 J11 J16 J17 K18 L18 T18 U18 V16 V17 V10 V11 T9 U9 K9 L9 AD25 AB24 AA22 V19 AC24 W20 AD24 Y25 Y24 V22 W21 Y22 AC25 AB25 AD26 AC26 Y23 W22 AA25 AB26 W23 U0201E 3 3 GND GND VCC3V3 C0316 100n VCC3V3 GND P6 N2 M10 P2 N11 P9 P3 P4 N5 M5 N12 P7 MACHXO_SLEEPN M3 N3 M4 N4 P5 N6 M6 N7 M7 N8 P8 M8 N9 M9 N10 P10 P11 M11 P12 P13 P14 C7 B11 C5 A10 B4 C9 A7 A1 B3 A2 A3 C4 A4 A5 B5 C6 B6 A6 B7 C8 B8 A8 A9 B9 C10 B10 C11 A11 C12 B12 B13 A12 A13 MACHXO_TMS MACHXO_TCK MACHXO_TDO MACHXO_TDI GP_INT1 GP_INT0 USB_CLK_O USBCF_I2C_SDA USBCF_I2C_SCL GP_IFCLK USBCF_WAKE JTAG_INIT JTAG_TRST JTAG_DONE GPIO_TDI JTAG_PROG GPIO_TDO GPIO_TMS GPIO_TCK GP_SLOE GP_WU2 GP_FIFOADR0 GP_FIFOADR1 GP_PKTEND VCC3V3 MACHXO_IO12 MACHXO_IO14 MACHXO_IO13 MACHXO_IO11 MACHXO_IO10 MACHXO_CLK0 MACHXO_CLK1 CLK_MACHXO USB_SDA USB_SCL MACHXO_IO9 MACHXO_IO8 MACHXO_IO0 MACHXO_IO3 MACHXO_IO1 MACHXO_IO2 MACHXO_IO5 MACHXO_IO4 MACHXO_IO6 MACHXO_IO7 WP# 1 2 3 4 5 6 7 8 VCCAUX PT2A PT2B/PT3A PT2C/PT2B PT2D/PT3B PT2F/PT3C PT3B/PT3D PT3D/PT4B PT3E/PT5A PT3F/PT5B PT4C/PT5C PT4D/PT5D PT5A/PT6D PT5B/PT6F (PCLKT) PT6A/PT7B PT6B/PT7D (PCLKT) PT7A/PT9A PT7B/PT9B PT7E/PT9E PT7F/PT9F PT8C/PT10C PT9A/PT10D PT9B/PT11A PT9C/PT10F PT9D/PT11C PT9E/PT11B PT9F/PT11D GND 16 15 14 13 12 11 10 9 C0304 100n BANK 3/6,7 VCC VCCIO1/VCCIO3 VCCIO1/VCCIO2 GNDIO1/GNDIO3 GNDIO1/GNDIO2 GND PR2A/PR2A PR2B/PR3C PR2C/PR2B PR2D/PR3D PR3C/PR4A PR3D/PR4B PR4B/PR5A PR4C/PR5B PR4D/PR6A PR5C/PR6B PR5D/PR6C PR6B/PR8A PR6C/PR8B PR6D/PR9A PR7A/PR9B PR7B/PR10A PR7C/PR10B PR8A/PR11A PR8B/PR11B PR8C/PR12A PR8D/PR12B PR10A/PR14A PR10B/PR14B PR11A/PR15A PR11B/PR16A PR11C/PR15B PR11D/PR16B BANK 1/2,3 C0303 100n C0317 100n C0318 100n C0319 100n C0320 100n VCC VCCIO3/VCCIO7 VCCIO3/VCCIO6 GNDIO3/GNDIO7 GNDIO3/GNDIO6 GND MACHXO-640/1200-132csBGA VCC VCCIO2/VCCIO5 VCCIO2/VCCIO4 GNDIO2/GNDIO5 GNDIO2/GNDIO4 GND PB2C PL2A PB2D PL2B/PL3C PB3B PL2C/PL2B PB3C/PB4A PL2D/PL4A PB3D/PB4B PL3A/PL3D PL3B/PL4B PB4E/PB5C PB4F/PB6A PL3D/PL4C PB5A/PB6F PL5A/PL6A PB5B/PB7B (PCLKT) (GSRN) PL5B/PL6B PB5D/PB7C PL5D/PL6D PB6A/PB7D PL6B/PL7C PB6B/PB7F (PCLKT) PL6C/PL7D PB7A/PB9A PL6D/PL8C PB7B/PB9B PL7A/PL8D PB7E/PB9C PL7B/PL10A PB7F/PB9D PL7C/PL10B PB8C/PB10A PL8A/PL11B PB8D/PB10B (TSALL) PL8C/PL11C PB9C/PB10C PL9A/PL11D PB9D/PB11C PL9B/PL12A PB9F/PB11D PL9C/PL12B PL10A/PL14A TMS PL10B/PL14B PL11A/PL15A TCK PL11B/PL16A TDO TDI PL11C/PL15B PL11D/PL16B SLEEPN VCCAUX BANK 2/4,5 VCC VCCIO0/VCCIO1 VCCIO0/VCCIO0 GNDIO0/GNDIO1 GNDIO0/GNDIO0 GND CLK DI NC NC NC NC GND WP M25P16-VMF6P 16Mb M25P16 HOLD VCC NC NC NC NC CS Q U0305 VCC3V3 U0302 BANK 0/0,1 CSSPIN SPIDO HOLD# R0304 10K0 VCC3V3 SPI Flash for Configuration H3 D2 K3 E1 L2 F1 B1 C1 B2 C2 C3 D1 D3 E2 E3 F2 F3 G1 G2 G3 H2 H1 J1 J2 J3 K2 K1 L1 L3 M1 N1 M2 P1 GND C0322 100n VCC3V3 GND + RJ0310 10K0 TP0311 TSALL C0324 4u70 RJ0309 nb_10K0 GND Source GND T0302 BSS138/SOT 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 Pull-Up Pull-Down X Pull-Up Pull-Down X X X X TP0308 JTAG_TCK JTAG_TDO JTAG_TMS JTAG_TDI TVi0 TVi1 1 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 Created: Saturday, April 29, 2006 A-4232 Hagenberg Page of 12 3 Authors: IFW: RJ0308 nb_0R00 03:35:54 Sh e e t: 0 3 _ F PG A_ Co n f Last modified: Thursday, July 10, 2008 13:36:54 VCC1V2_T Hp e _ min i L EC2 R01 csam VCC2V5_T TVo3 VCC3V3_T RJ0306 0R00 TVo2 VCC5V0 RJ0304 0R00 RJ0305 nb_10K0 RJ0307 10K0 PROGRAM# TP0310 SW0301 B3FS-1012 RJ0303 nb_10K0 GND 4 3 TVo0 GND RJ0302 0R00 RJ0301 nb_10K0 2 1 LD0303 LED yellow R0308 270R TVo1 TVi3 TVi2 Pr o je ct: Revision: TestContact TP0 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 X23 GND 1 VCC3V3 VCC3V3 GND SPIFASTN# CFG0 CFG1 CFG2 INIT# TP0309 DONE R0307 4k70 VCC3V3 PROGRAM# Test Adapter rev 1.1 0 0 0 1 1 1 0 0 1 CFG2 CFG1 CFG0 SPIFAST# SOT-23 Drain Gate SPI Normal SPI Fast Reserved SPIm Normal SPIm Fast Reserved Reserved Slave Serial Reserved Mode JTAG_INIT JTAG_DONE LD0302 LED red R0306 270R VCC3V3 T0301 BSS138/SOT LD0301 LED blue R0305 270R VCC3V3 Configuration Settings USB_RESET_n VCC3V3 C0323 1n00 2 GP_RDY2 GP_RDY3 GP_RDY4 GP_RDY5 GP_SLCS# GP_ADR1 GP_ADR0 GP_ADR2 MACHXO_TSALL GP_ADR3 GP_ADR5 GP_ADR4 GP_ADR6 GP_ADR7 GP_ADR8 GP_T1 GP_T0 GP_T2 GP_CTL5 GP_CTL3 GP_CTL4 GP_CTL2 GP_CTL1 GP_CTL0 GP_RDY0 GP_RDY1 GND VCC3V3 GP_TXD0 GP_RXD0 GP_BKPT GP_RXD1 GP_TXD1 GP_D0 GP_D1 GP_D4 GP_D3 GP_D2 GP_D6 GP_D5 GP_D9 GP_D8 GP_D7 GP_D10 GP_D11 GP_D13 GP_D15 GP_D12 GP_D14 MACHXO_IO15 C0321 100n G12 L12 E12 L13 D13 J14 A14 C13 B14 C14 D12 D14 E14 E13 F12 F13 F14 G14 G13 H12 H13 H14 J12 J13 K12 K13 K14 L14 M13 M12 N13 M14 N14 GND WP# CCLK SISPI BBV3_IO11 2 2 1 TP0301 1 2 2 1 Lattice ECP2-50 FPGA (Configuration) 1 2 1 2 MACHXO_IO[15:0] 1 2 1 2 2 1 2 MACHXO_IO[15:0] 1 2 1 4 1 2 1 Offpage 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 2 1 2 5 1 2 1 48 2 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 21. A B C D FLASH_CE# FLASH_RESET# FLASH_RY/BY#_A FLASH_RY/BY#_B FLASH_WP#/ACC FLASH_BYTE# SRAM_BE0# SRAM_BE1# SRAM_BE2# SRAM_BE3# SRAM_CE# FLASH_CE# FLASH_RESET# FLASH_RY/BY#_A FLASH_RY/BY#_B FLASH_WP#/ACC FLASH_BYTE# MEMORY_OE# MEMORY_WE# MEMORY_DQ[31:0] MEMORY_A[22:0] DDR_VREF DDR_S0# DDR_S1# DDR_WE# DDR_RAS# DDR_CAS# DDR_BA0 DDR_BA1 DDR_CKE0 DDR_CKE1 DDR_CK1+ DDR_CK1- DDR_CK0+ DDR_CK0- DDR_A[13:0] DDR_DM[3:0] DDR_DQS[3:0] 33R0 2 R0416 1 33R0 2 R0418 1 RN0413 CND1J 10K JTA 33R 1 10 9 2 8 3 4 7 5 6 RN0414 CND1J 10K JTA 33R 1 10 2 9 3 8 4 7 5 6 SODIMM_A5 SODIMM_A3 SODIMM_A1 SODIMM_A10 DDR_VTT SODIMM_BA0 SODIMM_WE# SODIMM_S0# SODIMM_A13 DDR_VTT 5 DDR_VTT SODIMM_CKE0 SODIMM_A11 SODIMM_A8 SODIMM_A6 RN0412 CND1J 10K JTA 33R 1 10 2 9 3 8 7 4 6 5 SODIMM_CKE1 SODIMM_A12 SODIMM_A9 SODIMM_A7 DDR_VTT DDR_VTT SODIMM_RAS# SODIMM_CAS# SODIMM_S1# DDR_VTT SODIMM_A4 SODIMM_A2 SODIMM_A0 SODIMM_BA1 DDR_VTT SODIMM_DQ28 SODIMM_DQ29 SODIMM_DQ30 SODIMM_DQ31 33R0 2 R0420 1 RN0411 CND1J 10K JTA 33R 1 10 2 9 3 8 7 4 5 6 SODIMM_DM3 DDR_VTT SODIMM_DQ20 SODIMM_DQ21 SODIMM_DQ22 SODIMM_DQ23 DDR_VTT SODIMM_DQ12 SODIMM_DQ13 SODIMM_DQ14 SODIMM_DQ15 DDR_VTT SODIMM_DQ4 SODIMM_DQ5 SODIMM_DQ6 SODIMM_DQ7 SODIMM_DQ24 SODIMM_DQ25 SODIMM_DQ26 SODIMM_DQ27 DDR_VTT 33R0 2 R0419 1 SODIMM_DQS3 RN0410 CND1J 10K JTA 33R 1 10 2 9 3 8 4 7 5 6 SODIMM_DM2 SODIMM_DQ16 SODIMM_DQ17 SODIMM_DQ18 SODIMM_DQ19 DDR_VTT 33R0 2 R0417 1 RN0409 CND1J 10K JTA 33R 1 10 2 9 3 8 4 7 5 6 SODIMM_DQS2 SODIMM_DQ8 SODIMM_DQ9 SODIMM_DQ10 SODIMM_DQ11 DDR_VTT SODIMM_DM1 SODIMM_DQS1 33R0 2 R0415 1 RN0408 CND1J 10K JTA 33R 1 10 2 9 3 8 4 7 5 6 33R0 2 R0414 1 SODIMM_DM0 SODIMM_DQ0 SODIMM_DQ1 SODIMM_DQ2 SODIMM_DQ3 DDR_VTT 33R0 2 R0413 1 SODIMM_DQS0 Parallel Termination Resistors - Place C0401 as close as possible to the PVIN pin - Place C0403 as close as possible to the VREF pin - Place a bulk cap (100-220 µF) capacitor at each end of the VTT island. (C04??, C04??) 2 SRAM_BE0# 2 SRAM_BE1# 2 SRAM_BE2# 2 SRAM_BE3# 2 SRAM_CE# 2 2 2 2 2 2 2 MEMORY_OE# 2 MEMORY_WE# 2 MEMORY_DQ[31:0] 2 MEMORY_A[22:0] 2 DDR_VREF 2 DDR_S0# 2 DDR_S1# 2 DDR_WE# 2 DDR_RAS# 2 DDR_CAS# 2 DDR_BA0 2 DDR_BA1 2 DDR_CKE0 2 DDR_CKE1 2 DDR_CK1+ 2 DDR_CK1- 2 DDR_CK0+ 2 DDR_CK0- 2 DDR_A[13:0] 2 DDR_DM[3:0] 2 DDR_DQS[3:0] 2 DDR_DQ[31:0] DDR_DQ[31:0] Offpage GND C0416 220u DDR_VTT SODIMM_A10 SODIMM_BA0 SODIMM_WE# SODIMM_S0# SODIMM_A13 SODIMM_A7 SODIMM_A5 SODIMM_A3 SODIMM_A1 SODIMM_A12 SODIMM_A9 SODIMM_CKE1 SODIMM_DQ26 SODIMM_DQ27 SODIMM_DQ25 SODIMM_DQS3 SODIMM_DQ19 SODIMM_DQ24 SODIMM_DQS2 SODIMM_DQ18 SODIMM_DQ16 SODIMM_DQ17 SODIMM_CK0+ SODIMM_CK0- SODIMM_DQ10 SODIMM_DQ11 SODIMM_DQ9 SODIMM_DQS1 SODIMM_DQ3 SODIMM_DQ8 C0417 100n GND VCC2V5 SODIMM_DQS0 SODIMM_DQ2 SODIMM_DQ0 SODIMM_DQ1 DDR_VREF GND C0401 47u VCC2V5 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 5 6 7 2 DQ20 DQ21 Vdd DM2 DQ22 Vss DQ23 DQ28 Vdd DQ29 DM3 Vss DQ30 DQ31 Vdd CB4/NC CB5/NC Vss DM8/NC CB6/NC Vdd CB7/NC NC Vss Vss Vdd Vdd CKE0 NC A11 A8 Vss A6 A4 A2 A0 Vdd BA1 RAS# CAS# S1#/NC NC Vss DQ36 DQ37 Vdd DM4 DQ38 Vss DQ39 DQ44 Vdd DQ45 DM5 Vss DQ46 DQ47 Vdd CK1CK1+ Vss DQ52 DQ53 Vdd DM6 DQ54 Vss DQ55 DQ60 Vdd DQ61 DM7 Vss DQ62 DQ63 Vdd SA0 SA1 SA2 NC C0418 100n C0419 100n DDR_SODIMM200 DQ16 DQ17 Vdd DQS2 DQ18 Vss DQ19 DQ24 Vdd DQ25 DQS3 Vss DQ26 DQ27 Vdd CB0/NC CB1/NC Vss DQS8/NC CB2/NC Vdd CB3/NC NC Vss CK2+/NC CK2-/NC Vdd CKE1/NC NC A12/NC A9 Vss A7 A5 A3 A1 Vdd A10/AP BA0 WE# S0# A13/NC Vss DQ32 DQ33 Vdd DQS4 DQ34 Vss DQ35 DQ40 Vdd DQ41 DQS5 Vss DQ42 DQ43 Vdd Vdd Vss Vss DQ48 DQ49 Vdd DQS6 DQ50 Vss DQ51 DQ56 Vdd DQ57 DQS7 Vss DQ58 DQ59 Vdd SDA SCL Vddspd Vddid X5B DDR_SODIMM200 Vref Vss DQ0 DQ1 Vdd DQS0 DQ2 Vss DQ3 DQ8 Vdd DQ9 DQS1 Vss DQ10 DQ11 Vdd CK0+ CK0Vss X5A 4 3 8 1 Vref Vss DQ4 DQ5 Vdd DM0 DQ6 Vss DQ7 DQ12 Vdd DQ13 DM1 Vss DQ14 DQ15 Vdd Vdd Vss Vss VREF VSENSE VTT NC LP2995MR VDDQ AVIN PVIN GND U0401 C0420 100n 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND C0402 220u C0403 100n 4 C0421 100n C0422 100n SODIMM_CK1SODIMM_CK1+ SODIMM_BA1 SODIMM_RAS# SODIMM_CAS# SODIMM_S1# SODIMM_A6 SODIMM_A4 SODIMM_A2 SODIMM_A0 SODIMM_A11 SODIMM_A8 SODIMM_CKE0 SODIMM_DQ30 SODIMM_DQ31 SODIMM_DQ29 SODIMM_DM3 SODIMM_DQ23 SODIMM_DQ28 SODIMM_DM2 SODIMM_DQ22 SODIMM_DQ20 SODIMM_DQ21 SODIMM_DQ14 SODIMM_DQ15 SODIMM_DQ13 SODIMM_DM1 SODIMM_DQ7 SODIMM_DQ12 SODIMM_DM0 SODIMM_DQ6 SODIMM_DQ4 SODIMM_DQ5 DDR_VREF VCC2V5 GND DDR_VREF DDR_VTT R0402 1 R0410 1 R0409 1 GND C0414 100n R0412 1 C0415 100n SODIMM_CK1+ R0411 1 RN04072 5 6 7 8 SODIMM_CK1- SODIMM_S0# SODIMM_S1# SODIMM_A13 GND DDR_CK1- C0413 100n DDR_CK1+ C0412 100n DDR_VREF 22R0 2 22R0 2 CN1j 4 JTA 22R DDR_S0# 4 DDR_S1# 3 DDR_A13 2 1 CN1j 4 JTA 22R DDR_BA0 4 DDR_RAS# 3 DDR_WE# 2 DDR_CAS# 1 CN1j 4 JTA 22R DDR_A1 4 DDR_A0 3 DDR_A10 2 DDR_BA1 1 RN04062 5 6 7 8 SODIMM_A1 SODIMM_A0 SODIMM_A10 SODIMM_BA1 RN04071 SODIMM_BA0 5 SODIMM_RAS# 6 SODIMM_WE# 7 SODIMM_CAS# 8 CN1j 4 JTA 22R DDR_A5 4 DDR_A4 3 DDR_A3 2 DDR_A2 1 CN1j 4 JTA 22R DDR_A9 4 DDR_A8 3 DDR_A7 2 DDR_A6 1 RN04061 5 6 7 8 RN04052 5 6 7 8 DDR_DM3 DDR_DQS3 CN1j 4 JTA 22R DDR_CKE1 4 DDR_CKE0 3 DDR_A12 2 DDR_A11 1 22R0 2 22R0 2 SODIMM_A5 SODIMM_A4 SODIMM_A3 SODIMM_A2 SODIMM_A9 SODIMM_A8 SODIMM_A7 SODIMM_A6 RN04051 SODIMM_CKE1 5 SODIMM_CKE0 6 SODIMM_A12 7 SODIMM_A11 8 SODIMM_DM3 SODIMM_DQS3 CN1j 4 JTA 22R DDR_DQ26 4 DDR_DQ30 3 DDR_DQ27 2 DDR_DQ31 1 DDR_DM2 DDR_DQS2 RN04042 SODIMM_DQ26 5 SODIMM_DQ30 6 SODIMM_DQ27 7 SODIMM_DQ31 8 22R0 2 22R0 2 CN1j 4 JTA 22R DDR_DQ18 4 DDR_DQ22 3 DDR_DQ19 2 DDR_DQ23 1 CN1j 4 JTA 22R DDR_DQ24 4 DDR_DQ28 3 DDR_DQ25 2 DDR_DQ29 1 R0408 1 R0407 1 DDR_CK0- DDR_CK0+ RN04041 SODIMM_DQ24 5 SODIMM_DQ28 6 SODIMM_DQ25 7 SODIMM_DQ29 8 SODIMM_DM2 SODIMM_DQS2 RN04032 SODIMM_DQ18 5 SODIMM_DQ22 6 SODIMM_DQ19 7 SODIMM_DQ23 8 DDR_DQS1 DDR_DM1 CN1j 4 JTA 22R DDR_DQ16 4 DDR_DQ20 3 DDR_DQ17 2 DDR_DQ21 1 22R0 2 R0406 1 RN04031 SODIMM_DQ16 5 SODIMM_DQ20 6 SODIMM_DQ17 7 SODIMM_DQ21 8 22R0 2 R0405 1 22R0 2 22R0 2 CN1j 4 JTA 22R DDR_DQ10 4 DDR_DQ14 3 DDR_DQ11 2 DDR_DQ15 1 SODIMM_CK0+ R0404 1 DDR_DM0 DDR_DQS0 CN1j 4 JTA 22R DDR_DQ8 4 DDR_DQ12 3 DDR_DQ9 2 DDR_DQ13 1 22R0 2 22R0 2 CN1j 4 JTA 22R DDR_DQ2 4 DDR_DQ6 3 DDR_DQ3 2 DDR_DQ7 1 SODIMM_CK0- SODIMM_DM1 SODIMM_DQS1 R0403 1 RN04022 SODIMM_DQ10 5 SODIMM_DQ14 6 SODIMM_DQ11 7 SODIMM_DQ15 8 RN04021 SODIMM_DQ8 5 SODIMM_DQ12 6 SODIMM_DQ9 7 SODIMM_DQ13 8 SODIMM_DM0 SODIMM_DQS0 R0401 1 RN04012 SODIMM_DQ2 5 SODIMM_DQ6 6 SODIMM_DQ3 7 SODIMM_DQ7 8 CN1j 4 JTA 22R DDR_DQ0 4 DDR_DQ4 3 DDR_DQ1 2 DDR_DQ5 1 Series Resistors RN04011 SODIMM_DQ0 5 SODIMM_DQ4 6 SODIMM_DQ1 7 SODIMM_DQ5 8 DDR_VTT DDR SDRAM socket (32 bit data bus) 3 MEMORY_A[22:0] FLASH_CE# MEMORY_OE# MEMORY_WE# FLASH_WP#/ACC FLASH_RESET# MEMORY_A0 MEMORY_A1 MEMORY_A2 MEMORY_A3 MEMORY_A4 MEMORY_A5 MEMORY_A6 MEMORY_A7 MEMORY_A8 MEMORY_A9 MEMORY_A10 MEMORY_A11 MEMORY_A12 MEMORY_A13 MEMORY_A14 MEMORY_A15 MEMORY_A16 MEMORY_A17 MEMORY_A18 MEMORY_A19 MEMORY_A20 MEMORY_A21 MEMORY_A22 FLASH_CE# MEMORY_OE# MEMORY_WE# FLASH_WP#/ACC FLASH_RESET# MEMORY_A0 MEMORY_A1 MEMORY_A2 MEMORY_A3 MEMORY_A4 MEMORY_A5 MEMORY_A6 MEMORY_A7 MEMORY_A8 MEMORY_A9 MEMORY_A10 MEMORY_A11 MEMORY_A12 MEMORY_A13 MEMORY_A14 MEMORY_A15 MEMORY_A16 MEMORY_A17 MEMORY_A18 MEMORY_A19 MEMORY_A20 MEMORY_A21 MEMORY_A22 GND C0404 4u70 C0405 100n GND C0406 4u70 NC NC NC NC NC NC RY/BY# BYTE# MX29LV128MBTI-90Q MACRONIX 30 1 27 28 55 56 17 53 FLASH_RY/BY#_A FLASH_BYTE# 30 1 27 28 55 56 17 53 35 37 39 41 44 46 48 50 36 38 40 42 45 47 49 51 C0407 100n FLASH_RY/BY#_B FLASH_BYTE# MEMORY_DQ16 MEMORY_DQ17 MEMORY_DQ18 MEMORY_DQ19 MEMORY_DQ20 MEMORY_DQ21 MEMORY_DQ22 MEMORY_DQ23 MEMORY_DQ24 MEMORY_DQ25 MEMORY_DQ26 MEMORY_DQ27 MEMORY_DQ28 MEMORY_DQ29 MEMORY_DQ30 MEMORY_DQ31 Flash HIGH DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 128 Megabit DQ7 (x16) DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 CE# OE# WE# WP#/ACC RESET# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 U0403 VCC3V3 GND NC NC NC NC NC NC RY/BY# BYTE# MX29LV128MBTI-90Q MACRONIX 35 37 39 41 44 46 48 50 36 38 40 42 45 47 49 51 MEMORY_DQ0 MEMORY_DQ1 MEMORY_DQ2 MEMORY_DQ3 MEMORY_DQ4 MEMORY_DQ5 MEMORY_DQ6 MEMORY_DQ7 MEMORY_DQ8 MEMORY_DQ9 MEMORY_DQ10 MEMORY_DQ11 MEMORY_DQ12 MEMORY_DQ13 MEMORY_DQ14 MEMORY_DQ15 Flash LOW DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 128 Megabit DQ7 (x16) DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 CE# OE# WE# WP#/ACC RESET# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 VCC3V3 32 34 13 16 14 31 26 25 24 23 22 21 20 10 9 8 7 6 5 4 3 54 19 18 11 12 15 2 32 34 13 16 14 31 26 25 24 23 22 21 20 10 9 8 7 6 5 4 3 54 19 18 11 12 15 2 U0402 VCC3V3 2 R0422 10K0 VCC3V3 MEMORY_DQ[31:16] R0421 10K0 VCC3V3 VCC3V3 MEMORY_A[17:0] VCC3V3 MEMORY_A[17:0] SAMSUNG 12 34 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38 11 33 17 41 6 40 39 1 2 3 4 5 18 19 20 21 22 23 24 25 26 27 42 43 44 GND GND IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 IO16 C0408 4u70 Pr o je ct: Revision: Authors: IFW: C0409 100n SAMSUNG K6R4016V1D-UI10 VCC VCC WE# OE# CS# UB# LB# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 U0405 GND Hp e _ min i L EC2 R01 csam C0411 100n MEMORY_DQ16 MEMORY_DQ17 MEMORY_DQ18 MEMORY_DQ19 MEMORY_DQ20 MEMORY_DQ21 MEMORY_DQ22 MEMORY_DQ23 MEMORY_DQ24 MEMORY_DQ25 MEMORY_DQ26 MEMORY_DQ27 MEMORY_DQ28 MEMORY_DQ29 MEMORY_DQ30 MEMORY_DQ31 C0410 4u70 12 34 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38 GND MEMORY_DQ0 MEMORY_DQ1 MEMORY_DQ2 MEMORY_DQ3 MEMORY_DQ4 MEMORY_DQ5 MEMORY_DQ6 MEMORY_DQ7 MEMORY_DQ8 MEMORY_DQ9 MEMORY_DQ10 MEMORY_DQ11 MEMORY_DQ12 MEMORY_DQ13 MEMORY_DQ14 MEMORY_DQ15 1 05:36:34 0 4 _ Me mo r y Sh e e t: Last modified: Monday, September 04, 2006 10:15:10 MEMORY_DQ[31:16] MEMORY_DQ[15:0] Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 Created: Friday, September 24, 2004 A-4232 Hagenberg Page of 12 4 GND GND GND IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 IO16 K6R4016V1D-UI10 VCC VCC WE# OE# CS# UB# LB# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 U0404 Async. SRAM HIGH 11 33 17 41 6 40 39 1 2 3 4 5 18 19 20 21 22 23 24 25 26 27 42 43 44 Async. SRAM LOW VCC3V3 MEMORY_WE# MEMORY_OE# SRAM_CE# SRAM_BE3# SRAM_BE2# MEMORY_A0 MEMORY_A1 MEMORY_A2 MEMORY_A3 MEMORY_A4 MEMORY_A5 MEMORY_A6 MEMORY_A7 MEMORY_A8 MEMORY_A9 MEMORY_A10 MEMORY_A11 MEMORY_A12 MEMORY_A13 MEMORY_A14 MEMORY_A15 MEMORY_A16 MEMORY_A17 MEMORY_WE# MEMORY_OE# SRAM_CE# SRAM_BE1# SRAM_BE0# MEMORY_A0 MEMORY_A1 MEMORY_A2 MEMORY_A3 MEMORY_A4 MEMORY_A5 MEMORY_A6 MEMORY_A7 MEMORY_A8 MEMORY_A9 MEMORY_A10 MEMORY_A11 MEMORY_A12 MEMORY_A13 MEMORY_A14 MEMORY_A15 MEMORY_A16 MEMORY_A17 (2 x 4 Mbit organized as 256k words of 32 bits) MEMORY_A[22:0] SRAM 1 Parallel Flash MEMORY_DQ[15:0] 2 (2 x 128 Mbit organized as 8M words of 32 bits) 3 43 Vcc 29 Vio Vss 33 Vss 52 43 Vcc 29 Vio Vss 33 Vss 52 4 1 5 1 2 1 2 1 2 1 2 1 2 1 2 1 2 49 2 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 22. A B C D LED0# LED1# LED2# LED3# LED4# LED5# LED6# LED7# TST_ROW0 TST_ROW1 TST_ROW2 TST_ROW3 TST_COL0 TST_COL1 TST_COL2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 LCD_REGSEL 2 LCD_RW 2 LCD_ENABLE 2 DSW0 2 DSW1 2 DSW2 2 DSW3 2 TST_STEP SEG_CA0# SEG_CA1# SEG_A# SEG_B# SEG_C# SEG_D# SEG_E# SEG_F# SEG_G# SEG_DP# 2 2 2 2 2 2 2 2 2 2 5 LCD_REGSEL LCD_RW LCD_ENABLE DSW0 DSW1 DSW2 DSW3 TST_STEP TST_ROW0 TST_ROW1 TST_ROW2 TST_ROW3 TST_COL0 TST_COL1 TST_COL2 LED0# LED1# LED2# LED3# LED4# LED5# LED6# LED7# SEG_CA0# SEG_CA1# SEG_A# SEG_B# SEG_C# SEG_D# SEG_E# SEG_F# SEG_G# SEG_DP# TP0501 nb_TEST POINT 8x LED LED0# LCD Connector SEG_DP# SEG_G# SEG_F# SEG_E# SEG_D# SEG_C# SEG_B# 2 2 2 2 1 2 2 2 R0511 R0526 5K Display Contrast 4 GND VCC5V0 GND LCD_RW SEG_A# SEG_C# SEG_E# SEG_G# SEG_DP#_X SEG_G#_X SEG_F#_X SEG_E#_X SEG_D#_X SEG_C#_X SEG_B#_X SEG_A#_X LCD_CONT 1 1 1 1 1 1 TP0504 nb_TEST POINT LED3# LD0503 LED red 330R R0503 X6 HDR2 LCD Backlight on/off 120R R0521 120R R0519 120R R0516 120R R0514 1K00 R0513 1K00 VCC5V0 1 1 1 R0524 10K0 120R R0522 120R R0520 120R R0518 120R 2 SEG_CA1# 2 2 SEG_A# LED2# LD0502 LED red 330R R0502 TP0503 nb_TEST POINT SEG_CA0# R0515 TP0502 nb_TEST POINT LED1# LD0501 LED red 330R R0501 VCC3V3 7-Segment Display GND 1 2 1 1 2 1 1 1 2 2 1 1 2 1 Offpage 1 2 1 3 5 7 9 11 13 15 E F 1 D G A D1 DP 2 4 6 8 10 12 14 16 C B VCC5V0 GND LCD_REGSEL LCD_ENABLE SEG_B# SEG_D# SEG_F# SEG_DP# D2 BC807-25 Q0502 1 BC807-25 Q0501 VCC3V3 3 TP0508 nb_TEST POINT LED7# LD0507 LED red 330R R0507 TP0507 nb_TEST POINT LED6# LD0506 LED red 330R R0506 TP0506 nb_TEST POINT LED5# LD0505 LED red 330R R0505 ELD-426SYGWA/S530-E2 A B C D E F G DP U0502 CON16A X7 7 6 4 1 3 8 9 2 SEG_CA1#_B SEG_CA0#_B TP0505 nb_TEST POINT LED4# LD0504 LED red 330R R0504 2 1 1 SEG_CA1#_X 1 2 1 1 2 3 10 C.A. D1 2 3 SEG_CA0#_X 5 2 1 LD0508 LED red 330R R0508 TP0509 nb_TEST POINT 1 3 TST_ROW0 2 GND R0525 1K00 TST_ROW3 GND R0523 1K00 TST_ROW2 GND R0517 1K00 TST_ROW1 GND 4 SW0501 B3FS-1012 1 3 R0512 1K00 4x DIP Switch Key Matrix GND Single Step Key TST_COL0 4 D0504 MMBD4148 4 4 D0507 MMBD4148 2 2 1 2 3 4 10K0 RP0502 8 7 6 5 D0510 MMBD4148 4 SW0511 B3FS-1012 1 3 2 SW0508 B3FS-1012 1 3 2 DSW0 DSW1 DSW2 DSW3 GND 4 D0501 MMBD4148 SW0505 B3FS-1012 1 3 2 SW0502 B3FS-1012 1 3 R0510 100K R0509 100K VCC3V3 2 GND C0501 100n TST_COL1 4 D0502 MMBD4148 D0505 MMBD4148 4 4 D0508 MMBD4148 2 SW DIP-4 D0511 MMBD4148 4 SW0512 B3FS-1012 1 3 2 SW0509 B3FS-1012 1 3 2 SW0506 B3FS-1012 1 3 2 TST_STEP 1 2 3 4 1K0 RP0501 8 7 6 5 74AHC1G14_SOT353 4 U0501 SW0503 B3FS-1012 1 3 GND nc SW0514 1 2 VCC3V3 5 3 5 TST_COL2 2 1 1 C.A. D2 1 2 1 2 1 2 1 50 2 D0506 MMBD4148 4 4 D0509 MMBD4148 2 Authors: IFW: Pr o je ct: Revision: D0512 MMBD4148 4 SW0513 B3FS-1012 1 3 2 SW0510 B3FS-1012 1 3 2 Hp e _ min i L EC2 R01 csam 1 05:31:55 Sh e e t: 0 5 _ L ED_ KEY Last modified: Monday, September 04, 2006 10:15:09 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 Created: Friday, September 24, 2004 A-4232 Hagenberg Page of 12 5 VCC3V3 4 D0503 MMBD4148 SW0507 B3FS-1012 1 3 2 SW0504 B3FS-1012 1 3 1 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 23. 51 A B C D 2 I2C_SDA1 2 I2C_SCL1 2,7,8,9 HPE_RESOUT# 2,3 HPE_RESET# 3 CLK_MACHXO 9 EXPCON_OSC 8 CLK_ETH 2 CLK_FPGA 5 I2C_SDA1 I2C_SCL1 HPE_RESOUT# HPE_RESET# CLK_MACHXO EXPCON_OSC CLK_ETH CLK_FPGA 2 HPE_RESOUT# GND GND 4 SW0601 B3FS-1012 1 3 nb_HDR2 1 2 2 1 BAT54A D0601 3 GND 4 C0602 1n00 BLM21PG331SN1D 2 1 FB0601 R0605 10K0 VCC3V3 VCC3V3 Clock Sources Reset Button Ext. Reset X8 Reset Control GND C0603 100n GND C0601 100n VCC3V3 8 RESET CAT1026SI-30 GND RESET SCL SDA VSENSE VLOW VCC U0601 2 1 CLK VCC 3 4 OSC_SMT4_25MHz GND EN U0603 VCC3V3_OSC GND C0604 100n VCC3V3_OSC CLK 7 1 2 GND 6 2 1 4 3 5 7 8 TP0601 TEST POINT CLK 1 CY2304NZ_TSSOP8 OUT1 VDD OUT2 OE BUF_IN OUT3 GND OUT4 U0604 3 R0607 nb_10K0 R0604 100K 3 GND R0603 10K0 VCC3V3 R0606 nb_10K0 VCC3V3 CAT_RESET# CAT_RESET VCC3V3_OSC CAT_I2C_SDA CAT_I2C_SCL Vth = 1.25V x (R0601+R0602)/R0602 = 4.4V R0602 10K7 CAT_I2C_SCL 6 CAT_I2C_SDA 5 CAT_VSENSE 3 1.25 V 4 R0601 27K0 VCC5V0 1 2 Offpage 4 1 2 33R0 R0615 33R0 R0614 33R0 R0613 33R0 R0612 Rs of the I2C bus R0611 22R0 R0610 22R0 GND nc HPE_RESET# EXPCON_OSC CLK_MACHXO CLK_ETH CLK_FPGA I2C_SDA1 R0608 2K7 VCC3V3 74AHC1G14_SOT353 4 U0602 I2C_SCL1 1 2 VCC3V3 5 3 5 R0609 Rp of the I2C bus 2K7 2 2 Hp e _ min i L EC2 R01 csam 1 05:38:11 Sh e e t: 0 6 _ Clo ck_ Re se t Last modified: Monday, September 04, 2006 10:15:09 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 Created: Friday, September 24, 2004 A-4232 Hagenberg Page of 12 6 Authors: IFW: Pr o je ct: Revision: 1 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 24. A B C D USB_PWEN0 USB_OC0# USB_PWEN1 USB_OC1# USB_PWEN2 USB_OC2# 2 2 2 2 2 2 2,6,8,9 HPE_RESOUT# 3 USB_SCL 3 USB_SDA USB_MISO USB_SSI# USB_SCK USB_MOSI USB_TXD USB_RXD USB_RTS USB_CTS 2 USB_GPIO[28:0] 2 2 2 2 2 2 2 2 5 HPE_RESOUT# USB_SCL USB_SDA USB_PWEN0 USB_OC0# USB_PWEN1 USB_OC1# USB_PWEN2 USB_OC2# GNDA_USB C0725 D0701 BAT54S C0724 100n 2 1 C0705 100n 2 15 6 16 13 8 14 7 GND VCC3V3 C0718 100n GND HPE_RESOUT# C0717 10u0 VCC3V3 100n USB_OTG_VBUS VCC3V3_USB 4 USB_OTG_DM1A USB_OTG_DP1A USB_DM1B USB_DP1B USB_MISO USB_SSI# USB_SCK USB_MOSI USB_TXD USB_RXD USB_RTS USB_CTS C0706 100n 0R00 2 R0701 1 C0720 100n C0721 100n CY7C67300_TQFP100 POWER AGND DM2A DP2A DM2B DP2B MEMSEL ROMSEL RAMSEL 1 26 51 75 100 29 28 16 15 14 6 9 10 4 5 34 35 36 GND GND VCC3V3 C0723 1n00 GNDA_USB C0722 100n VCC3V3_USB USB_XTALIN USB_XTALOUT GND GNDA_USB USB_DM2A USB_DP2A USB_DM2B USB_DP2B USB_GPIO0 USB_GPIO1 USB_GPIO2 USB_GPIO3 USB_GPIO4 USB_GPIO5 USB_GPIO6 USB_GPIO7 USB_GPIO8 USB_GPIO9 USB_GPIO10 USB_GPIO11 USB_GPIO12 USB_GPIO13 USB_GPIO14 USB_GPIO15 USB_GPIO16 USB_GPIO17 USB_GPIO18 USB_GPIO19 USB_GPIO20 USB_GPIO21 USB_GPIO22 USB_GPIO23 USB_GPIO24 USB_GPIO25 USB_GPIO26 USB_GPIO27 USB_GPIO28 USB_OTG_ID USB_SCL USB_SDA FB0704 BLM18PG600SN1 2 GND GND GND GND XTALIN XTALOUT BOOSTVCC BOOSTGND VSWITCH RESET / CLOCK RESET RESERVED VCC VCC VCC USB PORTS CHARGE PUMP OTGVBUS CSWITCHA CSWITCHB AVCC DM1A DP1A DM1B DP1B BEH WR RD 94 93 92 91 90 89 87 86 66 65 61 60 59 58 57 56 55 54 53 52 50 49 48 47 46 45 44 43 42 41 40 39 RS_DCD_LVTTL_X RS_DSP_LVTTL_X RS_DTP_LVTTL_X RS_CTS_LVTTL_X RS_TXD_LVTTL_X RS_RTS_LVTTL_X RS_RXD_LVTTL_X GPIO0/D0 GPIO1/D1 GPIO2/D2 GPIO3/D3 GPIO4/D4 GPIO5/D5 GPIO6/D6 GPIO7/D7 GPIO8/MISO/D8 GPIO9/SSI/D9 GPIO10/SCK/D10 GPIO11/MOSI/D11 GPIO12/D12 GPIO13/D13 GPIO14/D14 GPIO15/SSI/D15 GPIO16/TXD/I_A0 GPIO17/RXD/I_A1 GPIO18/RTS/I_A2 GPIO19/CS0/H_A0 GPIO20/CS1/H_A1 GPIO21/nCS GPIO22/WR/IOW GPIO23/RD/IOR GPIO24/INT/IORDY GPIO25 GPIO26/CTS/PWM3 GPIO27/RX GPIO28/TX GPIO29/OTGID GPIO30/SCL GPIO31/SDA GPIO 0R00 2 R0702 1 D0 D1 D2 D3 D4 D5 D6 D7 D8/MISO D9/SSI D10/SCK D11/MOSI D12/TXD D13/RXD D14/RTS D15/CTS EXT MEMORY CONTROL A0/BEL A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15/CLKSEL A16 A17 A18 U0702 EXT MEMORY C0719 100n 37 63 88 85 84 11 13 12 21 22 23 18 19 98 64 62 83 82 81 80 79 78 77 76 74 73 72 71 70 69 68 67 99 1 2 3 7 8 17 20 24 25 27 30 31 32 33 38 97 95 96 VCC3V3 GND USB_A15 R0703 47K0 VCC3V3 V+ GND V- VCC R1IN R2IN T1OUT T2OUT MAX3232/TSSOP C2+ C2- C1+ C1- R1OUT R2OUT T1IN T2IN U0701 USB Controller C0704 100n 4 5 C0703 100n 1 3 12 9 RS_RXD_LVTTL RS_CTS_LVTTL USB_GPIO[28:0] 11 10 RS_TXD_LVTTL RS_RTS_LVTTL RS232 Interface USB_MISO USB_SSI# USB_SCK USB_MOSI USB_TXD USB_RXD USB_RTS USB_CTS RS_TXD_LVTTL RS_RTS_LVTTL RS_RXD_LVTTL RS_CTS_LVTTL 2 1 2 RS_TXD_LVTTL 2 RS_RTS_LVTTL 2 RS_RXD_LVTTL 2 RS_CTS_LVTTL 3 CON_DSUB_9M X9 Q0701 CRYSTAL_12MHz R0706 15K0 VCC3V3 USB_GPIO[28:0] 5 9 4 8 3 7 2 6 1 1 2 Offpage 2 1 1 C0715 22p0 3 GND R0705 10K0 C0702 10u0 3 4 USB_OC1# USB_PWEN1 6 3 4 7 1 2 GNDA_USB USB_PWEN2 USB_OC2# GNDA_USB C0712 1u00 VCC5V0 1 2 USB_PWEN0 USB_OC0# 6 7 GNDA_USB GNDA_USB C0707 1u00 VCC5V0 VCC3V3 C0716 22p0 R0707 10K0 VCC3V3 R0704 10K0 GND C0701 100n VCC3V3 3 R0708 nb_1M00 2 4 2 1 1 2 1 2 OUTB OUTA OUTB OUTA SP2526-1EN GND FLGB ENB ENA FLGA IN U0704 SP2526-1EN GND FLGB ENB ENA FLGA IN U0703 GNDA_USB USB_SCL USB_SDA GNDA_USB + C0713 100u USB_VBUS2 GNDA_USB + C0710 100u USB_VBUS1 C0714 100n C0711 100n C0709 100n USB_VBUS0_X USB_VBUS1_X USB_VBUS2_X GND GPIO31 SDA 0 0 1 1 RJ0702 0R00 2 Host Port Interface (HPI) High-Speed Serial (HSS) Serial Peripheral Interface (SPI) I2C EEPROM (Standalone Mode) GND RJ0701 nb_10K0 GPIO30 SCL 0 1 0 1 RJ0704 0R00 RJ0703 nb_10K0 VCC3V3 BLM21PG331SN1D 2 FB0703 BLM21PG331SN1D 2 FB0702 BLM21PG331SN1D 2 FB0701 VCC3V3 1 1 1 Boot Configuration Interface 5 8 5 8 + C0708 100u USB_VBUS0 2 GND USB_OTG_VBUS_X FB0705 1500mA BLM21PG331SN1D 330 Ohm @ 100 MHz 1C 2C 3C 4C USB_VBUS2_X USB_DM2B USB_DP2B SHIELD SHIELD SHIELD Authors: IFW: Pr o je ct: Revision: 16 15 14 13 Hp e _ min i L EC2 R01 csam GNDA_USB USB_TypeA/Host VCC DATADATA+ GND X11C USB_TypeA/Host VCC DATADATA+ GND X11B USB_TypeA/Host VCC DATADATA+ GND SHIELD 6 VBUS SH1 7 DSH2 D+ 8 ID SH3 9 GND SH4 USB miniAB 440479-1 X10 X11A 1 2 3 4 5 1 GNDP 1 05:34:50 Sh e e t: 0 7 _ Se r ia l_ USB Last modified: Monday, September 04, 2006 10:15:10 USB HOST USB HOST USB HOST USB OTG Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 Created: Friday, September 24, 2004 A-4232 Hagenberg Page of 12 7 GND GNDA_USB 1B 2B 3B 4B 1A 2A 3A 4A USB_VBUS1_X USB_DM2A USB_DP2A USB_VBUS0_X USB_DM1B USB_DP1B C0727 nb_100n GND USB_OTG_DM1A USB_OTG_DP1A USB_OTG_ID C0726 4u70 USB_OTG_VBUS 1 2 5 1 2 1 2 1 2 1 52 2 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 25. 53 RJ0804 10K0 RJ0806 10K0 RJ0805 nb_10K0 ETH_RXCLK0 1 C0810 220n RP0802 10k0 VCC3V3 ETH_TXCLK0 1 FB0802 BLM18PG600SN1 1 2 VCC3V3 22R0 R0806 22R0 R0802 RJ0803 nb_10K0 2 2 C0813 10n0 4 GND_LAN 53 45 46 47 48 52 49 63 62 1 ETH_RXER ETH_RXD3 ETH_RXD2 ETH_RXD1 ETH_RXD0 ETH_RXDV ETH_CRS ETH_COL CLK_ETH 21 22 8 40 51 VCC3V3 9 10 44 32 33 39 4 ETH_MDC ETH_MDIO HPE_RESOUT# 64 43 42 3 ETH_MDINTR# VCC3V3_LAN VCC3V3_LAN GND 56 55 ETH_TXEN 2 54 60 59 58 57 ETH_TXER ETH_TXD3 ETH_TXD2 ETH_TXD1 ETH_TXD0 RP0801 10k0 LXT971A VCCA VCCA VCCIO VCCIO VCCD nc nc nc SLEEP PAUSE PWRDWN RESET# MDC MDIO MDDIS MDINT# XO REFCLK/XI CRS COL RX_CLK RX_DV RX_ER RXD3 RXD2 RXD1 RXD0 TX_EN TX_CLK TX_ER TXD3 TXD2 TXD1 TXD0 U0801 DGND DGND DGND DGND DGND DGND DGND TEST0 TEST1 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 TDI TDO TMS TCK TRST LED/CFG1 LED/CFG2 LED/CFG3 RBIAS TxSLEW0 TxSLEW1 SD/TP TPFIN TPFIP TPFON TPFOP 61 50 41 25 18 11 7 34 35 16 15 14 13 12 27 28 29 30 31 38 37 36 17 5 6 26 24 23 20 19 2 GND ETH_CFG1 ETH_CFG2 ETH_CFG3 0 0 1 1 GND 0 1 0 1 TxSLEW1 R0817 10K0 R0804 nb_10K0 VCC3V3 TxSLEW0 GND 3 R0816 22K1 2 1 GND C0802 270p 1 C0801 270p 1 2 2.5ns 3.1ns 3.7ns 4.3ns C0805 10n0 R0807 49R9 GND_LAN Slew Rate R0818 10K0 R0805 nb_10K0 C0803 100n R0808 49R9 LAN_RX- LAN_RX+ LAN_TX- LAN_TX+ C0804 100n 5 4 6 1 3 2 FB0801 BLM11B750S VCC3V3_LAN 2 RX+ CT_RX RX- TX+ CT_TX TX- 220n 1 C0809 PULSE H1112 RD+ CT_RD RD- TD+ CT_TD TD- U0802 8 9 7 C0806 1n00 2kV 2 12 10 11 2 R0809 49R9 C0807 1n00 2kV R0810 49R9 GNDP C0808 1n00 2kV R0814 49R9 R0811 49R9 R0815 49R9 R0812 49R9 GNDP ETH_RX- ETH_TX+ ETH_TXETH_RX+ 13 1 2 3 4 5 6 7 8 14 SHIELD TX+ TXRX+ nc nc RXnc nc SHIELD RJ-45-LED X12 LED1+ LED1- LED2+ LED2- R0801 220R Pr o je ct: Revision: R0803 220R Hp e _ min i L EC2 R01 csam LED0801 LED red R0813 220R VCC3V3 ETH_CFG3 ETH_CFG1 ETH_CFG2 11 12 9 10 VCC3V3 1 0 8 _ Eth e r n e t Sh e e t: Last modified: Monday, September 04, 2006 10:15:10 C D 1 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 Created: Tuesday, December 14, 2004 A-4232 Hagenberg Page of 12 8 Authors: IFW: 06:10:51 A 5 GND_LAN GND RJ0802 10K0 RJ0801 nb_10K0 VCC3V3 ETH_RXCLK ETH_TXCLK GND 3 A GND CLK_ETH HPE_RESOUT# ETH_MDC ETH_MDIO ETH_MDINTR# ETH_CRS ETH_COL ETH_RXCLK ETH_RXDV ETH_RXER ETH_RXD3 ETH_RXD2 ETH_RXD1 ETH_RXD0 Ethernet 1 B 6 CLK_ETH 2,6,7,9 HPE_RESOUT# 2 ETH_MDC 2 ETH_MDIO 2 ETH_MDINTR# 2 ETH_CRS 2 ETH_COL 2 ETH_RXCLK 2 ETH_RXDV 2 ETH_RXER 2 ETH_RXD3 2 ETH_RXD2 2 ETH_RXD1 2 ETH_RXD0 ETH_TXEN ETH_TXCLK ETH_TXER ETH_TXD3 ETH_TXD2 ETH_TXD1 ETH_TXD0 4 8 7 6 5 1 2 3 4 B C D 2 ETH_TXEN 2 ETH_TXCLK ETH_TXER ETH_TXD3 ETH_TXD2 ETH_TXD1 ETH_TXD0 1 2 2 1 2 2 1 2 2 1 1 2 2 1 1 2 2 1 2 1 1 2 2 1 2 1 1 1 2 2 2 2 2 2 1 2 1 2 2 1 2 2 Offpage 1 2 1 8 7 6 5 1 2 3 4 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 1 2 11 2 5 Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 26. A B C D 2 SATA_X2D0+ 2 SATA_X2D02 SATA_X2D1+ 2 SATA_X2D1- 2 SATA_X1D0+ 2 SATA_X1D02 SATA_X1D1+ 2 SATA_X1D1- 2 BB3V3_CLK0+ 2 BB3V3_CLK0- 2 BB3V3_IO[21:0] 2,6,7,8 HPE_RESOUT# 6 EXPCON_OSC 2 EXPCON_CLKIN 2 EXPCON_CLKOUT 2 CARDSEL# 2 EXPCON_IO[45:0] 5 SATA_X2D0+ SATA_X2D0SATA_X2D1+ SATA_X2D1- SATA_X1D0+ SATA_X1D0SATA_X1D1+ SATA_X1D1- BB3V3_CLK0+ BB3V3_CLK0- BB3V3_IO[21:0] HPE_RESOUT# EXPCON_OSC EXPCON_CLKIN EXPCON_CLKOUT CARDSEL# EXPCON_IO[45:0] GND EXPCON_IO16 EXPCON_IO17 EXPCON_IO18 EXPCON_IO19 EXPCON_IO21 EXPCON_IO22 EXPCON_IO24 EXPCON_IO25 EXPCON_IO27 EXPCON_IO28 HPE_RESOUT# EXPCON_IO0 EXPCON_IO2 EXPCON_IO4 EXPCON_IO6 EXPCON_IO8 EXPCON_IO10 EXPCON_IO12 EXPCON_IO14 4 SATA_XT2D0+ SATA_XT2D0- SATA_XT1D1+ SATA_XT1D1- SATA_XT1D0+ SATA_XT1D0- R0908 1 R0907 1 R0905 1 0R00 2 0R00 2 0R00 2 GND GND_HS 1 2 3 4 5 6 7 SATA_XT2D1SATA_XT2D1+ SATA_XT2D0+ SATA_XT2D0- GND_HS Sternpunkt X16 CON_SATA GND A+ AGND BB+ GND LVDS LVDS LVDS SATA_XT2D1+ SATA_XT2D10R00 2 0R00 2 R0914 1 R0916 1 0R00 2 R0913 1 R0915 nb_100R R0912 nb_100R R0909 nb_100R R0906 nb_100R 3 SATA_X2D1+ SATA_X2D1- SATA_X2D0+ SATA_X2D0- SATA_X1D1+ SATA_X1D1- SATA_X1D0+ SATA_X1D0- 3 LVDS LVDS LVDS LVDS BB3V3_IO[21:0] BB3V3_IO11 SPI_CCLK BB3V3_IO10 BB3V3_IO9 BB3V3_IO8 BB3V3_IO7 BB3V3_IO6 BB3V3_IO5 BB3V3_IO4 BB3V3_IO3 BB3V3_IO2 BB3V3_IO1 BB3V3_IO0 GND TP0912 TP0924 TP0911 TP0923 TP0910 TP0922 TP0909 TP0921 TP0908 TP0920 TP0907 TP0919 TP0906 TP0918 TP0905 TP0917 TP0904 TP0916 TP0903 TP0915 TP0902 TP0914 TP0901 TP0913 VCC3V3 TP0936 TP0948 TP0960 TP0972 TP0984 TP0935 TP0947 TP0959 TP0971 TP0983 TP0934 TP0946 TP0958 TP0970 TP0982 TP0933 TP0945 TP0957 TP0969 TP0981 TP0932 TP0944 TP0956 TP0968 TP0980 TP0931 TP0943 TP0955 TP0967 TP0979 TP0930 TP0942 TP0954 TP0966 TP0978 TP0929 TP0941 TP0953 TP0965 TP0977 TP0928 TP0940 TP0952 TP0964 TP0976 TP0927 TP0939 TP0951 TP0963 TP0975 TP0926 TP0938 TP0950 TP0962 TP0974 TP0925 TP0937 TP0949 TP0961 TP0973 Prototyping Area (RM2.54) of FPGA Place the 0402-resistors of the LVDS termination as close as possible to the FPGA. 0R00 2 LVDS LVDS LVDS R0911 1 LVDS LVDS GND R0904 10K0 VCC3V3 X16 SATA_XT1D1SATA_XT1D1+ SATA_XT1D0+ SATA_XT1D0- EXPCON_IO26 CARDSEL# EXPCON_IO23 EXPCON_IO20 EXPCON_IO1 EXPCON_IO3 EXPCON_IO5 EXPCON_IO7 EXPCON_IO9 EXPCON_IO11 EXPCON_IO13 EXPCON_IO15 EXPCON_3V3 GND EXPCON_IO29 EXPCON_IO31 EXPCON_IO33 EXPCON_IO35 EXPCON_IO37 EXPCON_IO39 EXPCON_IO41 EXPCON_IO43 EXPCON_IO45 CON_SATA 1 2 3 4 5 6 7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Pin 2 removed for coding of expansion board 0R00 2 GND A+ AGND BB+ GND HDR40 X14 HDR40 X13 R0910 1 X15 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 13 15 17 19 21 EXPCON_2V5 23 25 27 EXPCON_OSC 29 EXPCON_CLKIN 31 EXPCON_CLKOUT 33 35 37 EXPCON_3V3 39 EXPCON_2V5 EXPCON_IO30 EXPCON_IO32 EXPCON_IO34 EXPCON_IO36 EXPCON_IO38 EXPCON_IO40 EXPCON_IO42 EXPCON_IO44 SATA-Connector R0902 0R00 VCC3V3 VCC5V0 GND R0901 0R00 VCC2V5 Expansion Connector 1 2 Offpage 1 2 4 1 2 5 2 1 2 1 2 1 2 54 1 TP09133 2 TP0996 TP09108 TP09120 TP09132 TP09144 TP0995 TP09107 TP09119 TP09131 TP09143 TP0994 TP09106 TP09118 TP09130 TP09142 TP0993 TP09105 TP09117 TP09129 TP09141 TP0992 TP09104 TP09116 TP09128 TP09140 TP0991 TP09103 TP09115 TP09127 TP09139 TP0990 TP09102 TP09114 TP09126 TP09138 TP0989 TP09101 TP09113 TP09125 TP09137 TP0988 TP09100 TP09112 TP09124 TP09136 TP0987 TP0999 TP09111 TP09123 TP09135 TP0986 TP0998 TP09110 TP09122 TP09134 TP0985 TP0997 TP09109 TP09121 2 BB3V3_CLK0- BB3V3_CLK0+ BB3V3_IO21 BB3V3_IO20 BB3V3_IO19 BB3V3_IO18 BB3V3_IO17 BB3V3_IO16 BB3V3_IO15 BB3V3_IO14 BB3V3_IO13 BB3V3_IO12 DIFF BB3V3_IO[21:0] Hp e _ min i L EC2 R01 csam 1 06:28:58 0 9 _ Exp Co n _ Pr o to Ar e a Sh e e t: Last modified: Monday, February 23, 2009 10:17:01 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 Created: Tuesday, December 14, 2004 A-4232 Hagenberg Page of 12 9 Authors: IFW: Pr o je ct: Revision: 1 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 27. 55 A B C D 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 VGA_RD0 VGA_RD1 VGA_GR0 VGA_GR1 VGA_BL0 VGA_BL1 VGA_HSYNC VGA_VSYNC AC97_BITCLK AC97_SDATA_OUT AC97_SDATA_IN AC97_SYNC AC97_RESET# AC97_EXT_CLK AC97_EAPD GND GNDA_AUD Locate under CODEC use 60 mil wide trace between digital and analog GND planes VGA_RD0 VGA_RD1 VGA_GR0 VGA_GR1 VGA_BL0 VGA_BL1 VGA_HSYNC VGA_VSYNC AC97_BITCLK AC97_SDATA_OUT AC97_SDATA_IN AC97_SYNC AC97_RESET# AC97_EXT_CLK AC97_EAPD GND VGA_VSYNC VGA_HSYNC VGA_BL1 VGA_BL0 VGA_GR1 VGA_GR0 VGA_RD1 VGA_RD0 C1019 100n C1016 100n R1017 270R R1014 270R R1011 270R 2 LC1002 NFE31PT222Z1E9 2 GNDA_AC R1012 270R R1018 270R R1016 270R R1015 270R R1013 270R 4 VGA_BL_X GND VGA_GR_X VGA_RD_X GND GND PLL ---> AC97_AIN_R AC97_AIN_L Connect ANALOG GND to GND on Plane realized in CAMTASTIC R1010 270R VDDA5V0_AC97 C1018 100n VDD3V3_AC97 VGA Interface GNDA_AC C1015 1u00 FB1002 BLM18PG600SN1 1 2 VCC5V0 C1017 1u00 VCC3V3 FB1001 BLM18PG600SN1 1 2 Audio Codec 3 X19 1 5L 4L 1L 15 14 13 12 11 R1027 1M00 C1006 100p 1 C1008 1n00 2 Q1001 nb_24.576MHz 0R00 R1026 GNDA_AC R1006 1k00 GNDA_AC R1003 1k00 C1004 1n00 Shield ST-4235-3/3-N LINE-IN NF_L NF_R X17A FB1004 BLM21PG331SN1D 1 2 C1007 100p CON_DSUB_15F 6 1 7 2 8 3 9 4 10 5 33p0 C1029 33p0 C1028 1 FB1003 BLM21PG331SN1D 1 2 AC97_EXT_CLK R1005 0R00 R1002 0R00 GNDA_AC 1 LC1001 NFE31PT222Z1E9 2L 2 C1003 C1001 1u00 VDDA5V0_AC97 3 25 38 3DFLT/NC 3DN 3DP AFILT1/NC AFILT2/NC AFILT3/NC REFFLT VREFOUT MONO_OUT HP_OUT_L HP_OUT_C/NC HP_OUT_R AVDD NC/AVDD DVDD1 DVDD2 XTL_OUT XTL_IN RESET POWER CLOCK BIT_CLK SDATA_OUT SDATA_IN SYNC AVSS AVSS/NC DVSS1 DVSS2 SPDIF/NC EAPD/NC ID1 ID0 HPP/NC NC DIGITAL INTERFACE PHONE PC_BEEP AUX_L AUX_R VIDEO_L VIDEO_R MIC1 MIC2 CD_L CD_GND CD_R LINE_OUT_L LINE_OUT_R ANALOG LINE_IN_L LINE_IN_R U1001 AC'97 CODEC C1020 PB-Free Part: nb_100n LM4549BVHX GNDA_AC R1023 nb_0R00 1 9 3 AC97_XTL_OUT R1028 0R0 2 AC97_XTL_IN VDD3V3_AC97 11 AC97_RESET# ---> 13 12 14 15 16 17 21 22 18 19 20 23 24 6 5 8 10 R1021 33R0 GNDA_AC C1014 100n AC97_LINEIN_L AC97_LINEIN_R AC97_BITCLK AC97_SDATA_OUT AC97_SDATA_IN AC97_SYNC 1 1 <-----> <-----> R1007 1u00 47k0 2 R1004 47k0 26 42 4 7 48 47 46 45 44 43 32 33 34 29 30 31 27 28 37 39 40 41 35 36 GND C1011 22n0 GNDA_AC R1022 nb_0R00 3L NF_L NF_R 1U 5U 4U 1 1 C1002 1u00 1u00 R1020 nb_0R00 R1025 nb_0R00 2 2 1 R1008 47k0 1 LC1004 NFE31PT222Z1E9 C0805 2 TP1003 C1023 nb_10u0 10u0 (VT1612A) 1u00 (AD1881) C1024 nb_1n00 1u00 (AD1881) C0805 GNDA_AC R1009 47k0 GNDA_AC FB1006 BLM21PG331SN1D 2 AC97_SPDIF_OUT AC97_EAPD C1022 nb_100n 100n (VT1612A) 10n0 (CS4299) C0603 TP1002 TP1001 C1021 nb_22n0 47n0 (AD1881) C0603 C1005 GNDA_AC 2 LC1003 NFE31PT222Z1E9 2 2 FB1005 BLM21PG331SN1D 1 2 Shield 4 ST-4235-3/3-N Headphone / Line-out X17B GNDA_AC R1024 nb_0R00 100n (AD1881) 1n00 (CS4299) AC97_PIN48 AC97_PIN47 AC97_3DFLT AC97_3DN AC97_3DP AC97_AFILT1 AC97_AFILT2 AC97_AFILT3 AC97_VREF AC97_VREFOUT AC97_HP_OUT_L AC97_HP_OUT_C AC97_HP_OUT_R AC97_LINEOUT_L AC97_LINEOUT_R LOCATE SEPERATE ANALOG POWER AND ANALOG GROUND PLANES DIRECTLY ON TOP OF ONE ANOTHER WITHOUT OVERLAPPING DIGITAL POWER OR GROUND PLANES. A SINGLE ZERO OHM RESISTOR SHOULD LINK THE DIGITAL AND ANALOG GROUND PLANES AS CLOSE TO THE CODEC AS POSSIBLE. 3 3 Offpage 3 4 2 1 + 2 + 1 + + 1 C1025 nb_1n00 270p (VT1612A) C0603 C1010 1n00 AC97_AOUT_R C1009 1n00 AC97_AOUT_L 3 5 C1026 nb_1n00 270p (VT1612A) C0603 C0603 C1027 nb_1u00 270p (VT1612A) Authors: IFW: Pr o je ct: Revision: GNDA_AC Hp e _ min i L EC2 R01 csam C1013 10u0 10u0 (VT1612A) 3u30 (LM4480) 1u00 (CS4299) C1206 1 06:11:30 Sh e e t: 1 0 _ Au d io _ VG A Last modified: Monday, September 04, 2006 10:15:09 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 Created: Tuesday, December 14, 2004 A-4232 Hagenberg Page of 12 10 C1012 100n C0603 R1019 10k0 nb_10k0 (VT1612A) VDDA5V0_AC97 1 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 28. A B C D GND_PWR GND Connect ANALOG GND to GND on Plane 5 extra ANALOG GND plane connected with 6Vias to GND on plane C1120 100n 1 2 3 C1121 100n GND GND C1131 10u0 VCC5V0 1 2 3 D1102 2 SW VIN ISENSE 6 5 4 4 R1107 15K0 C1117 220p 10MQ040N 1 TPS64203DBVT EN GND FB U1102 C1122 33p0 VCC_KLD 2.5V/2.6V (2A) C1119 10n0 KLD-0202-A OUTSIDE OPENER CENTER 2 1 X20 R1116 1 R1115 1 C1123 33p0 + C1107 47u0 20V C7343 GND 10R0 2 3 G GND R1108 15K0 C1118 220p C1114 10u0 GND_PWR 0R033 2 GND_PWR + C1106 47u0 20V C7343 VCC5V0 D T1103 S Si3445DV D1106 10MQ040N GND R1118 36k0 1% 10u0 L1103 R1117 42K2 1% optional A1101 Jumper X21 HDR3 GND C1134 1u00 VCC2V5_T PW_BOOST2 PW_BOOST1 + C1133 100u GND 12 13 14 19 17 16 18 4 3 2 23 26 27 25 R1119 39k0 1% C1132 4p70 Vos2 SENSE2- SENSE2+ BG2 SW2 TG2 BOOST2 Vos1 SENSE1- SENSE1+ BG1 SW1 TG1 BOOST1 C1105 100n LTC1628-SSOP28 PGND SGND ITH2 ITH1 RUN/SS2 RUN/SS1 STBYMD 3V3Out FCB FLTCPL FREQSET INTVcc Ext_Vcc VIN U1101 GND C1104 10u0 3 3 2 PH1103 PlaceHolder 1 GND 1 LD1102 LED green 2.5V PG R1120 100R VCC2V5 Place the parts C1103, C1105 and C1124 as close as possible to the pins of the U1101 Set the jumper to 1-2 for 2.5V and to 3-2 for 2.6V (This is important for the DDR SDRAM module) GND 20 9 11 8 15 1 6 10 7 28 5 21 22 24 max 2.4A GND_PWR GND_PWR R1103 4k70 3.3V (1A) / 1.2V (2A) DC/DC-Converter 4 2 1 2 1 1 PW_T1B_GATE C1113 nb_10n0 GND_PWR C1103 100n TP1104 TEST POINT 2.5V C1125 nb_10n0 5 VCC5V0 R1110 5R10 C1126 1n00 PW_SW2 GND_PWR C1115 10u0 GNDP optional Label01 LABEL optional Pad1101 ArtNr05281 optional Pad1102 ArtNr05281 2 optional Pad1103 ArtNr05281 Miscellaneous DRILL1103 DRILL DRILL1101 DRILL PW_VOS2 R1105 5R10 C1108 1n00 PW_SW1 GND_PWR GND_PWR T1102B SI6966DQ T1102A SI6966DQ 2 C1101 10u0 GND_PWR T1101B SI6966DQ T1101A SI6966DQ VOS1 VCC5V0 Drill PW_T2B_GATE GND_PWR C1124 100n 4 5 D1101 PW_T1A_GATE 4 MBR0540LT1 D1104 MBR0540LT1 PW_T2A_GATE 2 5 4 1 2 5 6 2 1 1 2 3 2 1 1 2 1 2 3 8 7 6 1 2 3 8 7 6 2 1 2 1 2 1 2 GND max 2A C1127 1n00 R1111 0R05 max 1A C1112 1n00 R1102 0R025 GNDP 1 1 optional Pad1105 ArtNr05281 PW_SW2_L D1105 10MQ040N 100u0 L1102 C1116 100n PW_SW1_L D1103 10MQ040N 33u0 L1101 C1102 100n optional Pad1104 ArtNr05281 1 DRILL1104 DRILL DRILL1102 DRILL 2 2 C1128 180p C1109 180p 1 2 1 R1106 10K0 1% R1104 5K10 1% GND_PWR + C1111 220u 10V C7343H LESR40 Pr o je ct: Revision: Authors: IFW: PH1102 PlaceHolder 1 2 GND PH1101 PlaceHolder 1 2 Hp e _ min i L EC2 R01 csam + C1130 220u 10V C7343H LESR40 GND_PWR C1129 10u0 VCC3V3_T GND_PWR C1110 10u0 10V VCC1V2_T 1 1 TEST POINT 1.2V TP1101 1 GND 1 02:11:59 Sh e e t: 1 1 _ Po we r Su p p ly Last modified: Monday, September 04, 2006 10:14:07 TEST POINT 3.3V TP1103 1 LD1101 LED green 3.3V PG R1114 330R VCC3V3 TEST POINT GND TP1102 VCC1V2 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 Created: Friday, September 10, 2004 A-4232 Hagenberg 11 Page of 12 R1113 15K0 1% R1112 47K0 1% GND_PWR 2 2 1 2 1 2 1 Offpage 1 2 1 2 2 56 1 A B C D Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 29. 57 3 2 Hp e _ min i L EC2 R01 csam Sh e e t: 1 2 _ De sig n No te s Last modified: Wednesday, July 19, 2006 00:17:49 C D 1 Gleichmann Electronics Research (Austria) GmbH & Co KG Hauptstraße 119 Created: Friday, September 24, 2004 A-4232 Hagenberg Page of 12 12 Authors: IFW: 05:39:35 A Pr o je ct: Revision: 1 A 4 2 B 5 General routing requirements: Differential: routing as differential signals, length matching +/- 20 mils length max. 100mm, route as daisy chain Memory: Signals: max 150mm, length matching +/- 10mm 3 B C D 4 Clocks: max. 120mm, daisy chain routing Netclasses: 5 Lattice Semiconductor LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide Figure 30.