326 KB

The following document contains information on Cypress products.
S6E2DH Series
32-bit Microcontroller
FM4 Family
Fact Sheet
®
As part of Spansion’s FM4 Family this new Cortex -M4 based microcontroller series incorporates a dedicated
hardware graphics engine that allows rich display images with a cost-effective single-chip solution.
Ideal for embedded applications with TFT HMIs such as home appliances, multi-function printers, industrial
equipment, electronic musical instruments, security systems, and similar.
The graphics engine and 512 KB of video RAM allow complex image overlap, mirroring, scaling, and image
movement with very little CPU overhead. Previously this type of sophisticated graphics was possible only with
multi-chip solutions costing much more.
The Spansion solution comes complete with graphics authoring tools and low level libraries for the graphics engine.
1.

−
−

−

−
−
−
−
−
−
−

−
−
−
−
−
−




−








−
−


−
FEATURES
ARM Cortex-M4F CPU Core
Processor version: r0p1
FPU built-in, Support DSP instruction
Clock
Maximum clock frequency: 160 MHz
Graphics Display Controller (GDC)
2 Dimensional accelerator blit engine
Parallel RGB interface
TM
HyperBus interface
Quad-SPI interface
SDRAM interface
512 Kbyte on-chip VRAM
Optional 2 Mbyte VFlash for storing images
Multi-function Timer:1 unit (Max.)
16-bit free-run timer
×3 channels/unit
Input capture
×4 channels/unit
Output compare
×6 channels/unit
A/D activation compare ×6 channels/unit
Waveform generator
×3 channels/unit
16-bit PPG timer
×3 channels/unit
Quadrature Position Counter (QPRC) :1 channel
Dual Timer:1 unit
Watchdog Timer: 1 channel (SW) + 1 channel (HW)
Multi-function Serial Interface:8 channels (Max.)
2
Selectable from UART/SPI/LIN/I C
Real Time Clock: 1 unit
DMA Controller: 8 channels
Descriptor System Transfer Controller (DSTC): 128
channels
USB 2.0 FS (Device/Host): 1 unit
CAN-FD: 1 unit
SD card Interface: 1 unit
2
I S: 2 units
External Interrupt Controller Unit
External interrupt input pin: Max. 16 pins
Include one non-maskable interrupt (NMI)
12-bit A/D Converter: Max. 24 channels (2 units)
Low Power Consumption Mode
Sleep mode/Timer mode/RTC mode/Stop mode/Deep
standby RTC mode/Deep standby stop mode supported
Publication Number S6E2DH_NP709-00016
®

−
−





−
−




General Purpose I/O Port
S6E2DH5G:
98 (Max.)
S6E2DH5J:
154 (Max.)
Built-in 100 kHz and 4 MHz CR oscillators
Unique ID
Low Voltage Detector
Clock Supervisor
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM)
Power Supply: 2.7 to 3.6 V
Base Timer: 16 channels (Max.)
Watch counter
Programmable CRC accelerator
2.
PRODUCT LINEUP
Part number
S6E2DH5
G0A/J0A
S6E2DH5
GAA/JAA
S6E2DH5
GJA
VRAM
(for GDC)
512 Kbytes
384 Kbytes
512 Kbytes
VFlash
(for GDC)
―
―
2 Mbytes
Parameter
3.
SRAM
36 Kbytes
Flash
384 Kbytes
ORDERING INFORMATION
Package
Part number
S6E2DH5G0AMV20000
Plastic・LQFP (0.5 mm
pitch),
S6E2DH5GAAMV20000
120 pin (FPT-120P-M21)
S6E2DH5J0AGV20000
Plastic・LQFP (0.5 mm
pitch),
S6E2DH5JAAGV20000
176 pin (FPT-176P-M07)
S6E2DH5G0AGB10000
Plastic・BGA (0.5 mm pitch),
161 pin (FDJ161)
Revision 1.1
®
Issue Date February 19, 2015
Copyright © 2015 Spansion All rights reserved. Spansion , the Spansion logo, MirrorBit , Easy DesignSim™, Traveo™and combinations thereof, are trademarks
and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks
of their respective owners.
F a c t
4.
S h e e t
BLOCK DIAGRAM
S6E2DH5J0A / S6E2DH5G0A / S6E2DH5GJA
S6E2DH5JAA / S6E2DH5GAA
TRSTX,TCK,
TDI,TMS
TDO
SWJ-DP
ETM*
TRACEDx,
TRACECLK
TPIU*
ROM
Table
SRAM0
32Kbytes
SRAM2
4Kbytes
Cortex-M4 Core
@160MHz(Max)
I
MPU
NVIC
Sys
AHB-APB
Bridge:APB0(Max:80MHz)
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardw are)
MainFlash I/F
Multi-layer AHB (Max:160MHz)
D
FPU
Trace Buffer
(16Kbytes)
MainFlash
384Kbytes
Security
USB2.0
PHY
UDP0,UDM0
(Host/Func)
(host/device)
UHCONX0
DMAC
8ch.
CSV
DSTC
1unit(128ch.)
CLK
Source Clock
Sub
OSC
CROUT
TIOBx
AIN
BIN
ZIN
Unit 0
Unit 1
Base Timer
16bit 16ch./
32bit 8ch
QPRC
1ch.
A/D Activation Compare
6ch.
IC0
16bit Input Capture
4ch.
FRCK0
16bit Free-run Timer
3ch.
16bit Output Compare
6ch.
DTTI0x
RTO0x
Waveform Generator
3ch.
16bit PPG
3ch.
Multi-function Timer
VBAT
VMAKEUP
VREGCTL
RTCCO,SUBOUT
1unit
VBAT Domain
Real-Time Clock
Port Cntl.
I2S
2unit
GPIO
PIN-Function-Ctrl
HyperBus I/F
PLL
I2S Clock Cntl.
PLL
■SDRAM I/F
GE_SDCLK,GE_SDCKE,GE_SDCSX,
GE_SDCASX,GE_SDRASX,GE_SDWEX,
GE_SDDQM[3:0],GE_SDBA[1:0],
GE_SDA[11:0],GE_SDDQ[31:0]
■HyperBus I/F
GE_HBCK, GE_HBDQ[7:0], GE_HBCSX_0/1,
GE_HBRWDS, GE_HBRESETX,
GE_HBINTX, GE_HBRSTOX, GE_HBWPX
■HighSpeed Quad SPI
GE_SPCK, GE_SPDQ[3:0], GE_SPCSX_0
*S6E2DH5GJA Unavailable
CAN Prescaler
PLL
MADx
MADATAx
MCSXx,MDQMx,
MOEX,MWEX,
MALE,MRDY,
MNALE,MNCLE,
MNWEX,MNREX,
MCLKOUT,MSDWEX,
MSDCLK,MSDCKE,
MRASX,MCASX
■Panel I/F
PNL_DCLK, PNL_DEN, PNL_PWE,
PNL_LE, PNL_LH_SYNC, PNL_FV_SYNC,
PNL_PD[23:0], PNL_TSIG[11:0]
VFLASH
2Mbytes
*S6E2DH5GJA Only
Power-On
Reset
LVD
Regulator
IRQ-Monitor
S_CLK,S_CMD
S_DATAx
S_CD,S_WP
HighSpeed
Quad SPI
LVD Cntl.
Peripheral Clock Gating
Low -speed CR Prescaler
SD-CARD I/F
SDRAM I/F
USB Clock Cntl.
P0x,
P1x,
:
PFx
MD0,MD1
GDC unit
GDC Clock Cntl.
I2SMCLKx,
I2SWSx,I2SCKx
I2SDIx
I2SDOx
MODE-Cntl.
VRAM
512Kbytes/
384Kbytes
Graphic
Engine core
TX,RX
PRG-CRC
Accelerator
External Bus I/F
AHB-APB Bridge:APB2(Max:80MHz)
TIOAx
12bit A/D Converter 24ch.
AHB-APB Bridge:APB1(Max:160MHz)
AVCC,AVSS,
AVRH,AVRL
ANxx
ADTGx
AHB-AHB Bridge (Slave)
CR
4MHz
VBAT Domain
X0A
X1A
CAN FD
CR
100kHz
PLL
AHB-AHB Bridge (Master)
Main
OSC
AHB-AHB Bridge (Slave)
X0
X1
Deep Standby Cntl.
External Interrupt
Controller
16ch + NMI
C
WKUPx
INTx
NMIX
CRC Accelerator
Watch Counter
Multi-function Serial I/F
8ch.
(w ith FIFO ch.0 to ch.7)
HW flow control(ch.4,5)
SCKx
SINx
SOTx
CTSx
RTSx
SCSx
ARM and Cortex are the registerd trademarks of ARM Limited in the EU and other countries.
2
S6E2DH_NP709-00016-1v1-E, February 19, 2015
Similar pages