DATASHEET

DATASHEET
2-Phase Boost Controller with Integrated Drivers
ISL78227
Features
The ISL78227 is an automotive grade (AEC-Q100 Grade 1),
2-phase 55V synchronous boost controller intended to simplify
the design of high power boost applications. It integrates
strong half-bridge drivers, an analog/digital tracking input and
comprehensive protection functions.
• Input/output voltage range: 5V to 55V, withstands 60V
transients
• Supports synchronous or standard boost topology
• Peak current mode control with adjustable slope
compensation
The ISL78227 enables a simple, modular design for systems
requiring power and thermal scalability. It offers peak-current
mode control for fast line response and simple compensation.
Its synchronous 2-phase architecture enables it to support
higher current while reducing the size of input and output
capacitors. The integrated drivers feature programmable
adaptive dead time control offering flexibility in power stage
design. ISL78227 offers a 90°output clock and supports 1-,
2- and 4-phases.
• Secondary average current control loop
• Integrated 5V 2A sourcing/3A sinking N-channel MOSFET
drivers
• Switching frequency: 50kHz to 1.1MHz per phase
• External synchronization
• Programmable minimum duty cycle
• Programmable adaptive dead time control
The ISL78227 offers a highly robust solution for the most
demanding environments. Its unique soft-start control
prevents large negative current even in extreme cases, such as
a restart under high output prebias on high volume
capacitances. It also offers two levels of cycle-by-cycle
overcurrent protection, average current limiting, input OVP,
output UVP/OVP and internal OTP. In the event of a fault, the
fault protection response can be selected to be latch-off or
hiccup recovery.
• Optional diode emulation and phase dropping
Also integrated are several functions that ease system design.
A unique tracking input is available that can control the output
voltage, allowing it to track either a digital duty cycle (PWM)
signal or an analog reference. The ISL78227 provides input
average current limiting so the system can deliver transient
bursts of high load current while limiting the average current to
avoid overheating.
• 5mmx5mm 32 Ld WFQFN (Wettable Flank QFN) package
PVCC
PVCC
BOOT1
PGND
UG1
PH1
VIN
EN_IC
TRACK
BOOT2
UG2
PH2
CLOCK_OUT
RSEN2
• Automotive power system (e.g., 12V to 24V, 12V to 48V, etc.)
- Trunk audio amplifier
- Start-stop system
- Automotive boost applications
• Industrial and telecommunication power supplies
100
90
VO = 18V
85
80
VO = 24V
75
VO = 36V
70
65
60
CLKOUT
LG2
55
ISEN2N
50
SS
COMP
Applications
95
ISEN1P
PGOOD
• AEC-Q100 qualified, Grade 1: -40°C to +125°C
VIN
ISL78227
POWER-GOOD
• Selectable hiccup or latch-off fault response
RSEN1
ISEN1N
EN
• Comprehensive fault protections
VOUT
LG1
VIN
• Forced PWM operation with negative current limiting and
protection
EFFICIENCY (%)
PVCC
• PWM and analog track function
0
ISEN2P
FB
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
LOAD CURRENT (A)
NOTE: (See Typical Application in Figure 4 on page 8.)
FIGURE 1. SIMPLIFIED APPLICATION SCHEMATIC, 2-PHASE
SYNCHRONOUS BOOST
February 24, 2016
FN8808.2
1
FIGURE 2. EFFICIENCY CURVES, VIN = 12V, TA = +25°C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
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ISL78227
Table of Contents
Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Application - 2-Phase Synchronous Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operation Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiphase Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator and Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Initialization and Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGOOD Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adjustable Slope Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Light-Load Efficiency Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Protections/Indications and Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal 5.2V LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
25
26
28
29
30
30
30
30
32
32
33
36
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
37
37
37
38
38
38
38
38
40
40
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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2
FN8808.2
February 24, 2016
ISL78227
Pin Configuration
RDT
ATRK/DTRK
ISEN2P
ISEN2N
ISEN1P
ISEN1N
VIN
BOOT1
ISL78227
(32 LD 5x5 WFQFN)
TOP VIEW
32
31
30
29
28
27
26
25
VCC
1
24
UG1
SLOPE
2
23
PH1
FB
3
22
LG1
COMP
4
21
PVCC
SS
5
20
PGND
IMON
6
19
LG2
TRACK
7
18
PH2
PGOOD
8
17
UG2
9
10
11
12
13
14
15
16
FSYNC
HIC/LATCH
DE/PHDRP
RBLANK
PLLCOMP
EN
CLKOUT
BOOT2
SGND
Functional Pin Description
PIN NAME
PIN #
DESCRIPTION
VCC
1
IC bias power input pin for the internal analog circuitry. A minimum 1µF ceramic capacitor should be used between VCC
and ground for noise decoupling purposes. VCC is typically biased by PVCC or an external bias supply with voltage ranging
from 4.75V to 5.5V. Since PVCC is providing pulsing drive current, a small resistor like 10Ω or smaller between PVCC and
VCC can help to filter out the noises from PVCC to VCC.
SLOPE
2
This pin programs the slope of the internal slope compensation. A resistor should be connected from the SLOPE pin to
GND. Please refer to “Adjustable Slope Compensation” on page 32 for how to select this resistor value.
FB
3
The inverting input of the error amplifier for the voltage regulation loop. A resistor network must be placed between the
FB pin and the output rail to set the boost converter’s output voltage. Please refer to “Output Voltage Setting” on page 37
for more details.
There are also output overvoltage and undervoltage comparators monitoring this pin. Please refer to “Output Overvoltage
Fault Protection” and “Output Undervoltage Indication” on page 34 for more details.
COMP
4
The output of the transconductance error amplifier (Gm1) for the output voltage regulation loop. Place the compensation
network between the COMP pin and ground. Please refer to “Output Voltage Regulation Loop” on page 25 for more details.
The COMP pin voltage can also be controlled by the constant current control loop error amplifier (Gm2) output through
a diode (DCC) when the constant current control loop is used to control the input average current. Please refer to
“Constant Current Control (CC)” on page 35 for more details.
SS
5
A capacitor placed from SS to ground will set up the soft-start ramp rate and in turn determine the soft-start time. Please
refer to “Soft-Start” on page 30 for more details.
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FN8808.2
February 24, 2016
ISL78227
Functional Pin Description (Continued)
PIN NAME
PIN #
DESCRIPTION
IMON
6
IMON is the average current monitor pin for the sum of the two phases’ inductor currents. It is used for average current limiting
and average current protection functions.
The sourcing current from the IMON pin is the sum of the two CSA’s outputs plus a fixed 17µA offset current. With each CSA
sensing individual phase’s inductor current, the IMON signal represents the sum of the two phases’ inductor currents and it is
the input current for the boost. A resistor in parallel with a capacitor are needed to be placed from IMON to ground. The IMON
pin output current signal builds up the average voltage signal representing the average current sense signals.
A constant average current limiting function and an average current protection are implemented based on the IMON signal.
1. Constant Current Control: A Constant Current (CC) control loop is implemented to control the IMON average current
signal equal to a 1.6V reference (VREF_CC), which ultimately limits the total input average current to a constant
level.
2. Average Current Protection: If the IMON pin voltage is higher than 2V, the part will go into either Hiccup or Latch-off fault
protection depending on the HIC/LATCH pin configuration.
Refer to “Average Current Sense for 2 Phases - IMON” on page 31 for more details.
TRACK
7
External reference input pin for the IC output voltage regulation loop to follow. The input reference signal can be either digital
or analog signal selected by the ATRK/DTRK pin configuration.
If the TRACK function is not used, connect the TRACK pin to VCC and the internal VREF_1.6V will work as the reference. Refer
to “Digital/Analog Track Function” on page 25 for more details.
PGOOD
8
Provides an open-drain power-good signal. Pull up this pin with a resistor to this IC’s VCC for proper function. When the output
voltage is within OV/UV thresholds and soft-start is completed, the internal PGOOD open-drain transistor is open and PGOOD
is pulled HIGH. It will be pulled low once output UV/OV or input OV conditions are detected. Refer to “PGOOD Signal” on
page 30 for more details.
FSYNC
9
A dual-function pin for switching frequency setting and synchronization defined as follows:.
1. The PWM switching frequency can be programmed by a resistor RFSYNC from this pin to ground. The PWM frequency
refers to a single-phase switching frequency in this datasheet. The typical programmable frequency range is 50kHz
to 1.1MHz.
2. The PWM switching frequency can also be synchronized to an external clock applied on the FSYNC pin. The FSYNC
pin detects the input clock signal’s rising edge that it is to be synchronized with. The typical detectable minimum
pulse width of the input clock is 20ns. The rising edge of LG1 is delayed by 35ns from the rising edge of the input
clock signal at the FSYNC pin. Once the internal clock is locked to the external clock, it will latch to the external clock.
If the external clock on the FSYNC pin is removed, the switching frequency oscillator will shut down. The part will
then detect PLL_LOCK fault and go to either Hiccup mode or Latch-off mode depending on the HIC/LATCHOFF pin
configuration. If the part is set in Hiccup mode, the part will restart with frequency set by RFSYNC.
The typical synchronization frequency range is 50kHz to 1.1MHz.
The phase dropping mode is not allowed with external synchronization.
Refer to “Oscillator and Synchronization” on page 28 for more details.
HIC/LATCH
10
This pin is used to select either Hiccup or Latch-off response to faults including output overvoltage (monitoring the FB
pin), output undervoltage (monitoring the FB pin, default inactive), VIN overvoltage (monitoring the FB pin), peak
overcurrent protection (OC2_PEAK), and average current protection (monitoring the IMON pin), etc.
HIC/LATCH = HIGH to have Hiccup fault response.
HIC/LATCH = LOW to have Latch-off fault response. Either toggling the EN pin or recycling VCC POR resets the IC from
Latch-off status.
Refer to “Selectable Hiccup or Latch-Off Fault Response” on page 33 for more details.
DE/PHDRP
11
This pin is used to select Diode Emulation mode (DE), Phase Dropping (PH_DROP) mode or Continuous Conduction Mode
(CCM). There are 3 configurable modes: 1. DE mode; 2. DE plus PH_DROP mode; 3. CCM mode.
Refer to Table 2 on page 33 for the 3 configurable options.
The phase dropping mode is not allowed with external synchronization.
RBLANK
12
A resistor from this pin to ground programs the blanking time for current-sensing after the PWM is ON (LG is ON). This
blanking time is also termed as tMINON time meaning minimum ON-time once a PWM pulse is ON. Refer to “Minimum
On-Time (Blank Time) Consideration” on page 28 for the selection of RBLANK.
PLLCOMP
13
This pin serves as the compensation node for the switching frequency clock’s PLL (Phase Lock Loop). A second order
passive loop filter connected between this pin and ground compensates the PLL loop. Refer to “Oscillator and
Synchronization” on page 28 for more details.
EN
14
This pin is a threshold-sensitive enable input for the controller. When the EN pin is driven above 1.21V (typical), the
ISL78227 is enabled and the internal LDO is activated to power up PVCC followed by a start-up procedure. Driving the EN
pin below 0.95V will disable the IC and clear all fault states. Refer to “Enable” on page 30 for more details.
CLKOUT
15
This pin outputs a clock signal with same frequency to one phase’s switching frequency. The rising edge signal on the CLKOUT
pin is delayed by 90° from the rising edge of LG1 of the same IC. With CLKOUT connected to the FSYNC pin of the second
ISL78227, a 4-phase interleaving operation can be achieved. Refer to “Oscillator and Synchronization” on page 28 for more
details.
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FN8808.2
February 24, 2016
ISL78227
Functional Pin Description (Continued)
PIN NAME
PIN #
DESCRIPTION
BOOT2
16
This pin provides bias voltage to the Phase 2 high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable
to drive the external N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor are recommended between
the BOOT2 and PH2 pins. In the typical configuration, PVCC is providing the bias to BOOT2 through a fast switching diode.
In applications where a high-side driver is not needed (standard boost application for example), BOOT2 is recommended
to be connected to ground. The ISL78227 IC can detect BOOT2 being grounded during start-up and both the Phase 1 and
Phase 2 high-side drivers will be disabled. In addition, PH1 and PH2 should also be tied to ground.
UG2
17
Phase 2 high-side gate driver output. This output can be disabled by tying either BOOT1 and PH1 to ground or BOOT2 and
PH2 to ground.
PH2
18
Connect this pin to the source of the Phase 2 high-side MOSFETs and the drain of the low-side MOSFETs. This pin
represents the return path for the Phase 2 high-side gate drive.
LG2
19
Phase 2 low-side gate driver output. It should be connected to the Phase 2 low-side MOSFETs’ gates.
PGND
20
Provides the return path for the low-side MOSFET drivers. This pin carries a noisy driving current and traces connecting
from this pin to the low-side MOSFET source and PVCC decoupling capacitor ground pad should be as short as possible.
All the sensitive analog signal traces should not share common traces with this driver return path. Connect this pin to
the ground copper plane (wiring away from the IC instead of connecting through the IC bottom PAD) through several vias
as close as possible to the IC.
PVCC
21
Output of the internal linear regulator that provides bias for the low-side driver, high-side driver (PVCC connected to BOOTx
through diodes) and VCC bias (PVCC and VCC are typically connected through a small resistor like 10Ω or smaller, which helps
to filter out the noises from PVCC to VCC). The PVCC operating range is 4.75V to 5.5V. A minimum 10µF decoupling ceramic
capacitor should be used between PVCC and PGND. Refer to “Internal 5.2V LDO” on page 36 for more details.
LG1
22
Phase 1 low-side gate driver output. It should be connected to the Phase 1 low-side MOSFETs’ gates.
PH1
23
Connect this pin to the source of the Phase 1 high-side MOSFETs and the drain of the low-side MOSFETs. This pin
represents the return path for the Phase 1 high-side gate drive.
UG1
24
Phase 1 high-side MOSFET gate drive output. This output can be disabled by tying either BOOT1 and PH1 to ground or
BOOT2 and PH2 to ground.
BOOT1
25
This pin provides bias voltage to the Phase 1 high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable
to drive the external N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor are recommended between
BOOT1 and PH1 pins. In typical configuration, PVCC is providing the bias to BOOT1 through a fast switching diode.
In applications where a high-side driver is not needed (for example, standard boost application), the BOOT1 is
recommended to be connected to ground. The ISL78227 IC can detect BOOT1 being grounded during start-up and both
the Phase 1 and Phase 2 high-side drivers will be disabled. In addition, PH1 and PH2 should also be tied to ground.
VIN
26
Connect supply rail to this pin. Typically, connect boost input voltage to this pin. This pin is connected to the input of the internal
linear regulator, generating the power necessary to operate the chip. The DC voltage applied to VIN should not exceed 55V
during normal operation. VIN can withstand transients up to 60V, but in this case, the device's overvoltage protection will stop
it from switching to protect itself. Refer to “Input Overvoltage Fault Protection” on page 34 for more details.
ISEN1N
27
The ISEN1N pin is the negative potential input to the Phase 1 current sense amplifier. This amplifier continuously senses
the Phase 1 inductor current through a power current sense resistor in series with the inductor. The sensed current signal
is used for current mode control, peak current limiting, average current limiting and diode emulation.
ISEN1P
28
The ISEN1P pin is the positive potential input to the Phase 1 current sense amplifier.
ISEN2N
29
The ISEN2N pin is the negative potential input to the Phase 2 current sense amplifier. This amplifier continuously senses
the Phase 2 inductor current through a power current sense resistor in series with the inductor. The sensed current signal
is used for current mode control, peak current limiting, average current limiting and diode emulation.
ISEN2P
30
The ISEN2P pin is the positive phase input to the Phase 2 current sense amplifier.
ATRK/DTRK
31
The logic input pin to select the input signal format options for the TRACK pin. Pull this pin HIGH for the TRACK pin to
accept analog input signals. Pull this pin LOW for the TRACK pin to accept digital input signals. Refer to “Digital/Analog
Track Function” on page 25 for more details.
RDT
32
A resistor connected from this pin to ground programs the dead times between UGx OFF to LGx ON and LGx OFF to UGx
ON to prevent shoot-through. Please refer to “Driver Configuration” on page 24 for the selection of RDT.
SGND
-
Signal ground bottom pad for the internal sensitive analog circuits to be referred to, also serves as thermal pad. Connect
this pad to large ground plane. Put multiple vias (as many as possible) in this pad connecting to the ground copper plane to
help reduce the IC’s JA. In layout power flow planning, avoid having the noisy high frequency pulse current flow through
the SGND area.
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FN8808.2
February 24, 2016
ISL78227
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL78227ARZ
ISL7822 7ARZ
ISL78227EV1Z
Evaluation Board
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
-40 to +125
32 Ld 5x5 WFQFN
PKG.
DWG. #
L32.5x5H
NOTES:
1. Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate
- e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78227. For more information on MSL please see techbrief TB363.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART
NUMBER
TOPOLOGY
PMBus™
NTC
TRACK FUNCTION
ISL78229ARZ
2-Phase Boost Controller
Yes
Yes
Yes
40 Ld 6x6 WFQFN
ISL78227ARZ
2-Phase Boost Controller
No
No
Yes
32 Ld 5x5 WFQFN
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PACKAGE
FN8808.2
February 24, 2016
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Block Diagram
VIN
EN
EN
HIC/LATCH
÷ 48
VIN/48
PGOOD
VIN_OV
1.21V
1.21V
VIN_OV
5.2V
LDO
PVCC
VOUT_OV
OC_AVG
1.2*VREF_1.6V
POR
OTP
PLL
7
EN
FAULT LOGIC
OC2_PEAK_PH2
PLLCOMP_SHORT
VFB
PLL_LOCK
0.8*VREF_1.6V
HICCUP
/LATCHOFF
OC2_PEAK_PH1
EN
VOUT_OV
VCC
VOUT_UV
DELAY
EN_HICCP
5µA
CLOCK
EN_LATCHOFF
HICCUP
RETRY
DELAY
INITIALIZATION
DELAY
LATCH-OFF
LOGIC
SLOPE
COMPENSATION
EN_SS
SOFT-START
DELAYAND
LOGIC
FSYNC
PLLCOMP
CLKOUT
VCO
PLL
FAULT
SLOPE
SS_DONE
3.47V
SS
TRACK
0.3V
VREF_TRK
ATRAK/
DTRK
ATRK/DTRK
112µA
ISEN1
VRAMP
1k
ISEN1
OC2_PEAK_PH1
PWM
COMPARATOR
VREF_2.5V
SS
LP
Filter
M
U
X
VREF_TRK
VREF_1.6V
VFB
+
+
+
-
OC1_PH1
+
Gm1
-
OC_NEG_PH1
105µA
80µA
-48µA
ZCD_PH1
FAULT
R1
VREF_CC(1.6V)
+
CLOCK
ISEN1
ISEN1
BOOT1
ISEN1
UG1
DCC
VIMON
Q
PWM CONTROL
S
PROGRAMMABLE
ADAPTIVE DEAD
TIME
PH1
PVCC
LG1
Gm2
DUPLICATE FOR EACH PHASE
-
IMON
R2
PGND
CMP_PD
1.1V
+
-
2V
+
CMP_OCAVG
÷8
OC_AVG
ISEN1
(PHASE1)
IOUT


÷8
PHASE DROP
CONTROL
17µA
FN8808.2
February 24, 2016
ISEN2
(PHASE2)
SGND
(BOTTOM PAD)
FIGURE 3. BLOCK DIAGRAM
PGND
RDT
RBLANK
DROP_PHASE2
PHASE_DROP
ISEN1N
112µA
2µA
FB
COMP
ISEN1P
CSA
EN_DE
EN_PHASE_DROP
DE MODE
AND PHASE DROP MODE
SELECTION
DE/PHDRP
ISL78227
SS
ISL78227
Typical Application - 2-Phase Synchronous Boost
RVCC
10 
VCC
CVCC
PVCC
PVCC
VCC
CPVCC
1µF
SGND
10µF
PGND
PVCC_BT
DBOOT1
VIN
VIN
EN_IC
EN
VOUT
BOOT1
CBOOT1
0.47µF
UG1
POWER-GOOD
RPVCCBT
5.1 
PGOOD
COUT
Q1
L1
RSEN1
PH1
VIN
1m 
VCC
RPG
TRACK
CSS
CPLL1
6.8nF
RBIAS1B
SS
CISEN1
220pF
ISEN1P
RSET1B
ISL78227
DBOOT2
BOOT2
RPLL
3.3k 
RBIAS1A
ISEN1N
CLKOUT
CLOCK_OUT
RSET1A
PVCC_BT
CBOOT2
0.47µF
PLLCOMP
UG2
CPLL2
1nF
CIN
Q2
LG1
COUT
Q3
L2
RSEN2
PH2
1m 
RFS
FSYNC
Q4
LG2
CIN
RSLOPE
SLOPE
RBIAS2B
RBIAS2A
ISEN2N
RBLANK
RBLANK
RDT
RDT
ISEN2P
IMON
CISEN2
220pF
RSET2B
CIMON
ATRK/DTRK
HIC/LATCH
VCC
DE/PHDRP
VCC
RSET2A
RFB2
RIMON
FB
CCP1
RCP
COMP
RFB1
CCP2
ATRK/DTRK:
= VCC to track analog signal
= GND to track digital signal
Q1, Q2, Q3, Q4: 2 BUK9Y6R0-60E in parallel
HIC/LATCH:
= VCC for HICCUP mode
= GND for LATCHOFF mode
DE/PHDRP:
= VCC for DE mode
= FLOAT for DE and Phase-Drop mode
= GND for CCM mode
FIGURE 4. TYPICAL APPLICATION 2-PHASE SYNCHRONOUS BOOST
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FN8808.2
February 24, 2016
ISL78227
Absolute Maximum Ratings
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +60V
PH1, PH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +60V
BOOT1, BOOT2, UG1, UG2 . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +65.0V
Upper Driver Supply Voltage, VBOOTx - VPHx . . . . . . . . . . . . - 0.3V to +6.5V
PVCC, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +6.5V
ISEN1P, ISEN1N, ISEN2P, ISEN2N . . . . . . . . . . . . . . . . . . . . . - 0.3V to +60V
VISENxP - VISENxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.6V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to VCC + 0.3V
ESD Rating
Human Body Model (Tested per AEC-Q100-002) . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per AEC-Q100-011). . . . . . . . . . . . . 750V
Latch-Up Rating (Tested per AEC-Q100-004) . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance
JA (°C/W) JC (°C/W)
32 Ld 5x5 WFQFN Package (Notes 4, 5). . .
30
1.2
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to +55V
PVCC, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.5V
PH1, PH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +55V
Upper Driver Supply Voltage, VBOOTx - VPHx . . . . . . . . . . . . . . . . 3.5V to 6V
ISEN1P to ISEN1N and ISEN2P to ISEN2N Differential Voltage . . . . ±0.3V
ISEN1P, ISEN1N, ISEN2P, ISEN2N Common-Mode Voltage . . . . 4V to 55V
Operational Junction Temperature Range (Automotive) . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless
otherwise noted: VIN = 12V, VPVCC = 5.2V and VVCC = 5.2V, TA = -40°C to +125°C (Note 7). Typicals are at TA = +25°C. Boldface limits apply across
the operating temperature range, -40°C to +125°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
55
V
SUPPLY INPUT
Input Voltage Range
VIN
Input Supply Current to the VIN Pin (IC Enabled)
Switching, under the condition of internal
LDO having dropout (VIN - PVCC) less than
0.25V
5
IQ_SW
EN = 5V, VIN = 12V, PVCC = VCC, BOOT1 and
BOOT2 supplied by PVCC, RFSYNC = 40.2k
(fSW= 300kHz), LGx = OPEN, UGx = OPEN
8.0
10.0
mA
IQ_NON-SW
EN = 5V, VIN = 12V, PVCC = VCC, BOOT1 and
BOOT2 supplied by PVCC, non-switching,
LGx = OPEN, UGx = OPEN
6.0
8.5
mA
EN = GND, VIN = 55V
0.2
1.0
µA
-1
0
1
µA
56.5
58.0
59.5
V
Input Supply Current to the VIN Pin (IC
Shutdown)
I_SD_VIN_55V
Input Bias Current (IC Shutdown) to Each of
ISEN1P/ISEN1N/ISEN2P/ISEN2N Pins
I_SD_ISENxP/N EN = GND, VIN = 55V
ISEN1P (or ISEN1N/ISEN2P/ISEN2N) = 55V
INPUT OVERVOLTAGE PROTECTION
VIN OVP Rising Threshold (Switching Disable)
EN = 5V, VIN rising
VIN OVP Trip Delay
EN = 5V, VIN rising
5
µs
INTERNAL LINEAR REGULATOR
LDO Voltage (PVCC pin)
VPVCC
LDO Saturation Dropout Voltage (PVCC pin)
LDO Current Limit (PVCC pin)
IOC_LDO
LDO Output Short Current Limit (PVCC pin)
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VDROPOUT
9
IOCFB_LDO
VIN = 6V to 55V, CPVCC = 4.7µF,
IPVCC = 10mA
5.0
VIN = 4.9V, CPVCC = 4.7µF, I_PVCC = 80mA
VIN = 6V, VPVCC = 4.5V
VIN = 6V, VPVCC = 0V
5.2
5.4
0.3
V
V
130
195
250
mA
50
100
160
mA
FN8808.2
February 24, 2016
ISL78227
Electrical Specifications
Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless
otherwise noted: VIN = 12V, VPVCC = 5.2V and VVCC = 5.2V, TA = -40°C to +125°C (Note 7). Typicals are at TA = +25°C. Boldface limits apply across
the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
POWER-ON RESET (For both PVCC and VCC)
Rising VVCC POR Threshold
VPORH_VCC
4.35
4.50
4.75
V
Falling VVCC POR Threshold
VPORL_VCC
4.05
4.15
4.25
V
VVCC POR Hysteresis
VPORHYS_VCC
Rising VPVCC POR Threshold
VPORH_PVCC
4.35
4.50
4.75
V
Falling VPVCC POR Threshold
VPORL_PVCC
3.0
3.2
3.4
V
VPVCC POR Hysteresis
0.4
VPORHYS_PVCC
Soft-Start Delay
tSS_DLY
From POR rising to initiation of soft-start.
RFSYNC = 61.9k, fSW = 200kHz, PLLCOMP
pin network of RPLL = 3.24k, CPLL1 = 6.8nF
and CPLL2 = 1nF
V
1.3
V
0.85
ms
EN
Enable Threshold
VENH
EN Rising
1.13
1.21
1.33
V
VENL
EN Falling
0.85
0.95
1.10
V
VEN_HYS
Hysteresis
Input Impedance
250
mV
2
6
MΩ
RFSYNC = 249kΩ (0.1%)
46.0
50.2
54.5
kHz
RFSYNC = 82.5kΩ (0.1%)
142
150
156
kHz
RFSYNC = 40.2kΩ (0.1%)
290
300
310
kHz
RFSYNC = 10kΩ (0.1%)
990
1100
1170
kHz
EN = 4V
PWM SWITCHING FREQUENCY
PWM Switching Frequency (per phase)
FOSC
Minimum Adjustable Switching Frequency
50
kHz
Maximum Adjustable Switching Frequency
1100
kHz
0.5
V
FSYNC Pin Voltage
Minimum ON-Time (Blanking Time) on LGx
Maximum Duty Cycle
tMINON_1
Minimum duty cycle, CUG = CLG = OPEN
RBLANK = 80kΩ (0.1%)
315
410
525
ns
tMINON_2
Minimum duty cycle, CUG = CLG = OPEN
RBLANK = 50kΩ (0.1%)
175
260
325
ns
tMINON_3
Minimum duty cycle, CUG = CLG = OPEN
RBLANK = 25kΩ (0.1%)
100
140
180
ns
tMINON_4
Minimum duty cycle, CUG = CLG = OPEN
RBLANK = 10k
75
90
105
ns
88.5
89.0
90.5
%
DMAX
DMAX = T_LG_ ON/tSW, VCOMP = 3.5V,
fSW = 300kHz, RDT = 18.2kΩ, CUG = OPEN,
CLG = OPEN
SYNCHRONIZATION (FSYNC PIN)
Minimum Synchronization Frequency at FSYNC
Input
Maximum Synchronization Frequency at
FSYNC Input
Input High Threshold
VIH
Input Low Threshold
VIL
Input Minimum Pulse Width - Rise-to-Fall
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10
50
kHz
1100
kHz
3.5
V
1.5
20
V
ns
FN8808.2
February 24, 2016
ISL78227
Electrical Specifications
Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless
otherwise noted: VIN = 12V, VPVCC = 5.2V and VVCC = 5.2V, TA = -40°C to +125°C (Note 7). Typicals are at TA = +25°C. Boldface limits apply across
the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
Input Minimum Pulse Width - Fall-to-Rise
MIN
(Note 6)
TYP
MAX
(Note 6)
20
UNIT
ns
Delay Time from Input Pulse Rising to LG1
Rising Edge Minus Dead Time tDT1
CLG = OPEN, RDT = 50kΩ
35
ns
Input Impedance
Input impedance before synchronization
mode
1
kΩ
200
MΩ
VCC - 0.1
V
Input impedance after synchronization mode
CLKOUT
CLKOUTH
ICLKOUT = 500µA
CLKOUTL
ICLKOUT = -500µA
Output Pulse Width
CCLKOUT = 100pF, tSW is each phase’s
switching period
Phase Shift from LG1 Rising Edge to CLKOUT
Pulse Rising Edge
CLG1 = OPEN, CCLKOUT = OPEN,
fSW = 300kHz, tDT1 = 60ns (Please refer to
Figure 56 on page 28 for the timing
diagram)
VCC 0.5
0.1
0.4
V
1/12 * tSW
87
°
SOFT-START
Soft-Start Current
4.5
ISS
5.0
5.5
µA
Minimum Soft-Start Prebias Voltage
0
V
Maximum Soft-Start Prebias Voltage
1.6
V
VFB = 500mV
Soft-Start Prebias Voltage Accuracy
Soft-Start Clamp Voltage
VSSCLAMP
-25
0
25
mV
3.25
3.47
3.70
V
HICCUP RETRY DELAY (Please refer to “Selectable Hiccup or Latch-Off Fault Response” on page 33 for details)
Hiccup Retry Delay
If Hiccup fault response selected
500
ms
REFERENCE VOLTAGE FOR OUTPUT VOLTAGE REGULATION
System Reference Accuracy
Measured at the FB pin
1.576
1.600
1.620
V
FB Pin Input Bias Current
VFB = 1.6V, TRACK = Open
-0.05
0.01
0.05
µA
ERROR AMPLIFIER FOR OUTPUT VOLTAGE REGULATION (Gm1)
Transconductance Gain
Output Impedance
Unity Gain Bandwidth
CCOMP = 100pF from COMP pin to GND
Slew Rate
CCOMP = 100pF from COMP pin to GND
Output Current Capability
Maximum Output Voltage
3.5
Minimum Output Voltage
2
mA/V
7.5
MΩ
3.3
MHz
±3
V/µs
±300
µA
3.7
V
0.1
0.3
V
PWM CORE
SLOPE Pin Voltage
SLOPE Accuracy
500
520
mV
-20
0
20
%
RSLOPE = 40.2k (0.1%)
-20
3
20
%
VRSENx = 30mV, RSETx = 665Ω (0.1%),
RSLOPE = 27k, fSW = 150kHz,
VCOMP = 2.52V, Measure
(Ton_lg2 - Ton_lg1)/(Ton_lg2 + Ton_lg1) *2
Duty Cycle Matching
Submit Document Feedback
480
RSLOPE = 20k (0.1%)
11
3
%
FN8808.2
February 24, 2016
ISL78227
Electrical Specifications
Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless
otherwise noted: VIN = 12V, VPVCC = 5.2V and VVCC = 5.2V, TA = -40°C to +125°C (Note 7). Typicals are at TA = +25°C. Boldface limits apply across
the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
CURRENT SENSE AMPLIFIER
Minimum ISENxN and ISENxP Common-Mode
Voltage Range
Accuracy becomes worse when lower than
4V
Maximum ISENxN and ISENxP Common-Mode
Voltage Range
4
V
55
V
±0.3
V
Maximum Input Differential Voltage Range
VISENxP VISENxN
ISENxP/ISENxN Bias Current
ISENxP/N_BIAS
Sourcing out of pin, EN = 5V,
VISENxN = VISENxP, VCM = 4V to 55V
100
123
150
µA
VZCD_CSA
Measures voltage threshold before RSEN at
CSA inputs (equivalent to the voltage across
the current sense shunt resistor),
RSET = 665Ω (0.1%)
-4.0
1.3
6.0
mV
VIMON Phase-Drop Falling Threshold, to Drop
Phase 2
VPHDRP_TH_F
When VIMON falls below VPHDRP_TH_F, drop
off Phase 2
1.0
1.1
1.2
V
VIMON Phase-Add Rising Threshold, to Add
Phase 2
VPHADD_TH_R
When VIMON rise above VPHADD_TH_R, add
back Phase 2
1.05
1.15
1.25
V
VIMON Phase-Drop Threshold Hysteresis
VPHDRP_HYS
When VIMON<VPHDRP_TH_F - VPHDrop_HYS,
Add back Phase 2
45
50
55
mV
Cycle-by-cycle current limit threshold
(IOC1_TH = 80µA, compared with ISENx).
Measures the voltage threshold before RSETx
at CSA Inputs (equivalent to the voltage
across the current sense shunt resistor),
RSETx = 665Ω (0.1%)
40
53
65
mV
ZCD DETECTION - CSA
Zero Crossing Detection (ZCD) Threshold
PHASE DROPPING
PEAK OVERCURRENT CYCLE-BY-CYCLE LIMITNG (OC1)
Peak Current Cycle-by-Cycle Limit Threshold for
Individual Phase
VOC1
CLG = OPEN, from the time VOC1 tripped to
LG falling.
Peak Current Cycle-by-Cycle Limit Trip Delay
50
ns
PEAK OVERCURRENT FAULT PROTECTION OC2_PEAK, (Refer to “Peak Overcurrent Fault (OC2_PEAK) Protection” on page 35 for details)
Peak Current Fault Protection Threshold for
Individual Phase
VOC2
Peak current hiccup protection threshold
(IOC2_TH = 105µA, compared with ISENx).
Measures the voltage threshold before RSETx
at CSA Inputs (equivalent to the voltage
across the current sense shunt resistor),
RSETx = 665Ω (0.1%)
OC2_PEAK Trip Blanking Time
55
70
85
mV
3
cycles
-32
mV
NEGATIVE CURRENT CYCLE-BY-CYCLE LIMITNG (OC_NEG)
Negative Current Cycle-by-Cycle Limit
Threshold for Individual Phase
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12
VOC_NEG
Negative Current Cycle-by-Cycle Limit
(IOC_NEG_TH = -48µA, compared with ISENx).
Measures the voltage threshold before RSETx
at CSA Inputs (equivalent to the voltage
across the current sense shunt resistor),
RSET = 665Ω (0.1%)
FN8808.2
February 24, 2016
ISL78227
Electrical Specifications
Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless
otherwise noted: VIN = 12V, VPVCC = 5.2V and VVCC = 5.2V, TA = -40°C to +125°C (Note 7). Typicals are at TA = +25°C. Boldface limits apply across
the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
27.0
28.3
29.5
µA
16
17
18
µA
1.575
1.600
1.625
V
AVERAGE CONSTANT CURRENT CONTROL LOOP
IMON Current Accuracy
VRSENx = 30mV, RSETx = 665Ω (0.1%), with
ISENxP/N pins biased at 4V or 55V
common-mode voltage
IMON Offset Current
VRSENx = 0V, RSET = 665Ω (0.1%), with
ISENxP/N pins biased at 4V or 55V
common-mode voltage
Constant Current Control Reference Accuracy
VREFCC
Measure the IMON pin
AVERAGE OVERCURRENT FAULT PROTECTION OC_AVG, (Refer to “Average Overcurrent Fault (OC_AVG) Protection” on page 36 for details)
OC_AVG Fault Threshold at the IMON Pin
1.9
OC_AVG Fault Trip Delay
2.0
2.1
V
1
µs
1.2
Ω
2
A
0.6
Ω
GATE DRIVERS
UG Source Resistance
RUG_SOURCE
100mA source current, VBOOT - VPH = 4.4V
UG Source Current
IUG_SOURCE
VUG - VPH = 2.5V, VBOOT - VPH = 4.4V
UG Sink Resistance
RUG_SINK
100mA sink current, VBOOT - VPH = 4.4V
IUG_SINK
VUG - VPH = 2.5V, VBOOT - VPH = 4.4V
2.0
A
LG Source Resistance
RLG_SOURCE
100mA source current, PVCC = 5.2V
1.2
Ω
LG Source Current
ILG_SOURCE
VLG - PGND = 2.5V, PVCC = 5.2V
2.0
A
LG Sink Resistance
RLG_SINK
100mA sink current, PVCC = 5.2V
0.55
Ω
LG Sink Current
ILG_SINK
VLG - PGND = 2.5V, PVCC = 5.2V
3
A
UG to PH Internal Resistor
50
kΩ
LG to PGND Internal Resistor
50
kΩ
UG Sink Current
BOOT-PH UVLO Detection Threshold
2.8
3.0
3.2
V
BOOT-PH UVLO Detection Threshold Hysteresis
0.09
0.15
0.22
V
70
85
ns
Dead Time Delay - UG Falling to LG Rising
tDT1
CUG = CLG = OPEN, RDT = 10k (0.1%)
55
Dead Time Delay - LG Falling to UG Rising
tDT2
CUG = CLG = OPEN, RDT = 10k (0.1%)
65
80
95
ns
Dead Time Delay - UG Falling to LG rising
tDT1
CUG = CLG = OPEN, RDT = 18.2kΩ (0.1%)
85
100
115
ns
Dead Time Delay - LG Falling to UG Rising
tDT2
CUG = CLG = OPEN, RDT = 18.2kΩ (0.1%)
95
110
125
ns
Dead Time Delay - UG Falling to LG Rising
tDT1
CUG = CLG = OPEN, RDT = 50kΩ (0.1%)
185
210
240
ns
Dead Time Delay - LG Falling to UG Rising
tDT2
CUG = CLG = OPEN, RDT = 50kΩ (0.1%)
205
230
260
ns
Dead Time Delay - UG Falling to LG Rising
tDT1
CUG = CLG = OPEN, RDT = 64.9kΩ (0.1%)
235
265
295
ns
Dead Time Delay - LG Falling to UG Rising
tDT2
CUG = CLG = OPEN, RDT = 64.9kΩ (0.1%)
260
290
320
ns
OUTPUT OVERVOLTAGE DETECTION/PROTECTION MONITOR THE FB PIN, (Refer to “Output Overvoltage Fault Protection” on page 34 for details)
FB Overvoltage Rising Trip Threshold
VFBOV_RISE
Percentage of VREF_1.6V
(Selectable Hiccup/Latch-off response)
118
120
122
%
FB Overvoltage Falling Recovery Threshold
VFBOV_FALL
Percentage of VREF_1.6V
(Selectable Hiccup/Latch-off response)
114
116
118
%
Overvoltage Threshold Hysteresis
4
%
FB Overvoltage Trip Delay
1
µs
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FN8808.2
February 24, 2016
ISL78227
Electrical Specifications
Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless
otherwise noted: VIN = 12V, VPVCC = 5.2V and VVCC = 5.2V, TA = -40°C to +125°C (Note 7). Typicals are at TA = +25°C. Boldface limits apply across
the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
OUTPUT UNDERVOLTAGE DETECTION (MONITOR THE FB PIN, (Refer to “Output Undervoltage Indication” on page 34 for details)
Undervoltage Falling Trip Threshold
VFBUVREF_FALL Percentage of VREF_1.6V
78
80
82
%
Undervoltage Rising Recovery Threshold
VFBUVREF_RISE Percentage of VREF_1.6V
82.5
84.0
86.5
%
Undervoltage Threshold Hysteresis
4
%
POWER-GOOD MONITOR (PGOOD PIN)
PGOOD Leakage Current
PGOOD HIGH, VPGOOD = 5V
1
PGOOD Low Voltage
PGOOD LOW, IPGOOD = 0.5mA
0.06
PGOOD Rising Delay (DE mode)
The PGOOD rising delay from
VSSPIN = VSSPCLAMP (3.47V) and
VREF_TRK ≥ 0.3V to PGOOD HIGH when DE
mode is selected (DE/PHDRP = VCC or
FLOAT)
0.5
ms
PGOOD Rising Delay (CCM mode)
The PGOOD rising delay from
VSSPIN = VSSPCLAMP (3.47V) and
VREF_TRK ≥ 0.3V to PGOOD HIGH when CCM
mode is selected (DE/PHDRP = GND)
100
ms
10
µs
PGOOD Falling Blanking Time
0.40
µA
V
HIC/LATCH, ATRK/DTRK PIN DIGITAL LOGIC INPUT
Input Leakage Current
EN <1V
-1
Input Pull Down Current
EN >2V, Pin Voltage = 2.1V
0.7
1.0
Logic Input Low
Logic Input High
1
µA
2.0
µA
0.8
V
2.1
V
DE/PHDRP PIN DIGITAL LOGIC INPUT (HIGH/LOW/FLOAT)
Input Leakage Current
-1
1
µA
FLOAT Impedance - PIN to VCC
PIN = GND
100
200
300
kΩ
FLOAT Impedance - PIN to GND
PIN = VCC
100
200
300
kΩ
Output Voltage on FLOAT Pin
PIN = FLOAT
2.1
2.6
2.7
V
3
V
Tri-State Input Voltage MAX
Tri-State Input Voltage MIN
1.8
Logic Input Low
PIN voltage falling
Logic Input High
PIN voltage rising
V
0.7
VCC 0.4
V
V
TRACK PIN - DIGITAL INPUT LOGIC
Input Leakage Current
EN <1V, pin voltage = 5V, VCC = 0V
-1
Input Pull-Up Current
EN >2V, pin voltage = 0V, VCC = 5V
0.8
Input Pull-Up Current Compliance Voltage
EN >2V, pin open
Logic Input Low
PIN voltage falling
Logic Input High
PIN voltage rising
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1.1
1
µA
1.5
µA
0.8
V
2.5
2
V
V
FN8808.2
February 24, 2016
ISL78227
Electrical Specifications
Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless
otherwise noted: VIN = 12V, VPVCC = 5.2V and VVCC = 5.2V, TA = -40°C to +125°C (Note 7). Typicals are at TA = +25°C. Boldface limits apply across
the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
Duty Cycle Conversion (FB accuracy)
MIN
(Note 6)
TYP
25% duty cycle input, frequency = 400kHz,
measure at the FB pin
0.600
0.625
0.650
V
50% duty cycle input, frequency = 400kHz,
measure at the FB pin
1.218
1.253
1.288
V
60% duty cycle input, measure at the FB pin
1.45
1.49
1.53
V
V TRACK = 1.6V, leakage current into this pin
to ground
-1.0
-0.6
-0.3
µA
1.6
V
4.0
%
TEST CONDITIONS
0% duty cycle input, measure at the FB pin
MAX
(Note 6)
0
UNIT
V
TRACK PIN - ANALOG INPUT
Input Leakage Current
TRACK Input Reference Voltage Range
TRACK Input Reference Voltage Accuracy
0
Measure at the FB pin, V TRACK = 1.5V
Measure at the FB pin, V TRACK = 0.5V
TRACK SS_DONE Detection Threshold
-4.0
-0.5
-6.0
1.8
6.0
%
0.29
0.30
0.31
V
OVER-TEMPERATURE PROTECTION
Over-Temperature Trip Point
160
°C
Over-Temperature Recovery Threshold
145
°C
NOTES:
6. Compliance to datasheet limits are assured by one or more methods: production test, characterization and/or design.
7. The IC is tested in conditions with minimum power dissipations in the IC meaning TA ≈ TJ.
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FN8808.2
February 24, 2016
ISL78227
Performance Curves
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V,
VOUT = 36V and TA = +25°C.
VOUT 1.0V/DIV WITH 36V OFFSET
100
95
EFFICIENCY (%)
90
IL1 5.0A/DIV
85
80
DE WITH PHASE DROP
75
PH1 30.0V/DIV
DE WITHOUT PHASE DROP
70
65
CCM
60
55
50
0.01
SS 3.0V/DIV
0.10
1.00
10.00
100.00
NOTE: (See Typical Application
in Figure
4 on page
LOAD
CURRENT
(A) 8.)
FIGURE 5. EFFICIENCY vs LOAD, 2-PHASE BOOST, 3 MODES
OPERATION, fSW = 200kHz, VIN = 12V, VOUT = 36V,
TA = +25°C
10ms/DIV
FIGURE 6. EN INTO PREBIASED OUTPUT, CCM MODE
(DE/PHDRP = GND), IOUT = 0A
PVCC 2.0V/DIV
VOUT 20.0V/DIV
PLLCOMP 500mV/DIV
PGOOD 5.0V/DIV
SS 700mV/DIV
PH1 30.0V/DIV
SS 3.0V/DIV
PH1 30.0V/DIV
500µs/DIV
20ms/DIV
FIGURE 7. EN ON AND INITIALIZATION TO START-UP, IOUT = 0A
FIGURE 8. SOFT-START, CCM MODE (DE/PHDRP = GND), IOUT = 8A
VOUT 20.0V/DIV
PLLCOMP 500mV/DIV
PGOOD 5.0V/DIV
CLKOUT 5.0V/DIV
PH1 30.0V/DIV
SS 2.0V/DIV
PVCC 2.0V/DIV
SS 3.0V/DIV
200µs/DIV
FIGURE 9. EN ON AND INITIALIZATION TO START-UP, IOUT = 0A
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5ms/DIV
FIGURE 10. SOFT-START, DE+PHDROP MODE (DE/PHDRP = FLOAT),
IOUT = 8A
FN8808.2
February 24, 2016
ISL78227
Performance Curves
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V,
VOUT = 36V and TA = +25°C. (Continued)
VOUT 20.0V/DIV
PVCC 2.0V/DIV
PGOOD 5.0V/DIV
PGOOD 3.0V/DIV
PH1 30.0V/DIV
SS 2.0V/DIV
SS 3.0V/DIV
PH1 30.0V/DIV
5ms/DIV
20ms/DIV
FIGURE 11. SOFT-START, DE MODE (DE/PHDRP = VCC), IOUT = 8A
FIGURE 12. EN SHUTDOWN, PVCC/PGOOD/SS FALL, IOUT = 0A
PGOOD 5.0V/DIV
IL1 4.0A/DIV
VOUT 20.0V/DIV
LG2 5.0V/DIV
LG1 5.0V/DIV
PH1 40.0V/DIV
PH2 40.0V/DIV
20µs/DIV
VOUT 30.0V/DIV
10µs/DIV
FIGURE 13. EN SHUTDOWN, IOUT = 8A
FIGURE 14. CCM MODE (DE/PHDRP = GND), PHASE 1 INDUCTOR
RIPPLE CURRENT, IOUT = 0A
IL2 4.0A/DIV
PGOOD 4.0V/DIV
VOUT 20.0V/DIV
LG2 5.0V/DIV
PH2 30.0V/DIV
LG1 5.0V/DIV
PH1 30.0V/DIV
VOUT 30.0V/DIV
5ms/DIV
10µs/DIV
FIGURE 15. EN SHUTDOWN, IOUT = 8A
FIGURE 16. CCM MODE (DE/PHDRP = GND), PHASE 2 INDUCTOR
RIPPLE CURRENT, IOUT = 0A
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FN8808.2
February 24, 2016
ISL78227
Performance Curves
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V,
VOUT = 36V and TA = +25°C. (Continued)
VOUT 10.0V/DIV
PGOOD 4.0V/DIV
VOUT 1.0V/DIV WITH 36V OFFSET
PH2 20.0V/DIV
PH2 30.0V/DIV
PH1 20.0V/DIV
PH1 30.0V/DIV
2µs/DIV
5µs/DIV
FIGURE 17. DE MODE (DE/PHDRP = VCC), DIODE EMULATION
OPERATION, PULSE SKIPPING, IOUT = 0A
VOUT 10.0V/DIV
PH2 30.0V/DIV
FIGURE 18. DE MODE (DE/PHDRP = VCC), DIODE EMULATION
OPERATION, IOUT = 29mA
VOUT 10.0V/DIV
PH1 30.0V/DIV
PH2 30.0V/DIV
PH1 30.0V/DIV
10µs/DIV
FIGURE 19. DE MODE (DE/PHDRP = VCC), PH1 AND PH2 DIODE
EMULATION OPERATION, PULSE SKIPPING, IOUT = 7mA
2µs/DIV
FIGURE 20. DE+PH_DROP MODE (DE/PHDRP = FLOAT), PH1 DIODE
EMULATION WITH PH2 DROPPED, IOUT = 29mA
VOUT 10.0V/DIV
IMON 300mV/DIV
I_LOAD 5.0A/DIV
PH1 30.0V/DIV
PH1 30.0V/DIV
PH2 30.0V/DIV
PH2 30.0V/DIV
10µs/DIV
10ms/DIV
FIGURE 21. DE+PHDRP MODE (DE/PHDRP = FLOAT), PH1 DIODE
EMULATION WITH PH2 DROPPED, IOUT = 7mA
FIGURE 22. DE+PHDRP MODE (DE/PHDRP = FLOAT), PH2 ADDED
AND DROPPED, UNDER TRANSIENT STEP LOAD OF 1A
TO 8A
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FN8808.2
February 24, 2016
ISL78227
Performance Curves
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V,
VOUT = 36V and TA = +25°C. (Continued)
FB 300mV/DIV
FB 300mV/DIV
VOUT 6.8V/DIV
VOUT 6.8V/DIV
TRACK 300mV/DIV
TRACK 300mV/DIV
PH1 20.0V/DIV
PH1 20.0V/DIV
2ms/DIV
2ms/DIV
FIGURE 23. ANALOG TRACKING 100Hz SINUSOIDAL SIGNAL, CCM
MODE (DE/PHDRP = GND), ATRK/DTRAK = VCC,
IOUT = 1A
FIGURE 24. ANALOG TRACKING 300Hz SINUSOIDAL SIGNAL AT THE
TRACK PIN, CCM MODE (DE/PHDRP = GND),
ATRK/DTRAK = VCC, IOUT = 1A
TRACK 4.0V/DIV
IMON 500mV/DIV
I_IN 16A/DIV
VOUT 7.0V/DIV
PH1 30.0V/DIV
PH2 40.0V/DIV
VOUT 30.0V/DIV
PH1 40.0V/DIV
1µs/DIV
50µs/DIV
FIGURE 25. STEADY-STATE OPERATION OF INPUT CONSTANT
CURRENT MODE, IIN CONTROLLED AT 43A CONSTANT,
VOUT = 19.5V
FIGURE 26. DIGITAL TRACKING (TRACKING SIGNAL,
FREQUENCY = 400kHz, D = 0.5, VOUT = 28.3V
TRACK 4.0V/DIV
IMON 500mV/DIV
I_IN 16A/DIV
VOUT 7.0V/DIV
PH1 30.0V/DIV
PH2 40.0V/DIV
VOUT 30.0V/DIV
1s/DIV
FIGURE 27. LOAD CURRENT KEEP INCREASING FROM NO LOAD TO
OVERLOAD (25A), VOUT STARTS TO DROP WHEN INPUT
CONSTANT CURRENT MODE STARTS TO WORK, INPUT
CURRENT IS FINALLY CONTROLLED TO BE CONSTANT
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PH1 40.0V/DIV
1µs/DIV
FIGURE 28. DIGITAL TRACKING (TRACKING SIGNAL,
FREQUENCY = 400kHz, D = 0.3), VOUT = 17V
FN8808.2
February 24, 2016
ISL78227
Performance Curves
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V,
VOUT = 36V and TA = +25°C. (Continued)
TRACK 4.0V/DIV
VOUT 2.0V/DIV WITH 36V OFFSET
VOUT 1.0V/DIV WITH 28V OFFSET
I_LOAD 5.0A/DIV
PH2 40.0V/DIV
PH1 30.0V/DIV
PH2 30.0V/DIV
PH1 40.0V/DIV
10µs/DIV
10ms/DIV
FIGURE 29. DIGITAL TRACKING, (TRACKING SIGNAL,
FREQUENCY = 200kHz, D = 0.5), VOUT = 28.3V
FIGURE 30. DE MODE (DE/PHDRP = VCC), TRANSIENT RESPONSE,
IOUT = 0.03A TO 8A STEP LOAD
VOUT 1.0V/DIV WITH 36V OFFSET
VOUT 1.0V/DIV WITH 36V OFFSET
I_LOAD 5.0A/DIV
I_LOAD 5.0A/DIV
PH1 30.0V/DIV
PH2 30.0V/DIV
PH1 30.0V/DIV
PH2 30.0V/DIV
5ms/DIV
1ms/DIV
FIGURE 31. CCM MODE (DE/PHDRP = GND), TRANSIENT RESPONSE,
IOUT = 0A TO 8A STEP LOAD
FIGURE 32. DE+PH_DROP MODE (DE/PHDRP = FLOAT), TRANSIENT
RESPONSE, IOUT = 1A TO 8A STEP LOAD
0.5
10
9
0.4
8
Iq_SW (mA)
I_SD_VIN (µA)
7
0.3
0.2
6
5
4
3
0.1
2
1
0.0
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
FIGURE 33. SHUTDOWN CURRENT AT THE VIN PIN I_SD vs
TEMPERATURE, VIN = 55V
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20
150
0
-50
-25
0
25
50
75
100
125
150
TEMPERATURE (°C)
FIGURE 34. IC OPERATIONAL QUIESCENT CURRENT vs
TEMPERATURE, IC SWITCHING, NO LOAD ON LGX AND
UGX
FN8808.2
February 24, 2016
ISL78227
Performance Curves
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V,
VOUT = 36V and TA = +25°C. (Continued)
10
VREF_CC SYSTEM ACCURACY (V)
9
Iq_NON-SW (mA)
8
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
100
125
150
1.610
1.609
1.608
1.607
1.606
1.605
1.604
1.603
1.602
1.601
1.600
1.599
1.598
1.597
1.596
1.595
1.594
1.593
1.592
1.591
1.590
-50
-25
0
TEMPERATURE (°C)
VREF_1.6V SYSTEM ACCURACY (V)
29.0
IMON CURRENT (µA)
28.5
28.0
VIN = 4V
VIN = 55V
27.0
26.5
26.0
-50
-25
0
25
50
75
100
125
-50
150
IOCFB_LDO, IOC_LDO (mV)
VDROPOUT_LDO (V)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
25
50
75
100
125
150
TEMPERATURE (°C)
FIGURE 39. INTERNAL LDO DROPOUT VOLTAGE vs TEMPERATURE,
80mA LOAD CURRENT ON LDO OUTPUT (PVCC)
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125
150
-25
0
25
50
75
100
125
150
FIGURE 38. VREF_1.6V SYSTEM ACCURACY vs TEMPERATURE,
MEASURED AT THE FB PIN
1.0
0
100
TEMPERATURE (°C)
FIGURE 37. IMON OUTPUT CURRENT ACCURACY
(CURRENT-SENSING SIGNAL OUTPUT) vs
TEMPERATURE, VRSENx = 30mV, RSETx = 665Ω (0.1%)
-25
75
1.610
1.609
1.608
1.607
1.606
1.605
1.604
1.603
1.602
1.601
1.600
1.599
1.598
1.597
1.596
1.595
1.594
1.593
1.592
1.591
1.590
TEMPERATURE (°C)
-50
50
FIGURE 36. VREF_CC SYSTEM ACCURACY vs TEMPERATURE,
MEASURED AT THE IMON PIN, VREF_CC = 1.6V
FIGURE 35. IC OPERATIONAL QUIESCENT CURRENT vs
TEMPERATURE, IC NOT SWITCHING
27.5
25
TEMPERATURE (°C)
220
210
200
190
180
170
160
150
140
130
120
110
100
90
80
70
60
50
IO C_LDO (mA)
IOCFB_LD O (mA)
-50
-25
0
25
50
75
100
125
150
TEMPERATURE (°C)
FIGURE 40. INTERNAL LDO OVERCURRENT THRESHOLD AND ITS
FOLDBACK OVERCURRENT THRESHOLD vs
TEMPERATURE
FN8808.2
February 24, 2016
ISL78227
Performance Curves
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V,
VOUT = 36V and TA = +25°C. (Continued)
4.6
VPORH_PVCC, VPORH_VCC (V)
60
VIN_OV_RISE (V)
59
58
57
56
4.5
4.4
4.3
55
-50
-25
0
25
50
75
100
125
4.2
150
-50
-25
0
TEMPERATURE (°C)
VPORL_PVCC, VPORL_VCC (V)
60
55
VOC1 (mV)
50
45
40
35
30
-25
0
25
50
75
TEMPERATURE (°C)
1 00
125
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
100
125
150
VPORL_PVCC (V)
VPORL_VCC (V)
-50
150
-25
0
25
50
75
100
125
150
TEMPERATURE (°C)
FIGURE 43. OC1 VOLTAGE THRESHOLD (ACROSS RSEN) vs
TEMPERATURE
FIGURE 44. PVCC/VCC POR FALLING THRESHOLD vs TEMPERATURE
1.5
3
ANALOG TRACK REFERENCE
SYSTEM ACCURACY_1.5V (%)
ANALOG TRACK REFERENCE
SYSTEME ACCURACY_0.5V (%)
25
50
75
TEMPERATURE (°C)
FIGURE 42. PVCC/VCC POR RISING THRESHOLD vs TEMPERATURE
FIGURE 41. VIN OV RISING THRESHOLD vs TEMPERATURE
-50
VPORH_PVCC (V)
VPOR H_VCC (V)
1.3
1.1
0.9
0.7
0.5
-50
-25
0
25
50
75
1 00
125
150
TEMPERATURE (°C)
FIGURE 45. ANALOG TRACKING REFERENCE SYSTEM ACCURACY vs
TEMPERATURE, MEASURED AT THE FB PIN,
V TRACK = 0.5V
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2
1
0
-1
-2
-3
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
150
FIGURE 46. ANALOG TRACKING REFERENCE SYSTEM ACCURACY vs
TEMPERATURE, MEASURED AT THE FB PIN,
V TRACK = 1.5V
FN8808.2
February 24, 2016
ISL78227
Performance Curves
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V,
1.265
100
1.263
90
1.261
80
1.259
70
DEAD TIME (ns)
DIGITAL TRACK REFERENCE
SYSTEM ACCURACY (V)
VOUT = 36V and TA = +25°C. (Continued)
1.257
1.255
1.253
tDT2
60
tDT1
50
40
1.251
30
1.249
20
1.247
10
0
1.245
-50
-25
0
25
50
75
100
125
-50
150
-25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 48. GATE DRIVE DEAD TIME vs TEMPERATURE, RDT = 10k,
tDT1 REFERS TO UG FALLING TO LG RISING, tDT2
REFERS TO LG FALLING TO UG RISING
FIGURE 47. DIGITAL TRACKING REFERENCE SYSTEM ACCURACY vs
TEMPERATURE, MEASURED AT THE FB PIN, DUTY
CYCLE OF TRACK PIN SIGNAL IS 0.5
150
140
DEAD TIME (ns)
130
120
tDT2
110
100
90
tDT1
80
70
60
50
-50
-25
0
25
50
75
100
125
150
TEMPERATURE (°C)
FIGURE 49. GATE DRIVE DEAD TIME vs TEMPERATURE, RDT = 18.2k, tDT1 REFERS TO UG FALLING TO LG RISING, tDT2 REFERS TO LG FALLING TO
UG RISING
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FN8808.2
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ISL78227
Operation Description
DRIVER CONFIGURATION
The ISL78227 is a 2-phase synchronous boost controller with
integrated drivers. It supports wide input and output ranges of 5V
to 55V during normal operation and the VIN pin withstands
transients up to 60V.
The ISL78227 is integrated with 2A sourcing/3A sinking strong
drivers to support high efficiency and high current synchronous
boost applications. The drivers have a unique feature of adaptive
dead time control of which the dead time can be programmed
for different external MOSFETs, achieving both optimized
efficiency and reliable MOSFET driving. The ISL78227 has
selectable diode emulation and phase dropping functions for
enhanced light-load efficiency.
The PWM modulation method is a constant frequency Peak
Current Mode Control (PCMC), which have benefits of input
voltage feed-forward, a simpler loop to compensate compared to
voltage mode control and inherent current sharing capability.
The ISL78227 offers a track function with unique features of
accepting either digital or analog signals for the user to adjust
reference voltage externally. The digital signal track function
greatly reduces the complexity of the interface circuits between
the central control unit and the boost regulator. Equipped with
cycle-by-cycle positive and negative current limiting, the track
function can be reliably facilitated to achieve an envelope
tracking feature in audio amplifier applications, which can
significantly improve system efficiency.
In addition to the cycle-by-cycle current limiting, the ISL78227 is
implemented with a dedicated average Constant Current (CC)
control loop for input current. For devices having only peak
current limiting, the average current under peak current limiting
varies quite largely because the inductor ripple varies with
changes of VIN and VOUT and tolerances of fSW and inductors.
The ISL78227’s unique CC control feature is able to have the
average input current accurately controlled to be constant
without shutdown. Under certain constant input voltage, this
means constant power limiting, which is especially useful for the
boost converter. It helps the user optimize the system with the
power devices’ capability fully utilized by well controlled constant
input power.
Details of the functions are described in the following sections.
Synchronous Boost
In order to improve efficiency, the ISL78227 employs
synchronous boost architecture as shown in Figure 4 on page 8.
The UGx output drives the high-side synchronous MOSFET, which
replaces the freewheeling diode and reduces the power losses
due to the voltage drop of the freewheeling diode.
As shown in Figure 4 on page 8, the upper side UGx drivers are
biased by the CBOOTx voltage between BOOTx and PHx (where “x”
indicates the specific phase number and same note applied
throughout this document). CBOOTx is charged by a charge pump
mechanism. PVCC charges BOOTx through the Schottky diode
DBOOTx when LGx is high pulling PHx low. BOOTx rises with PHx
and maintains the voltage to drive UGx as the DBOOTx is reverse
biased.
At start-up, the charging to CBOOTx from 0 to ~4.5V will cause
PVCC to dip a little. So a typical 5.1Ω resistor RPVCCBT is
recommended between PVCC and DBOOTx to prevent PVCC from
falling below VPORL_PVCC. The typical value for CBOOTx is
0.47µF.
The BOOTx to PHx voltage is monitored by UVLO circuits. When
BOOTx to PHx falls below a 3V threshold, the UGx output is
disabled. When BOOTx to PHx rises back to be above this
threshold plus 150mV hysteresis, the high-side driver output is
enabled.
For standard boost application when upper side drivers are not
needed, both UG1 and UG2 can be disabled by connecting either
BOOT1 or BOOT2 to ground before part start-up initialization. PHx
should be connected to ground.
PROGRAMMABLE ADAPTIVE DEAD TIME CONTROL
The UGx and LGx drivers are designed to have an adaptive dead
time algorithm that optimizes operation with varying operating
conditions. In this algorithm, the device detects the off timing of
LGx (UGx) voltages before turning on UGx (LGx).
In addition to the adaptive dead time control, the dead time
between UGx ON and LGx ON can be programmed by the resistor
at the RDT pin. The typical range of programmable dead time is
55ns to 200ns, or larger. This is intended for different external
MOSFETs applications to adjust the dead time, maximizing the
efficiency while at the same time preventing shoot-through.
Refer to Figure 50 on page 25 for the selection of the RDT
resistor and dead time, where tDT1 refers to the dead time
between UG Falling to LG rising, and tDT2 refers to the dead time
between LG Falling to UG rising. The dead time is smaller with a
lower value RDT resistor, and it’s clamped to minimum 57ns
when RDT is shorted to ground. Since a current as large as 4mA
will be pulled from the RDT pin if the RDT pin is shorted to
ground, it is recommended to use 5kΩ as the smallest value for
the RDT resistor where the current drawing from the RDT pin is
0.5V/5kΩ = 100µA.
While the boost converter is operating in steady state Continuous
Conduction Mode (CCM), with each phase’s low-side MOSFET
controlled to turn on with duty cycle D and ideally the upper
MOSFET will be ON for (1-D). Equation 1 shows the input to
output voltage DC transfer function for boost is:
V IN
V OUT = ------------1–D
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(EQ. 1)
24
FN8808.2
February 24, 2016
ISL78227
Digital/Analog Track Function
300
The TRACK input provides an external reference voltage to be
applied for the output voltage loop to follow, which is useful if the
user wants to change the output voltage as required. An example
is to employ envelope tracking technology in audio power
amplifier applications. The ISL78227 boost stage output is
powering the audio power amplifier stage input, where the boost
output tracks the music envelope signal applied at the TRACK
pin. Ultimately, higher system efficiency can be achieved.
DEAD TIME, tDTx (ns)
250
tDT2
200
150
tDT1
100
50
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
RD T (k)
FIGURE 50. DEAD TIME vs RDT, tDT1 REFERS TO UG FALLING TO LG
RISING, tDT2 REFERS TO LG FALLING TO UG RISING
PWM Control
The ISL78227 uses fixed frequency peak current mode control
architecture. As shown in Figure 3 on page 7 and the typical
schematic diagram, error amplifier (Gm1) compares the FB pin
voltage and reference voltage and generates a voltage loop error
signal at the COMP pin. This error signal is compared with the
current ramp signal (VRAMP) by the PWM comparator. The PWM
comparator output combined with fixed frequency clock signal
controls the SR flip-flop to generate the PWM signals (Refer to
“Peak Current Mode Control” on page 26).
OUTPUT VOLTAGE REGULATION LOOP
The resistor divider RFB2 and RFB1 from VOUT to FB (Figure 4 on
page 8) can be selected to set the desired VOUT. VOUT can be
calculated by Equation 2.
R FB2

V OUT = V REF   1 + ---------------
R FB1

(EQ. 2)
Where in normal operation after soft-start, VREF can be either
VREF_1.6V or VREF_TRK whichever is lower.
There are 3 inputs for the reference voltage for Gm1: soft-start
ramp SS, VREF_TRK and VREF_1.6V. The Gm1 uses the lowest
value among SS, VREF_TRK and VREF_1.6V. SS, VREF_TRK and
VREF_1.6V are valid for Gm1 during and after soft-start. In
general application, VREF_TRK is normally HIGH before soft-start
and SS normally ramps up from a voltage lower than VREF_TRK
and VREF_1.6V, in which case SS controls the output voltage
ramp-up during soft-start. After soft-start is complete, the user
can adjust VREF_TRK for the desired voltage. Since VREF_TRK is
valid before soft-start, to set VREF_TRK to be lower than SS can
make the SS ramp ineffective since Gm1 uses the lower
VREF_TRK voltage. In such a case, the VREF_TRK becomes the
real soft-start ramp that controls the output voltage ramp-up.
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25
The TRACK pin can accept either a digital signal or an analog
signal by configuring the ATRK/DTRK pin to be connected to
ground or VCC. Figure 51 on page 26 shows the track function
block diagram. VREF_TRK is fed into Gm1 as one of the
reference voltages. The Gm1 takes the lowest voltage of SS,
VREF_TRK and VREF_1.6V as the actual reference. When
VREF_TRK is the lowest voltage, it becomes the actual reference
voltage for Gm1 and the output voltage can be adjusted with
TRACK signal changes. Regarding the effective VREF_TRK range:
• There is no limit for the minimum voltage on the TRACK pin,
but note the lower reference voltage and the lower voltage
feedback regulation accuracy. Note the SS_DONE signal is
checking VREF_TRK ≥0.3V as one of the conditions (refer to
Figure 58 on page 29 and t8-t9 description on page 30). Also,
for the boost converter, the regulated output minimum voltage
is usually the input voltage minus the upper MOSFET’s body
diode drop, in which case, the corresponding voltage at FB
voltage is the minimum effective voltage for the VREF_TRK.
• The Gm1 takes the lowest voltage of SS, VREF_TRK and
VREF_1.6V as the actual reference. The maximum effective
range for VREF_TRK is determined by VREF_1.6V or SS signal,
whichever is lower. For example, after soft-start, when the SS
pin equals to 3.47V (typical), the maximum effective voltage
for VREF_TRK is 1.6V (VREF_1.6V).
When ATRK/DTRK = GND (DTRK mode), the TRACK pin accepts
digital signal inputs. VREF_TRK (as one of the references input
for the error amplifier Gm1) equals to the average duty cycle
value of the PWM signal’s at the TRACK pin. As shown in
Figure 51 on page 26, the MUX is controlled by the ATRK/DTRK
pin configurations. When ATRK/DTRK = GND, the MUX connects
the output of the Q1 and Q2 switch bridge to the input of a
2-stage RC filter (R1, C1, R2 and C2). The PWM signal at the
TRACK pin controls Q1 and Q2 to chop the 2.5V internal
reference voltage. The phase node of Q1 and Q2 is a PWM signal
with accurate 2.5V amplitude and duty cycle D, where D is the
input PWM duty cycle on the TRACK input pin. The RC filter
smooths out the PWM AC components and the voltage
VREF_TRK after the RC filter becomes a DC voltage equal to
2.5V*D:
V REFTRK = 2.5  D
(EQ. 3)
According to Equation 3, the PWM signals’ amplitude at the TRACK
pin doesn’t affect the VREF_TRK accuracy and only the duty cycle
value changes the VREF_TRK value. In general, the VREF_TRK
reference accuracy is as good as the 2.5V reference. The built-in low
pass filter (R1, C1, R2 and C2) converts the PWM signal’s duty cycle
value to a low noise reference. The low pass filter has cutoff
frequency of 1.75kHz and a gain of -40dB at 400kHz. The 2.5V
FN8808.2
February 24, 2016
ISL78227
PEAK CURRENT MODE CONTROL
PWM signal at phase node of Q1 and Q2 will have around 25mV at
VREF_TRK, which is 1.56% of 1.6V reference. This will not affect the
boost output voltage because of the limited bandwidth of the
system. 400kHz frequency is recommended for the PWM signal at
the TRACK pin. Lower frequency at the TRACK input is possible, but
VREF_TRK will have higher AC ripple. Bench test evaluation is
needed to make sure the output voltage is not affected by this
VREF_TRK AC ripple.
As shown in the Figure 3 on page 7, each phase’s PWM
operation is initialized by the fixed clock for this phase from the
oscillator (refer to “Oscillator and Synchronization” on page 28).
The clocks for Phase 1 and Phase 2 are 180° out-of-phase. The
low-side MOSFET is turned on (LGx) by the clock (after dead time
delay of tDT1) at the beginning of a PWM cycle and the inductor
current ramps up. The ISL78227’s Current Sense Amplifiers
(CSA) sense each phase inductor current and generates the
current sense signal ISENx. The ISENx is added with the
compensating slope and generates VRAMPx. When VRAMPx
reaches the error amplifier (Gm1) output voltage, the PWM
comparator is triggered and LGx is turned off to shut down the
low-side MOSFET. The low-side MOSFET stays off until the next
clock signal comes for the next cycle.
When ATRK/DTRK = VCC (ATRK mode), the MUX connects the
TRACK pin voltage to the input of the 2-stage RC filter
R1/C1/R2/C2. The TRACK pin accepts analog signal inputs, with the
Gm1’s VREF_TRK input equal to the voltage on the TRACK pin. The
low pass filter has the same cutoff frequency of 1.75kHz.
If not used, the TRACK pin should be left floating or tied to VCC
and the internal VREF_1.6V is working as the reference.
After the low-side MOSFET is turned off, the high-side MOSFET
turns on after dead time tDT2. The turn-off time of the high-side
MOSFET is determined by either the PWM turn-on time at the
next PWM cycle or when the inductor current become zero if the
Diode Emulation mode is selected.
The TRACK function is enabled before the SS pin soft-start. The
VOUT reference can be controlled by TRACK inputs at start-up.
After the SS pin ramps up to the upper clamp AND the VREF_TRK
reaches 0.3V, the upper side FET is controlled to turn on
gradually to achieve smooth transitions from DCM mode to CCM
mode, of which transition duration is 100ms (when set at CCM
mode). After this transition, PGOOD is allowed to be pulled HIGH
as long as when output voltage is in regulation (within OV/UV
threshold).
Multiphase Power Conversion
For an n-phase interleaved multiphase boost converter, the PWM
switching of each phase is distributed evenly with 360°/n phase
shift. The total combined current ripples at the input and output
are reduced where smaller input and output capacitors can be
used. In addition, it is beneficial to have a smaller equivalent
inductor for a faster loop design. Also in some applications,
especially in a high current case, multiphase makes it possible to
use a smaller inductor for each phase rather than one big
inductor (single-phase), which is sometimes more costly or
unavailable on the market at the high current rating. Smaller size
inductors also help to achieve low profile design.
There is limitation of the maximum reference’s (VREF_TRK at
Figure 51) frequency for the boost output voltage being able to
track, which is determined by the boost converter’s loop
bandwidth. Generally, the tracking reference signal’s frequency
should be 10 times lower than the boost loop crossover
frequency. Otherwise, the boost output voltage cannot track the
tracking reference signal and the output voltage will be distorted.
For example, for a boost converter with 4kHz loop crossover
frequency, the boost can track reference signals up to 400Hz,
typically. Figures 23 and 24 on page 19 show performances
tracking 100Hz and 300Hz signals.
ATRAK/
DTRK
ATRK/DTRK
TRACK
The ISL78227 is a controller for 2-phase interleaved converter
where the 2 phases are operating with 180° phase shift,
meaning each PWM pulse is triggered 1/2 of a cycle after the
start of the PWM pulse of the previous phase. Figure 52 illustrates
the interleaving effect on input ripple current. The AC component
of the two phase currents (IL1 and IL2) are interleaving each
other and the combined AC current ripple (IL1 + IL2) at input are
reduced. Equivalently, the frequency of the AC inductor ripple at
input is 2 times of the switching frequency per phase.
1k
VREF_2.5V
Q1
Q2
M
U
X
R1
2M
C1
20p
R2
2M
2.5*D
C2
20p
SS
+
VREF_1.6V
+
Gm1
VREF_TRK
+
-
IC INTERNAL CIRCUITS
FB
COMP
FIGURE 51. TRACK FUNCTION BLOCK DIAGRAM
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ISL78227
CURRENT SHARING BETWEEN PHASES
The peak current mode control inherently has current sharing
capability. As shown in Figure 3 on page 7, the current sense
ramp VRAMPx of each phase are compared to the same error
amplifier’s output at the COMP pin by the PWM comparators to
turn off LGx when VRAMPx reaches COMP. Thus, the VRAMPx
peaks are controlled to be the same for each phase. VRAMPx is
the sum of instantaneous inductor current sense ramp and the
compensating slope. Since the compensating slopes are the
same for both phases, the inductor peak current of each phase is
controlled to be the same.
IL1
t
180°
IL2
IL1+IL2
t
t
FIGURE 52. PHASE NODE AND INDUCTOR-CURRENT WAVEFORMS
FOR 2-PHASE CONVERTER
To understand the reduction of the ripple current amplitude in the
multiphase circuit, examine Equation 4 representing an individual
phase’s peak-to-peak inductor current.
In Equation 4, VIN and VOUT are the input and the output voltages
respectively, L is the single-phase inductor value and fSW is the
switching frequency.
 V OUT – V IN  V IN
I PPCH = ----------------------------------------------L f SW V
(EQ. 4)
OUT
The input capacitors conduct the ripple component of the
inductor current. In the case of a 2-phase boost converter, the
capacitor current is the sum of the ripple currents from each of
the individual phases. Use Equation 5 to calculate the
peak-to-peak ripple of the total input current which goes through
the input capacitors, where KP-P can be found in Figure 53 under
specific duty cycle.
I PPALL = K P-P  I PPCH
(EQ. 5)
The same mechanism applies to the case when multiple
ISL78227s are configured in parallel for multiphase boost
converter. Basically, the COMP pin of each ISL78227 are tied
together for each phase’s current sense ramp peak to be
compared with the same COMP voltage (VRAMPx = COMP),
meaning the inductor peak current of all the phases are
controlled to be the same. The “4-Phase Operation” section
describes how to configure two ISL78227 in parallel for a
4-phase interleaved boost converter.
4-PHASE OPERATION
Two ISL78227s can be used in parallel to achieve interleaved
4-phase operation. Figure 54 shows the recommended
configuration. The CLKOUT from the master IC drives FSYNC of
the slave IC to synchronize the switching frequencies. This
achieves a 90° phase shift for the 4 phases switching and the
respective COMP, FB, SS, EN and IMON pins of the two ICs are
connected.
CLKOUT is 90°out-of-phase with the rising edge of LG1.
Therefore, the two phases of the second IC are interleaved with
the two phases of the first IC.
CLKOUT
COMP
MASTER IC
ISL78227
FB
FB
SS
SS
IMON
EN
0.9
0.8
FSYNC
COMP
SLAVE IC
ISL78227
IMON
EN
FIGURE 54. CONFIGURATIONS FOR DUAL IC 4-PHASE OPERATION
0.7
KP-P
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.4 5 0.5 0.55 0.6 0.65 0 .7 0.75 0.8 0.85 0.9
DUTY CYCLE
FIGURE 53. KP-P vs DUTY CYCLE
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ISL78227
Oscillator and Synchronization
The switching frequency is determined by the selection of the
frequency-setting resistor, RFSYNC, connected from the FSYNC
pin to GND. Equation 6 is provided to assist in selecting the
correct resistor value, where fSW is the switching frequency of
each phase.
R FSYNC = 2.49x  10 
10  0.505
–8
--------------- – 5.5X10 
 f

SW
(EQ. 6)
Figure 55 shows the relationship between RFSYNC and switching
frequency.
parallel for 4-phase interleaved operation, with the master IC’s
CLKOUT being connected to the FSYNC pin of the slave IC. The
master IC outputs CLKOUT signal with delay of (tSW/4 - tDT1)
after LG1_master. The slave IC FSYNC pin takes the
CLKOUT_master as the input and the slave’s IC LG1 is delayed by
a time of (35ns + tDT1). Therefore, the LG1_slave is delayed by
(tSW/4+35ns) to LG1_master which is around 90° phase shift.
With 90°phase shift between LG1 and respective LG2 for each
IC, an interleaved 4-phases with 90° phase shift boost is
achieved.
LG1_IC_Master
300
tSW/4 - tDT1
250
CLKOUT_IC_Master
RFSYNC (kΩ)
200
FSYNC_IC_Slave
150
35ns + tDT1
100
LG1_IC_Slave
50
t1 t2 t3
0
0
100
200
300
400
500
600
700
800
900 100 0 110 0
f SW (kHz)
FIGURE 55. fSW vs RFS
The ISL78227 contains a Phase Lock Loop (PLL) circuit. Refer to
Figure 4 on page 8, the PLL is compensated with a series
resistor-capacitor (RPLL and CPLL1) from the PLLCOMP pin to
GND and a capacitor (CPLL2) from PLLCOMP to GND. At 300kHz
switching frequency, typical values are RPLL = 3.24kΩ,
CPLL1 = 6.8nF, CPLL2 = 1nF. The PLL locking time is around
0.7ms. Generally, the same PLL compensating network can be
used in the frequency range of 50kHz to 1.1MHz. With the same
PLL compensation network, at a frequency range higher than
500kHz, the PLL loop is overcompensated. However, the PLL
loop is stable just with slow frequency response. If a faster
frequency response is required at a higher operating frequency,
the PLL compensation network can be tuned to have a faster
response. An Excel spreadsheet to calculate the PLL
compensation is provided on the ISL78227 web page.
The ISL78227’s switching frequency can be synchronized to the
external clock signals applied at the FSYNC pin. The ISL78227
detects the input clock’s rising edge and synchronizes the rising
edge of LG1 to the input clock’s rising edge with a dead time
delay of tDT1. The switching frequency of each phase equals the
fundamental frequency of the clock input at FSYNC. Since the
ISL78227 detects only the edge of the input clock instead of its
pulse width, the input clock’s pulse width can be as low as 20ns
(as minimum), tens of ns, or hundreds of ns depending on the
capability of the specific system to generate the external clock.
The CLKOUT pin outputs a clock signal with the same frequency
of the per phase switching frequency. Its amplitude is VCC and
pulse width is 1/12 of per phase switching period (tSW/12).
Figure 56 shows the application example to put two ISL78227 in
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FIGURE 56. TIMING DIAGRAM OF CLKOUT vs LG1 AND FSYNC vs LG1
(CLKOUT_MASTER CONNECTED TO FSYNC_SLAVE)
Once the ISL78227 latches to being synchronized with the
external clock, if the external clock on the FSYNC pin is removed,
the switching frequency oscillator will shut down. Then the part
will detect PLL_LOCK fault (refer to Table 3 on page 34), and go
to either Hiccup mode or Latch-off mode depending on the
HIC/LATCHOFF pin configuration. If the part is set in Hiccup
mode, the part will restart with frequency set by the resistor at
the FSYNC pin.
The switching frequency range of the ISL78227 set by RFSYNC or
by synchronization is typically 50kHz to 1.1MHz.
The low end 50kHz is determined by a PLL_LOCK fault
protection, which shuts down the IC when frequency is lower than
37kHz typical.
The phase dropping mode is not allowed with external
synchronization.
MINIMUM ON-TIME (BLANK TIME) CONSIDERATION
The minimum ON-time (also called BLANK time) of LGx is the
minimum ON pulse width as long as LGx is turned ON and it is
also intended for the internal circuits to blank out the noise
spikes after LGx turns on. The tMINON can be programmed by a
resistor at the RBLANK pin.
The selection of the tMINON depends on 2 considerations.
1. The noise spike durations after LGx turns on, which is
normally in a range of tens of ns to 100ns or longer depending
on the external MOSFET switching characteristic and noise
coupling path to current-sensing.
2. Ensure the charging of the boot capacitor during operations of
LGx operating at tMINON. One typical case is an operation
when the input voltage is close to the output voltage. The duty
FN8808.2
February 24, 2016
ISL78227
cycle is smallest at tMINON and CBOOTx is charged by PVCC via
DBOOTx with short duration of tMINON minus the delay to pull
phase low. If such operation is required, especially when a
large MOSFET with large Qg is used to support heavy load
application, larger tMINON can be programmed with the
resistor at the RBLANK pin to ensure CBOOTx can be
sufficiently charged during minimum duty cycle operation.
EN
1.2V
POR_R
PVCC/VCC
PLLCOMP
Please refer to Figure 57 for the selection of RBLANK resistor
and tMINON time. A 5kΩ resistor is recommended as the
minimum RBLANK resistor.
CLKOUT
500
LG
450
400
tMINON (ns)
350
UG
300
COMP_Ramp_Offset
COMP
250
200
SS
150
VFB
100
50
PGOOD
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
R BLANK (k)
FIGURE 57. tMINON vs RBLANK
Operation Initialization and Soft-Start
Prior to converter initialization, the EN pin voltage needs to be
higher than its rising threshold and the PVCC/VCC pin needs to be
higher than the rising POR threshold. When these conditions are
met, the controller begins initialization and soft-start. Figure 58
shows the ISL78227 internal start-up timing diagram from the
power-up to soft-start.
t1 t2 t3
t4t5 t6
t7
t8 t9
FIGURE 58. CIRCUIT INITIALIZATION AND SOFT-START
Assuming input voltage is applied to the VIN pin before t1 and VCC
is connected to PVCC, as shown on Figure 58, the descriptions for
start-up procedure is elaborated in the following:
t1 - t2: The enable comparator holds the ISL78227 in shutdown
until the VEN rises above 1.2V (typical) at the time of t1. During
t1 - t2 VPVCC/VCC will gradually increase and reaches the internal
Power-on Reset (POR) rising threshold 4.5V (typical) at t2.
t2 - t3: During t2 - t3, the ISL78227 will go through a
self-calibration process to detect certain pin configurations
(HIC/LATCH, DE/PHDRP, ATRK/DTRAK) to latch in the selected
operation modes. The time duration for t2 - t3 is typically 195µs.
t3 - t4: During this period, the ISL78227 will wait until the internal
PLL circuits are locked to the preset oscillator frequency. When
PLL locking is achieved at t4, the oscillator will generate output
at the CLK_OUT pin. The time duration for t3 - t4 depends on the
PLLCOMP pin configuration. The PLL is compensated with a
series resistor-capacitor (RPLL and CPLL1) from the PLLCOMP pin
to GND and a capacitor (CPLL2) from PLLCOMP to GND. At
300kHz switching frequency, typical values are RPLL = 3.24kΩ,
CPLL1 = 6.8nF, CPLL2 = 1nF. With this PLLCOMP compensation,
the time duration for t3 - t4 is around 0.7ms.
t4 - t5: The PLL locks the frequency t4 and the system is
preparing to soft-start. The ISL78227 has one unique feature to
prebias the SS pin voltage to be equal to VFB during t4 - t5, which
is around 50µs.
t5 - t6: At t5 the soft-start ramps up at the SS pin (VSSPIN) and the
COMP voltage starts to ramp-up as well. Drivers are enabled but
not switching during t5 - t6 since the COMP is still below the
current sense ramp offset. The device operates in diode
emulation mode during soft-start period t5 - t8. The slew rate of
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ISL78227
the SS ramp and the duration of t5 - t8 are determined by the
capacitor used at the SS pin.
t6 - t7: At t6 COMP is above the current sense ramp offset and the
drivers start switching. Output voltage ramps up while FB voltage
is following SS ramp during this soft-start period. At t7, output
voltage reaches the regulation level and FB voltage reaches
VREF_1.6V.
VIN
VCC
FROM
EXTERNAL
EN CONTROL
EN
5k
+
5.2V
CLAMP
TO INTERNAL
CIRCUITS
-
5M
1.2V
t7 - t8: SS continues ramping up until it reaches SS clamp voltage
(VSSPCLAMP) 3.47V at t8 indicating the SS pin ramp-up is
completed. At t8, the ISL78227 generates an internal SS_DONE
signal, which goes HIGH when both VSSPIN = VSSPCLAMP (3.47V)
and VREF_TRK ≥ 0.3V (as shown in Figure 3 on page 7). This
indicates the soft-start has completed.
t8 - t9: After t8, a delay time of either 0.5ms or 100ms is inserted
before the PGOOD pin is released HIGH at t9 depending on the
selected mode (please refer to Table 2 on page 33).
1. If the DE/PHDRP pin = GND or FLOAT to have DE mode
selected, the PGOOD rising delay from VSSPIN = VSSPCLAMP
(3.47V) AND VREF_TRK ≥0.3V to PGOOD rising is 0.5ms.
2. If the DE/PHDRP pin = GND to have CCM mode selected, the
PGOOD rising delay from VSSPIN = VSSPCLAMP (3.47V) AND
VREF_TRK ≥0.3V to PGOOD rising is 100ms, during which
period, the device is transitioning from DE mode to CCM
mode. The high-side gate UGx is controlled to gradually
increase the ON-time to finally merged with CCM ON-time.
This synchronous MOSFET “soft-ON” feature is unique and
ensures smooth transition from DCM mode to CCM mode
after soft-start completes. More importantly, this “SYNC FET
soft-ON” function eliminates the large negative current, which
often occurs when starting up to a high prebiased output
voltage. This feature makes the system robust for all the
challenging start-up conditions and greatly improves the
system reliability.
Enable
To enable the device, the EN pin needs to be driven higher than
1.2V (typical) by the external enable signal or resistor divider
between VIN and GND. The EN pin has an internal 5MΩ (typical)
pull-down resistor. Also, this pin internally has a 5.2V (typical)
clamp circuit with a 5kΩ (typical) resistor in series to prevent
excess voltage applied to the internal circuits. When applying the
EN signal using resistor divider from VIN, internal pull-down
resistance needs to be considered. Also, the resistor divider ratio
needs to be adjusted as its EN pin input voltage may not exceed
5.2V.
To disable or reset all fault status, the EN pin needs to be driven
lower than 1.1V (typical). When the EN pin is driven low, the
ISL78227 turns off all of the blocks to minimize the off-state
quiescent current.
FIGURE 59. ENABLE BLOCK
Soft-Start
Soft-start is implemented by an internal 5µA current source
charging the soft-start capacitor (CSS) at SS to ground. The
voltage on the SS pin slowly ramps up as the reference voltage
for the FB voltage to follow during soft-start.
Typically, for boost converter before soft-start, its output voltage
is charged up to be approximately a diode drop below the input
voltage through the upper side MOSFETs’ body diodes. To more
accurately correlate the soft-start ramp time to the output
voltage ramp time, the ISL78227 SS pin voltage is prebiased
with voltage equal to FB voltage before soft-start begins. The
soft-start ramp time for the boost output voltage ramping from
VIN to the final regulated voltage VOUTreg, can be calculated by
Equation 7, where VREF is 1.6V (VREF_1.6V) with the TRACK pin
tied HIGH:
V IN
C SS

t SS = V REF   1 – ------------------------  -----------
V OUTreg 5A

(EQ. 7)
PGOOD Signal
The PGOOD pin is an open-drain logic output to indicate that the
soft-start period is completed, the input voltage is within safe
operating range and the output voltage is within the specified
range. The PGOOD comparator monitors the FB pin to check if
output voltage is within 80% to 120% of the reference voltage
VREF_1.6V.
As described at the t8 - t9 duration in “Operation Initialization
and Soft-Start” on page 29, the PGOOD pin is pulled low during
soft-start and it’s released high after SS_DONE with a 0.5ms or
100ms delay.
PGOOD will be pulled low if any of the comparators for FB_UV,
FB_OV or VIN_OV is triggered for a duration longer than 10µs.
In normal operation after start-up, under fault recovery, the
PGOOD will be released high with the same 0.5ms delay time
after the fault is removed.
Current Sense
The ISL78227 peak current control architecture senses the
inductor current continuously for fast response. A sense resistor
is placed in series with the power inductor for each phase. The
ISL78227 Current Sense Amplifiers (CSA) continuously sense the
respective inductor current as shown in Figure 60 by sensing the
voltage signal across the sense resistor RSENx (where “x”
indicates the specific phase number and same note applied
throughout this document). The sensed current for each active
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ISL78227
phase will be used for peak current mode control loop, phase
current balance, individual phase cycle-by-cycle peak current
limiting (OC1), individual phase overcurrent fault protection
(OC2_PEAK), input average Constant Current (CC) control and
average overcurrent protection (OC_AVG), diode emulation and
phase drop control. The internal circuitry shown in Figure 60
represents a single phase. This circuitry is repeated for each
phase.
CURRENT SENSE FOR INDIVIDUAL PHASE - ISENX
+
VIN
RSENx
IL
-
+
RSETxA
- CISENx
ISENx+112µA
+
RSETxB
ISENxP
112µA
+
RBIASxB
ISENxN
AVERAGE CURRENT SENSE FOR 2 PHASES - IMON
The IMON pin serves to monitor the total average input current of
the 2-phase boost. As shown in Figure 3 on page 7, the individual
current sense signals (ISENx) are divided by 8 and summed
together. A 17µA offset current is added to form a current source
output at the IMON pin with the value calculated as shown by
Equation 12.
IBIAS
112µA
 I L1  R SEN1 I L2  R SEN2
–6
IMON =  -------------------------------- + --------------------------------  0.125 + 17  10
R SET2 
 R SET1
ISENx
R SEN
–6
IMON = I IN  ----------------  0.125 + 17  10
R
FIGURE 60. CURRENT-SENSING BLOCK DIAGRAM
The RC network between RSENx and ISENxP/N pins as shown in
Figure 60 is the recommended configuration. The ISENxP pin
should be connected to the positive potential of the RSEN_CHx
through resistor RSETx, where in Figure 60 RSETx is composed by
RSETxA plus RSETxB. RSET is used to set the current sense gain
externally.
(EQ. 8)
R SETx = R SETxA + R SETxB
Since there is an 112µA bias current sinking to each of the
ISENxP and ISENxN pins, RBIASx with same value to RSETx should
be placed between the ISENxN pin to the low potential of the
RSENx, where in Figure 60 RBIASx is composed by RBIASxA plus
RBIASxB.
R BIASx = R BIASxA + R BIASxB
(EQ. 9)
(EQ. 10)
R BIASx = R SETx
It is recommended to have RSETxA = RBIASxA and
RSETxB = RBIASxB, and insert a capacitor CISENx between them
as shown in Figure 60. This will form a symmetric noise filter for
the small current sense signals. The differential filtering time
constant equals to (RSETxA+RBIASxA)*CISENx. This time constant
31
(EQ. 12)
Assume RSEN1 = RSEN2, RSET1 = RSET2, and IIN = IL1+IL2 (which
is the total boost input average current):
IC INTERNAL CIRCUITS
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(EQ. 11)
RSENx is normally selected with smallest resistance to minimize
the power loss on it. With RSENx selected, RSETx is selected by
the desired cycle-by-cycle peak current limiting level OC1 (refer to
“Peak Current Cycle-by-Cycle Limiting (OC1)” on page 35).
CSA
ISENx
CSA generates the sensed current signal ISENx by forcing ISENxP
voltage to be equal to ISENxN voltage. Since RSETx equals to
RBIASx, the voltage drop across RSETx and RBIASx incurred by the
fixed 112µA bias current cancels each other. Therefore, the
resulting current at CSA output ISENx is proportional to each
phase inductor current ILx. ISENx per phase can be derived in
Equation 11, where ILx is the per phase current flowing through
RSENx.
R SENx
I SENx = I Lx  ------------------R SETx
VOUT
L
+
RBIASxA
-
112µA
is typically selected in range of tens of ns depending on the
actual noise levels.
(EQ. 13)
SET
As shown in Figure 4 on page 8, a resistor RIMON is placed
between the IMON pin and ground, which turns the current sense
output from the IMON pin to a voltage VIMON. A capacitor CIMON
should be used in parallel with RIMON to filter out the ripple such
that VIMON represents the total average input current of the
2-phase boost. VIMON can be calculated using Equation 14.
V IMON = IMON  R IMON
(EQ. 14)
As shown in Figure 3 on page 7, VIMON is sent to inputs of Gm2
and comparators of CMP_PD and CMP_OCAVG for the following
functions:
1. VIMON is compared with 1.6V (VREF_CC) at error amplifier
Gm2 inputs to achieve constant current control function. The
CC control threshold for the boost input current is typically set
in a way that the per phase average inductor current (when CC
control) is lower than the per phase cycle-by-cycle peak
current limiting (OC1) threshold. Please refer to “Constant
Current Control (CC)” on page 35 for detailed descriptions.
2. VIMON is compared with phase dropping thresholds (1.1V
falling to drop phase2, 1.15V rising to add phase2). Please
refer to “Automatic Phase Dropping/Adding” on page 33 for
detailed descriptions.
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ISL78227
3. VIMON is compared with 2V for OC_AVG fault protections.
Please refer to “Average Overcurrent Fault (OC_AVG)
Protection” on page 36 for detailed descriptions.
The typical scenario when fast overloading is applied is described
as the following. When large overload is suddenly applied at
boost output, the phase inductor peak currents are initially
limited by OC1 cycle-by-cycle, during which time the IMON
voltage slowly rises up due to the filter delay of RIMON and
CIMON. When VIMON reaches 1.6V, the CC loop starts to limit and
control the average current to be constant, which lowers down
the inductor current (as described previously, CC threshold
normally is set lower than the OC1 cycle-by-cycle limiting
threshold). Typically tens of nF are used for CIMON. In the case
when a longer time delay is needed, larger CIMON can be used.
“Constant Current Control (CC)” on page 35 has a more detailed
description.
Adjustable Slope Compensation
The ISL78227 features adjustable slope compensation by setting
the resistor value RSLOPE from the SLOPE pin to ground. This
function will ease the compensation design and provide more
flexibility in choosing the external components.
Figure 61 shows the block diagram related to slope compensation.
For current mode control, in theory, the compensation slope slew
rate mSL needs to be larger than 50% of the inductor current
down ramp slope slew rate mb.
Equation 15 shows the resistor value RSLOPE at the SLOPE pin to
create a compensation ramp.
5
(EQ. 15)
SENx
Where KSLOPE is the selected gain of compensation slope over
inductor down slope. For example, KSLOPE = 1 gives the RSLOPE
value generating a compensation slope equal to inductor current
down ramp slope. Theoretically, the KSLOPE needs to be larger
than 0.5, but practically more than 1.0 is used in the actual
application. To cover the operating range, the maximum of VOUT
and minimum of VIN should be used in Equation 15 to calculate
the RSLOPE.
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32
RSENx
-
IL
VOUT
L
RSETx
RBIASx
k1*ISENx
ISENxN
VRAMP
CSA
ISENxP
RRAMP
SLOPE
RSLOPE
ISLOPE = k2*0.5V/RSLOPE
VSL
ISL
0.5V
CSL
LGx
ISL0
For a boost converter with peak current mode control, slope
compensation is needed when duty cycle is larger than 50%. It is
advised to add slope compensation when the duty cycle is
approximately 30% to 40% since a transient load step can push
the duty cycle higher than the steady state level. When slope
compensation is too low, the converter suffers from subharmonic
oscillation, which may result in noise emissions at half the
switching frequency. On the other hand, overcompensation of the
slope may reduce the phase margin. Therefore, proper design of
the slope compensation is needed.
6.67  10  L x  R SETx
R SLOPE = ----------------------------------------------------------------------------------------   
K SLOPE   V OUT – V IN   R
+
VIN
ma
mb
ISENx
ISL
mSL
ma1 = ma + mSL
VRAMP
VRAMP = (ISENx+ISL)*RRAMP
FIGURE 61. SLOPE COMPENSATION BLOCK DIAGRAM
Light-Load Efficiency Enhancement
For switching mode power supplies, the total loss is related to
conduction loss and switching loss. The conduction loss
dominates at heavy load, while the switching loss dominates at
light load condition. Therefore, if a multiphase converter is
running at a fixed phase number for the entire load range, the
efficiency starts to drop significantly below a certain load current.
The ISL78227 has selectable automatic phase dropping,
cycle-by-cycle diode emulation and pulse skipping features to
enhance the light-load efficiency. By observing the total input
current on-the-fly and dropping an active phase, the system can
achieve optimized efficiency over the entire load range.
The phase dropping (PH_DROP) and Diode Emulation (DE)
functions can be selected to be active or inactive by setting the
DE/PHDRP pin. Please refer to Table 2 for the 3 configuration
modes.
1. When DE/PHDRP = VCC, Diode Emulation function is enabled,
and Phase Drop function is disabled.
2. When DE/PHDRP = FLOAT, both Diode Emulation and Phase
Drop functions are enabled.
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3. When DE/PHDRP = GND, both diode emulation and phase
drop functions are disabled. The part is set in Continuous
Conduction Mode (CCM).
TABLE 2. CCM/DE/PH_DROP MODE SETTING (DE/PHDRP PIN)
MODE NUMBER
(NAME)
(ISENx>80µA) in either of the 2 phases, Phase 2 will be added
back immediately.
After Phase 2 is added, the phase dropping function will be
disabled for 1.5ms. After this 1.5ms expires, the phase dropping
circuit will be activated again and Phase 2 can be dropped
automatically as usual.
DE/PHDRP PIN
SETTING
DE MODE
PHASE-DROP
MODE
VCC
Enabled
Disabled
DIODE EMULATION AT LIGHT LOAD CONDITION
FLOAT
Enabled
Enabled
GND
Disabled
Disabled
When the Diode Emulation mode (DE) is selected to be enabled
(Mode 1 and 2 in Table 2), the ISL78227 has cycle-by-cycle diode
emulation operation at light load achieving Discontinuous
Conduction Mode (DCM) operation. With DE mode operation,
negative current is prevented and the conduction loss is reduced,
therefore high efficiency can be achieved at light load conditions.
1 (DE)
2 (DE+PH_DROP)
3 (CCM)
AUTOMATIC PHASE DROPPING/ADDING
When the phase drop function is enabled, the ISL78227
automatically drops or adds Phase 2 by comparing the VIMON to
the phase dropping/adding thresholds. VIMON is proportional to
the average input current indicating the level of the load.
The phase dropping mode is not allowed with external
synchronization.
Phase Dropping
When load current drops and VIMON falls below 1.1V, Phase 2 is
disabled. For better transient response during phase dropping,
the ISL78227 will gradually reduce the duty cycle of the phase
from steady state to zero, typically within 8 to 10 switching
cycles. This gradual dropping scheme will help smooth the
change of the PWM signal and stabilize the system when phase
dropping happens.
From Equations 13 and 14, the phase dropping current threshold
level for the total 2-phase boost input current can be calculated
by Equation 16.
Diode emulation occurs during t5-t8 (on Figure 58 on page 29),
regardless of the DE/PHDRP operating modes (Table 2).
PULSE SKIPPING AT DEEP LIGHT LOAD CONDITION
If the converter enters diode emulation mode and the load is still
reducing, eventually pulse skipping will occur to increase the
deep light-load efficiency. Either Phase 1 or Phase 2, or both, will
be pulse skipping at these deep light load conditions.
Fault Protections/Indications and Current
Limiting
The ISL78227 is implemented with comprehensive fault
protections/indications and current limitings to design a highly
reliable boost converter. Most of the fault protections’ response
can be selected to be either Hiccup or Latch-off by configuring
the HIC/LATCH pin, which offers the flexibility upon the specific
requirements for different applications.
Selectable Hiccup or Latch-Off Fault Response
– 6 R SET
1.1
I INphDRP =  ------------------- – 17  10   ----------------  8  A 
R
 R
IMON
SEN
(EQ. 16)
Phase Adding
The phase adding is decided by two mechanisms listed below.
The Phase 2 will be added immediately if either of the two
following conditions are met.
1. VIMON > 1.15V, the IMON pin voltage is higher than phase
adding threshold 1.15V. The phase adding current threshold
level for the total 2-phase boost input current can be
calculated by Equation 17.
– 6 R SET
1.15
I INphADD =  ------------------- – 17  10   ----------------  8  A 
R
 R
IMON
SEN
(EQ. 17)
2. ISENx > 80µA (OC1), individual phase current triggers OC1.
The first is similar to the phase dropping scheme. When the load
increases causing VIMON>1.15V, Phase 2 will be added back
immediately to support the increased load demand. Since the
IMON pin normally has large RC filter and VIMON is average
current signal, this mechanism has a slow response and is
intended for slow load transients.
Table 3 on page 34 lists the fault protections that can have either
Hiccup or Latch-off fault response determined by HIC/LATCH pin
configurations.
• When the HIC/LATCH pin is pulled high (VCC), the fault response
is in Hiccup mode.
• When the HIC/LATCH pin is pulled low (GND), the fault response is
in Latch-off mode.
In Hiccup mode, the device will stop switching when a fault
condition in Table 3 on page 34 is detected, and restart from
soft-start after 500ms (typical). This operation will be repeated
until fault conditions are completely removed.
In Latch-off mode, the device will stop switching when a fault
condition in Table 3 on page 34 is detected and PWM switching
being kept off even after fault conditions are removed. In
Latch-off status, the internal LDO is alive to keep PVCC voltage
regulated. By either toggling the EN pin or cycling VCC/PVCC
below the POR threshold will restart the system.
The second mechanism is intended to handle the case when load
increases quickly. If the quick load increase triggers OC1
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TABLE 3. FAULT NAMES LIST FOR THE HICCUP OR LATCH-OFF FAULT RESPONSE
FAULT RESPONSE
HIC/LATCH = VCC: HICCUP
HIC/LATCH = GND: LATCH-OFF
FAULT NAME
DESCRIPTIONS
VIN_OV
Set by the HIC/LATCH pin
Input overvoltage fault (VIN_PIN >58V) protection
response is Hiccup when HIC/LATCH = VCC, and Latch-off
when HIC/LATCH = GND
OC_AVG
Set by the HIC/LATCH pin
Input average overcurrent fault (IMON_PIN >2V) protection
response is Hiccup when HIC/LATCH = VCC, and Latch-off
when HIC/LATCH = GND
OC2_PEAK
Set by the HIC/LATCH pin
Peak overcurrent fault (ISENx >105µA) protection response
is Hiccup when HIC/LATCH = VCC, and Latch-off when
HIC/LATCH = GND
VOUT_OV
Set by the HIC/LATCH pin
Output overvoltage fault (FB_PIN >120%*VREF_1.6V)
protection response is Hiccup when HIC/LATCH = VCC, and
Latch-off when HIC/LATCH = GND
PLLCOMP_SHORT
Set by the HIC/LATCH pin
PLLCOMP_SHORT fault (PLLCOMP_PIN >1.7V) protection
response is Hiccup when HIC/LATCH = VCC, and Latch-off
when HIC/LATCH = GND
PLL_LOCK
Set by the HIC/LATCH pin
PLL loop fault (detect the minimum frequency of 37kHz as
typical) protection response is Hiccup when
HIC/LATCH = VCC, and Latch-off when HIC/LATCH = GND
INPUT OVERVOLTAGE FAULT PROTECTION
As shown in Figure 3 on page 7, the ISL78227 monitors the VIN
pin voltage divided by 48 (VIN/48) as the input voltage
information. This fault detection is active at the beginning of
soft-start (t5 as shown in Figure 58 on page 29).
The VIN_OV comparator compares VIN/48 to 1.21V reference to
detect if VIN_OV fault is triggered. Equivalently, when VIN >58V
(for 5µs), VIN_OV fault event is triggered. The PGOOD pin will be
pulled low.
At the same time the VIN_OV fault condition is triggered, the
ISL78227 will respond with fault protection actions to shut down
the PWM switching and enters either Hiccup or Latch-off mode
depending on HIC/LATCH pin configuration as described in
“Selectable Hiccup or Latch-Off Fault Response” on page 33 and
Table 3 on page 34.
Under the selection of Hiccup response for the VIN_OV fault,
when the output voltage falls down to be lower than the VIN_OV
threshold 58V, the device will return to normal switching through
Hiccup soft-start. PGOOD will be released to be pulled high after
a 0.5ms delay.
the PWM switching and enters either Hiccup or Latch-off mode
depending on HIC/LATCH pin configuration as described in
“Selectable Hiccup or Latch-Off Fault Response” on page 33 and
Table 3 on page 34.
Under the selection of Hiccup response for the VOUT_OV fault,
when the output voltage falls down to be lower than the VOUT_OV
threshold of 120%*VREF_1.6V minus 4% hysteresis, the device
will return to normal switching through Hiccup soft-start. The
PGOOD pin will be released to be pulled high after 0.5ms delay.
Equivalently the VOUT overvoltage threshold is set at the same
percentage of VOUT target voltage VOUT_TARGET (set by
VREF_1.6V) since the device uses the same FB voltage to
regulate the output voltage with the same resistor divider
between VOUT and the FB pin (refer to Equation 2 on page 25).
Therefore the VOUT overvoltage protection threshold is set at
120% of VOUT_TARGET. According to Equation 2 on page 25, the
VOUT overvoltage protection threshold can be calculated using
Equation 18.
R FB2

VOUT OVP = 1.2  1.6   1 + ---------------
R FB1

(EQ. 18)
OUTPUT OVERVOLTAGE FAULT PROTECTION
OUTPUT UNDERVOLTAGE INDICATION
The ISL78227 monitors the FB pin voltage to detect if output
overvoltage fault (VOUT_OV) occurs. This fault detection is active
at the beginning of soft-start (t5 as shown in the Figure 58 on
page 29).
The ISL78227 monitors the FB pin voltage to detect if output
undervoltage (VOUT_UV) occurs.
If the FB pin voltage is higher than 120% of the voltage
regulation reference VREF_1.6V, the VOUT_OV comparator is
triggered to indicate VOUT_OV fault and the PGOOD pin will be
pulled low.
If the FB pin voltage is lower than 80% of the voltage regulation
reference VREF_1.6V, the VOUT_UV comparator is triggered to
indicate VOUT_UV occurring and the PGOOD pin will be pulled
low. But there is no fault protection actions for the VOUT_UV
condition, meaning the ISL78227 continue to keep PWM
switching and normal operation when VOUT_UV occurs.
At the same time, when a VOUT_OV fault is triggered, the
ISL78227 will respond with fault protection actions to shut down
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ISL78227
When the output voltage rises back to be above the VOUT_UV
threshold of 80%*VREF_1.6V plus 4% hysteresis, PGOOD will be
released to be pulled high after a 0.5ms delay.
Equivalently, the VOUT undervoltage threshold is set at the same
percentage of VOUT target voltage VOUT_TARGET (set by
VREF_1.6V) since the device uses the same FB voltage to
regulate the output voltage with the same resistor divider
between VOUT and the FB pin (refer to Equation 2 on page 25).
Therefore the VOUT undervoltage threshold is set at 80% of
VOUT_TARGET. According to Equation 2 on page 25, the VOUT
undervoltage protection threshold can be calculated using
Equation 19.
R FB2

VOUT UV = 0.8  1.6   1 + ---------------
R FB1

(EQ. 19)
OVERCURRENT LIMITING AND FAULT PROTECTION
The ISL78227 has multiple levels of overcurrent
protection/limiting. Each phase’s peak inductor current is
protected from overcurrent conditions by limiting its peak current
and the combined total current is protected on an average basis.
Also, each phase is implemented with instantaneous
cycle-by-cycle negative current limiting (OC_NEG_TH = -48µA).
Peak Current Cycle-by-Cycle Limiting (OC1)
Each individual phase’s inductor peak current is protected with
cycle-by-cycle peak current limiting (OC1) without triggering
Hiccup or Latch-off shutdown of the IC. The controller
continuously compares the CSA output current sense signal
ISENx (calculated by Equation 11 on page 31) to an overcurrent
limiting threshold (OC1_TH = 80µA) in every cycle. When ISENx
reaches 80µA, the respective phase’s LGx is turned off to stop
inductor current further ramping up. In such a way, peak current
cycle-by-cycle limiting is achieved.
The equivalent cycle-by-cycle peak inductor current limiting for
OC1 can be calculated by Equation 20:
I OC1x = 80  10
– 6 R SETx
 -------------------  A 
R SENx
(EQ. 20)
Negative Current Cycle-by-Cycle Limiting (OC_NEG)
Each individual phase’s inductor current is protected with
cycle-by-cycle negative current limiting (OC_NEG) without
triggering Hiccup or Latch-off shutdown of the IC. The controller
continuously compares the CSA output current sense signal
ISENx (calculated by Equation 11 on page 31) to a negative
current limiting threshold (OC_NEG_TH = -48µA) in every cycle.
When ISENx falls below -48µA, the respective phase’s UGx is
turned off to stop the inductor current further ramping down. In
such a way, negative current cycle-by-cycle limiting is achieved.
The equivalent negative inductor current limiting level can be
calculated by Equation 21:
I OCNEGx = – 48  10
– 6 R SETx
 -------------------  A 
R SENx
(EQ. 21)
Peak Overcurrent Fault (OC2_PEAK) Protection
If either of the two individual phase’s current sense signal ISENx
(calculated by Equation 11 on page 31) reaches 105µA
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35
(OC2_TH = 105µA), the Peak Overcurrent fault (OC2_PEAK) will
be triggered. The ISL78227 will respond with fault protection
actions to shut down the PWM switching and enters either
Hiccup or Latch-off mode depending on HIC/LATCH pin
configuration as described in “Selectable Hiccup or Latch-Off Fault
Response” on page 33 and Table 3 on page 34.
This fault protection is intended to protect the device by
shutdown (Hiccup or Latch-off) from the worst case condition
where OC1 cannot limit the inductor peak current.
This fault detection is active at the beginning of soft-start (t5 as
shown in the Figure 58 on page 29).
Under the selection of Hiccup response for the OC2_PEAK fault,
when both phases’ peak current sense signal ISENx no longer trip
the OC2_PEAK thresholds (105µA), the device will return to
normal switching and regulation through Hiccup soft-start.
The equivalent inductor peak current threshold for the
OC2_PEAK fault protection can be calculated by Equation 22:
I OC2x = 105  10
– 6 R SETx
 -------------------  A 
R SENx
(EQ. 22)
Constant Current Control (CC)
A dedicated constant average Current Control (CC) loop is
implemented in the ISL78227 to control the input current to be
constant at overload conditions, which means constant input
power control under certain constant input voltage.
As shown in Figure 3 on page 7, the VIMON represents the total
input average current and is sent to the error amplifier Gm2 input to
be compared with the internal CC reference VREF_CC (1.6V). Gm2
output is driving COMP voltage through a diode DCC. Thus, the
COMP voltage can be controlled by either Gm1 output or Gm2
output through DCC depending on load conditions.
At normal operation without overloading, VIMON is lower than the
VREF_CC (1.6V at default). Therefore, Gm2 output is HIGH and DCC is
reversely blocked and not forward conducting. In this case, the
COMP voltage is controlled by the voltage loop error amplifier Gm1’s
output to have the output voltage regulated.
At input average current overloading case, when VIMON reaches
VREF_CC (1.6V), Gm2 output falls and DCC is forward conducting,
and Gm2 output overrides Gm1 output to drive COMP. In this way
the CC loop overrides the voltage loop, meaning VIMON is controlled
to be constant and input average constant current operation is
achieved. Under certain constant input voltage, input CC makes
input power constant for the boost converter. Compared to peak
current limiting schemes, the average constant current control is
more accurate to control the average current to be constant, which
is beneficial for the user to accurately control the maximum average
power for the converter to handle.
The CC current threshold should be set lower than the OC1 peak
current threshold with margin. Generally, the OC1 peak current
threshold (per phase) is set 1.5 to 2 times higher than the CC
current threshold (here referred to per phase average current).
This matches with the physics of the power devices that normally
has higher transient peak current rating and lower average
current ratings. The OC1 provides protection against the transient
peak current. The CC controls the average current with slower
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February 24, 2016
ISL78227
1. When fast changing overloading occurs, since VIMON has
sensing delay of RIMON*CIMON, CC does not trip at initial
transient load current until it reaches the CC reference 1.6V.
OC1 will be triggered at the beginning to limit the inductor
peak current cycle-by-cycle.
2. After the delay of RIMON*CIMON, when VIMON reaches the CC
reference 1.6V, CC control starts to work and limit duty cycles
to reduce the inductor current and keep the sum of the two
phases’ inductor currents being constant. The time constant
of the RIMON*CIMON is typically on the order of 10 times
slower than the voltage loop bandwidth so that the 2 loops
will not interfere with each other.
CC loop is active at the beginning of soft-start.
From Equations 13 and 14 on page 31, the constant current
control current threshold level for the total 2-phase boost input
current can be calculated by Equations 23.
– 6 R SET
1.6
I INCC =  ------------------- – 17  10   ----------------  8  A 
R
 R
IMON
SEN
(EQ. 23)
Average Overcurrent Fault (OC_AVG) Protection
The ISL78227 monitors the IMON pin voltage (which represents
the boost total input average current signal) to detect if Average
Overcurrent (OC_AVG) fault occurs. As shown in Figure 3 on
page 7, the comparator CMP_OCAVG compares VIMON to 2V
threshold to detect this fault. This fault detection is active at the
beginning of soft-start (t5 as shown in Figure 58 on page 29).
When VIMON is higher than 2V, the OC_AVG fault is triggered.
ISL78227 will respond with fault protection actions to shut down
the PWM switching and enters either Hiccup or Latch-off mode
depending on HIC/LATCH pin configuration as described in
“Selectable Hiccup or Latch-Off Fault Response” on page 33 and
Table 3 on page 34.
Under the selection of Hiccup response for the OC_AVG fault,
when the IMON voltage falls down to be lower than the 2V
threshold, the device will return to normal switching through
Hiccup soft-start.
From Equations 13 and 14 on page 31, the OC_AVG fault’s
current threshold level for the total 2-phase boost input current
can be calculated by Equation 24.
– 6 R SET
2
I INOCAVG =  ------------------- – 17  10   ----------------  8  A 
R
 R
IMON
SEN
INTERNAL DIE OVER-TEMPERATURE PROTECTION
The ISL78227 PWM will be disabled if the junction temperature
reaches +160°C (typical) while the internal LDO is alive to keep
PVCC/VCC biased (VCC connected to PVCC). A +15°C hysteresis
ensures that the device will restart with soft-start when the
junction temperature falls below +145°C (typical).
Internal 5.2V LDO
The ISL78227 has an internal LDO with input at VIN and a fixed
5.2V/100mA output at PVCC. The internal LDO tolerates an input
supply range of VIN up to 55V (60V absolute maximum). A 10µF,
10V or higher X7R type of ceramic capacitor is recommended
between PVCC to GND. At low VIN operation when the internal
LDO is saturated, the dropout voltage from the VIN pin to the
PVCC pin is typically 0.3V under 80mA load at PVCC as shown in
the “Electrical Specifications” table on page 9. This is one of the
constraints to estimate the required minimum VIN voltage.
The output of this LDO is mainly used as the bias supply for the
gate drivers. With VCC connected to PVCC as in the typical
application, PVCC also supplies other internal circuitry. To provide
a quiet power rail to the internal analog circuitry, it is
recommended to place an RC filter between PVCC and VCC. A
minimum of 1µF ceramic capacitor from VCC to ground should
be used for noise decoupling purpose. Since PVCC is providing
noisy drive current, a small resistor like 10Ω or smaller between
the PVCC and VCC helps to prevent the noises interfering from
PVCC to VCC.
Figure 62 shows the internal LDO’s output voltage (PVCC)
regulation versus its output current. The PVCC will drop to 4.5V
(typical) when the load is 195mA (typical) because of the LDO
current limiting circuits. When the load current further increases,
the voltage will drop further and finally enter current foldback
mode where the output current is clamped to 100mA (typical). At
the worst case when LDO output is shorted to ground, the LDO
output is clamped to 100mA.
5.5
5.0
4.5
4.0
V_PVCC (V)
response, but with much more accurate control of the maximum
power the system has to handle at overloading conditions.
3.5
3.0
2.5
2.0
1.5
1.0
(EQ. 24)
0.5
0.0
0.00
0.05
0.10
0.15
IOUT_PVCC (A)
0.20
0.25
FIGURE 62. INTERNAL LDO OUTPUT VOLTAGE vs LOAD
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February 24, 2016
ISL78227
Based on the junction to ambient thermal resistance RJA of the
package, the maximum junction temperature should be kept below
+125°C. However, the power losses at the LDO need to be
considered, especially when the gate drivers are driving external
MOSFETs with large gate charges. At high VIN, the LDO has
significant power dissipation that may raise the junction
temperature where the thermal shutdown occurs.
With an external PNP transistor as shown in Figure 63, the power
dissipation of the internal LDO can be moved from the ISL78227
to the external transistor. Choose RS to be 68Ω so that the LDO
delivers about 10mA when the external transistor begins to turn
on. The external circuit increases the minimum input voltage to
approximately 6.5V.
Once the switching frequency fSW is decided, the frequency
setting resistor (RFSYNC) can be determined by Equation 6 on
page 28.
Input Inductor Selection
While the boost converter is operating in steady state Continuous
Conduction Mode (CCM), the output voltage is determined by
Equation 1 on page 24. With the required input and output voltage,
duty cycle D can be calculated by Equation 25:
V IN
D = 1 – ---------------V OUT
(EQ. 25)
Where D is the on-duty of the boost low-side power transistor.
Under this CCM condition, the inductor peak-to-peak ripple
current of each phase can be calculated as Equation 26:
VIN
VIN
I L  P-P  = D  T  ---------L
RS
Where T is the switching cycle 1/fSW and L is each phase
inductor’s inductance.
VIN
PVCC
ISL78227
PVCC
From the previous equations, the inductor value is determined by
Equation 27:
V IN 
V IN

L =  1 – ----------------  --------------------------------V
I

OUT L  P-P   f SW
FIGURE 63. SUPPLEMENTING LDO CURRENT
Application Information
There are several ways to define the external components and
parameters of boost regulators. This section shows one example
of how to decide the parameters of the external components
based on the typical application schematics as shown in Figure 4
on page 8. In the actual application, the parameters may need to
be adjusted and additional components may be needed for the
specific applications regarding noise, physical sizes, thermal,
testing and/or other requirements.
Output Voltage Setting
The Output Voltage (VOUT) of the regulator can be programmed
by an external resistor divider connecting from VOUT to FB and FB
to GND as shown in Figure 4 on page 8. Use Equation 2 on
page 25 to calculate the desired VOUT, where VREF can be either
VREF_1.6V or VREF_TRK, whichever is lower. In the actual
application, the resistor value should be decided by considering
the quiescent current requirement and loop response. Typically,
between 4.7kΩ to 20kΩ will be used for the RFB1.
Switching Frequency
Switching frequency is determined by requirements of transient
response time, solution size, EMC/EMI, power dissipation and
efficiency, ripple noise level, input and output voltage range.
Higher frequency may improve the transient response and help
to reduce the solution size. However, this may increase the
switching losses and EMC/EMI concerns. Thus, a balance of
these parameters are needed when deciding the switching
frequency.
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(EQ. 26)
37
(EQ. 27)
Use Equation 27 to calculate L, where values of VIN, VOUT and
IL(P-P) are based on the considerations described in following:
• One method is to select the minimum input voltage and the
maximum output voltage under long term operation as the
conditions to select the inductor. In this case, the inductor DC
current is the largest.
• The general rule to select inductor is to have its ripple current
IL(P-P) around 30% to 50% of maximum DC current. The
individual maximum DC inductor current for the 2-phase boost
converter can be calculated by Equation 28, where POUTmax is
the maximum DC output power, EFF is the estimated efficiency:
P OUTmax
I Lmax = -------------------------------------------V INmin  EFF  2
(EQ. 28)
Using Equation 27 with the two conditions listed above, a
reasonable starting point for the minimum inductor value can be
estimated from Equation 29, where K is typically selected as
30%.
2
 EFF  2
V INmin  V INmin

L min =  1 – ---------------------------  --------------------------------------------------V OUTmax P OUTmax  K  f SW

(EQ. 29)
Increasing the value of the inductor reduces the ripple current
and therefore the ripple voltage. However, the large inductance
value may reduce the converter’s response time to a load
transient. This also reduces the current sense ramp signal and
may cause a noise sensitivity issue.
The peak current at maximum load condition must be lower than
the saturation current rating of the inductor with enough margin.
In the actual design, the largest peak current may be observed at
some transient conditions like the start-up or heavy load
transient. Therefore, the inductor’s size needs to be determined
with the consideration of these conditions. To avoid exceeding
FN8808.2
February 24, 2016
ISL78227
the inductor’s saturation rating, OC1 peak current limiting (refer
to “Peak Current Cycle-by-Cycle Limiting (OC1)” on page 35) should
be selected below the inductor’s saturation current rating.
Output Capacitor
To filter the inductor current ripples and to have sufficient
transient response, output capacitors are required. A
combination of electrolytic and ceramic capacitors are normally
used.
The ceramic capacitors are used to filter the high frequency
spikes of the main switching devices. In layout, these output
ceramic capacitors must be placed as close as possible to the
main switching devices to maintain the smallest switching loop
in layout. To maintain capacitance over the biased voltage and
temperature range, good quality capacitors such as X7R or X5R
are recommended.
As the UG and LG gate drivers are 5V output, the MOSFET VGS
need to be in this range.
The MOSFET should have low Total Gate Charge (Qg), low
ON-resistance (rDS(ON)) at VGS = 4.5V and small gate resistance
(Rg <1.5Ω is recommended). It is recommended that the
minimum VGS threshold is higher than 1.2V but not exceeding
2.5V, in order to prevent false turn-on by noise spikes due to high
dv/dt during phase node switching and maintain low rDS(ON)
under limitation of maximum gate drive voltage, which is 5.2V
(typical) for low-side MOSFET and 4.5V (typical) due to diode drop
of boot diode for high-side MOSFET.
Bootstrap Capacitor
The power required for high-side MOSFET drive is provided by the
boot capacitor connected between BOOT and PH pins. The
bootstrap capacitor can be chosen using Equation 32:
The electrolytic capacitors are normally used to handle the load
transient and output ripples. The boost output ripples are mainly
dominated by the load current and output capacitance volume.
Q gate
C BOOT  -----------------------dV BOOT
For boost converter, the maximum output voltage ripple can be
estimated using Equation 30, where IOUTmax is the load current
at output, C is the total capacitance at output, and DMIN is the
minimum duty cycle at VINmax and VOUTmin.
Where Qgate is the total gate charge of the high-side MOSFET
and dVBOOT is the maximum droop voltage across the bootstrap
capacitor while turning on the high-side MOSFET.
I OUTmax   1 – D MIN 
V OUTripple = ---------------------------------------------------------C  2  f SW
(EQ. 30)
For 2-phase boost converter, the RMS current going through the
output current can be calculated by Equation 30 for D > 0.5,
where IL is per phase inductor DC current. For D < 0.5, time
domain simulation is recommended to get the accurate calculation
of the input capacitor RMS current.
I CoutRMS = I L   1 – D    2D – 1  
(EQ. 31)
It is recommended to use multiple capacitors in parallel to
handle this output RMS current.
Input Capacitor
Depending upon the system input power rail conditions, the
aluminum electrolytic type capacitor is normally used to provide
a stable input voltage. The input capacitor should be able to
handle the RMS current from the switching power devices. Refer
to Equation 5 and Figure 53 on page 27 to estimate the RMS
current the input capacitors need to handle.
Ceramic capacitors must be placed near the VIN and PGND pin of
the IC. Multiple ceramic capacitors including 1µF and 0.1µF are
recommended. Place these capacitors as close as possible to the IC.
Power MOSFET
(EQ. 32)
Though the maximum charging voltage across the bootstrap
capacitor is PVCC minus the bootstrap diode drop (~4.5V), large
excursions below GND by PH node requires at least 10V rating for
this ceramic capacitor. To keep enough capacitance over the
biased voltage and temperature range, a good quality capacitor
such as X7R or X5R is recommended.
RESISTOR ON BOOTSTRAP CIRCUIT
In the actual application, sometimes a large ringing noise at the
PH node and the BOOT node are observed. This noise is caused
by high dv/dt phase node switching, parasitic PH node
capacitance due to PCB routing and the parasitic inductance. To
reduce this noise, a resistor can be added between the BOOT pin
and the bootstrap capacitor. A large resistor value will reduce the
ringing noise at PH node but limits the charging of the bootstrap
capacitor during the low-side MOSFET on-time, especially when
the controller is operating at very low duty cycle. Also large
resistance causes voltage dip at BOOT each time the high-side
driver turns on the high-side MOSFET. Make sure this voltage dip
will not trigger the high-side BOOT to PH UVLO threshold 3V (typical),
especially when a MOSFET with large Qg is used.
Loop Compensation Design
The ISL78227 uses constant frequency peak current mode
control architecture with a Gm amp as the error amplifier.
Figures 64 and 65 on page 39 show the conceptual schematics
and control block diagram, respectively.
The external MOSFETs driven by the ISL78227 controller need to
be carefully selected to optimize the design of the synchronous
boost regulator.
The MOSFET's BVDSS rating needs to have enough voltage
margin against the maximum boost output voltage plus the
phase node voltage transient spikes during switching.
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38
FN8808.2
February 24, 2016
ISL78227
Vo
VIN
Slope
+
Gm
-
RSEN
R1
Gvcvo(s)
RFB2
L
C1
Vfb
FB
+
-
Vc
Resr
ROEA
VREF
RFB1
VOUT
+
COMP
Gm
RCP
RL
COUT
CCP2
He1(s)
CCP1
He2(s)
FIGURE 64. CONCEPTUAL BLOCK DIAGRAM OF PEAK CURRENT MODE CONTROLLED BOOST REGULATOR
&XUUHQWPRGHFRQWURO
3RZHU6WDJH
(UURU$PS
9UHI
䏓9IE
䏓9R
䏓9F
+HV
RLOAD is the load resistance, Leq is the equivalent inductance
for multiphase boost with N number of phases, L is each
phase’s inductor’s inductance.
*YFYRV
L
L eq = ---N
9IE
.IE
FIGURE 65. CONCEPTUAL CONTROL BLOCK DIAGRAM
TRANSFER FUNCTION FROM VC TO VOUT
Transfer function from error amplifier output VC to output voltage
VOUT Gvcvo(s) can be expressed as Equation 33.
s  
s
 1 + -----------  1 – ---------------

 esr 
 RHZ
G vcvo  s  = K DC  ---------------------------------------------------------------------------------------s 2
s
s  
 1 + ---------  1 + ------------------- +  ------- 
  

Q 
  
p1
p
n
(EQ. 33)
n
The expressions of the poles and zeros are listed below:
R LOAD   1 – D 
K DC = ------------------------------------------K ISEN
• KISEN is the current sense gain as shown in Equation 34,
where RSENx and RSETx are per phase current sense resistor
and setting resistors described in “Current Sense for Individual
Phase - ISENX” on page 31.
R SENx  6500
K ISEN = ------------------------------------R SETx
(EQ. 34)
• Se/Sn is gain of the selected compensating slope over the
sensed inductor current up-ramp. It can be calculated in
Equation 36, where KSLOPE is the gain of selected
compensating slope over the sensed IL down slope (refer to
Equation 15 on page 32).
Se
 V OUT

------- = K SLOPE   --------------- – 1
Sn
 V IN

(EQ. 35)
Equation 33 shows that the system is mainly a single order
system plus a Right Half Zero (RHZ), which commonly exists for
boost converter. The main pole ωpPS is determined by load and
output capacitance and the ESR zero ωESR is the same as buck
converter.
2
R LOAD   1 – D 
 RHZ = ---------------------------------------------L eq
1
 esr = --------------------------------C OUT  R esr
Since the ωRHZ changes with load, typically the boost converter
crossover frequency is set 1/5 to 1/3 of the ωRHZ frequency.
2
 pPS = ----------------------------------------C OUT  R LOAD
1
Q p = --------------------------------------------------------------------Se
   1 – D   ------- + 0.5 + D
Sn
The double pole ωn is at half of the fSW and has minimum
effects at crossover frequency for most of the cases when the
crossover frequency is fairly low.
2
 n = -------f sw
Where,
• N is the number of phases, RESR is the output capacitor’s
Equivalent Series Resistance (ESR) of the total capacitors,
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February 24, 2016
ISL78227
COMPENSATOR DESIGN
Where,
Generally simple Type-2 compensator can be used to stabilize
the system. In the actual application, however, an extra phase
margin will be provided by a Type-3 compensator.
1
 p1 = ----------------------------------------------------------------------------------------------------------------R FB2  R FB1 + R FB2  R 1 + R FB1  R 1
C 1  ----------------------------------------------------------------------------------------------------R FB2 + R FB1
Vo
The total transfer function with compensation network and gain
stage will be expressed:
R1
RFB2
C1
FB
G open  s  = G vcvo  s   H e1  s   H e2  s 
Vc
COMP
+
Gm
-
VREF
RFB1
1
 z1 = --------------------------------------------C 1   R FB2 + R 1 
CCP1
He1(s)
Use f = ω/2π to convert the pole and zero expressions to
frequency domain, and from Equations 33, 38 and 39, select the
compensator’s pole and zero locations.
ROEA
RCP
CCP2
He2(s)
FIGURE 66. TYPE-3 COMPENSATOR
The transfer function at the error amplifier and its compensation
network can be expressed as Equation 36.
VC
H e2  s  = ----------- = g m  Z COMP =
V FB
(EQ. 39)
(EQ. 36)
 1 + sR
R
C
CP CP 1 OEA
g m ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2
1 + sR
C
S
+R
C
+C
 + C
C
R
R
CP CP1
CP2
O E A CP1
C P 2 CP1 CP O EA
If ROEA>>RCP, CCP1>>CCP2, and ROEA = infinite, the equation
can be simplified as shown in Equation 37:
s
1 + ---------1 + s  R CP  C CP1
1
 z2
H e2  s  = g m  ---------------------------------------------------------------------------------- = -------  -------------------s
s  C CP1   1 + s  R CP  C CP2 
s
1 + --------- p2
(EQ. 37)
Where,
In general, as described earlier, a type-2 compensation is
enough. Typically the crossover frequency is set 1/5 to 1/3 of the
ωRHZ frequency. For the compensator as general rule, set
ωp2/2π at very low end frequency; set ωz2/2π at 1/5 of the
crossover frequency; set ωp3/2π at the ESR zero or the RHZ
frequency ωRHZ/2π, whichever is lower.
VCC Input Filter
To provide a quiet power rail to the internal analog circuitry, it is
recommended to place an RC filter between PVCC and VCC. A
10Ω resistor between PVCC and VCC and at least 1µF ceramic
capacitor from VCC to GND are recommended.
Current Sense Circuit
To set the current sense resistor, the voltage across the current
sense resistor should be limited to within ±0.3V. In a typical
application, it is recommended to set the voltage across the
current sense resistor in range around 30mV to 100mV for the
typical load current condition.
Layout Considerations
For DC/DC converter design, the PCB layout is a very important to
ensure the desired performance.
gm
 p2 = --------------C CP1
1
 z2 = -------------------------------R CP  C CP1
1. Place input ceramic capacitors as close as possible to the IC's
VIN and PGND/SGND pins.
1
 p3 = -------------------------------R CP  C CP2
2. Place the output ceramic capacitors as close as possible to
the power MOSFETs. Keep this loop (output ceramic capacitor
and MOSFETs for each phase) as small as possible to reduce
voltage spikes induced by the trace parasitic inductances
when MOSFETs switching ON and OFF.
If Type-3 compensation is needed, the transfer function at the
feedback resistor network is:
s
1 + ---------R FB1
 z1
H e1  S  = ------------------------------------  -------------------R FB1 + R FB2
s
1 + --------- p1
(EQ. 38)
3. Place the output aluminum capacitors close to the power
MOSFETs.
4. Keep the phase node copper area small but large enough to
handle the load current.
5. Place the input aluminum and some ceramic capacitors close
to the input inductors and power MOSFETs.
6. Place multiple vias under the bottom pad of the IC. The
bottom pad should be connected to the ground copper plane
with as large an area as possible in multiple layers to
effectively reduce the thermal impedance. Figure 67 shows
the layout example for vias in the IC bottom pad.
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February 24, 2016
ISL78227
12. The current-sensing traces must be laid out very carefully
since they carry tiny signals with only tens of mV.
For the current-sensing traces close to the power sense resistor
(RSENx), the layout pattern shown in Figure 68 is recommended.
Assuming the RSENx is placed in the top layer (red), route one
current sense connection from the middle of one RSENx pad in
the top layer under the resistor (red trace). For the other currentsensing trace, from the middle of the other pad on RSENx in top
layer, after a short distance, via down to the second layer and
route this trace right under the top layer current sense trace.
FIGURE 67. RECOMMENDED LAYOUT PATTERN FOR VIAS IN THE
IC BOTTOM PAD
13. Keep the current-sensing traces far from the noisy traces like
gate driving traces (LGx, UGx and PHx), phase nodes in power
stage, BOOTx signals, output switching pulse currents, driving
bias traces and input inductor ripple current signals, etc.
7. Place the 10µF decoupling ceramic capacitor at the PVCC pin
and as close as possible to the IC. Put multiple vias close to
the ground pad of this capacitor.
8. Place the 1µF decoupling ceramic capacitor at the VCC pin
and as close as possible to the IC. Put multiple vias close to
the ground pad of this capacitor.
9. Keep the bootstrap capacitors as close as possible to the IC.
10. Keep the driver traces as short as possible and with relatively
large width (25mil to 40mil is recommended), and avoid
using via or minimal number of vias in the driver path to
achieve the lowest impedance.
FIGURE 68. RECOMMENDED LAYOUT PATTERN FOR CURRENT
SENSE TRACES REGULATOR
11. Place the current sense setting resistors and the filter
capacitors (shown as RSETxB, RBIASxB and CISENx in Figure 60
on page 31) as close as possible to the IC. Keep each pair of
the traces close to each other to avoid undesired switching
noise injections.
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FN8808.2
February 24, 2016
ISL78227
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
February 24, 2016
FN8808.2
-Figure 16 on page 17:
changed the label "IL1" to "IL2" and in figure title, changed "PHASE1" to "PHASE 2".
-Updated POD L32.5x5H to most recent revision with change as follows:
Detail "X" - Added dimple dimension 0.10 ±0.05 back on (left side).
Detail "X" - Changed the tolerance back (in the seating plane box) to 0.08.
Bottom View - Removed 0.15 ±0.10 this is a duplicate dim with detail A.
Bottom View - Extended the dimension line to the bottom of the exposed pad
December 24, 2015
FN8808.1
Updated expression Qp and Equation 35 on page 39.
Removed text after Equation 35 on page 39 and before paragraph that begins with “Equation 33”.
November 23, 2015
FN8808.0
Initial Release
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FN8808.2
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ISL78227
Package Outline Drawing
L32.5x5H
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN WITH WETABLE FLANK)
Rev 2, 1/16
5.00
A
PIN 1
INDEX AREA
SEE DETAIL “A”
3.3
4.75
4X 0.42 ±0.18
2X
N
5
0.50
DIAMETER
2X
0.10 C A
0.10 C B
1
2
3
4X 0.42 ±0.18
4.75
0.10 M C A B
PIN #1 ID
R0.20
N
0.45
1
2
3
3.3
5.00
0.10 M C A B
0.10 C B
2X
(0.45)
0.40 ±0.10
B
0.10 C A
2X
0.25 ±0.05
0.10 M C A B
0.05 M C
0.50
(0.45)
TOP VIEW
BOTTOM VIEW
SEE DETAIL “X”
0.85 ±0.05
0.50
0.15 ±0.10
SIDE VIEW
0.15 ±0.05
0.40 ±0.10
0 - 12
0.25 ±0.05
0.10 M C A B
C
0.10 ±0.05
SEATING PLANE
0.08 C
4
DETAIL “A”
0.00 MIN
0.05 MAX
DETAIL “X”
NOTES:
(4.80)Sq
28X (0.50)
(3.30)Sq
32X (0.25)
1.
Dimensions are in millimeters.
Dimensions in ( ) for reference only.
2.
Dimensioning and tolerancing conform to ASMEY 14.5m-1994.
3.
Unless otherwise specified, tolerance: Decimal ± 0.05
4.
Dimension applies to the plated terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
6.
Reference document: JEDEC MO220
32X (0.60)
TYPICAL RECOMMENDED LAND PATTERN
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either a mold or mark feature.
FN8808.2
February 24, 2016
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