X9C303 ® Logarithmic Digitally Controlled Potentiometer (XDCP™) Data Sheet January 24, 2007 Terminal Voltage ±5V, 100 Taps, Log Taper FN8223.1 Features • Solid-state potentiometer Description • Three-wire serial interface The Intersil X9C303 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a three-wire interface. • 100 wiper tap points - Wiper position stored in nonvolatile memory and recalled on power-up • 99 resistive elements, log taper - Temperature compensated - End to end resistance, 32kΩ ±15% - Terminal voltages, ±5V The resistor array is composed of 99 resistive elements. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. • Low power CMOS - VCC = 5V - Active current, 3mA max. - Standby current, 750µA max. The device can be used as a three-terminal potentio-meter or as a two-terminal variable resistor in a wide variety of applications ranging from control, to signal processing, to parameter adjustment. Digitally-controlled potentiometers provide three powerful application advantages; (1) the variability and reliability of a solid-state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the use of nonvolatile memory for potentiometer settings retention. • High reliability - Endurance, 100,000 data changes per bit - Register data retention, 100 years • Packages - 8 Ld TSSOP - 8 Ld SOIC - 8 Ld PDIP Block Diagram U/D INC CS 7-Bit Up/Down Counter 99 RH/VH 98 97 7-Bit Nonvolatile Memory 96 One of OneHundred Decoder Transfer Gates Resistor Array 2 VCC VSS Store and Recall Control Circuitry 1 0 RL/VL RW/VW 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9C303 Ordering Information PART NUMBER X9C303P PART MARKING X9C303P TEMPERATURE RANGE (°C) 0 to +70 PACKAGE PKG. DWG. # 8 Ld PDIP MDP0031 X9C303PI X9C303P I -40 to +85 8 Ld PDIP MDP0031 X9C303PIZ (Note) X9C303P ZI -40 to +85 8 Ld PDIP (300 mil) (Pb-free) MDP0031 X9C303PZ (Note) X9C303P Z 0 to +70 8 Ld PDIP (300 mil) (Pb-free) MDP0031 X9C303S8* X9C303S 0 to +70 8 Ld SOIC (150 mil) MDP0027 X9C303S8I* X9C303S I -40 to +85 8 Ld SOIC (150 mil) MDP0027 X9C303S8IZ* (Note) X9C303S ZI -40 to +85 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X9C303S8Z* (Note) X9C303S Z 0 to +70 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X9C303V8* 9C303 0 to +70 8 Ld TSSOP (4.4mm) M8.173 X9C303V8I* C303 I -40 to +85 8 Ld TSSOP (4.4mm) M8.173 X9C303V8IZ* (Note) C303 IZ -40 to +85 8 Ld TSSOP (4.4mm) (Pb-free) M8.173 X9C303V8Z* (Note) 9CC303 Z 8 Ld TSSOP (4.4mm) (Pb-free) M8.173 X9C303S8I-2.7 X9C303S G -40 to +85 8 Ld SOIC (150 mil) MDP0027 X9C303S8IZ-2.7 (Note) X9C303S ZG -40 to +85 8 Ld SOIC (150 mil) (Pb-free) MDP0027 0 to +70 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "T1" suffix for tape and reel. Pin Descriptions Pinout X9C303 (8 LD SOIC, 8 LD TSSOP, 8 LD PDIP) TOP VIEW VH and VL The high (VH) and low (VL) terminals of the device are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is –5V and the maximum is +5V. It should be noted that the terminology of VL and VH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. (CS) INC 1 (VCC) U/D 2 (INC) 3 VH (U/D) V SS X9C303 8 VCC (VL) 7 CS 6 VL (VSS) VW (VH) 5 4 (VW) VW VW is the wiper terminal, equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40Ω. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incriminated or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Chip Select (CS) Pin Names SYMBOL DESCRIPTION VH High Terminal (Potentiometer) VW Wiper Terminal (Potentiometer) VL Low Terminal (Potentiometer) VSS Ground VCC Supply Voltage U/D Up/Down Control Input INC Increment Control Input CS Chip Select Control Input NC No Connection The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the device will be placed in the low power standby mode until the device is selected once again. 2 FN8223.1 January 24, 2007 X9C303 Potentiometer Relationships Instructions and Programming S100 VH (VS) R99 S99 R98 S98 VW S3 R2 S2 R1 S1 VL R1 + R2 + . . . + Ri VW G i = 20Log ------------------------------------------------- = --------- ( V L = 0V ) R V TOTAL S R +R +...+R = R 1 2 99 TOTAL (Refer Test Circuit 1) Principles of Operation There are three sections of the X9C303: the input control, counter and decode section; the nonvolatile memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. Under the proper conditions the contents of the counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of 99 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a seven-bit counter. The output of this counter is decoded to select one of onehundred wiper positions along the resistive array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. The system may select the X9C303, move the wiper, and deselect the device without having to store the latest wiper position in nonvolatile memory. The wiper movement is performed as described above; once the new position is reached, the system would the keep INC LOW while taking CS HIGH. The new wiper position would be maintained until changed by the system or until a power-down/up cycle recalled the previously stored data. This would allow the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference: system parameter changes due to temperature drift, etc... The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. Mode Selection CS INC U/D MODE L H Wiper Up L L Wiper Down H X Store Wiper Position X X Standby Current L X No Store, Return to Standby L H Wiper Up (not recommended) L L Wiper Down (not recommended) H The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered-down, the last counter position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the counter is reset to the value last stored. 3 FN8223.1 January 24, 2007 X9C303 Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Typical Electrical Taper 100.0% 90.0% 80.0% % TOTAL RESISTANCE 70.0% 60.0% 50.0% 40.0% 30.0% 20.0% 10.0% 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 45 48 42 39 36 33 30 27 24 21 18 15 9 R(VH - VW) R(VW - VL) 12 6 3 0 0.0% TAP Test Circuit #1 Test Circuit #2 Circuit #3 SPICE Macro Model VH VH RTOTAL Test Point VS Test Point VW VW VL VL Force Current RH CH CW 10pF 25pF CL RL 10pF RW 4 FN8223.1 January 24, 2007 X9C303 Absolute Maximum Ratings Recommended Operating Conditions Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage on CS, INC, U/D and VCC with Respect to VSS . -1V to +7V Voltage on VH and VL Referenced to VSS . . . . . . . . . . . . -8V to +8V ΔV = |VH - VL| X9C303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C Wiper Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1mA Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C Military Temperature Range. . . . . . . . . . . . . . . . . . .-55°C to +125°C Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10% Power Rating at +25°C X9C303 . . . . . . . . . . . . . . . . . . . . . . .10mW Physical Characteristics Marking Includes Manufacturer’s Trademark Resistance Value or Code Date Code CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Analog Specifications Over recommended operating conditions unless otherwise specified. LIMITS SYMBOL RTOTAL PARAMETER TEST CONDITIONS MIN End-to-End Resistance TYP (NOTE 1) MAX UNIT κΩ 32 End-to-End Resistance Tolerance -15 +15 % VH VH Terminal Voltage -5 +5 V VL VL Terminal Voltage -5 +5 V RW Wiper Resistance Max Wiper Current ±1mA 100 Ω Tap position relative step size error Error = log (Vw(n)) - log (Vw(n - 1)) for tap n = 2 - 99, VH-VL = 10V 0.115 dB Resistor Noise At 1kHz 23 nV(RMS)/ √Hz Charge Pump Noise At 2.5MHz 20 mV(RMS) End-to-End Resistance Temperature Coefficient T = -40°C to +85°C ±400 ppm/°C Ratiometric Temperature Coefficient Tap position 84 ±20 ppm/°C Potentiometer Capacitance See Circuit 3 10/10/25 pF CH/CL/CW (Note 3) DC Electrical Specifications 40 0.005 Over recommended operating conditions unless otherwise specified. LIMITS SYMBOL PARAMETER TEST CONDITIONS ICC Vcc Active Current CS = VIL, U/D = VIL or VIH and INC = 0.4V to 2.4V @ Max tCYC ISB Standby Supply Current CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V ILI CS, INC, U/D Input Leakage Current VIN = VSS to VCC VIH CS, INC, U/D Input HIGH Voltage VIL CS, INC, U/D Input LOW voltage CIN (Note 3) CS, INC, U/D Input Capacitance 5 MIN TYP (NOTE 1) MAX UNIT 1 3 mA 200 750 µA +10 µA -10 2 V 0.8 VCC = 5V, VIN = VSS, TA = +25°C, f = 1MHz 10 V pF FN8223.1 January 24, 2007 X9C303 DC Electrical Specifications Over recommended operating conditions unless otherwise specified. (Continued) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP (NOTE 1) MAX UNIT EEPROM SPECS EEPROM Endurance Wiper storage operations over recommended operation conditions EEPROM Retention At +55°C 100,000 Cycles 100 Years Standard Parts PART NUMBER MAXIMUM RESISTANCE WIPER INCREMENTS MINIMUM RESISTANCE 32kΩ Log Taper 40Ω Typical X9C303 NOTES: 1. Typical values are for TA = +25°C and nominal supply voltage. A.C. Conditions of Test Input pulse levels 0V to 3V Input rise and fall times 10ns Input reference levels 1.5V AC Electrical Specifications Over recommended operating conditions unless otherwise specified. LIMITS SYMBOL PARAMETER MIN TYP (Note 2) MAX UNIT tCl CS to INC Set-up 100 ns tlD INC HIGH to U/D Change 100 ns tDI U/D to INC Set-up 2.9 µs tlL INC LOW Period 1 µs tlH INC HIGH Period 1 µs tlC INC Inactive to CS Inactive 1 µs tCPH CS Deselect Time 20 ms tIW (Note 3) INC to VW Change tCYC tR, tF (Note 3) tPU (Note 3) INC Cycle Time 100 2 µs INC Input Rise and Fall Time 500 Power-up to Wiper Stable tR VCC (Note 3) VCC Power-up Rate 6 µs 500 0.2 ns µs 50 mV/µs FN8223.1 January 24, 2007 X9C303 A.C. Timing CS tCYC tCI tIL tIC tIH tCPH 90% INC 90% 10% tID tDI tF tR U/D tIW MI VW (Note 4) NOTES: 2. Typical values are for TA = +25°C and nominal supply voltage. 3. This parameter is not 100% tested. 4. MI in the A.C. timing diagram refers to the minimum incremental change in the VW output due to a change in the wiper position. 7 FN8223.1 January 24, 2007 X9C303 Thin Shrink Small Outline Plastic Packages (TSSOP) M8.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M L A D -C- e α A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE A2 c 0.10(0.004) C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX α 8 0o 8 7 8o Rev. 1 12/00 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 8 FN8223.1 January 24, 2007 X9C303 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference N 8 14 16 Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 9 FN8223.1 January 24, 2007 X9C303 Plastic Dual-In-Line Packages (PDIP) E D A2 SEATING PLANE L N A PIN #1 INDEX E1 c e b A1 NOTE 5 1 eA eB 2 N/2 b2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE A 0.210 0.210 0.210 0.210 0.210 MAX A1 0.015 0.015 0.015 0.015 0.015 MIN A2 0.130 0.130 0.130 0.130 0.130 ±0.005 b 0.018 0.018 0.018 0.018 0.018 ±0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 D 0.375 0.750 0.750 0.890 1.020 ±0.010 E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 E1 0.250 0.250 0.250 0.250 0.250 ±0.005 e 0.100 0.100 0.100 0.100 0.100 Basic eA 0.300 0.300 0.300 0.300 0.300 Basic eB 0.345 0.345 0.345 0.345 0.345 ±0.025 L 0.125 0.125 0.125 0.125 0.125 ±0.010 N 8 14 16 18 20 Reference NOTES 1 2 Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN8223.1 January 24, 2007