Data Sheet

HEF4104B-Q100
Quad low-to-high voltage translator with 3-state outputs
Rev. 1 — 24 March 2014
Product data sheet
1. General description
The HEF4104B-Q100 is a quad low voltage-to-high voltage translator with 3-state outputs.
It provides the capability of interfacing low voltage circuits to high-voltage circuits. For
example, low voltage Local Oxidation Complementary MOS (LOCMOS) and
Transistor-Transistor Logic (TTL) to high-voltage LOCMOS. It has four data inputs (A0 to
A3) and an active HIGH output enable input (OE). It also has four data outputs (B0 to
B3) with their complements (B0 to B3).
With OE = HIGH, the outputs B0 to B3 and B0 to B3 are in the low impedance ON-state.
The inputs A0 to A3 determine whether it is HIGH or LOW. With OE = LOW, the outputs
B0 to B3 and B0 to B3 are in the high-impedance OFF-state.
It uses a common negative supply (VSS) and separate positive supplies for the inputs
(VDD(A)) and the outputs (VDD(B)). VDD(A) must always be less than or equal to VDD(B), even
during power turn-on and turn-off. For the permissible operating range of VDD(A) and
VDD(B), see Figure 4.
Each input protection circuit is terminated between VDD(B) and VSS. It allows the input
signals to be driven from any potential between VDD(B) and VSS, without regard to current
limiting. When driving from potentials greater than VDD(B) or less than VSS, the current at
each input must be limited to 10 mA.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 3)
 Specified from 40 C to +85 C
 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 Inputs and outputs are protected against electrostatic effects
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Complies with JEDEC standard JESD 13-B
HEF4104B-Q100
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
3. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C.
Type number
Package
Name
HEF4104BT-Q100 SO16
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
4. Functional diagram
VDD(A)
VDD(B)
16
1
3
A0
4
B0
LEVEL
CONVERTER
A0
2
B0
B0
B0
A1
6
5
7
A2
11
LEVEL
CONVERTER
B1
LEVEL
CONVERTER
A1
B1
B1
LEVEL
CONVERTER
A2
10
B1
B2
B2
B2
9
A3
B2
LEVEL
CONVERTER
A3
12
13
B3
B3
LEVEL
CONVERTER
OE
14
OE
15
B3
B3
VDD(A)
VDD(B)
001aag264
8
VSS
Fig 1.
Logic symbol
HEF4104B_Q100
Product data sheet
001aag262
Fig 2.
Logic diagram
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Quad low-to-high voltage translator with 3-state outputs
5. Pinning information
5.1 Pinning
+()%4
9''%
9''$
%
2(
%
%
$
%
$
$
%
$
%
%
966
%
DDD
Fig 3.
Pin configuration
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
VDD(B)
1
supply voltage port B
B0 to B3
2, 7, 9, 14
complementary data output
B0 to B3
3, 6, 10, 13
data output
A0 to A3
4, 5, 11, 12
data input
VSS
8
common negative supply voltage (0 V)
OE
15
output enable input
VDD(A)
16
supply voltage port A
6. Functional description
Table 3.
Function table[1]
Control
Output
OE
Bn
Bn
H
An
An
L
Z
Z
[1]
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
HEF4104B_Q100
Product data sheet
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Rev. 1 — 24 March 2014
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NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD(A)
supply voltage A
port A; VDD(A)  VDD(B)
0.5
+18
V
VDD(B)
supply voltage B
port B; VDD(B)  VDD(A)
0.5
+18
V
IIK
input clamping current
VI < 0.5 V or VI > VDD(A) + 0.5 V
-
10
mA
VI
input voltage
0.5
VDD(A) + 0.5 V
IOK
output clamping current
-
10
-
10
mA
-
50
mA
65
+150
C
40
+85
C
II/O
input/output current
IDD
supply current
Tstg
storage temperature
Tamb
ambient temperature
VO < 0.5 V or VO > VDD(B) + 0.5 V
[1]
Ptot
total power dissipation
Tamb = 40 C to +85 C
P
power dissipation
per output
[1]
IDD is the combined current of IDD(A) and IDD(B).
[2]
For SO16 packages: above Tamb = 70 C, Ptot derates linearly at 8 mW/K.
[2]
mA
-
500
mW
-
100
mW
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VDD(A)
VDD(B)
Min
Typ
supply voltage A
3
-
 VDD(B)
V
supply voltage B
 VDD(A)
-
15
V
VI
input voltage
0
-
VDD(A)
V
Tamb
ambient temperature
in free air
40
-
+85
C
t/V
input transition rise and fall rate
VDD(A) = 5 V
-
-
3.75
s/V
VDD(A) = 10 V
-
-
0.5
s/V
VDD(A) = 15 V
-
-
0.08
s/V
HEF4104B_Q100
Product data sheet
Conditions
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
Max
Unit
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Quad low-to-high voltage translator with 3-state outputs
9. Static characteristics
Table 6.
Static characteristics
VDD(A) = VDD(B); VSS = 0 V; VI = VSS or VDD(A); unless otherwise specified.
Symbol Parameter
Conditions
Tamb = 40 C Tamb = +25 C Tamb = +85 C Unit
VDD[1]
Min
HIGH-level
input voltage
VIH
LOW-level
input voltage
VIL
VOH
VOL
IO < 1 A
LOW-level
output voltage
IO < 1 A
LOW-level
output current
IOL
supply current
IDD
OFF-state
output current
IOZ
input capacitance
CI
Max
5V
3.5
-
3.5
-
3.5
-
V
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
V
5V
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
V
mA
5V
-
1.7
-
1.4
-
1.1
5V
-
0.52
-
0.44
-
0.36 mA
VO = 9.5 V
10 V
-
1.3
-
1.1
-
0.9
mA
VO = 13.5 V
15 V
-
3.6
-
3.0
-
2.4
mA
VO = 0.4 V
5V
0.52
-
0.44
-
0.36
-
mA
VO = 0.5 V
10 V
1.3
-
1.1
-
0.9
-
mA
VO = 1.5 V
15 V
3.6
-
3.0
-
2.4
-
mA
-
0.3
-
0.3
-
1.0
A
15 V
-
20
-
20
-
150
A
10 V
-
40
-
40
-
300
A
15 V
-
80
-
80
-
600
A
HIGH level;
VO = VDD(B)
15 V
-
1.6
-
1.6
-
12.0
A
LOW level;
VO = VSS
15 V
-
1.6
-
1.6
-
12.0 A
digital inputs
-
-
-
-
7.5
-
all valid input
combinations;
IO = 0 A
[1]
VDD is the same as VDD(A) and VDD(B).
IDD is the combined current of IDD(A) and IDD(B).
Product data sheet
Min
VO = 2.5 V
[2]
HEF4104B_Q100
Max
VO = 4.6 V
input leakage current
II
Min
10 V
IO < 1 A
HIGH-level
output voltage
HIGH-level
output current
IOH
IO < 1 A
Max
5V
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
-
pF
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Quad low-to-high voltage translator with 3-state outputs
001aag265
15
VDD(B)
(V)
operating area
10
5
0
0
5
10
15
VDD(A) (V)
The shaded area shows the permissible operating range.
Fig 4.
VDD(B) as a function of VDD(A)
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Tamb = 25 C, unless otherwise specified. For test circuit, see Figure 7.
Symbol Parameter
tPHL
tPLH
tTHL
tTLH
tPHZ
HIGH to LOW
propagation delay
LOW to HIGH
propagation delay
Extrapolation formula[1]
Min
Typ
Max
Unit
VDD(A) = VDD(B) = 5 V
143 ns + (0.55 ns/pF)CL
-
170
340
ns
VDD(A) = VDD(B) = 10 V
69 ns + (0.23 ns/pF)CL
-
80
160
ns
VDD(A) = VDD(B) = 15 V
57 ns + (0.16 ns/pF)CL
-
65
135
ns
143 ns + (0.55 ns/pF)CL
-
170
340
ns
VDD(A) = VDD(B) = 10 V
69 ns + (0.23 ns/pF)CL
-
80
160
ns
VDD(A) = VDD(B) = 15 V
62 ns + (0.16 ns/pF)CL
-
70
140
ns
10 ns + (1.00 ns/pF)CL
-
60
120
ns
VDD(A) = VDD(B) = 10 V
9 ns + (0.42 ns/pF)CL
-
30
60
ns
VDD(A) = VDD(B) = 15 V
6 ns + (0.28 ns/pF)CL
-
20
40
ns
10 ns + (1.00 ns/pF)CL
-
60
120
ns
VDD(A) = VDD(B) = 10 V
9 ns + (0.42 ns/pF)CL
-
30
60
ns
VDD(A) = VDD(B) = 15 V
6 ns + (0.28 ns/pF)CL
-
20
40
ns
VDD(A) = VDD(B) = 5 V
-
70
135
ns
VDD(A) = VDD(B) = 10 V
-
55
110
ns
VDD(A) = VDD(B) = 15 V
-
60
120
ns
Conditions
An to Bn, Bn; see Figure 5
An to Bn, Bn; see Figure 5
VDD(A) = VDD(B) = 5 V
HIGH to LOW output Bn or Bn; see Figure 6
transition time
VDD(A) = VDD(B) = 5 V
LOW to HIGH output Bn or Bn; see Figure 6
transition time
VDD(A) = VDD(B) = 5 V
HIGH to OFF-state
propagation delay
HEF4104B_Q100
Product data sheet
OE to Bn, Bn; see Figure 6
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Quad low-to-high voltage translator with 3-state outputs
Table 7.
Dynamic characteristics …continued
Tamb = 25 C, unless otherwise specified. For test circuit, see Figure 7.
Extrapolation formula[1]
Symbol Parameter
Conditions
tPLZ
OE to Bn, Bn; see Figure 6
LOW to OFF-state
propagation delay
OFF-state to HIGH
propagation delay
tPZH
OFF-state to LOW
propagation delay
tPZL
[1]
Min
Typ
Max
Unit
VDD(A) = VDD(B) = 5 V
-
70
135
ns
VDD(A) = VDD(B) = 10 V
-
55
105
ns
VDD(A) = VDD(B) = 15 V
-
55
110
ns
VDD(A) = VDD(B) = 5 V
-
195
395
ns
VDD(A) = VDD(B) = 10 V
-
95
195
ns
VDD(A) = VDD(B) = 15 V
-
80
165
ns
VDD(A) = VDD(B) = 5 V
-
195
395
ns
VDD(A) = VDD(B) = 10 V
-
95
190
ns
VDD(A) = VDD(B) = 15 V
-
80
160
ns
OE to Bn, Bn; see Figure 6
OE to Bn, Bn; see Figure 6
Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).
Table 8.
Dynamic power dissipation
VDD(A) = VDD(B); VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.
Symbol Parameter
dynamic power
dissipation
PD
VDD[1] Typical formula (W)
where
5V
PD = 3000  fi + (fo  CL)  VDD
10 V
PD = 12200  fi + (fo  CL)  VDD
15 V
PD = 31000  fi + (fo  CL)  VDD2
2
fi = input frequency in MHz;
2
fo = output frequency in MHz;
CL = output load capacitance in pF;
(fo  CL) = sum of the outputs;
VDD = supply voltage in V.
[1]
VDD is the same as VDD(A) and VDD(B).
HEF4104B_Q100
Product data sheet
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Quad low-to-high voltage translator with 3-state outputs
11. Waveforms
VI
An input
VM
0V
tPHL
VOH
tPLH
VY
Bn output
VM
VX
VOL
tTHL
tTLH
tPLH
VOH
tPHL
VY
Bn output
VX
VOL
tTLH
tTHL
001aaj783
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
Data input (An) to data output (Bn, Bn) propagation delays and output transition times
VI
OE input
VM
VSS
tPLZ
output
LOW-to-OFF
OFF-to-LOW
tPZL
VOH
VY
VX
VOL
tPHZ
VOH
tPZH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VX
VOL
outputs on
outputs off
outputs on
001aaj782
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
Table 9.
Enable and disable times
Measurement points
Input
Output
VI
VM
VM
VX
VY
VSS or VDD(A)
0.5VDD(A)
0.5VDD(B)
0.1VDD(B)
0.9VDD(B)
HEF4104B_Q100
Product data sheet
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Quad low-to-high voltage translator with 3-state outputs
tW
VI
90 %
90 %
negative
pulse
VM
VM
10 %
0V
10 %
tf
tr
tr
tf
VI
90 %
positive
pulse
90 %
VM
VM
10 %
0V
10 %
tW
001aaj781
a. Input waveforms
VEXT
VDD
VI
RL
VO
G
DUT
RT
CL
001aaj915
b. Test circuit
Test data given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 7.
Test circuit for measuring switching times
Table 10.
Test data
Supplies
Input
Load
VDD(A) = VDD(B)
tr, tf
RL
CL
tPHL, tPLH
tPZL, tPLZ
tPZH, tPHZ
5 V to 15 V
 20 ns
1 k
50 pF
open
VDD(B)
VSS
HEF4104B_Q100
Product data sheet
VEXT
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Quad low-to-high voltage translator with 3-state outputs
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 8.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT109-1 (SO16)
HEF4104B_Q100
Product data sheet
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Rev. 1 — 24 March 2014
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13. Abbreviations
Table 11.
Abbreviations
Acronym
Description
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
MIL
Military
14. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4104B_Q100 v.1
20140324
Product data sheet
-
-
HEF4104B_Q100
Product data sheet
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF4104B_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
12 of 14
HEF4104B-Q100
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4104B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 14
HEF4104B-Q100
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 March 2014
Document identifier: HEF4104B_Q100