TPS65910x Schematic Checklist Version B Application Report Literature Number: SWCA139B April 2012 – Revised September 2012 WARNING: EXPORT NOTICE Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorisation from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws. This provision shall survive termination or expiration of this Agreement. According to our best knowledge of the state and end-use of this product or technology, and in compliance with the export control regulations of dual-use goods in force in the origin and exporting countries, this technology is classified as follows: US ECCN: EAR99 EU ECCN: EAR99 And may require export or re-export license for shipping it in compliance with the applicable regulations of certain countries. Application Report SWCA139B – April 2012 – Revised September 2012 TPS65910x Schematic Checklist ..................................................................................................................................................... ABSTRACT This application note for TPS65910x, a power companion device for application processors (see the device data sheet) lists the connection details for each pin. The ball details include a brief explanation of the function of each pin or signal and whether the signal is analog or digital. Use this information to check the connectivity for each ball on a system schematic. In addition to this list, customers are advised to use the information in the data sheet, (TI literature number SWCS046). NOTE: Customer must ensure that the power-up sequence for the application processor is met. This document does not cover the details of the power-up sequence for TPS65910 or the application processor. Refer to the device data sheet and the reference designs for the application processors for the correct power-up sequence requirements. 1 Recommended Operating Conditions Parameter Test Conditions VCC: Input voltage range on pins/balls VCC1, VCC2, VCCIO, VCC3, VCC4, VCC5, VCC7 (1) (2) Min Nom Max Unit 2.7 3.6 5.5 V VCCP: Input voltage range on pins/balls VCC6 1.7 3.6 5.5 V Input voltage range on pins/balls VDDIO (3) 1.65 1.8/3.3 3.45 V Input voltage range on pins/balls PWRON 0 3.6 5.5 V Input voltage range on pins/balls SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1, SLEEP 1.65 VDDIO 3.45 V Input voltage range on pins/balls PWRHOLD, GPIO_CKSYNC 1.65 VDDIO 5.5 V Input voltage range on balls BOOT1, BOOT0, OSC32KIN 1.65 VRTC 1.95 V (1) (2) (3) VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that VCC2 and VCC4 can be higher than VCC7. VCC2 and VCC4 must be connected together (to the same voltage). If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3. SmartReflex is a trademark of Texas Instruments. SWCA139B – April 2012 – Revised September 2012 Copyright © 2012, Texas Instruments Incorporated TPS65910x Schematic Checklist 3 TPS65910x Schematic Checklist 2 www.ti.com TPS65910x Schematic Checklist Table 1. TPS65910x Schematic Checklist Name BGA Pin Type I/O (1) Description Recommended Connection (2) Not Used Features PWRHOLD 1 Digital I Switch on, switch off control signal, mode defined in EEPROM Switch-on, switch-off mode: Can be connected to an external signal for PMIC power-up/powerdown control Floating (internal pulldown or active by default) If control is not required, then can be tied to VRTC VMMC 2 Power O LDO regulator output Connect to a 2.2-µF filter capacitor Floating VCC3 3 Power I VMMC and VAUX33 power input Connect to VBAT with a 4.7-µF capacitor Connected to VCCs VAUX33 4 Power O LDO regulator output Connect to a 2.2-µF filter capacitor Floating VDIG2 5 Power O LDO regulator output Connect to a 2.2-µF filter capacitor Floating Connected to VCCs VCC6 6 Power I VDIG1 and VDIG2 power input Connect to VBAT with a 4.7-µF capacitor. Needs external input or preregulated output from TPS65910x VDIG1 7 Power O LDO regulator output Connect to a 2.2-µF filter capacitor Floating External 1.2-k pullup to I/O supply N/A External 1.2-k pullup to I/O supply N/A SDA_SDI 8 Digital I/O I2C bidirectional data signal/serial peripheral interface data input (multiplexed) SCL_SCK 9 Digital I/O I2C bidirectional clock signal/serial peripheral interface clock input (multiplexed) 2 SDASR/EN2 10 Digital I/O Enable for supplies/voltage scaling dedicated I2C data Processor I C for SmartReflex™ control with external pullup to VIO or connected to GPIO for Floating DC-DC/LDO control; external1.2-k pullup to I/O supply Enable for supplies/voltage scaling dedicated I2C clock Processor I2C for SmartReflex control with external pullup to VIO or connected to GPIO for Floating DC-DC/LDO control; external1.2-k pullup to I/O supply SCLSR/EN1 11 Digital I/O VDDIO 12 Power I Digital I/Os supply Connect to system I/O supply: an external I/O supply or I/O supply provided by TPS65910x (usually VIO). N/A VCCIO 13 Power I VIO DC-DC power Input Connect to VBAT with a 10-µF capacitor Connected to VCCs Floating SWIO 14 Power O VIO DC-DC switched output Connected to a 2.2-µH inductor and a 10-µF capacitor to ground GNDIO 15 Power I/O VIO DC-DC power ground GND GND VIO feedback voltage Connected to a 2.2-µH inductor (other node that is away from the device) GND or floating (internal pulldown) VFBIO (1) (2) 4 16 Analog I I = Input; O = Output; OD = Open Drain VBAT is the battery or any input source other than preregulation. The maximum level is 5.5 V. TPS65910x Schematic Checklist SWCA139B – April 2012 – Revised September 2012 Copyright © 2012, Texas Instruments Incorporated TPS65910x Schematic Checklist www.ti.com Table 1. TPS65910x Schematic Checklist (continued) BGA Pin Type REFGND 17 Analog I/O Reference ground Connect to AGND (clean ground), same as 32K crystal GND N/A VREF 18 Analog O Bandgap voltage Connect to 0.1-µF capacitor to REFGND. Capacitor close to device N/A BOOT1 19 Digital I Power-up sequence selection Connect to VRTC for the EEPROM boot up sequence N/A 32-kHz crystal oscillator Depending on EEPROM configuration: – If RC oscillator, then OSC32KIN: grounded – If crystal oscillator, then crystal oscillator connected to OSC32KIN – If bypass clock, then OSC32KIN: input N/A N/A Name OSC32KIN 20 Analog I/O (1) I Description Recommended Connection (2) Not Used Features OSC32KOUT 21 Analog I 32-kHz Crystal oscillator Depending on EEPROM configuration: – If RC oscillator, then OSC32KOUT: floating – If crystal oscillator, then crystal oscillator connected to OSC32KOUT – If bypass clock, then OSC32KOUT: floating VDAC 22 Power O LDO regulator output Connect to a 2.2-µF filter capacitor Floating VCC5 23 Power I VDAC and VPLL power input Connec to VBAT with a 4.7-µF capacitor Connected to VCCs VPLL 24 Power O LDO regulator output Connect to a 2.2-µF filter capacitor Floating TESTV 25 Analog O Analog test output (DFT) Floating Floating BOOT0 26 Digital I Digital I Power-up sequence selection Connect to GND for the EEPROM boot up N/A Connected to VCC7 VBACKUP 27 Power I Backup battery input Backup battery - supercap or rechargeable coincell; CBB = 10 mF VCC7 28 Power I VRTC power input and analog references supply VBAT (5.5-V maximum) or other preregulated supply. Must be first supply provided for TPS65910x. Connect to a 4.7-μF filter capacitor N/A VRRTC 29 Power O LDO regulator output Connect to a 2.2-µF filter capacitor N/A GND VFB3 30 Analog I VDD3 feedback voltage Connect to an LED and to a 10-µF capacitor to GND. See page 2 of the datasheet. SW3 31 Power O VDD3 DC-DC switched output Connect to a LED and to a 4.7-µH inductor to VBAT and use a 4.7-µF input capacitor. See page 2 of the datasheet. Floating VFB1 32 Analog I VDD1 feedback voltage Connected to a 2.2-µH inductor (other node that is away from the device) GND or floating (internal pulldown) PWRON 33 Digital I External switch-on control (on button) Push-button. PWRON transition low will power up PMIC Floating (internal pullup active by default) GND1 34 Power I/O VDD1 DC-DC power ground GND GND VDD1 DC-DC switched output Connected to a 2.2-µH inductor and a 10-µF capacitor to ground Floating SW1 35 Power O SWCA139B – April 2012 – Revised September 2012 TPS65910x Schematic Checklist Copyright © 2012, Texas Instruments Incorporated 5 TPS65910x Schematic Checklist www.ti.com Table 1. TPS65910x Schematic Checklist (continued) Name VCC1 BGA Pin Type I/O 36 Power I (1) Description Recommended Connection (2) Not Used Features VDD1 DC-DC power input Connect to VBAT with a 10-µF capacitor Connected to VCCs GND or floating SLEEP 37 Digital I ACTIVE-to-SLEEP state transition control signal Connected to processor control pin (that is, GPIO or any other low-power mode control pin). The polarity of SLEEP signal is set in DEVCTRL2_REG.SLEEPSIG_POL. CLK32KOUT 38 Digital O 32-kHz clock output To processor 32K clock input Floating GPIO (GPI with PU set by default) or DC-DCs synchronization clock input Floating GPIO_CKSYNC 39 Digital I/O Configurable general-purpose I/O or DC-DCs synchronization clock input signal NRESPWRON 40 Digital O Power off reset Connect to reset input of the processor or any other similar function to show device power up is complete N/A VCC2 41 Power I VDD2 DC-DC power input Connect to VBAT with a 10-µF capacitor Connected to VCCs Floating SW2 42 Power O VDD2 DC-DC switched output Connected to a 2.2-µH inductor and a 10-µF capacitor to ground GND2 43 Power I/O VDD2 DC-DC power ground GND GND VFB2 44 Analog I VDD2 DC-DC feedback voltage Connected to a 2.2-µH inductor (other node that is away from the device) GND or floating (internal pulldown) INT1 45 Digital O Interrupt flag Connect to the processor interrupt pin or a GPIO (optional) Floating VAUX1 46 Power O LDO regulator output Connect to a 2.2-µF filter capacitor Floating VCC4 47 Power I VAUX1 and VAUX2 power input Connect to VBAT with a 4.7-µF capacitor GND if VAUX1 and VAUX2 are not used VAUX2 48 Power O LDO regulator output Connect to a 2.2-µF filter capacitor Floating 6 TPS65910x Schematic Checklist SWCA139B – April 2012 – Revised September 2012 Copyright © 2012, Texas Instruments Incorporated Revision History www.ti.com 3 Revision History The following table summarizes the TPS65910x Schematic Checklist versions. Note: Numbering may vary from previous versions. (1) (2) (3) Version Literature Number Date * SWCA139 April 2012 See Notes (1) A SWCA139A May 2012 See (2) B SWCA139B September 2012 See (3) TPS65910x Schematic Checklist, (SWCA139) - initial release. TPS65910x Schematic Checklist, (SWCA139A) • Update Table 1 - Update OSC32KIN and OSC32KOUT Recommended Connection and Not Used Features TPS65910x Schematic Checklist, (SWCA139B) • Update Table 1 - Update VBACKUP: Replace Connected to VCC5 by Connected to VCC7 SWCA139B – April 2012 – Revised September 2012 Copyright © 2012, Texas Instruments Incorporated TPS65910x Schematic Checklist 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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