5 4 3 2 1 KSZ8462_8441_8852 Eval Board Revision 1.2 REVISION HISTORY Table of Contents D D DATE: DESCRIPTION REVISION 12/17/2010 Initial release 1.0 11/16/2011 2.5V/1.8V regulator schematic is corrected 1.1 2/27/2015 Change schematic title (was KSZ8462HLL_LQFP Demo Board) 1.2 Revise U11: part number, signal names for pins 6, 16, 40, 51 (sheet 2) PAGE PAGE PAGE PAGE PAGE PAGE PAGE 01: 02: 03: 04: 05: 06: 07: Revision History KSZ8462HL Device and CPU Port Device Configuration and LEDs Ethernet Interface Fiber Interface1 Fiber interface2 Power Revise names for low voltage (formerly 1.2V) global power nodes. Move pin 16 to VDD_AL and remove VDD_COL1.2 (sheets 2, 7). Change values of crystal load caps.(sheet 2) Remove R8-R11, JP77 and JP78 on FXSD1 and FXSD2 (sheet 2) Remove TP9, X1 and X2 (sheet 2) Correct U2 part number (sheet 2) Remove R6 (sheet 2) C C Change pull-down strapping resistors R123, 127 and 129 from 1k to 4.7k (sheet 3) Add test points TP11 and TP12 to P1LED1 and P2LED1 (sheet 3) Change line-side TVS diode device part number (sheet 4) Separate center taps on line side of magnetics (sheet 4) Simplify termination of unused RJ-45 pairs (sheet 4) Chassis GND connection: replace R242, R243 with FB30, FB31 (sheet 4) Remove chip-side termination for fiber interface (R62, R63, C17, R72-R75, C24, R195-R198, R84, R90, C38, R85, R78, R91, R83, C39, R212, R206, R207, R209) (sheets 5 & 6) Update values for fiber termination resistors. (sheets 5 & 6) Remove extra jumper JP408 on VDD_L. (sheet 7) Remove extra ferrite bead FB19 (sheet 7) Update U4 part number. (sheet 7) B B A A CONFIDENTIAL & PROPRIETARY Title KSZ8462_8441_8852 EVAL BOARD Size Document Number Rev 1.2 Revision History Date: 5 4 3 2 Friday, February 27, 2015 Sheet 1 1 of 7 4 3 2 VDD_IO Serial EEPROM MAC Address / User Data JP409 D R218 1K 8 7 6 5 VCC NC ORG GND 2X1 MBR0520L D16 U2 CS SK DI DO RSTN R241 PME_EESEL R235 C117 R15 R16 R17 R22 R26 4.7K 4.7K 4.7K 4.7K CPU_RSTN CPU_PME 33 33 INTRN R215 33 VDD_L SD0 SD1 SD2 SD3 SD4 SD5 SD6 R240 R239 R238 R237 R236 R234 R233 33 33 33 33 33 33 33 33 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GPIO1 GPIO2 GPIO3_EESK GPIO4_EEDIO GPIO5_EECS R226 33 R217 R225 R227 R224 33 33 33 33 R228 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 C GPIO6 Sht.3 Sht.3 Sht.3 Sht.3 P1LED1 P1LED0 P2LED1 P2LED0 Sht.5 FXSD1 P1LED1 P1LED0 P2LED1 P2LED0 RST_SWN KSZ_FXSD1 J12 1 3 2 4 CON4A + C6 GPIO1 DGND VDD_L GPIO2 GPIO3/EESK GPIO4/EEDIO GPIO5/EECS VDD_IO DGND GPIO6 P1LED1 P1LED0/H816 P2LED1 P2LED0/LEBE RSTN FXSD1 KSZ8462HL / FHL SD7 SD8 VDD_IO DGND SD9 SD10 SD11 SD12 SD13 SD14 SD15 VDD_IO DGND X2 X1 PWRDN 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 Note: place series resistors near pins of U11 SD7 SD8 R232 R231 33 33 CPU_D7 CPU_D8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 R230 R229 R223 R222 R221 R220 R219 33 33 33 33 33 33 33 CPU_D9 CPU_D10 CPU_D11 CPU_D12 CPU_D13 CPU_D14 CPU_D15 CPU_D1 CPU_D3 CPU_D5 CPU_D7 CPU_D9 CPU_D11 CPU_D13 CPU_D15 Y1 25MHz CL=18pF 22pF Power_ON Reset + C C2 22pF LAIRD 2X1 HI1206N101R-10 +5V Chip Power Down (active low) 1 3 TXM2 TXP2 RXM2 RXP2 TXM1 TXP1 S2 1 3 B RXM1 RXP1 10K CPU_D0 CPU_D2 CPU_D4 CPU_D6 CPU_D8 CPU_D10 CPU_D12 CPU_D14 2X1 KSZ_FXSD2 Push Button Reset Note: CPU_D[15:8] must be tied to GND in 8-bit bus mode. 90131-0780 FB24 1 2 FBEAD J13 R5 Note: VDD_IO must be compatible with master plugged into parallel port. JP3 C1 JP2 10UF DNI D2 MBR0520L 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 CPU_D[15:0] VDD_AL +3.3A VDD_AL VDD_IO J16 X2 X1 PWRDN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1-2 for Fiber, 3-4 for RJ45 GPIO0 CSN PME/EESEL WRN RDN INTRN CMD SD0 VDD_L DGND SD1 SD2 SD3 SD4 SD5 SD6 GPIO Header CPU_D0 CPU_D1 CPU_D2 CPU_D3 CPU_D4 CPU_D5 CPU_D6 Note: KSZ8462HL is parallel port slave device VDD_IO Sht.3 D U11 RXM1 RXP1 AGND TXM1 TXP1 VDD_AL ISET AGND VDD_A3.3 RXM2 RXP2 AGND TXM2 TXP2 FXSD2 VDD_COL VDD_IO CPU_PME CPU_CSN CPU_WRN CPU_RDN CPU_INTRN CPU_CMD 0.1uF 93C46 R216 VDD_IO VDD_IO 4.7K Note: ORG = "1" for x16 organization GPIO0 VDD_IO VDD_IO NOTE: install jumper for bi-directional RSTN VDD_IO 1 2 3 4 1 CPU_+5V 5 C116 0.1uF 2 4 CON4A 1-2 for Fiber, 3-4 for RJ45 2 4 SW PUSHBUTTON B + C4 C5 10UF DNI R4 6.49K 10UF TP10 FXSD2 FXSD2 DIFFERENTIAL_PAIR = DP2 DIFFERENTIAL_PAIR = DP2 DIFFERENTIAL_PAIR = DP4 DIFFERENTIAL_PAIR = DP4 Note: The KSZ8852 and KSZ8441 are footprint compatible with the KSZ8462. DIFFERENTIAL_PAIR = DP1 DIFFERENTIAL_PAIR = DP1 DIFFERENTIAL_PAIR = DP3 DIFFERENTIAL_PAIR = DP3 Sht.6 TXP2 TXM2 Sht.6 Sht.6 RXP2 RXM2 Sht.6 Sht.6 TXP1 TXM1 Sht.5 Sht.5 RXP1 RXM1 Sht.5 Sht.5 GPIO HEADER A A J15 GPIO6 GPIO5_EECS GPIO4_EEDIO GPIO3_EESK GPIO2 GPIO1 GPIO0 13 11 9 7 5 3 1 14 12 10 8 6 4 2 CONFIDENTIAL & PROPRIETARY Title KSZ8462_8441_8852 EVAL BOARD 2x7 Size Document Number Rev 1.2 KSZ8462 Device and CPU Port Date: 5 4 3 2 Friday, February 27, 2015 Sheet 1 2 of 7 5 4 3 +3.3V_EXT FDY3000NZ Q1-1 D Sht.2 For KSZ8441, do not install LEDs and transistors for port 2, but do install JP302 and resistors. SPEED D14 6 1 FDY3000NZ Q1-2 SC89 Sht.2 R31 220 2 P1LED1 1 +3.3V_EXT R60 220 TP11 2 P1_LED1 1 P1_LED0 3 2 4 LEDX2 D LINK / ACT 3 LEDs may be powered from VDD_IO at 3.3V or 2.5V. Do not power from VDD_IO when it is 1.8V; instead power them from the 3.3V supply as shown here. 5 P1LED0 The KSZ8462 / 8441 / 8852 can drive LEDs as shown here, or it can drive them directly (pulled low) without external transistors. 4 SC89 +3.3V_EXT R188 220 FDY3000NZ Q2-1 TP12 Sht.2 P2LED1 If an LED pin must be pulled low (during reset) for a strapping / configuration option, this is easily done when external transistors are used as shown here. If the chip drives the LEDs directly and the LED supply voltage is 3.3V, then a 750 ohm pull-down resistor is required (and the LED never turns off completely). When the LED supply voltage is 2.5V, a 1k ohm pull-down is required. +3.3V_EXT R34 220 SPEED D15 6 2 1 FDY3000NZ Q2-2 SC89 P2_LED1 1 P2_LED0 3 2 4 LEDX2 3 LINK / ACT C C Sht.2 5 P2LED0 4 SC89 VDD_IO R128 4.7K 1 2 3 R127 4.7K JP301 3X1 Strapping / Configuration Options B VDD_IO JP301 B 0 = 8-bit Bus Width R124 4.7K 1 2 3 R123 4.7K Parallel Bus Width Select 1 = 16-bit Bus Width (default) JP302 JP302 Parallel Bus Endian Mode Select 1 = Little Endian (default) 0 = Big Endian 3X1 JP303 EEPROM Select 1 = EEPROM Present 0 = EEPROM Not Present (default) VDD_IO R130 4.7K 1 2 3 Sht.2 CPU_PME A R129 4.7K JP303 A 3X1 CONFIDENTIAL & PROPRIETARY Title KSZ8462_8441_8852 EVAL BOARD Size Document Number Rev 1.2 Device Configuration and LEDs Date: 5 4 3 2 Friday, January 23, 2015 Sheet 1 3 of 7 5 4 3 2 1 Compatible Isolation Transformers C87 1000pf/2KV DNI Pulse H1102NL FB30 1 Transpower HB726 2 Bel Fuse S558-5999-U7 TDK MPZ1608S102A LanKom LF-H41S 1 2 3 4 5 6 7 8 DELTA LF8505 CHASSIS GND RX1P RX1M TX1P 1 2 3 4 5 6 7 8 D T1 R171 75 R172 75 CMT1 TX1M R174 75 R173 10 SHLD 9 SHLD D RJ45 CAT5 SHLD J1 75 C66 TX1P CMT1 TX1M CMR1 1000pf/2KV RX1P CMR1 RX1M 16 15 14 13 12 11 10 9 TX+ TCM TXNC NC RX+ RCM RX- 1 2 3 4 5 6 7 8 TD+ TC TDNC NC RD+ RC RD- TXP_1 DIFFERENTIAL_PAIR = DP7 TXM_1 DIFFERENTIAL_PAIR = DP7 RXP_1 DIFFERENTIAL_PAIR = DP9 RXM_1 DIFFERENTIAL_PAIR = DP9 H1102NL C67 Sht.5 TXM_1 Sht.5 RXP_1 Sht.5 RXM_1 Sht.5 C68 0.1uF Line Side Protection (test option) TXP_1 0.1uF Chip Side Protection (test option) Place near RJ-45 connector D6 TXP_1 8 2 7 RXP_1 RX1M 3 3 6 4 5 TX1P RX1P 3 6 4 5 SP2502L SP2502L Littelfuse Littelfuse D7 RX1P 2 TX1P TXM_1 C 4 1 D8 SR3.3 SR3.3 PROTEK DEVICES PROTEK DEVICES 1 7 RX1M 3 2 TX1M 2 8 4 1 1 D5 TX1M C RXM_1 Compatible Isolation Transformers C88 Pulse H1102NL FB31 1 Transpower HB726 2 TDK MPZ1608S102A DELTA LF8505 CHASSIS GND RX2P RX2M TX2P 1 2 3 4 5 6 7 8 B T2 R19 75 R20 75 CMT2 R24 75 R27 75 CMR2 TX2M 10 SHLD 9 SHLD 1 2 3 4 5 6 7 8 Bel Fuse S558-5999-U7 LanKom LF-H41S RJ45 CAT5 SHLD J2 B Note: For KSZ8441HL and KSZ8441FHL, which have only one port, do not install any of these components for port #2. 1000pf/2KV DNI C9 1000pf/2KV TX2P CMT2 TX2M RX2P CMR2 RX2M 16 15 14 13 12 11 10 9 TX+ TCM TXNC NC RX+ RCM RX- 1 2 3 4 5 6 7 8 TD+ TC TDNC NC RD+ RC RD- TXP_2 DIFFERENTIAL_PAIR = DP11 TXM_2 DIFFERENTIAL_PAIR = DP11 RXP_2 DIFFERENTIAL_PAIR = DP13 RXM_2 DIFFERENTIAL_PAIR = DP13 H1102NL C10 Sht.6 TXM_2 Sht.6 RXP_2 Sht.6 RXM_2 Sht.6 C11 0.1uF Line Side Protection (test option) TXP_2 0.1uF Chip Side Protection (test option) Place near RJ-45 connector D10 TXP_2 7 2 7 6 3 6 RXP_2 RX2M TX2P 4 5 TX2P RX2P 4 D11 RX2P 5 SP2502L SP2502L Littelfuse Littelfuse 2 A 4 8 TXM_2 A D12 SR3.3 SR3.3 PROTEK DEVICES PROTEK DEVICES RXM_2 1 1 3 3 RX2M 2 2 TX2M 4 8 3 1 1 D9 TX2M CONFIDENTIAL & PROPRIETARY Title KSZ8462_8441_8852 EVAL BOARD Size Document Number Rev 1.2 Ethernet Interface Date: 5 4 3 2 Friday, February 27, 2015 Sheet 1 4 of 7 5 4 3 2 1 JP10 3X1 1 2 3 +3.3V_EXT +5V LAIRD HI1206N101R-10 FB4 D 1 2 FBEAD C13 VCC_FT1 Place components in dotted box close to fiber transceiver Route TX pairs on component side Refer to fiber transceiver's reference design for the actual values of these resistors Route TX & RX differential pairs close together, 8mil/8mil parallel spacing, and keep other signals 20 mil (minimum) away D Route RX pairs on solder side FB5 0.1uF 1 2 FBEAD C15 C14 + 0.1uF C16 47uF / 16V 0.1uF VCC_FT1 VCCRX1 VCCTX1 DIFFERENTIAL_PAIR = DP1 C18 R64 R65 R66 R67 0.1uF 82 82 130 130 DIFFERENTIAL_PAIR = DP1 C C19 TX N/C RX 1x9/SC/SIP N/C TX_GND TD+ TDVCCTX VCCRX SD RDRD+ RX_GND 9 8 7 6 5 4 3 2 1 FT_TDP1 FT_TDM1 DIFFERENTIAL_PAIR = DP18 DIFFERENTIAL_PAIR = DP18 FT_SD1 FT_RDM1 FT_RDP1 DIFFERENTIAL_PAIR = DP14 DIFFERENTIAL_PAIR = DP14 0.1uF R69 0 DIFFERENTIAL_PAIR = DP7 C20 0.1uF R200 0 DIFFERENTIAL_PAIR = DP7 C21 0.1uF R201 0 DIFFERENTIAL_PAIR = DP9 0 DIFFERENTIAL_PAIR = DP9 FIBER RX C22 R68 R199 FIBER TX R70 0.1uF R202 R71 TXP1 Sht.2 TXM1 Sht.2 TXP_1 Sht.4 TXM_1 Sht.4 RXM_1 Sht.4 RXP_1 Sht.4 RXM1 Sht.2 RXP1 Sht.2 C TOP VIEW DNI U6 DNI 130 DIFFERENTIAL_PAIR = DP3 130 FIBER TRANSCEIVER DIFFERENTIAL_PAIR = DP3 AFBR-5803AZ (+3.3V) C23 Layout will support direct and 1x9 SIP Socket mounting for U6 VCC_FT1 0.1uF DNI B C19/20/21/22 = Do Not Install, R199/200/201/202 = 0 ohm when port 1 is copper. R76 0 FXSD1 Compatible Fiber Transceivers Avago AFBR-5803 (+3.3V) Avago AFBR-5205 (+5V) Avago AFBR-5103 (+5V) DELTA OPT-155A1H1 Sht.2 B C19/20/21/22 = 0.1uF, R199/200/201/202 = Do Not Install when port 1 is fiber. R77 130 Nominal termination and DC biasing for LVPECL and PECL Fiber Transceivers (+5V) LUMINENT B-13/15-155-T3-SSC3 LUMINENT B-13/15-155-T-SSC3 (+3.3V) VCC_FT R64, R65 R66, R67 R70, R71 R76 +3.3V 82 Ohms 130 Ohms 130 Ohms 0 Ohm 130 Ohms +5V 68 Ohms 191 Ohms 270 Ohms 4.75K 1% 5.62K 1% (+5V) R77 A A CONFIDENTIAL & PROPRIETARY Title KSZ8462_8441_8852 EVAL BOARD Size Document Number Rev 1.2 Fiber Interface 1 Date: 5 4 3 2 Friday, February 27, 2015 Sheet 1 5 of 7 5 4 3 2 1 JP11 3X1 1 2 3 +3.3V_EXT +5V For KSZ8441HL and KSZ8441FHL, do not install any of the components on this page. LAIRD HI1206N101R-10 Place components in dotted box close to fiber transceiver FB7 1 2 D FBEAD C26 VCC_FT2 D FB6 0.1uF 1 Refer to fiber transceiver's reference design for the actual values of these resistors 2 FBEAD C25 C32 + 0.1uF C33 47uF / 16V 0.1uF VCC_FT2 VCCRX2 VCCTX2 DIFFERENTIAL_PAIR = DP2 C TX N/C RX 1x9/SC/SIP N/C TX_GND TD+ TDVCCTX VCCRX SD RDRD+ RX_GND 9 8 7 6 5 4 3 2 1 C31 R93 R80 R89 R92 0.1uF 82 82 130 130 FT_TDP2 FT_TDM2 DIFFERENTIAL_PAIR = DP19 DIFFERENTIAL_PAIR = DP19 FT_SD2 FT_RDM2 FT_RDP2 DIFFERENTIAL_PAIR = DP15 DIFFERENTIAL_PAIR = DP15 DIFFERENTIAL_PAIR = DP2 0.1uF R211 0 DIFFERENTIAL_PAIR = DP11 C34 0.1uF R205 0 DIFFERENTIAL_PAIR = DP11 C30 0.1uF R208 0 DIFFERENTIAL_PAIR = DP13 C37 0.1uF R210 0 DIFFERENTIAL_PAIR = DP13 FIBER RX R81 R82 R87 DNI DNI 130 130 Sht.2 TXM2 Sht.2 TXP_2 Sht.4 TXM_2 Sht.4 RXM_2 Sht.4 RXP_2 Sht.4 RXM2 Sht.2 RXP2 Sht.2 C C36 FIBER TX R79 TXP2 TOP VIEW U10 DIFFERENTIAL_PAIR = DP4 FIBER TRANSCEIVER DIFFERENTIAL_PAIR = DP4 AFBR-5803AZ (+3.3V) C35 Layout will support direct and 1x9 SIP Socket mounting for U6 VCC_FT2 C36/34/30/37= Do Not Install, R205/208/210/211=0 ohm when port 2 is copper. 0.1uF DNI R86 0 B B FXSD2 Compatible Fiber Transceivers Avago AFBR-5803 (+3.3V) Avago AFBR-5205 (+5V) Avago AFBR-5103 (+5V) DELTA OPT-155A1H1 Sht.2 R88 C36/34/30/37=0.1uF, R205/208/210/211= Do Not Install when port 2 is fiber. 130 Nominal termination and DC biasing for LVPECL and PECL Fiber Transceivers (+5V) LUMINENT B-13/15-155-T3-SSC3 LUMINENT B-13/15-155-T-SSC3 (+3.3V) VCC_FT R93, R80 R89, R92 R82, R87 R86 +3.3V 82 Ohms 130 Ohms 130 Ohms 0 Ohm 130 Ohms +5V 68 Ohms 191 Ohms 270 Ohms 4.75K 1% 5.62K 1% (+5V) R88 A A CONFIDENTIAL & PROPRIETARY Title KSZ8462_8441_8852 EVAL BOARD Size Document Number Rev 1.2 Fiber Interface 2 Date: 5 4 3 2 Friday, February 27, 2015 Sheet 1 6 of 7 5 4 3 2 1 VDD_AL LAIRD HI1206N101R-10 FB16 JP405 2X1 1 VDD_AL Current Probe +3.3V_EXT U11 - KSZ8462HL Decouple VDD_AL Pins 6, 16 2 FBEAD C93 C124 + 0.1UF D + 22UF / 20V C129 22UF / 20V DNI C94 C100 0.1UF 0.1UF D R178 2 220 D13 VDD_L U11 - KSZ8462HL Decouple VDD_L Pins 40, 51 1 POWER LED C128 + TP21 TP22 GND TP24 GND TP23 GND 22UF / 20V +3.3A LAIRD HI1206N101R-10 JP403 2 1 2.5V 5 6 1.8V IN EN GND GND OUT 3 ADJ GND GND 4 8 7 VDD_IO 1-2 1.8V / 2.5V 2-3 2X1 1 2 FBEAD JP406 470pF R194 10.7K VOUT 4 VREG_3.3V ADJ 5 R179 GND VIN C131 22UF / 20V C107 0.1UF C137 + 0.1UF 22UF / 20V 2X1 R204 8.45K VDD_IO LAIRD HI1206N101R-10 1 2 3 VDD_IO FB21 1 U11 - KSZ8462HL Decouple VDD_IO Pins 21, 30, 56 2 FBEAD + C133 C110 100UF / 16V + 0.1UF C134 22UF / 20V C111 C112 C103 0.1UF 0.1UF 0.1UF + C132 B C109 2.49K 100UF / 16V 3 VIN + 0.1UF VDD_IO Current Probe U4 MIC29302WT 2 C106 100UF / 16V 3X1 1 C130 + JP404 +5V DC C C119 R203 10.5K Install JP406 for 1.8V C120 3.3V B U11 - KSZ8462HL Decouple +3.3A (VDD_A3.3) Pin 9 1.8_2.5V MIC5209YM JP404 +3.3A U21 1.8_2.5V CLOSED 0.1UF FB20 +3.3A Current Probe VOUT = 1.242 X [ 1 + (R194/ (R203 || R204)) ] OPEN C101 0.1UF GND C JP406 C102 0.1UF R180 +3.3V_EXT LAIRD HI1206N101R-10 1.50K FB23 1 VOUT = 1.24 X [ 1 + ( R179 / R180 ) ] 2 FBEAD + LAIRD HI1206N101R-10 J11 5VDC C136 C118 100UF / 16V +5V 0.1UF FB22 +5VDCIN 1 1 2 2 3 FBEAD + C144 470UF / 16V C114 + 0.1UF C135 100UF / 16V C115 0.1UF A A CONFIDENTIAL & PROPRIETARY Title KSZ8462_8441_8852 EVAL BOARD Size Document Number Rev 1.2 Power Date: 5 4 3 2 Thursday, February 26, 2015 Sheet 1 7 of 7