Data Sheet

74AHC595-Q100;
74AHCT595-Q100
8-bit serial-in/serial-out or parallel-out shift register with
output latches
Rev. 1 — 12 July 2012
Product data sheet
1. General description
The 74AHC595-Q100; 74AHCT595-Q100 are high-speed Si-gate CMOS devices and are
pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
with JEDEC standard No. 7A.
The 74AHC595-Q100; 74AHCT595-Q100 are 8-stage serial shift registers with a storage
register and 3-state outputs. The registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP).
The data in each register is transferred to the storage register on a positive-going
transition of the storage register clock input (STCP). If both clocks are connected together,
the shift register is always one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Balanced propagation delays
 All inputs have Schmitt trigger action
 Inputs accept voltages higher than VCC
 Input levels:
 The 74AHC595-Q100 operates with CMOS input levels
 The 74AHCT595-Q100 operates with TTL input levels
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
 Multiple package options
NXP Semiconductors
74AHC595-Q100; 74AHCT595-Q100
8-bit serial-in/serial-out or parallel-out shift register with output latches
3. Applications
 Serial-to-parallel data conversion
 Remote control holding register
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AHC595D-Q100
40 C to +125 C
SO16
plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
74AHC595PW-Q100
40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
74AHC595BQ-Q100
40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
16 terminals; body 2.5  3.5  0.85 mm
SOT763-1
40 C to +125 C
SO16
plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
74AHCT595PW-Q100 40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
74AHCT595BQ-Q100 40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
16 terminals; body 2.5  3.5  0.85 mm
74AHC595-Q100
74AHCT595-Q100
74AHCT595D-Q100
SOT763-1
5. Functional diagram
14 DS
11 SHCP
10 MR
8-STAGE SHIFT REGISTER
Q7S
12 STCP
13 OE
9
8-BIT STORAGE REGISTER
3-STATE OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
15 1
Fig 1.
2
3
4
5
6
7
mna554
Functional diagram
74AHC_AHCT595_Q100
Product data sheet
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Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
2 of 22
74AHC595-Q100; 74AHCT595-Q100
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
13
EN3
12
11
10
SHCP STCP
C1/
1D
2D
15
3
1
2
3
Q3
3
4
Q4
4
5
Q5
5
6
Q6
6
7
Q7
7
OE
10
9
13
mna552
mna553
Logic symbol
Fig 3.
STAGE 0
DS
R
2
Q2
Fig 2.
14
1
Q1
MR
SRG8
15
Q0
DS
11
9
Q7S
14
C2
12
D
IEC logic symbol
STAGES 1 TO 6
Q
D
STAGE 7
Q
D
CP
Q7S
Q
FF7
FF0
CP
R
R
SHCP
MR
D
Q
D
Q
LATCH
LATCH
CP
CP
STCP
OE
mna555
Q0
Fig 4.
Q1 Q2 Q3 Q4 Q5 Q6
Q7
Logic diagram
74AHC_AHCT595_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
3 of 22
74AHC595-Q100; 74AHCT595-Q100
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
6. Pinning information
6.1 Pinning
4
WHUPLQDO
LQGH[DUHD
$+&4
$+&74
9&&
$+&4
$+&74
4
4
'6
4
9&&
4
4
4
4
2(
4
'6
4
67&3
4
2(
67&3
4
4
4
6+&3
4
4
05
*1'
46
46
6+&3
05
*1'
*1'
7UDQVSDUHQWWRSYLHZ
DDD
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO16 and TSSOP16
Fig 6.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
Q1
1
parallel data output 1
Q2
2
parallel data output 2
Q3
3
parallel data output 3
Q4
4
parallel data output 4
Q5
5
parallel data output 5
Q6
6
parallel data output 6
Q7
7
parallel data output 7
GND
8
ground (0 V)
Q7S
9
serial data output
MR
10
master reset (active LOW)
SHCP
11
shift register clock input
STCP
12
storage register clock input
OE
13
output enable input (active LOW)
DS
14
serial data input
Q0
15
parallel data output 0
VCC
16
supply voltage
74AHC_AHCT595_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
4 of 22
74AHC595-Q100; 74AHCT595-Q100
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
7. Functional description
Function table[1]
Table 3.
Control
Input
Output
Function
SHCP STCP OE
MR
DS
Q7S
Qn
X
X
L
NC
X
L
L
a LOW-level on MR only affects the shift registers
X

L
L
X
L
L
empty shift register loaded into storage register
X
X
H
L
X
L
Z
shift register clear; parallel outputs in high-impedance OFF-state

X
L
H
H
Q6S
NC
logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X

L
H
X
NC
QnS
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages


L
H
X
Q6S
QnS
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
[1]
H = HIGH voltage state;
L = LOW voltage state;
 = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
DS
STCP
MR
OE
Z-state
Q0
Z-state
Q1
Z-state
Q6
Z-state
Q7
Q7S
Fig 7.
Timing diagram
74AHC_AHCT595_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
5 of 22
NXP Semiconductors
74AHC595-Q100; 74AHCT595-Q100
8-bit serial-in/serial-out or parallel-out shift register with output latches
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
VI
input voltage
IIK
input clamping current
VI < 0.5 V
[1]
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
[1]
IO
output current
VO = 0.5 V to (VCC + 0.5 V)
ICC
IGND
Tstg
storage temperature
Min
Max
Unit
0.5
+7.0
V
0.5
+7.0
V
20
-
mA
20
+20
mA
25
+25
mA
supply current
-
+75
mA
ground current
75
-
mA
65
+150
C
-
500
mW
total power dissipation
Ptot
Conditions
Tamb = 40 C to +125 C
[2]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For TSSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of Ptot derates linearly at 4.5 mW/K.
9. Recommended operating conditions
Table 5.
Operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.0
5.0
5.5
V
74AHC595-Q100
VCC
supply voltage
VI
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
40
+25
+125
C
t/V
input transition rise and fall rate VCC = 3.0 V to 3.6 V
-
-
100
ns/V
VCC = 4.5 V to 5.5 V
-
-
20
ns/V
74AHCT595-Q100
VCC
supply voltage
4.5
5.0
5.5
V
VI
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
40
+25
+125
C
t/V
input transition rise and fall rate VCC = 4.5 V to 5.5 V
-
-
20
ns/V
74AHC_AHCT595_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
6 of 22
NXP Semiconductors
74AHC595-Q100; 74AHCT595-Q100
8-bit serial-in/serial-out or parallel-out shift register with output latches
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
-
-
1.5
-
1.5
-
V
VCC = 3.0 V
2.1
-
-
2.1
-
2.1
-
V
VCC = 5.5 V
3.85
-
-
3.85
-
3.85
-
V
VCC = 2.0 V
-
-
0.5
-
0.5
-
0.5
V
VCC = 3.0 V
-
-
0.9
-
0.9
-
0.9
V
VCC = 5.5 V
-
-
1.65
-
1.65
-
1.65
V
HIGH-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 50 A; VCC = 3.0 V
2.9
3.0
-
2.9
-
2.9
-
V
IO = 50 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 4.0 mA; VCC = 3.0 V
2.58
-
-
2.48
-
2.40
-
V
IO = 8.0 mA; VCC = 4.5 V
74AHC595-Q100
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
3.94
-
-
3.80
-
3.70
-
V
LOW-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 3.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA; VCC = 4.5 V
-
-
0.36
-
0.44
-
0.55
V
-
-
0.1
-
1.0
-
2.0
A
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
IOZ
OFF-state
VI = VIH or VIL;
output current VO = VCC or GND; VCC = 5.5 V
-
-
0.25
-
2.5
-
10
A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
4.0
-
40
-
80
A
CI
input
capacitance
-
3
10
-
10
-
10
pF
74AHCT595-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 50 A
4.4
4.5
-
4.4
-
4.4
-
V
3.94
-
-
3.80
-
3.70
-
V
-
0
0.1
-
0.1
-
0.1
V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA
VOL
LOW-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 50 A
IO = 8.0 mA
74AHC_AHCT595_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
7 of 22
NXP Semiconductors
74AHC595-Q100; 74AHCT595-Q100
8-bit serial-in/serial-out or parallel-out shift register with output latches
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
Min
Typ
Max
Min
Max
Min
Max
-
-
0.1
-
1.0
-
2.0
A
II
input leakage
current
IOZ
OFF-state
VI = VIH or VIL;
output current VO = VCC or GND per input pin;
other inputs at VCC or GND;
IO = 0 A; VCC = 5.5 V
-
-
0.25
-
2.5
-
10
A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
4.0
-
40
-
80
A
ICC
additional
per input pin; VI = VCC  2.1 V;
supply current other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
-
-
1.35
-
1.5
-
1.5
mA
CI
input
capacitance
-
3
10
-
10
-
10
pF
74AHC_AHCT595_Q100
Product data sheet
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
40 C to +85 C 40 C to +125 C Unit
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
8 of 22
NXP Semiconductors
74AHC595-Q100; 74AHCT595-Q100
8-bit serial-in/serial-out or parallel-out shift register with output latches
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
Min
Max
CL = 15 pF
-
5.7
13.0
1.0
15.0
1.0
16.5
ns
CL = 50 pF
-
7.7
16.5
1.0
18.5
1.0
20.1
ns
-
4.0
8.2
1.0
9.4
1.0
10.5
ns
-
5.4
10.0
1.0
11.4
1.0
12.5
ns
CL = 15 pF
-
5.9
11.9
1.0
13.5
1.0
15.0
ns
CL = 50 pF
-
7.7
15.4
1.0
17.0
1.0
18.5
ns
-
4.2
7.4
1.0
8.5
1.0
9.5
ns
-
5.5
9.0
1.0
10.5
1.0
11.5
ns
CL = 15 pF
-
5.9
12.8
1.0
13.7
1.0
15.0
ns
CL = 50 pF
-
7.4
16.3
1.0
17.2
1.0
18.7
ns
CL = 15 pF
-
4.4
8.0
1.0
9.1
1.0
10.0
ns
CL = 50 pF
-
5.6
10.0
1.0
11.1
1.0
12.0
ns
74AHC595-Q100
tpd
propagation SHCP to Q7S; see Figure 8
delay
VCC = 3.0 V to 3.6 V
[2]
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
STCP to Qn; see Figure 9
[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
MR to Q7S; see Figure 11
[3]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
ten
enable time OE to Qn; see Figure 12
[4]
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
5.6
11.5
1.0
13.5
1.0
15.0
ns
CL = 50 pF
-
7.4
15.0
1.0
17.0
1.0
18.5
ns
-
4.0
8.6
1.0
10.0
1.0
11.0
ns
-
5.3
10.6
1.0
12.0
1.0
13.0
ns
CL = 15 pF
-
5.4
11.0
1.0
13.0
1.0
14.5
ns
CL = 50 pF
-
8.7
15.7
1.0
16.2
1.0
17.5
ns
CL = 15 pF
-
3.8
8.0
1.0
9.5
1.0
10.5
ns
CL = 50 pF
-
5.8
10.3
1.0
11.0
1.0
12.0
ns
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
tdis
disable time OE to Qn; see Figure 12
[5]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
74AHC_AHCT595_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
9 of 22
74AHC595-Q100; 74AHCT595-Q100
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter
fmax
tW
maximum
frequency
pulse width
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
Min
Max
VCC = 3.0 V to 3.6 V
80
125
-
60
-
40
-
MHz
VCC = 4.5 V to 5.5 V
130
170
-
110
-
90
-
MHz
VCC = 3.0 V to 3.6 V
5.0
-
-
5.0
-
5.0
-
ns
VCC = 4.5 V to 5.5 V
5.0
-
-
5.0
-
5.0
-
ns
VCC = 3.0 V to 3.6 V
5.0
-
-
5.0
-
5.0
-
ns
VCC = 4.5 V to 5.5 V
5.0
-
-
5.0
-
5.0
-
ns
VCC = 3.0 V to 3.6 V
5.0
-
-
5.0
-
5.0
-
ns
VCC = 4.5 V to 5.5 V
5.0
-
-
5.0
-
5.0
-
ns
VCC = 3.0 V to 3.6 V
3.5
-
-
3.5
-
3.5
-
ns
VCC = 4.5 V to 5.5 V
3.0
-
-
3.0
-
3.0
-
ns
VCC = 3.0 V to 3.6 V
8.5
-
-
8.5
-
8.5
-
ns
VCC = 4.5 V to 5.5 V
5.0
-
-
5.0
-
5.0
-
ns
VCC = 3.0 V to 3.6 V
1.5
-
-
1.5
-
1.5
-
ns
VCC = 4.5 V to 5.5 V
2.0
-
-
2.0
-
2.0
-
ns
3.0
-
-
3.0
-
3.0
-
ns
2.5
-
-
2.5
-
2.5
-
ns
-
180
-
-
-
-
-
pF
-
3.8
8.2
1.0
9.0
1.0
10.0
ns
-
5.2
10.0
1.0
11.0
1.0
12.0
ns
-
4.0
7.4
1.0
8.5
1.0
9.5
ns
-
5.3
9.0
1.0
10.5
1.0
11.5
ns
CL = 15 pF
-
4.6
8.2
1.0
9.5
1.0
10.5
ns
CL = 50 pF
-
5.8
10.5
1.0
11.5
1.0
12.5
ns
SHCP or STCP;
see Figure 8 and 9
SHCP HIGH or LOW;
see Figure 8
STCP HIGH or LOW;
see Figure 9
MR LOW; see Figure 11
tsu
set-up time
DS to SHCP; see Figure 9
SHCP to STCP;
see Figure 10
th
trec
hold time
recovery
time
DS to SHCP; see Figure 10
MR to SHCP; see Figure 11
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CPD
power
fi = 1 MHz; VI = GND to VCC
dissipation
capacitance
[6]
[7]
74AHCT595-Q100; VCC = 4.5 V to 5.5 V
tpd
propagation SHCP to Q7S; see Figure 8
delay
CL = 15 pF
[2]
CL = 50 pF
STCP to Qn; see Figure 9
[2]
CL = 15 pF
CL = 50 pF
MR to Q7S; see Figure 11
74AHC_AHCT595_Q100
Product data sheet
[3]
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10 of 22
74AHC595-Q100; 74AHCT595-Q100
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter
25 C
Conditions
Min
ten
tdis
Typ[1]
40 C to +85 C 40 C to +125 C Unit
Max
Min
Max
Min
Max
[4]
enable time OE to Qn; see Figure 12
CL = 15 pF
-
4.8
9.0
1.0
11.0
1.0
12.0
ns
CL = 50 pF
-
6.2
11.6
1.0
13.0
1.0
14.5
ns
-
3.6
6.9
1.0
8.0
1.0
9.0
ns
[5]
disable time OE to Qn; see Figure 12
CL = 15 pF
-
5.8
10.3
1.0
11.0
1.0
12.0
fmax
maximum
frequency
SHCP and STCP;
see Figure 8 and Figure 9
CL = 50 pF
130
170
-
110
-
90
-
MHz
tW
pulse width
SHCP HIGH or LOW;
see Figure 8
5.0
-
-
5.0
-
5.0
-
ns
STCP HIGH or LOW;
see Figure 9
5.0
-
-
5.0
-
5.0
-
ns
MR LOW; see Figure 11
5.0
-
-
5.0
-
5.0
-
ns
tsu
set-up time
ns
DS to SHCP; see Figure 9
3.0
-
-
3.0
-
3.0
-
ns
SHCP to STCP;
see Figure 10
5.0
-
-
5.0
-
5.0
-
ns
th
hold time
DS to SHCP; see Figure 10
2.0
-
-
2.0
-
2.0
-
ns
trec
recovery
time
MR to SHCP; see Figure 11
3.0
-
-
3.0
-
3.0
-
ns
CPD
power
fi = 1 MHz; VI = GND to VCC
dissipation
capacitance
-
190
-
-
-
-
-
pF
[1]
[7]
Typical values are measured at nominal supply voltage.
[2]
tpd is the same as tPHL and tPLH.
[3]
tpd is the same as tPHL only.
[4]
ten is the same as tPZL and tPZH.
[5]
tdis is the same as tPLZ and tPHZ.
[6]
[6]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL  VCC2  fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
[7]
All 9 outputs switching.
74AHC_AHCT595_Q100
Product data sheet
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74AHC595-Q100; 74AHCT595-Q100
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
12. Waveforms
1/fmax
VI
SHCP input
VM
GND
tW
t PHL
t PLH
VOH
VM
Q 7S output
VOL
mna557
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8.
Shift clock pulse, maximum frequency and input to output propagation delays
VI
SHCP input
VM
GND
1/fmax
t su
VI
STCP input
VM
GND
tW
t PHL
t PLH
VOH
VM
Q n output
VOL
mna558
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9.
Storage clock to output propagation delays
74AHC_AHCT595_Q100
Product data sheet
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Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
12 of 22
74AHC595-Q100; 74AHCT595-Q100
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
VI
VM
SHCP input
GND
t su
t su
th
th
VI
VM
DS input
GND
VOH
VM
Q 7S output
VOL
mna560
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. Data set-up and hold times
VI
VM
MR input
GND
tW
t rec
VI
SHCP input
VM
GND
t PHL
VOH
VM
Q 7S output
VOL
mna561
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. Master reset to output propagation delays
74AHC_AHCT595_Q100
Product data sheet
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Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
13 of 22
74AHC595-Q100; 74AHCT595-Q100
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
VI
VM
OE input
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VOL + 0.3 V
VOL
tPHZ
VOH
tPZH
VOH − 0.3 V
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna450
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Enable and disable times
Table 8.
Measurement points
Type
Input
Output
VM
VM
74AHC595-Q100
0.5VCC
0.5VCC
74AHCT595-Q100
1.5 V
0.5VCC
74AHC_AHCT595_Q100
Product data sheet
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Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
14 of 22
74AHC595-Q100; 74AHCT595-Q100
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VCC
VCC
G
VI
VO
RL
S1
open
DUT
CL
RT
001aad983
Test data is given in Table 9.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
S1 = test selection switch.
Fig 13. Load circuitry for switching times
Table 9.
Test data
Type
74AHC595-Q100
Input
Product data sheet
S1 position
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
VCC
 3.0 ns
15 pF, 50 pF
1 k
open
GND
VCC
 3.0 ns
15 pF, 50 pF
1 k
open
GND
VCC
74AHCT595-Q100 3.0 V
74AHC_AHCT595_Q100
Load
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Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
15 of 22
74AHC595-Q100; 74AHCT595-Q100
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 14. Package outline SOT109-1 (SO16)
74AHC_AHCT595_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
16 of 22
74AHC595-Q100; 74AHCT595-Q100
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 15. Package outline SOT403-1 (TSSOP16)
74AHC_AHCT595_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
17 of 22
74AHC595-Q100; 74AHCT595-Q100
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT763-1
16 terminals; body 2.5 x 3.5 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
7
y
y1 C
v M C A B
w M C
b
L
1
8
Eh
e
16
9
15
10
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
c
D (1)
Dh
E (1)
Eh
0.2
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
e
0.5
e1
L
v
w
y
y1
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT763-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 16. Package outline SOT763-1 (DHVQFN16)
74AHC_AHCT595_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
18 of 22
74AHC595-Q100; 74AHCT595-Q100
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
14. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
MIL
Military
15. Revision history
Table 11.
Revision history
Document ID
Release date
74AHC_AHCT595_Q100 v.1 20120712
74AHC_AHCT595_Q100
Product data sheet
Data sheet status
Change notice
Supersedes
Product data sheet
-
-
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
19 of 22
NXP Semiconductors
74AHC595-Q100; 74AHCT595-Q100
8-bit serial-in/serial-out or parallel-out shift register with output latches
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AHC_AHCT595_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
20 of 22
NXP Semiconductors
74AHC595-Q100; 74AHCT595-Q100
8-bit serial-in/serial-out or parallel-out shift register with output latches
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT595_Q100
Product data sheet
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Rev. 1 — 12 July 2012
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21 of 22
NXP Semiconductors
74AHC595-Q100; 74AHCT595-Q100
8-bit serial-in/serial-out or parallel-out shift register with output latches
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Contact information. . . . . . . . . . . . . . . . . . . . . 21
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 July 2012
Document identifier: 74AHC_AHCT595_Q100