INTERSIL CA3083M96

CA3083
®
Data Sheet
February 7, 2006
General Purpose High Current NPN
Transistor Array
FN481.6
Features
The CA3083 is a versatile array of five high current (to
100mA) NPN transistors on a common monolithic substrate.
In addition, two of these transistors (Q1 and Q2) are
matched at low current (i.e., 1mA) for applications in which
offset parameters are of special importance.
• High IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA (Max)
• Low VCE sat (at 50mA). . . . . . . . . . . . . . . . . . . 0.7V (Max)
• Matched Pair (Q1 and Q2)
- VIO (VBE Match) . . . . . . . . . . . . . . . . . . . . . ±5mV (Max)
- IIO (at 1mA) . . . . . . . . . . . . . . . . . . . . . . . . 2.5µA (Max)
Independent connections for each transistor plus a separate
terminal for the substrate permit maximum flexibility in circuit
design.
• 5 Independent Transistors Plus Separate Substrate
Connection
Ordering Information
Applications
PART
NUMBER
TEMP.
RANGE
PART
(°C)
MARKING
PACKAGE
• Pb-Free Plus Anneal Available (RoHS Compliant)
PKG.
DWG. #
• Signal Processing and Switching Systems Operating from
DC to VHF
E16.3
• Lamp and Relay Driver
CA3083
CA3083
-55 to 125 16 Ld PDIP
CA3083Z
(Note)
CA3083Z
-55 to 125 16 Ld PDIP* (Pb-free) E16.3
CA3083M96
3083
-55 to 125 16 Ld SOIC
Tape and Reel
CA3083MZ
(Note)
3083MZ
-55 to 125 16 Ld SOIC (Pb-Free) M16.15
CA3083MZ96 3083MZ
(Note)
-55 to 125 16 Ld SOIC (Pb-Free) M16.15
Tape and Reel
M16.15
• Differential Amplifier
• Temperature Compensated Amplifier
• Thyristor Firing
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
• See Application Note AN5296 “Applications of the
CA3018 Circuit Transistor Array” for Suggested
Applications
Pinout
CA3083
(PDIP, SOIC)
TOP VIEW
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
16
1
2
3
15
Q1
14
Q2
13
4
SUBSTRATE
Q5
5
12
11
6
Q3
7
8
1
Q4
10
9
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1998, 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
CA3083
Absolute Maximum Ratings
Thermal Information
The following ratings apply for each transistor in the device:
Collector-to-Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . . . 15V
Collector-to-Base Voltage, VCBO. . . . . . . . . . . . . . . . . . . . . . . . 20V
Collector-to-Substrate Voltage, VCIO (Note 1). . . . . . . . . . . . . . 20V
Emitter-to-Base Voltage, VEBO . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Collector Current (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Base Current (IB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Thermal Resistance (Typical, Note 2)
θJA (°C/W) θJC (°C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
135
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
200
N/A
Maximum Power Dissipation (Any One Transistor) . . . . . . . 500mW
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3083 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage
which is more negative than any collector voltage in order to maintain isolation between transistors and provide normal transistor action. To
avoid undesired coupling between transistors, the substrate Terminal (5) should be maintained at either DC or signal (AC) ground. A suitable
bypass capacitor can be used to establish a signal ground.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
For Equipment Design, TA = 25°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
FOR EACH TRANSISTOR
Collector-to-Base Breakdown Voltage
V(BR)CBO
IC = 100µA, IE = 0
20
60
-
V
Collector-to-Emitter Breakdown Voltage
V(BR)CEO
IC = 1mA, IB = 0
15
24
-
V
Collector-to-Substrate Breakdown Voltage
V(BR)CIO
ICI = 100µA, IB = 0, IE = 0
20
60
-
V
Emitter-to-Base Breakdown Voltage
V(BR)EBO
IE = 500µA, IC = 0
5
6.9
-
V
Collector-Cutoff-Current
ICEO
VCE = 10V, IB = 0
-
-
10
µA
Collector-Cutoff-Current
ICBO
VCB = 10V, IE = 0
-
-
1
µA
DC Forward-Current Transfer Ratio (Note 3) (Figure 1)
hFE
VCE = 3V
IC = 10mA
40
76
-
IC = 50mA
40
75
-
Base-to-Emitter Voltage (Figure 2)
VBE
VCE = 3V, IC = 10mA
0.65
0.74
0.85
V
VCE SAT
IC = 50mA, IB = 5mA
-
0.40
0.70
V
fT
VCE = 3V, IC = 10mA
-
450
-
MHz
Absolute Input Offset Voltage (Figure 6)
|VIO|
VCE = 3V, IC = 1mA
-
1.2
5
mV
Absolute Input Offset Current (Figure 7)
|IIO|
VCE = 3V, IC = 1mA
-
0.7
2.5
µA
Collector-to-Emitter Saturation Voltage (Figures 3, 4)
Gain Bandwidth Product
FOR TRANSISTORS Q1 AND Q2 (As a Differential Amplifier)
NOTE:
3. Actual forcing current is via the emitter for this test.
2
FN481.6
February 7, 2006
CA3083
100
0.9
VCE = 3V
VCE = 3V
90
BASE-TO-EMITTER VOLTAGE (V)
DC FORWARD CURRENT TRANSFER RATIO
Typical Performance Curves
TA = 70°C
TA = 25°C
80
TA = 0°C
70
60
1
10
TA = 0°C
TA = 25°C
0.7
TA = 70°C
0.6
0.5
0.1
50
0.1
0.8
100
COLLECTOR CURRENT (mA)
FIGURE 1. hFE vs IC
1.2
hFE = 10, TA = 25oC
0.8
0.6
0.4
MAXIMUM
0.2
TYPICAL
1
10
0.8
0.6
0.4
0
100
FIGURE 3. VCE SAT vs IC
ABSOLUTE INPUT OFFSET VOLTAGE (mV)
BASE-TO-EMITTER
SATURATION VOLTAGE (V)
hFE = 10, TA = 25°C
0.9
0.8
0.7
0.6
0.5
3
TYPICAL
1
10
COLLECTOR CURRENT (mA)
100
FIGURE 4. VCE SAT vs IC
1
FIGURE 5. VBE SAT vs IC
MAXIMUM
0.2
COLLECTOR CURRENT (mA)
10
COLLECTOR CURRENT (mA)
hFE = 10, TA = 70°C
1
0
1
100
FIGURE 2. VBE vs IC
COLLECTOR-TO-EMITTER
SATURATION VOLTAGE (V)
COLLECTOR-TO-EMITTER
SATURATION VOLTAGE (V)
1
1
10
COLLECTOR CURRENT (mA)
100
6
VCE = 3V, TA = 25°C
5
4
3
2
1
0
0.1
1
COLLECTOR CURRENT (mA)
10
FIGURE 6. VIO vs IC (TRANSISTORS Q1 AND Q2 AS A
DIFFERENTIAL AMPLIFIER)
FN481.6
February 7, 2006
CA3083
ABSOLUTE INPUT OFFSET CURRENT (µA)
Typical Performance Curves
(Continued)
10
VCE = 3V, TA = 25°C
1
0.1
0.1
1
COLLECTOR CURRENT (mA)
10
FIGURE 7. IIO vs IC (TRANSISTORS Q1 AND Q2 AS A DIFFERENTIAL AMPLIFIER)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
4
FN481.6
February 7, 2006