D N EW ® ESIG EL7563 NS F OR DED 554 N E 7 OM M S E E ELSheet Data R EC T O N May 13, 2005 Monolithic 4 Amp DC/DC Step-Down Regulator FN7296.2 Features • Integrated synchronous MOSFETs and current mode controller The EL7563 is an integrated, full-featured synchronous stepdown regulator with output voltage adjustable from 1.0V to 2.5V. It is capable of delivering 4A continuous current at up to 95% efficiency. The EL7563 operates at a constant frequency pulse width modulation (PWM) mode, making external synchronization possible. Patented on-chip resistorless current sensing enables current mode control, which provides cycle-by-cycle current limiting, over-current protection, and excellent step load response. The EL7563 features power tracking, which makes the start-up sequencing of multiple converters possible. A junction temperature indicator conveniently monitors the silicon die temperature, saving the designer time on the tedious thermal characterization. The minimal external components and full functionality make this EL7563 ideal for desktop and portable applications. • 4A continuous output current • Up to 95% efficiency • Internal patented current sense • Cycle-by-cycle current limit • 3V to 3.6V input voltage • Adjustable output voltage 1V to 2.5V • Precision reference • ±0.5% load and line regulation • Adjustable switching frequency to 1MHz • Oscillator synchronization possible • Internal soft-start The EL7563 is offered in 20-pin SO and 28-pin HTSSOP packages. • Over-voltage protection • Junction temperature indicator Pinout • Over-temperature protection EL7563 (20-PIN SO) TOP VIEW • Under-voltage lockout • Multiple supply start-up tracking • Power-good indicator C5 0.1µF 1 VREF EN 20 • 20-pin SO (0.300”) package 2 SGND FB 19 • 28-pin HTSSOP package 3 COSC PG 18 C4 R4 C3 22Ω 0.22µF C2 4 VDD VDRV 17 5 VTJ VHI 16 2.2nF VIN 3.3V C1 330µF 6 PGND LX 15 7 PGND LX 14 8 VIN PGND 13 9 STP PGND 12 10 STN PGND 11 D1 C6 0.22µF D3 C8 0.22µF C9 0.1µF VOUT L1 4.7µH • Pb-Free available (RoHS compliant) D4 D2 390pF C10 2.2nF C7 330µF 2.5V 4A R2 1.58kΩ R1 1kΩ Applications • DSP, CPU core, and I/O supplies • Logic/Bus supplies • Portable equipment • DC/DC converter modules • GTL + Bus power supply Typical Application Diagrams continued on page 3 Manufactured Under U.S. Patent No. 5,7323,974 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL7563 Ordering Information PACKAGE TAPE & REEL PKG. DWG. # EL7563CM 20-Pin SO (0.300”) - MDP0027 EL7563CMZ (See Note) 20-Pin SO (0.300”) (Pb-free) - MDP0027 EL7563CMZ-T13 (See Note) 20-Pin SO (0.300”) (Pb-free) 13” MDP0027 EL7563CRE 28-Pin HTSSOP - MDP0048 EL7563CRE-T7 28-Pin HTSSOP 7” MDP0048 EL7563CRE-T13 28-Pin HTSSOP 13” MDP0048 EL7563CREZ (See Note) 28-Pin HTSSOP (Pb-free) - MDP0048 EL7563CREZ-T7 (See Note) 28-Pin HTSSOP (Pb-free) 7” MDP0048 EL7563CREZ-T13 (See Note) 28-Pin HTSSOP (Pb-free) 13” MDP0048 PART NUMBER NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7296.2 May 13, 2005 EL7563 Absolute Maximum Ratings (TA = 25°C) Supply Voltage between VIN or VDD and GND . . . . . . . . . . . . +4.5V VLX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN +0.3V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, VDD +0.3V VHI Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, VLX +6V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER VDD = VIN = 3.3V, TA = TJ = 25°C, COSC = 390pF, unless otherwise specified. DESCRIPTION VREF Reference Accuracy VREFTC Reference Temperature Coefficient VREFLOAD Reference Load Regulation VRAMP Oscillator Ramp Amplitude IOSC_CHG Oscillator Charge Current IOSC_DIS CONDITIONS MIN TYP MAX 1.24 1.26 1.28 50 0 < IREF < 50µA UNIT V ppm/°C -1 % 1.15 V 0.1V < VOSC < 1.25V 200 µA Oscillator Discharge Current 0.1V < VOSC < 1.25V 8 mA IVDD+VDRV VDD+VDRV Supply Current VEN = 2.7V, FOSC = 120kHz IVDD_OFF VDD Standby Current EN = 0 2 5.5 6.5 mA 1 1.5 mA VDD_OFF VDD for Shutdown 2.4 2.65 V VDD_ON VDD for Startup 2.6 2.95 V TOT Over Temperature Threshold 135 °C THYS Over Temperature Hysteresis 20 °C ILEAK Internal FET Leakage Current ILMAX Peak Current Limit RDSON FET On Resistance RDSONTC RDSON Tempco ISTP Auxiliary Supply Tracking Positive Input Pull Down Current VSTP = VIN/2 ISTN Auxiliary Supply Tracking Negative Input Pull Up Current VSTN = VIN/2 VPGP Positive Power Good Threshold With respect to target output voltage VPGN Negative Power Good Threshold VPG_HI VPG_LO VOVP Over Voltage Protection VFB Output Initial Accuracy ILOAD = 0A VFB_LINE Output Line Regulation VIN = 3.3V, ∆VIN = 10%, ILOAD = 0A 0.5 % VFB_LOAD Output Load Regulation 0.5A < ILOAD < 4A 0.5 % VFB_TC Output Temperature Stability -40°C < TA < 85°C, ILOAD = 2A ±1 % IFB Feedback Input Pull Up Current VFB = 0V 100 EN = 0, LX = 3.3V (low FET), LX = 0V (high FET) 10 5 Wafer level test only A 30 -4 µA 60 mΩ 0.2 mΩ/°C 2.5 µA 4 µA 6 16 % With respect to target output voltage -16 -6 % Power Good Drive High IPG = 1mA 2.7 Power Good Drive Low IPG = -1mA VEN_HI EN Input High Level VEN_LO EN Input Low Level IEN Enable Pull Up Current 3 2.5 V 0.5 10 0.977 0.992 % 1.007 200 2.7 1 VEN = 0 -4 V V nA V V -2.5 µA FN7296.2 May 13, 2005 EL7563 Closed-Loop AC Electrical Specifications PARAMETER VS = VIN = 3.3V, TA = TJ = 25°C, COSC = 390pF, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 310 365 420 kHz FOSC Oscillator Initial Accuracy tSYNC Minimum Oscillator Sync Width 25 ns MSS Soft Start Slope 0.5 V/ms tBRM FET Break Before Make Delay 15 ns tLEB High Side FET Minimum On Time 150 ns DMAX Maximum Duty Cycle 95 % Typical Application Diagrams (Continued) C5 1 VREF EN 28 2 SGND FB 27 3 COSC PG 26 0.1µF C4 22Ω C3 0.22µF 4 VDD C2 5 VTJ C1 330µF D4 VDRV 25 VHI 24 2.2nF VIN 3.3V D2 390pF R4 D1 6 PGND LX 23 C6 0.22µF 7 PGND LX 22 L1 8 PGND LX 21 4.7µH 9 PGND LX 20 10 VIN LX 19 11 VIN LX 18 12 NC NC 17 13 STP PGND 16 14 STN PGND 15 D3 C8 0.22µF C9 0.1µF C10 2.2nF C7 330µF VOUT 2.5V 4A R2 1.58kΩ R1 1kΩ 28-PIN HTSSOP 4 FN7296.2 May 13, 2005 EL7563 Pin Descriptions 20-PIN SO (0.300”) 28-PIN HTSSOP PIN NAME 1 1 VREF Bandgap reference bypass capacitor; typically 0.1µF to SGND 2 2 SGND Control circuit negative supply or signal ground 3 3 COSC Oscillator timing capacitor (see performance curves) 4 4 VDD Control circuit positive supply; normally connected to VIN through an RC filter 5 5 VTJ Junction temperature monitor; connected with 2.2nF to 3.3nF to SGND 6, 7 6, 7, 8, 9 PGND 8 10, 11 VIN Power supply input of the regulator; connected to the drain of the high-side NMOS power FET 9 13 STP Auxiliary supply tracking positive input; tied to regulator output to synchronize start up with a second supply; leave open for stand alone operation; 2µA internal pull down current 10 14 STN Auxiliary supply tracking negative input; connect to output of a second supply to synchronize start up; leave open for stand alone operation; 2µA internal pull up current 11, 12, 13 15, 16 PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET 14, 15 18, 19, 20, 21, 22, 23 LX Inductor drive pin; high current output whose average voltage equals the regulator output voltage 16 24 VHI Positive supply of high-side driver; boot strapped from VDRV to LX with an external 0.22µF capacitor 17 25 VDRV 18 26 PG Power good window comparator output; logic 1 when regulator output is within ±10% of target output voltage 19 27 FB Voltage feedback input; connected to external resistor divider between VOUT and SGND; a 125nA pull-up current forces VOUT to SGND in the event that FB is floating 20 28 EN Chip enable, active high; a 2µA internal pull up current enables the device if the pin is left open; a capacitor can be added at this pin to delay the start of converter PIN FUNCTION Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET Positive supply of low-side driver and input voltage for high side boot strap Typical Performance Curves (20 Pin SO Package) NOTE: The 28-Pin HTSSOP Package Offers Improved Performance VIN=3.3V VIN=3.3V 100 100 VO=2.5V 95 VO=1.8V EFFICIENCY (%) EFFICIENCY (%) 95 90 85 80 VO=1.2V 75 70 VO=1V 0 0.5 1 1.5 2 2.5 90 85 VO=1.8V 80 VO=1.2V 75 70 65 3 3.5 LOAD CURRENT IO (A) FIGURE 1. EL7563CM EFFICIENCY vs IO 5 VO=2.5V 4 60 0.1 0.6 1.1 1.6 2.1 2.6 3.1 3.6 4 IO (A) FIGURE 2. EL7563CRE EFFICIENCY FN7296.2 May 13, 2005 EL7563 Typical Performance Curves (20 Pin SO Package) (Continued) NOTE: The 28-Pin HTSSOP Package Offers Improved Performance VIN=3.3V 1.6 1.8 VO=1.8V 1.6 1.4 VO=1.2V 1 0.8 VO=1V 0.6 0.4 VO=2.5V 1.2 1.2 PLOSS (W) POWER LOSS (W) 1.4 1 0.8 VO=1.2V 0.6 0.4 VO=2.5V 0.2 0.2 0 0 0.5 1 2 1.5 2.5 3 3.5 0 4 0 1 2 OUTPUT CURRENT IO (A) FIGURE 3. EL7563CM CONVERTER POWER LOSS vs IO 2.505 0.6 VIN=3.6V VIN=3.3V 0.2 VIN=3.3V VO (V) (%) OUTPUT VOLTAGE (V) VO=2.5V 0.4 2.495 2.49 2.485 VIN=3V 2.48 VIN=3.6V 0 -0.2 -0.4 2.475 VIN=3V -0.6 2.47 2.465 0.5 1 1.5 2 2.5 3 3.5 -0.8 4 0 0.5 1 1.5 FIGURE 5. EL7563CM LOAD REGULATION 50 3 3.5 4 CONDITION: EL7563CRE THERMAL PAD SOLDERED TO 2-LAYER PCB WITH 0.039” THICKNESS AND 1 OZ. COPPER ON BOTH SIDES 45 WITH NO AIRFLOW θJA (°C/W) THERMAL RESISTANCE (°C/W) 2.5 FIGURE 6. EL7563CRE LOAD REGULATION TEST CONDITION: CHIP IN THE CENTER OF COPPER AREA 46 2 IO (A) LOAD CURRENT IO (A) 50 4 FIGURE 4. EL7563CRE TOTAL CONVERTER POWER LOSS VO=2.5V 2.5 3 IO (A) 42 38 40 35 WITH 100 LFPM AIRFLOW 34 30 30 1 OZ. COPPER PCB USED 1 1.5 2 2.5 3 3.5 PCB COPPER HEAT-SINKING AREA (in2) FIGURE 7. EL7563CM θJA vs COPPER AREA 6 4 25 0 1.5 2 2.5 3 3.5 4 PCB AREA (in2) FIGURE 8. EL7563CRE THERMAL RESISTANCE vs PCB AREA - NO AIR FLOW FN7296.2 May 13, 2005 EL7563 Typical Performance Curves (20 Pin SO Package) (Continued) NOTE: The 28-Pin HTSSOP Package Offers Improved Performance JUNCTION TEMPERATURE RISE (°C) 60 45 40 50 35 NO AIRFLOW 100 LFM 30 20 25 20 15 200 LFM 10 0 30 TJ RISE 40 10 500 LPF 0 1 5 3 2 0 4 1 1.5 2 IO (A) FIGURE 9. EL7563CM JUNCTION TEMPERATURE RISE ON DEMO BOARD 900 800 IO=4A 700 330 FS (kHz) OSCILLATOR FREQUENCY (kHz) 4 1000 350 320 310 3.5 FIGURE 10. EL7563CRE JUNCTION TEMPERATURE RISE ON DEMO BOARD - NO AIR FLOW 360 340 3 2.5 IO (A) IO=0A 600 500 400 300 300 290 200 280 -40 -20 20 0 40 60 100 100 80 200 300 400 500 600 700 800 900 1000 COSC (pF) TEMPERATURE (°C) FIGURE 12. SWITCHING FREQUENCY vs COSC FIGURE 11. SWITCHING FREQUENCY vs TEMPERATURE 8 1.5 6 1.3 VIN=3.3V VIN=3.6V VTJ ILMT (A) 7 VIN=3V 5 1.1 4 3 -40 0.9 -20 0 20 40 60 80 TJ (°C) FIGURE 13. CURRENT LIMIT vs TJ 7 100 120 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) FIGURE 14. VTJ vs JUNCTION TEMPERATURE FN7296.2 May 13, 2005 EL7563 Typical Performance Curves (20 Pin SO Package) (Continued) NOTE: The 28-Pin HTSSOP Package Offers Improved Performance VIN=3.3V, VO=1.8V, IO=0.2A-4A VIN=3.3V, VO=1.8V, IO=4A ∆VIN VLX IO iL ∆VO ∆VO FIGURE 15. SWITCHING WAVEFORMS FIGURE 16. TRANSIENT RESPONSE VIN=3.3V, VO=1.8V, IO=0.2A VIN=3.3V, VO=1.8V, IO=4A VIN VO FIGURE 17. POWER-UP FIGURE 18. POWER-DOWN VIN=3.3V, VO=1.8V AT 4A VIN=3.3V, VO=1.8V AT 4A EN EN VO VO FIGURE 19. ENABLE 8 FIGURE 20. DISABLE FN7296.2 May 13, 2005 EL7563 Typical Performance Curves (20 Pin SO Package) (Continued) NOTE: The 28-Pin HTSSOP Package Offers Improved Performance VIN=3.3V, VO=1.8V, IO=4A TO SHORT IO VO FIGURE 21. SHORT-CIRCUIT PROTECTION Block Diagram 390pF 0.1µF VREF COSC D2 VTJ JUNCTION TEMPERATURE VOLTAGE REFERENCE OSCILLATOR 2.2nF 22Ω 3.3V 0.22µF PWM CONTROLLER POWER FET 0.22µF POWER TRACKING D1 0.1µF 4.7µH DRIVERS VOUT (2.5V, 4A) 330µF PGND EN STN D3 VIN VDD POWER FET STP 0.22µF VHI CONTROLLER SUPPLY D4 VDRV 1.58kΩ 2.2nF 1kΩ CURRENT SENSE VREF - PG + SGND 9 FB FN7296.2 May 13, 2005 EL7563 Applications Information Circuit Description General The EL7563 is a fixed frequency, current mode controlled DC/DC converter with integrated N-channel power MOSFETs and a high precision reference. The device incorporates all the active circuitry required to implement a cost effective, user-programmable 4A synchronous stepdown regulator suitable for use in DSP core power supplies. By combining fused-lead packaging technology with an efficient synchronous switching architecture, high power output (10W) can be realized without the use of discrete external heat sinks. PWM Controller The EL7563 regulates output voltage through the use of current-mode controlled pulse width modulation. The three main elements in a PWM controller are the feedback loop and reference, a pulse width modulator whose duty cycle is controlled by the feedback error signal, and a filter which averages the logic level modulator output. In a step-down (buck) converter, the feedback loop forces the time-averaged output of the modulator to equal the desired output voltage. Unlike pure voltage-mode control systems, current-mode control utilizes dual feedback loops to provide both output voltage and inductor current information to the controller. The voltage loop minimizes DC and transient errors in the output voltage by adjusting the PWM duty-cycle in response to changes in line or load conditions. Since the output voltage is equal to the time-averaged of the modulator output, the relatively large LC time constant found in power supply applications generally results in low bandwidth and poor transient response. By directly monitoring changes in inductor current via a series sense resistor the controller's response time is not entirely limited by the output LC filter and can react more quickly to changes in line and load conditions. This feedforward characteristic also simplifies AC loop compensation since it adds a zero to the overall loop response. Through proper selection of the current-feedback to voltage-feedback ratio the overall loop response will approach a one-pole system. The resulting system offers several advantages over traditional voltage control systems, including simpler loop compensation, pulse by pulse current limiting, rapid response to line variation and good load step response. The heart of the controller is an input direct summing comparator which sum voltage feedback, current feedback, slope compensation ramp and power tracking signals together. Slope compensation is required to prevent system instability that occurs in current-mode topologies operating at duty-cycles greater than 50% and is also used to define the open-loop gain of the overall system. The slope compensation is fixed internally and optimized for 500mA inductor ripple current. The power tracking will not contribute any input to the comparator steady-state operation. Current 10 feedback is measured by the patented sensing scheme that senses the inductor current flowing through the high-side switch whenever it is conducting. At the beginning of each oscillator period the high-side NMOS switch is turned on. The comparator inputs are gated off for a minimum period of time of about 150ns (LEB) after the high-side switch is turned on to allow the system to settle. The Leading Edge Blanking (LEB) period prevents the detection of erroneous voltages at the comparator inputs due to switching noise. If the inductor current exceeds the maximum current limit (ILMAX) a secondary over-current comparator will terminate the high-side switch on time. If ILMAX has not been reached, the feedback voltage FB derived from the regulator output voltage VOUT is then compared to the internal feedback reference voltage. The resultant error voltage is summed with the current feedback and slope compensation ramp. The high-side switch remains on until all four comparator inputs have summed to zero, at which time the high-side switch is turned off and the low-side switch is turned on. However, the maximum on-duty ratio of the high-side switch is limited to 95%. In order to eliminate cross-conduction of the high-side and low-side switches a 15ns break-beforemake delay is incorporated in the switch drive circuitry. The output enable (EN) input allows the regulator output to be disabled by an external logic control signal. Output Voltage Setting In general: R V OUT = 0.992V × 1 + ------2- R 1 However, due to the relatively low open loop gain of the system, gain errors will occur as the output voltage and loopgain is changed. This is shown in the performance curves. A 100nA pull-up current from FB to VDD forces VOUT to GND in the event that FB is floating. NMOS Power FETs and Drive Circuitry The EL7563 integrates low on-resistance (30mΩ) NMOS FETs to achieve high efficiency at 4A. In order to use an NMOS switch for the high-side drive it is necessary to drive the gate voltage above the source voltage (LX). This is accomplished by bootstrapping the VHI pin above the LX voltage with an external capacitor CVHI and internal switch and diode. When the low-side switch is turned on and the LX voltage is close to GND potential, capacitor CVHI is charged through internal switch to VDRV, typically 6V with external charge-pump. At the beginning of the next cycle the highside switch turns on and the LX pins begin to rise from GND to VIN potential. As the LX pin rises the positive plate of capacitor CVHI follows and eventually reaches a value of VDRV+VIN, typically 9V, for VIN=3.3V. This voltage is then level shifted and used to drive the gate of the high-side FET, via the VHI pin. A value of 0.22µF for CVHI is recommended. FN7296.2 May 13, 2005 EL7563 Reference Junction Temperature Sensor A 1.5% temperature compensated bandgap reference is integrated in the EL7563. The external VREF capacitor acts as the dominant pole of the amplifier and can be increased in size to maximize transient noise rejection. A value of 0.1µF is recommended. An internal temperature sensor continuously monitors die temperature. In the event that die temperature exceeds the thermal trip-point, the system is in fault state and will be shut down. The upper and low trip-points are set to 135°C and 115°C respectively. Oscillator The VTJ pin is an accurate indication of the internal silicon junction temperature (see performance curve.) The junction temperature TJ (°C) can be deducted from the following relation: The system clock is generated by an internal relaxation oscillator with a maximum duty-cycle of approximately 95%. Operating frequency can be adjusted through the COSC pin or can be driven by an external source. If the oscillator is driven by an external source care must be taken in selecting the ramp amplitude. Since CSLOPE value is derived from the COSC ramp, changes to COSC ramp will change the CSLOPE compensation ramp which determine the open-loop gain of the system. When external synchronization is required, always choose COSC such that the free-running frequency is at least 20% lower than that of sync source to accommodate component and temperature variations. Figure 22 shows a typical connection. 100pF BAT54S EXTERNAL OSCILLATOR 390pF 1 20 2 19 3 18 5 16 6 EL7563 – VTJ T J = 75 + 1.2 ------------------------0.00384 Where VTJ is the voltage at VTJ pin in volts. Power Good and Power On Reset During power up the output regulator will be disabled until VIN reaches a value of approximately 2.9V. About 300mV hysteresis is present to eliminate noise-induced oscillations. Under-voltage and over-voltage conditions on the regulator output are detected through an internal window comparator. A logic high on the PG output indicates that the regulated output voltage is within about +10% of the nominal selected output voltage. 15 7 14 8 13 9 12 10 11 FIGURE 22. OSCILLATOR SYNCHRONIZATION 11 FN7296.2 May 13, 2005 EL7563 Power Tracking 2. Offset Tracking The power tracking pins STP and STN are the inputs to a comparator, whose HI output forces the PWM controller to skip switching cycle. The intended start-up sequence is shown in Figure 24. In this configuration, VC will not start until VP reaches a preset value of: 1. Linear Tracking RB --------------------- × V IN RA + RB In this application, it is always the case that the lower voltage supply VC tracks the higher output supply VP. See Figure 23. 1 20 2 19 6 15 7 EL7563 8 VC 14 13 9 + - 10 VP 12 11 1 20 2 19 6 15 VOUT VC TIME 7 EL7563 8 VP 14 13 9 + - 10 12 11 FIGURE 23. LINEAR POWER TRACKING 1 20 2 19 6 15 VIN 7 RA 8 9 RB 10 EL7563 VC 14 13 STP + STN - VP 12 11 1 20 2 19 6 15 VOUT VC TIME 7 EL7563 8 9 10 VP 14 13 STP + STN - 12 11 FIGURE 24. OFFSET POWER TRACKING 12 FN7296.2 May 13, 2005 EL7563 3. External Soft Start The second way of offset tracking is to use the EN and Power Good pins, as shown in Figure 25. In this configuration, VP does not have to be larger than VC. An external soft start can be combined with auxiliary supply tracking to provide desired soft start other than internally preset soft start (Figure 26). The appropriate start-up time is: VO t s = R × C × --------V IN 1 EN 20 2 19 3 PG 18 5 16 6 EL7563 15 7 14 8 13 9 12 10 11 VC VP VC 1 EN 20 2 19 3 PG 18 5 16 6 EL7563 TIME 15 7 14 8 13 9 12 10 11 VP FIGURE 25. OFFSET TRACKING VIN 1 20 2 19 6 15 7 R EL7563 8 9 10 VOUT 14 13 STP STN + - 12 11 C FIGURE 26. EXTERNAL SOFT START 13 FN7296.2 May 13, 2005 EL7563 Start-up Delay The EL7563CRE utilizes the 28-pin HTSSOP package. The majority of heat is dissipated through the heat pad exposed at the bottom of the package. Therefore, the heat pad needs to be soldered to the PCB. The thermal resistance for this package is as low as 29°C/W, better than that of the SO20. Typical performance is shown in the curve section. The actual junction temperature can be measured at VTJ pin. A capacitor can be added to the EN pin to delay the converter start-up (Figure 27) by utilizing the pull-up current. The delay time is approximately: t d ( ms ) = 1200 × C ( µF ) Thermal Management Since the thermal performance of the IC is heavily dependent on the board layout, the system designer should exercise care during the design phase to ensure that the IC will operate under the worst-case environmental conditions. The EL7563CM utilizes “fused lead” packaging technology in conjunction with the system board layout to achieve a lower thermal resistance than typically found in standard SO20 packages. By fusing (or connecting) multiple external leads to the die substrate within the package, a very conductive heat path is created to the outside of the package. This conductive heat path MUST then be connected to a heat sinking area on the PCB in order to dissipate heat out and away from the device. The conductive paths for the SO20 package are the fused leads: # 6, 7, 11, 12, and 13. If a sufficient amount of PCB metal area is connected to the fused package leads, a junction-to-ambient resistance of 43°C/W can be achieved (compared to 85°C/W for a standard SO20 package). The general relationship between PCB heat-sinking metal area and the thermal resistance for this package is shown in the Performance Curves section of this data sheet. It can be readily seen that the thermal resistance for this package approaches an asymptotic value of approximately 43°C/W without any airflow, and 33°C/W with 100 LFPM airflow. Additional information can be found in Application Note #8 (Measuring the Thermal Resistance of Power Surface-Mount Packages). For a thermal shutdown die junction temperature of 135°C, and power dissipation of 1.5W, the ambient temperature can be as high as 70°C without airflow. With 100 LFPM airflow, the ambient temperature can be extended to 85°C. 1 20 2 19 6 15 Layout Considerations The layout is very important for the converter to function properly. Power Ground ( ) and Signal Ground ( ) should be separated to ensure that the high pulse current in the Power Ground never interferes with the sensitive signals connected to Signal Ground. They should only be connected at one point (normally at the negative side of either the input or output capacitor.) The trace connected to the FB pin is the most sensitive trace. It needs to be as short as possible and in a “quiet” place, preferably between PGND or SGND traces. In addition, the bypass capacitor connected to the VDD pin needs to be as close to the pin as possible. The heat of the chip is mainly dissipated through the PGND pins and through the heat pad at the bottom of the CRE package. Maximizing the copper area around these pins is preferable. In addition, a solid ground plane is always helpful for the EMI performance. The demo board is a good example of layout based on these principles. Please refer to the EL7563 Application Brief for the layout. C 7 EL7563 8 9 10 VOUT 14 VIN 13 STP + STN - 12 VO td 11 TIME FIGURE 27. START-UP DELAY 14 FN7296.2 May 13, 2005 EL7563 SO Package Outline Drawing 15 FN7296.2 May 13, 2005 EL7563 HTSSOP Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at <http://www.intersil.com/design/packages/index.asp> All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN7296.2 May 13, 2005