RFD10P03L, RFD10P03LSM, RFP10P03L
Data Sheet
July 1999
10A, 30V, 0.200 Ohm, Logic Level,
P-Channel Power MOSFET
3515.2
Features
• 10A, 30V
These products are P-Channel power MOSFETs
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI circuits,
gives optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, and relay drivers. These transistors can be operated
directly from integrated circuits.
Formerly developmental type TA49205.
• rDS(ON) = 0.200Ω
• Temperature Compensating PSPICE® Model
• PSPICE Thermal Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
Symbol
Ordering Information
PART NUMBER
File Number
D
PACKAGE
BRAND
RFD10P03L
TO-251AA
10P03L
RFD10P03LSM
TO-252AA
10P03L
RFP10P03L
TO-220AB
F10P03L
G
S
NOTE: When ordering, use the entire part number. Add the suffix, 9A,
to obtain the TO-252AA variant in tape and reel, i.e. RFD10P03LSM9A..
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
GATE
SOURCE
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
7-3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFD10P03L, RFD10P03LSM, RFP10P03L
Absolute Maximum Ratings
TC = 25oC Unless Otherwise Specifie
RFD10P03L, RFD10P03LSM,
RFP10P03L
-30
-30
±10
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20KΩ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
RMS Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Lead Temperature for Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
(0.063in (1.6mm) from case for 10s)
UNITS
V
V
V
10
See Figure 5
Refer to UIS Curve
65
0.43
-55 to 175
300
A
W
W/oC
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V (Figure 11)
-30
-
-
V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 12)
-1
-
-2
V
-
-
-1
µA
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
IGSS
VDS = -30V,
-
-
-50
µA
VGS = ±10V
-
-
±100
nA
ID = 10A, VGS = -5V (Figures 9, 10)
-
-
0.200
Ω
0.220
Ω
-
-
100
ns
VGS = 0V
Drain to Source On Resistance
(Note 1)
rDS(ON)
TC = 25oC
TC = 150oC
ID = 10A, VGS = -4.5V (Figures 9, 10)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
VDD = 15V, ID ≅ 10A, RL = 1.5Ω,
RGS = 5Ω, VGS = -5V
(Figure 13)
-
15
-
ns
tr
-
50
-
ns
td(OFF)
-
35
-
ns
tf
-
20
-
ns
tOFF
-
-
80
ns
-
25
30
nC
Qg(TOT)
VGS = 0 to -10V
Gate Charge at -5V
Qg(-5)
VGS = 0 to -5V
Threshold Gate Charge
Qg(TH)
VGS = 0 to -1V
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance, Junction to Case
RθJC
Thermal Resistance, Junction to Ambient
RθJA
VDD = -24V, ID ≅ 10A,
RL = 2.4Ω
Ig(REF) = -0.25mA
(Figure 14)
VDS = -25V, VGS = 0V, f = 1MHz
(Figure 15)
RFD10P03L, RFD10P03LSM
-
13
16
nC
-
1.2
1.5
nC
-
1035
-
pF
-
340
-
pF
-
35
-
pF
-
-
2.30
oC/W
-
-
100
oC/W
80
oC/W
RFP10P03L
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Forward Voltage
Reverse Recovery Time
VSD
trr
NOTE:
2. Pulse Test: Pulse width ≤ 300µs, Duty Cycle ≤ 2%.
7-4
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISD = -10A
-
-
-1.5
V
ISD = -10A, dISD/dt = -100A/µs
-
-
75
ns
RFD10P03L, RFD10P03LSM, RFP10P03L
1.2
-12
1.0
-10
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves Unless Otherwise Specified
0.8
0.6
0.4
-8
-6
-4
-2
0.2
0
25
0
0
25
50
75
100
125
TC , CASE TEMPERATURE (oC)
175
150
75
150
125
100
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
ZθJC, NORMALIZED THERMAL IMPEDANCE
50
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2.0
1.0
0.5
0.2
PDM
0.1
0.1
0.05
0.02
0.01
t1
t2
SINGLE PULSE
0.01
10-5
NOTES: DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC+ TC
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
101
100
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
ID , DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
100µs
-10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
-1
-1
10ms
VDSS MAX = -30V
100ms
DC
-10
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
7-5
-100
IDM , PEAK CURRENT CAPABILITY (A)
-100
-100
TC = 25oC
FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
VGS = -10V
175 – T C
I = I 25 ------------------------
150
VGS = -5V
-10
-5
10-5
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
FIGURE 5. PEAK CURRENT CAPABILITY
101
RFD10P03L, RFD10P03LSM, RFP10P03L
Typical Performance Curves Unless Otherwise Specified
(Continued)
-50
-25
IAS , AVALANCHE CURRENT (A)
STARTING TJ = 25oC
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
ID, DRAIN CURRENT (A)
-20
-10
VGS = -10V
VGS = -4V
-15
STARTING TJ = 150oC
If R = 0
tAV = (L) (IAS)/(1.3 RATED BVDSS - VDD)
IF R ≠ 0
tAV = (L/R) ln [(IAS*R)/(1.3 RATED BVDSS - VDD) + 1]
-1
0.01
VGS = -5V
0.1
1
tAV, TIME IN AVALANCHE (ms)
VGS = -3.5V
-10
VGS = -3V
-5
0
10
0
-2
-1
-3
-5
-4
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
400
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
VDD = -15V
25oC
175oC
-15
-10
-5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
ON RESISTANCE (mΩ)
-20
-55oC
rDS(ON), DRAIN TO SOURCE
ID(ON), ON-STATE DRAIN CURRENT (A)
-25
FIGURE 7. SATURATION CHARACTERISTICS
300
ID = -20A
ID = -10A
ID = -2.5A
100
0
0
-1.5
-3.0
-4.5
ID = -5A
200
0
-2
-6.0
-4
VGS, GATE TO SOURCE VOLTAGE (V)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
1.2
1.5
1.0
0.5
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
7-6
-10
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = -5V, ID = -10A
0
-80
-8
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
2.0
-6
200
ID =- 250uA
1.1
1.0
0.9
0.8
-80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RFD10P03L, RFD10P03LSM, RFP10P03L
Typical Performance Curves Unless Otherwise Specified
(Continued)
150
1.2
VDD = -15V, ID = -10A, RL= 1.50Ω
VGS = VDS, ID = -250µA
SWITCHING TIME (ns)
NORMALIZED GATE
THRESHOLD VOLTAGE
125
1.0
0.8
tr
100
td(OFF)
75
tf
50
0.6
td(ON)
25
0.4
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
0
200
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
-3.75
-22.5
RL = 3.0Ω
IG(REF) = -0.25mA
-15
-7.5
-2.50
0.75 BVDSS
0.75 BVDSS
0.50 BVDSS
0.50 BVDSS
0.25 BVDSS
0.25 BVDSS
-1.25
VGS = -5V
CISS
1000
20
IG(REF)
IG(ACT)
t, TIME ( µs)
80
VGS = 0V, f = 0.1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
800
600
COSS
400
200
CRSS
0.00
0
50
1200
C, CAPACITANCE (pF)
VDD = BVDSS
VDD =BVDSS
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 13. SWITCHING TIME vs GATE RESISTANCE
-5.00
VGS , GATE TO SOURCE VOLTAGE (V)
VDS , DRAIN TO SOURCE VOLTAGE (V)
-30
0
0
IG(REF)
0
IG(ACT)
-5
-10
-15
-20
VDS , DRAIN TO SOURCE VOLTAGE (V)
-25
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
FIGURE 15. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VDS
tAV
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0
-
RG
+
0V
VGS
DUT
tP
IAS
VDD
IAS
VDS
tP
0.01Ω
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
7-7
VDD
BVDSS
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
RFD10P03L, RFD10P03LSM, RFP10P03L
Test Circuits and Waveforms
(Continued)
tON
tOFF
td(OFF)
td(ON)
tf
tr
0
RL
-
DUT
VGS
VDS
VDD
RG
+
10%
10%
90%
90%
VGS
0
10%
50%
50%
PULSE WIDTH
90%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS
RL
VDS
Qg(TH)
0
VGS= -1V
VGS
-
Qg(-5)
+
DUT
VGS= -5V
-VGS
VDD
VGS= -10V
VDD
IG(REF)
Qg(TOT)
0
Ig(REF)
FIGURE 20. GATE CHARGE TEST CIRCUIT
7-8
FIGURE 21. GATE CHARGE WAVEFORMS
RFD10P03L, RFD10P03LSM, RFP10P03L
PSpice Electrical Model
.SUBCKT RFD10P03L 2 1 3
REV 22 Aug 96
CA 12 8 1.29e-9
CB 15 14 9.90e-10
CIN 6 8 1.01e-9
LDRAIN
ESG
-
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DPLCAP 10 6 DPLCAPMOD
10
DRAIN
2
5
+
8
6
RLDRAIN
RSLC1
51
+
EBREAK 5 11 17 18 -36.49
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
RSLC2
5
51
EBREAK
ESLC
+
17
18
-
-
50
DPLCAP
RDRAIN
EVTHRES
+ 19 8
IT 8 17 1
LGATE
LDRAIN 2 5 1e-9
LGATE 1 9 3.40e-9
LSOURCE 3 7 3.22e-9
EVTEMP
RGATE
GATE
1
9
-
20
21
16
MWEAK
6
18 +
22
DBODY
11
MMED
DBREAK
MSTRO
RLGATE
LSOURCE
CIN
MMED 16 6 8 8 MmedMOD
MSTRO 16 6 8 8 MstroMOD
MWEAK 16 21 8 8 MweakMOD
8
SOURCE
3
7
RSOURCE
RLSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 68.25e-3
RGATE 9 20 2.54
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RSourceMOD 25.00e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
12
S2A
13
8
14
13
S1B
18
RVTEMP
CB
6
8
EGS
-
19
14
+
+
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
17
S2B
13
CA
RBREAK
15
-
IT
VBAT
5
8
EDS
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*33),5.0))}
.MODEL DBODYMOD D (IS=9.15e-13 RS=3.25e-2 IKF=0.05 N=0.97 TRS1=4.11e-5 TRS2=2.03e-6 CJO=1.13e-9 M=0.40 TT=3.72e-8)
.MODEL DBREAKMOD D ( RS=2.62e-1 TRS1=1.74e-3 TRS2=-3.81e-6)
.MODEL DPLCAPMOD D (CJO=1.46e-10 IS=1e-30 N=10 M=0.50)
.MODEL MSTRONGMOD PMOS (VTO=-1.95 KP=11.60 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MMEDMOD PMOS (VTO=-1.65 KP=1.00 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.54)
.MODEL MWEAKMOD PMOS (VTO=-1.43 KP=0.09 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=25.4 RS=0.1)
.MODEL RBREAKMOD RES (TC1=9.17e-4 TC2=-2.74e-7)
.MODEL RDRAINMOD RES (TC1=6.35e-3 TC2=1.98e-5)
.MODEL RSOURCEMOD RES (TC1=0 TC2=0)
.MODEL RSCLMOD RES (TC1=2e-3 TC2=0)
.MODEL RVTHRESMOD RES (TC1=1.23e-3 TC2=1.97e-6)
.MODEL RVTEMPMOD RES (TC1=-1.18e-3 TC2=1.44e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.80 VOFF=1.80)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.80 VOFF=4.80)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.40 VOFF=-3.40)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.40 VOFF=-0.40)
ENDS
For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFet Featuring Global Temperature Options; authored by
William J. Hepp and C. Frank Wheatley.
7-9
RFD10P03L, RFD10P03LSM, RFP10P03L
PSpice Thermal Model
7
JUNCTION
REV 29 Aug 96
RFP10P03L
CTHERM1 7 6 5.00e-7
CTHERM2 6 5 5.35e-4
CTHERM3 5 4 5.50e-4
CTHERM4 4 3 1.75e-3
CTHERM5 3 2 1.25e-2
CTHERM6 2 1 0.45
RTHERM1
CTHERM1
6
RTHERM1 7 6 1.00e-2
RTHERM2 6 5 2.05e-2
RTHERM3 5 4 5.39e-2
RTHERM4 4 3 5.45e-1
RTHERM5 3 2 1.01
RTHERM6 2 1 0.50
RTHERM2
CTHERM2
5
RTHERM3
RFD10P03L, RFD10P03LSM
CTHERM1 7 6 5.00e-7
CTHERM2 6 5 5.35e-4
CTHERM3 5 4 5.50e-4
CTHERM4 4 3 1.75e-3
CTHERM5 3 2 1.25e-2
CTHERM6 2 1 0.11
CTHERM3
4
RTHERM4
RTHERM1 7 6 1.00e-2
RTHERM2 6 5 2.05e-2
RTHERM3 5 4 5.39e-2
RTHERM4 4 3 5.45e-1
RTHERM5 3 2 1.01
RTHERM6 2 1 0.50
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
1
CASE
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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