UJA1018 LIN system basis chip with LED drivers Rev. 1 — 10 July 2012 Product data sheet 1. General description The UJA1018 is a LIN 2.0/2.1/2.2/SAE J2602 transceiver with an integrated low-drop voltage regulator. The voltage regulator can deliver up to 70 mA at 5.0 V. The UJA1018 facilitates the development of compact nodes in LIN bus systems. In addition, the UJA1018 supports LIN node address assignment in daisy chain networks via a LIN bus switch. To support robust designs, the UJA1018 offers strong ElectroStatic Discharge (ESD) performance and can withstand high voltages on the LIN bus. In order to minimize current consumption, the UJA1018 supports a Sleep mode in which the LIN transceiver and the voltage regulator are powered down while still having wake-up capability via the LIN bus. Three high-side switches are integrated into the UJA1018. They are intended to support a variety of applications, including LED control for ambient lighting. The UJA1018 comes in a 3.5 mm 5.5 mm HVSON16 package to help minimize board size. The exposed center pad in the HVSON16 package provides enhanced thermal performance. 2. Features and benefits 2.1 General LIN 2.0/2.1/2.2 compliant SAE J2602 compliant Downward compatible with LIN 1.3 Internal LIN slave termination resistor Slave Node Position Detection (SNPD) supported by LIN bus switch Voltage regulator offering 5 V, 70 mA capability 2 % voltage regulator accuracy over specified temperature and supply ranges Voltage regulator output undervoltage detection with reset output Voltage regulator short-circuit proof to ground Voltage regulator stable with ceramic, tantalum and aluminum electrolyte capacitors 3 high-side switches delivering up to 30 mA (e.g. to provide complete control over color blending and brightness in LEDs) Robust ESD performance; 8 kV according to IEC61000-4-2 for pins LIN and BAT Pins LIN and BAT protected against transients in the automotive environment (ISO 7637) Very low LIN bus leakage current of <2 A when battery not connected LIN pin short-circuit proof to battery and ground UJA1018 NXP Semiconductors LIN system basis chip with LED drivers Transmit data (TXD) dominant time-out function Thermally protected Very low ElectroMagnetic Emissions (EME) High ElectroMagnetic Immunity (EMI) Typical Standby mode current of 47 A Typical Sleep mode current of 14 A LIN bus wake-up function K-line compatible Leadless HVSON16 package with improved Automated Optical Inspection (AOI) capability Dark green product (halogen free and Restriction of Hazardous Substances (RoHS) compliant) 3. Ordering information Table 1. Ordering information Type number UJA1018TK Package Name Description Version HVSON16 plastic thermal enhanced very thin small outline package; no leads; 16 terminals; body 3.5 5.5 0.85 mm SOT1308-1 4. Marking Table 2. UJA1018 Product data sheet Marking codes Type number Marking code UJA1018TK UJA1018 All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 2 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 5. Block diagram UJA1018 OVERTEMP DETECTION VOLTAGE REFERENCE BAT VCC VOLTAGE REGULATOR VCC UV DET VBAT UV DET HS0 HS1 HS2 VCC CONTROL RSTN VCC LIN TRANSCEIVER TXD TIMEOUT TIMER TXD LIN RXD EN GND LINSW LINOFF HSON0 HSON1 HSON2 Fig 1. 015aaa321 Block diagram UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 3 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 6. Pinning information 6.1 Pinning Transparent top view terminal 1 index area HS0 1 16 HSON0 HS1 2 15 HSON1 HS2 3 14 HSON2 BAT 4 13 VCC UJA1018 EN 5 12 RSTN GND 6 11 TXD LIN 7 10 RXD LINSW 8 9 LINOFF 015aaa322 Fig 2. Pin configuration diagram 6.2 Pin description Table 3. Symbol Pin Description HS0 1 high-side switch output 0 HS1 2 high-side switch output 1 HS2 3 high-side switch output 2 BAT 4 battery supply for UJA1018 EN 5 enable input GND 6[1] ground LIN 7 LIN bus line LINSW 8 LIN switch LINOFF 9 LIN switch control input RXD 10 LIN receive data output TXD 11 LIN transmit data input RSTN 12 reset output (active LOW) VCC 13 voltage regulator output HSON2 14 high-side switch input 2 HSON1 15 high-side switch input 1 HSON0 16 high-side switch input 0 [1] UJA1018 Product data sheet Pin description For enhanced thermal and electrical performance, the exposed center pad of the HVSON16 package should be soldered to board ground (and not to any other voltage level). All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 4 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 7. Functional description The UJA1018 combines the functionality of a LIN transceiver and a voltage regulator in a single chip and supports wake-up by bus activity. The voltage regulator is designed to power the Electronic Control Unit's (ECU) microcontroller and its peripherals. The LIN transceiver is the interface between the LIN master/slave protocol controller and the physical bus in a LIN network. According to the Open System Interconnect (OSI) model, these modules make up the LIN physical layer. The LIN transceiver is optimized for, but not limited to, automotive applications with a transmission speed of 20 kBd (the maximum specified in the LIN standard) and excellent ElectroMagnetic Compatibility (EMC) performance. The UJA1018 comes with three integrated high-side switches for use in applications such as LED ambient lighting. The switches are designed to drive up to 30 mA. 7.1 Slave Node Position Detection (SNPD) The UJA1018 supports Slave Node Position Detection (SNPD). The LIN switch method (LSM) is used to detect the position of LSM slave nodes in a daisy chain LIN network. Unique addresses are assigned to individual nodes at start-up based on their position on the bus, allowing a number of functionally identical modules to be included in a network. LSM slave nodes can be combined with standard nodes in any order. In order to detect the position of an LSM slave node in a network, a switch is connected between pins LIN and LINSW. When closed, this switch connects the LIN bus to the next node in the daisy chain, allowing the master to address each node in turn. 7.2 LIN 2.x/SAE J2602 compliant The UJA1018 is fully LIN 2.0, LIN 2.1, LIN 2.2 and SAE J2602 compliant. Since the LIN physical layer is independent of higher OSI model layers (e.g. the LIN protocol), nodes containing a LIN 2.2-compliant physical layer can be combined, without restriction, with LIN physical layer nodes that comply with earlier revisions (i.e. LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3, LIN 2.0 and LIN 2.1). 7.3 Operating modes The UJA1018 supports four operating modes: Normal, Standby, Sleep and Off. The operating modes, and the transitions between modes, are illustrated in Figure 3. UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 5 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers aII states VBAT < Vth(det)poff OR Tvj > Tth(act)otp remote wake-up VBAT > Vth(det)pon AND Tvj < Tth(rel)otp OFF LIN = off RXD = floating RSTN = LOW EN = 1 AND RSTN = 1 STANDBY NORMAL(1) LIN = off (RXD signals wake source) EN = 1 0 AND TXD = 1 AND RSTN = 1 LIN = on EN = 1 0 AND(3) EN = 1 TXD = 0 AND RSTN = 1 wake-up(3) event SLEEP LIN = off RXD = VCC(2) RSTN = LOW Voltage regulator - on Voltage regulator - off 015aaa323 (1) In Normal mode, the LIN transmitter is enabled - but if EN and/or RSTN go LOW, the LIN transmitter will be disabled. Remote wake-up signaling will be activated. (2) Until VCC drops below 2 V. (3) If a wake-up event and a go-to-sleep event occur simultaneously, the device will switch directly to Standby mode without initiating a reset. Fig 3. State diagram 7.3.1 Off mode The UJA1018 switches to Off mode from all other modes if the battery supply voltage drops below the power-off detection threshold (Vth(det)poff) or the junction temperature exceeds the overtemperature protection activation threshold (Tth(act)otp). The voltage regulator and the LIN physical layer are disabled in Off mode, and pin RSTN is forced LOW. 7.3.2 Standby mode Standby mode is a low-power mode that guarantees very low current consumption. The UJA1018 switches from Off mode to Standby mode as soon as the battery supply voltage rises above the power-on detection threshold (VBAT > Vth(det)pon), provided the junction temperature is below the overtemperature protection release threshold (Tvj < Tth(rel)otp). The UJA1018 switches to Standby mode from Normal mode during the mode select window if TXD is HIGH and EN is LOW (see Section 7.3.5), provided RSTN is HIGH. A remote wake-up event triggers a transition to Standby mode from Sleep mode. A remote wake-up event is signalled by a continuous LOW level on pin RXD. UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 6 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers In Standby mode, the voltage regulator is on, the LIN physical layer is disabled and remote wake-up detection is active. The wake-up source is indicated by the level on RXD (LOW indicates a remote wake-up). 7.3.3 Normal mode If the EN pin is pulled HIGH while the UJA1018 is in Standby mode (with RSTN = 1) or Sleep mode, the device enters Normal mode. The LIN physical layer and the voltage regulator are enabled in Normal mode. 7.3.3.1 The LIN transceiver in Normal mode The LIN transceiver is activated when the UJA1018 enters Normal mode. In Normal mode, the transceiver can transmit and receive data via the LIN bus. The receiver detects data streams on the LIN pin and transfers them to the microcontroller via pin RXD. LIN recessive is represented by a HIGH level on RXD, LIN dominant by a LOW level. The transmitter converts data streams received from the protocol controller into bus signals with optimized slew rate and wave shaping to minimize EME. A LOW level on the TXD input is converted to a LIN dominant level while a HIGH level is converted to a LIN recessive level. 7.3.4 Sleep mode Sleep mode features extremely low power consumption. The UJA1018 switches to Sleep mode from Normal mode during the mode select window if TXD and EN are both LOW (see Section 7.3.5), provided RSTN is HIGH. The voltage regulator and the LIN physical layer are disabled in Sleep mode. Pin RSTN is forced LOW. Remote wake-up detection is active. 7.3.5 Transition from Normal to Sleep or Standby mode When EN is driven LOW in Normal mode, the UJA1018 disables the transmit path. The mode select window opens tmsel(min) after EN goes LOW. It closes tmsel(max) after EN goes LOW (see Figure 4). The TXD pin is sampled in the mode select window. A transition to Standby mode is triggered if TXD is HIGH, or to Sleep mode if TXD is LOW. TXD must remain HIGH or LOW, as appropriate, while the mode select window is open. To avoid complicated timing in the application, EN and TXD can be pulled LOW at the same time without affecting the LIN bus. To ensure that the remote wake-up time (twake(dom)LIN) is not reset on a transition to Sleep mode, TXD should be pulled LOW at least td(EN-TXD) after EN goes LOW. This functionality is guaranteed by design. UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 7 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers EN TXD operating mode mode select window Normal Normal with TXD path blocked Sleep or Standby depending on TXD level in mode select window tmsel(min) tmsel(max) 015aaa087 TXD is sampled during the mode select window. The UJA1018 switches to Standby (TXD HIGH) or Sleep (TXD LOW) mode after sampling. Fig 4. Transition from Normal to Sleep/Standby mode 7.4 Power supplies 7.4.1 Battery (pin BAT) The UJA1018 contains a single supply pin, BAT. An external diode is needed in series to protect the device against negative voltages. The operating range is from 5.5 V to 18 V. The UJA1018 can handle voltages up to 40 V (max). If the voltage on pin BAT falls below Vth(det)poff, the UJA1018 switches to Off mode, shutting down the internal logic and the voltage regulator and disabling the LIN transmitter. The UJA1018 exits Off mode as soon as the voltage rises above Vth(det)pon, provided the junction temperature is below Tth(rel)otp. 7.4.2 Voltage regulator (pin VCC) The UJA1018 contains a voltage regulator, supplied via pin BAT, that delivers up to 70 mA. It is designed to supply the microcontroller and its periphery via pin VCC. 7.4.3 Reset (pin RSTN) The output voltage on pin VCC is monitored continuously and a system reset signal is generated (pin RSTN goes LOW) if an undervoltage event is detected (VCC < Vuvd for tdet(uv)(VCC)). Pin RSTN will go HIGH again once the voltage on VCC exceeds the undervoltage recovery threshold (Vuvr) for trst. 7.5 LIN transceiver The transceiver is the interface between a LIN master/slave protocol controller and the physical bus in a LIN network. It is primarily intended for in-vehicle subnetworks using baud rates from 2.4 kBd up to 20 kBd and is LIN 2.0/LIN 2.1/LIN 2.2/SAE J2602 compliant. 7.6 Remote wake-up A remote wake-up is triggered by a falling edge on pin LIN, followed by LIN remaining LOW for at least twake(dom)LIN, followed by a rising edge on pin LIN (see Figure 5). UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 8 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers LIN recessive VBAT VBUSrec VLIN VBUSdom twake(dom)LIN LIN dominant ground Standby/Sleep mode RXD Sleep: floating/Standby: HIGH Standby mode LOW 015aaa088 Fig 5. Remote wake-up behavior The remote wake-up request is communicated to the microcontroller in Standby mode by a continuous LOW level on pin RXD. Note that twake(dom)LIN is measured in Sleep and Standby modes, and in Normal mode if TXD is HIGH. 7.7 LIN switch The LIN switch is controlled via input pin LINOFF. When LINOFF is LOW, the switch is closed and the LIN bus is connected to the output pin LINSW. If pin LINOFF is HIGH, the LIN bus transmission from LIN to LINSW is interrupted. An internal pull-down resistor ensures that a defined signal level is always present on pin LINOFF. The input level on pin LINOFF is ignored when pin RSTN is LOW or overtemperature protection has been activated. The internal default input state is LOW (transmission activated). 7.8 High-side switches The high-side switches on pins HS0, HS1 and HS2 are controlled via input pins HSON0, HSON1 and HSON2, respectively. A high-side switch is ON when the corresponding control input pin is HIGH. Internal pull-down resistors on HSON0, HSON1 and HSON2 ensure that a defined level is always present on these pins when the switch is off. The input levels on pins HSON0, HSON1 and HSON2 are ignored when RSTN is LOW. The internal default input state is LOW. 7.9 Fail-safe features 7.9.1 General fail-safe features The following general fail-safe features have been implemented: • An internal pull-up towards VCC on pin TXD guarantees a recessive bus level if the pin is left floating by a bad solder joint or a floating microcontroller port pin. UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 9 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers • The current in the transmitter output stage is limited to protect the transmitter against short circuits to pin BAT. • A loss of power (pins BAT and GND) has no impact on the microcontroller; no reverse currents flow from the bus. • The LIN transmitter is automatically disabled when either EN or RSTN is LOW. • After a transition to Normal mode, the LIN transmitter will only be activated when pin TXD is HIGH (LIN recessive). 7.9.2 TXD dominant time-out function If a hardware or software application failure causes TXD to be held permanently LOW, a TXD dominant time-out timer circuit is activated. This function prevents the bus line being driven to a permanent dominant state (blocking all network communications). The timer is triggered by a negative edge on the TXD pin. If TXD remains LOW for longer than the TXD dominant time-out time (tto(dom)TXD), the transmitter is disabled, driving the bus line to a recessive state. The timer is reset by a positive edge on TXD. 7.9.3 Temperature protection The temperature of the IC is monitored in Normal, Standby and Off modes. If the temperature is too high (Tvj > Tth(act)otp), the UJA1018 switches to Off mode (if in Standby or Normal modes). The voltage regulator and the LIN transmitter are switched off and the RSTN pin is driven LOW. When the temperature falls below the overtemperature protection release threshold (Tvj < Tth(rel)otp), the UJA1018 switches to Standby mode. UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 10 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VBAT battery supply voltage DC; continuous 0.3 +40 V Vx voltage on pin x DC value pin VCC 0.3 +7 V pins TXD, RXD, RSTN, EN, HSONx, HSx and LINOFF 0.3 VCC + 0.3 V pins LIN and LINSW with respect to GND; VLIN = VLINSW 40 +40 V pins LINSW with respect to LIN; VLINOFF = VCC 0.3 +18 V 200 +200 mA 8 +8 kV 2 +2 kV 8 +8 kV 250 +250 V 750 +750 V I(LIN-LINSW) current from pin LIN to pin LINSW VESD electrostatic discharge voltage [1] HBM pins LIN, LINSW and BAT [2] any other pin IEC 61000-4-2 [3] pins LIN, LINSW and BAT [4] MM any pin [5] CDM corner pins 500 +500 V [6] 150 +100 V [7] 40 +150 C 55 +150 C any other pin transient voltage Vtrt on pin BAT via reverse polarity diode/capacitor; on pins LIN and LINSW via 1 nF coupling capacitor Tvj virtual junction temperature Tstg storage temperature [1] Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k). [2] VCC and BAT connected to GND, emulating application circuit. [3] ESD performance of pins LIN and BAT according to IEC 61000-4-2 (150 pF, 330 ) has been verified by an external test house. [4] Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 H, 10 ). [5] Charged Device Model (CDM): according to AEC-Q100-011 (field induced charge; 4 pF). [6] Verified by an external test house to ensure that the pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b. [7] Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tj = Tamb + P Rth(j-a), where Rth(j-a) is a fixed value. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 11 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 9. Thermal characteristics Table 5. Symbol Rth(j-a) Thermal characteristics Parameter Conditions thermal resistance from junction to ambient Typ Unit HVSON16; single-layer board [1] 80 K/W HVSON16; four-layer board [2] 40 K/W [1] According to JEDEC JESD51-2 and JESD51-3 at natural convection on 1s board. [2] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer. 10. Static characteristics Table 6. Static characteristics VBAT = 5.5 V to 18 V; Tvj = 40 C to +150 C; RL(LIN-BAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Standby mode; VLIN = VBAT - 47 61 A Sleep mode; VLIN = VBAT - 14 20 A Normal mode; bus recessive; VLIN = VBAT; VRXD = VCC; VRSTN = HIGH - 850 1800 A Normal mode; bus dominant; VBAT = 12 V; VTXD = 0 V; VRSTN = HIGH - 2.0 4.5 mA VBAT = 2 V to 28 V - - 5.25 V Supply; pin BAT IBAT battery supply current Vth(det)pon power-on detection threshold voltage Vth(det)poff power-off detection threshold voltage 3 - 4.2 V Vhys(det)pon power-on detection hysteresis voltage 50 - - mV 5 5.1 V Supply; pin VCC VCC supply voltage VCC(nom) = 5 V; ICC = 70 mA to 0 mA 4.9 IOlim output current limit VCC = 0 V to 5.5 V 250 - 70 mA Vuvd undervoltage detection voltage VCC(nom) = 5 V 4.5 - 4.75 V Vuvr undervoltage recovery voltage VCC(nom) = 5 V 4.6 - 4.9 V R(BAT-VCC) resistance between pin BAT and pin VCC VCC(nom) = 5 V; VBAT = 4.5 V to 5.5 V; ICC = 70 mA to 5 mA; regulator in saturation Tvj = 85 C - - 7 Tvj = 150 C - - 9 1.8 10 - F Co equivalent series resistance < 5 output capacitance [1] [2] [2] LIN transmit data input; pin TXD Vth(sw) switching threshold voltage VCC = 4.5 V to 5.5 V 0.3 VCC - 0.7 VCC V Vhys(i) input hysteresis voltage VCC = 4.5 V to 5.5 V 200 - - mV UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 12 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers Table 6. Static characteristics …continued VBAT = 5.5 V to 18 V; Tvj = 40 C to +150 C; RL(LIN-BAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified. Symbol Parameter Rpu pull-up resistance Conditions Min Typ Max Unit 5 12 25 k LIN receive data output; pin RXD IOH HIGH-level output current Normal mode; VLIN = VBAT; VRXD = VCC 0.4 V - - 0.4 mA IOL LOW-level output current Normal mode; VLIN = GND; VRXD = 0.4 V 0.4 - - mA Enable input; pin EN Vth(sw) switching threshold voltage 0.8 - 2 V Rpd pull-down resistance 50 130 400 k High-side switch inputs; pins HSON0, HSON1 and HSON2 Vth(sw) switching threshold voltage VCC = 4.5 V to 5.5 V 0.3 VCC - 0.7 VCC V Vhys(i) input hysteresis voltage VCC = 4.5 V to 5.5 V 200 - - mV Rpd pull-down resistance 50 130 400 k 0.3 VCC - 0.7 VCC V LIN switch control input; pin LINOFF Vth(sw) switching threshold voltage VCC = 4.5 V to 5.5 V Vhys(i) input hysteresis voltage VCC = 4.5 V to 5.5 V Rpd pull-down resistance 200 - - mV 50 130 400 k Reset output; pin RSTN Rpu pull-up resistance VRSTN = VCC 0.4 V; VCC = 4.5 V to 5.5 V 3 - 12 k IOL LOW-level output current VRSTN = 0.4 V; VCC = 4.5 V to 5.5 V; 40 C < Tvj < 195 C 3.2 - 40 mA VOL LOW-level output voltage VCC = 2.5 V to 5.5 V; 40 C < Tvj < 195 C 0 - 0.5 V VOH HIGH-level output voltage 40 C < Tvj < 195 C 0.8 VCC - VCC + 0.3 V High-side switch outputs; pins HS0, HS1 and HS2 Ron on-state resistance from pin HSx to pin VCC; VHSONx = VCC; IHSx = 30 mA - 4 8 IL leakage current VHSONx = 0 V; VHSx = 0 V - - 1 A LIN switch; pin LINSW Ron on-state resistance from pin LIN to pin LINSW; VLIN = 1 V; VLINOFF = 0 V; VBAT = 4.5 V to 18 V - 1 2 IL leakage current VLINOFF = VCC; VLINSW = VBAT; measured after recessive-to-dominant transition - - 1 A LIN bus line; pin LIN IBUS_LIM current limitation for driver dominant state VBAT = VLIN = 18 V; VTXD = 0 V 40 - 100 mA IBUS_PAS_rec receiver recessive input leakage current VLIN = 18 V; VBAT = 5.5 V; VTXD = VCC - - 2 A UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 13 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers Table 6. Static characteristics …continued VBAT = 5.5 V to 18 V; Tvj = 40 C to +150 C; RL(LIN-BAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IBUS_PAS_dom receiver dominant input leakage current including pull-up resistor Normal mode; VTXD = VCC; VLIN = 0 V; VBAT = 12 V 600 - - A IBUS_NO_GND loss-of-ground bus current VBAT = 18 V; VLIN = 0 V 750 - +10 A IBUS_NO_BAT loss-of-battery bus current VBAT = 0 V; VLIN = 18 V - - 2 A VBUSrec receiver recessive state 0.6 VBAT - - V VBUSdom receiver dominant state - - 0.4 VBAT V VBUS_CNT receiver center voltage VBUS_CNT = (VBUSdom + VBUSrec) / 2 0.475 0.5 VBAT VBAT 0.525 VBAT V VHYS receiver hysteresis voltage VHYS = VBUSrec VBUSdom 0.05 VBAT 0.15 VBAT 0.175 VBAT V VSerDiode voltage drop at the serial diode in pull-up path with Rslave; ISerDiode = 0.9 mA [2] 0.4 - 1.0 V CLIN capacitance on pin LIN with respect to GND [2] - - 39 pF VO(dom) dominant output voltage Normal mode; VTXD = 0 V; VBAT = 7 V - - 1.4 V Normal mode; VTXD = 0 V; VBAT = 18 V - - 2.0 V between pins LIN and BAT VLIN = 0 V; VBAT = 12 V 27 40 60 k Rslave slave resistance Temperature protection Tth(act)otp overtemperature protection activation threshold temperature 165 180 195 C Tth(rel)otp overtemperature protection release threshold temperature 126 138 150 C [1] See Figure 1. [2] Not tested in production; guaranteed by design. UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 14 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 015aaa367 7 R(BAT-VCC)(typ) (Ω) 6 5 4 3 2 -50 0 50 100 150 Tvj (°C) Fig 6. UJA1018 Product data sheet Graph of R(BAT-VCC)(typ) as a function of junction temperature (Tvj) All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 15 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 11. Dynamic characteristics Table 7. Dynamic characteristics VBAT = 5.5 V to 18 V; Tvj = 40 C to +150 C; RL(LIN-BAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1] Symbol Parameter Conditions Min duty cycle 1 Vth(rec)(max) = 0.744VBAT; Vth(dom)(max) = 0.581VBAT; tbit = 50 s; VBAT = 7 V to 18 V [2] Vth(rec)(max) = 0.76VBAT; Vth(dom)(max) = 0.593VBAT; tbit = 50 s; VBAT = 5.5 V to 7.0 V [2] Vth(rec)(min) = 0.422VBAT; Vth(dom)(min) = 0.284VBAT: tbit = 50 s; VBAT = 7.6 V to 18 V [3] Vth(rec)(min) = 0.41VBAT; Vth(dom)(min) = 0.275VBAT; tbit = 50 s; VBAT = 6.1 V to 7.6 V [3] Vth(rec)(max) = 0.778VBAT; Vth(dom)(max) = 0.616VBAT; tbit = 96 s; VBAT = 7 V to 18 V [2][3] Vth(rec)(max) = 0.797VBAT; Vth(dom)(max) = 0.630VBAT; tbit = 96 s; VBAT = 5.5 V to 7 V [2][3] Vth(rec)(min) = 0.389VBAT Vth(dom)(min) = 0.251VBAT tbit = 96 s VBAT = 7.6 V to 18 V [3][4] Vth(rec)(min) = 0.378VBAT; Vth(dom)(min) = 0.242VBAT; tbit = 96 s; VBAT = 6.1 V to 7.6 V [3][4] Typ Max Unit Duty cycles 1 2 3 4 duty cycle 2 duty cycle 3 duty cycle 4 0.396 - - 0.396 - - - - 0.581 - - 0.581 [3][4] [3][4] [4][5] [4][5] 0.417 - - 0.417 - - - - 0.590 - - 0.590 - - 6 [4] [4] [5] [5] Timing characteristics rising and falling; CRXD = 20 pF s trx_pd receiver propagation delay trx_sym receiver propagation delay symmetry CRXD = 20 pF 2 - +2 s twake(dom)LIN LIN dominant wake-up time Sleep mode 30 80 150 s tto(dom)TXD TXD dominant time-out time VTXD = 0 V 6 - 20 ms tmsel mode select time 3 - 20 s 0 - 1 s 1 - 15 s 2 - 8 ms [6] td(EN-TXD) delay time from EN to TXD tdet(uv)(VCC) undervoltage detection time on pin VCC CRSTN = 20 pF Reset output; pin RSTN trst UJA1018 Product data sheet reset time All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 16 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers Table 7. Dynamic characteristics …continued VBAT = 5.5 V to 18 V; Tvj = 40 C to +150 C; RL(LIN-BAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit LIN switch; pin LINSW ton turn-on time to switch closed 4 - 14 s toff turn-off time to switch open 10 - 60 s High-side switch outputs; pins HS0, HS1 and HS2 ton turn-on time HSONx 01; CL = 20 pF; RL = 162 ; 90 % voltage 0.5 - 6 s toff turn-off time HSONx 10; CL = 20 pF; RL = 162 ; 10 % voltage 0.5 - 6 s [1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage ranges. [2] t bus rec min . Variable tbus(rec)(min) is illustrated in the LIN timing diagram in Figure 7. 1 3 = ------------------------------2 t bit [3] Bus load conditions are: CBUS = 1 nF and RBUS = 1 k; CBUS = 6.8 nF and RBUS = 660 ; CBUS = 10 nF and RBUS = 500 . [4] For VBAT > 18 V, the LIN transmitter may be suppressed; the LIN transmitter output is recessive if TXD is HIGH. [5] t bus rec max 2 4 = ------------------------------- . Variable tbus(rec)(max) is illustrated in the LIN timing diagram in Figure 7. 2 t bit [6] Not tested in production; guaranteed by design. tbit tbit tbit VTXD tbus(rec)(min) tbus(dom)(max) Vth(rec)(max) Vth(dom)(max) VBAT LIN bus signal Vth(rec)(min) Vth(dom)(min) tbus(dom)(min) output of receiving node A VRXD output of receiving node B VRXD thresholds of receiving node A thresholds of receiving node B tbus(rec)(max) trx_pdf trx_pdr trx_pdr trx_pdf 015aaa199 Fig 7. LIN transceiver timing diagram UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 17 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 12. Application information 12.1 Application diagram LIN BUS LINE VECU VCC VDD RXD RX0 TXD TX0 Px.x MICROCONTROLLER EN Px.y 4 11 9 8 LINSW 5 UJA1018 RST_N Py.x0 Py.x1 GND LINOFF 10 BAT 13 Py.x2 RSTN HSON0 HSON1 HSON2 12 7 LIN 16 15 14 1 2 HS0 6 3 HS1 HS2 GND 015aaa324 Fig 8. Application diagram 12.2 ESD robustness according to LIN EMC test specification ESD robustness (IEC 61000-4-2) has been tested by an external test house according to the LIN EMC test specification (part of Conformance Test Specification Package for LIN 2.1, October 10th, 2008). The test report is available on request. Table 8. Pin Test configuration Value Unit LIN no capacitor connected to LIN pin 11 kV 220 pF capacitor connected to LIN pin 10 kV no capacitor connected to LINSW pin > 11 kV 220 pF capacitor connected to LIN pin > 10 kV 100 nF capacitor connected to VBAT pin > 12 kV LINSW VBAT UJA1018 Product data sheet ESD robustness (IEC 61000-4-2) according to LIN EMC test specification All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 18 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 12.3 Hardware requirements for LIN interfaces in automotive applications The UJA1018 satisfies the "Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications", Version 1.2, March 2011. 13. Test information 13.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 19 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 14. Package outline HVSON16: plastic thermal enhanced very thin small outline package; no leads; 16 terminals; body 3.5 x 5.5 x 0.85 mm SOT1308-1 X D B A A E A1 A3 detail X terminal 1 index area terminal 1 index area e1 e v w b 1 8 C C A B C y1 C y L E1 K 16 9 D1 0 3 Unit mm 6 mm scale Dimensions A A1 max 1.00 0.05 nom 0.85 min 0.80 0.00 A3 b D D1 E E1 0.2 0.35 0.32 0.29 5.6 5.5 5.4 3.75 3.70 3.65 3.6 3.5 3.4 e e1 1.85 1.80 0.65 4.55 1.75 k L v 0.1 0.2 0.55 0.50 0.45 w y 0.05 0.05 y1 0.1 sot1308-1_po Outline version SOT1308-1 Fig 9. References IEC JEDEC JEITA European projection Issue date 11-07-04 11-11-25 MO-229 Package outline SOT1308 (HVSON16) UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 20 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 16.3 Wave soldering Key characteristics in wave soldering are: UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 21 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 10) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9 and 10 Table 9. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 10. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 10. UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 22 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 10. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 17. Soldering of HVSON packages Section 16 contains a brief introduction to the techniques most commonly used to solder Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON leadless package ICs can be found in the following application notes: • AN10365 ‘Surface mount reflow soldering description” • AN10366 “HVQFN application information” UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 23 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 18. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes UJA1018 v.1 20120710 Product data sheet - - UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 24 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. UJA1018 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 25 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] UJA1018 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 July 2012 © NXP B.V. 2012. All rights reserved. 26 of 27 UJA1018 NXP Semiconductors LIN system basis chip with LED drivers 21. Contents 1 2 2.1 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.3.1 7.3.4 7.3.5 7.4 7.4.1 7.4.2 7.4.3 7.5 7.6 7.7 7.8 7.9 7.9.1 7.9.2 7.9.3 8 9 10 11 12 12.1 12.2 12.3 13 13.1 14 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Slave Node Position Detection (SNPD) . . . . . . 5 LIN 2.x/SAE J2602 compliant . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5 Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7 The LIN transceiver in Normal mode . . . . . . . . 7 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Transition from Normal to Sleep or Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 8 Battery (pin BAT) . . . . . . . . . . . . . . . . . . . . . . . 8 Voltage regulator (pin VCC) . . . . . . . . . . . . . . . 8 Reset (pin RSTN) . . . . . . . . . . . . . . . . . . . . . . . 8 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 8 Remote wake-up . . . . . . . . . . . . . . . . . . . . . . . 8 LIN switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 High-side switches . . . . . . . . . . . . . . . . . . . . . . 9 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 9 General fail-safe features . . . . . . . . . . . . . . . . . 9 TXD dominant time-out function . . . . . . . . . . . 10 Temperature protection. . . . . . . . . . . . . . . . . . 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal characteristics . . . . . . . . . . . . . . . . . 12 Static characteristics. . . . . . . . . . . . . . . . . . . . 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 16 Application information. . . . . . . . . . . . . . . . . . 18 Application diagram . . . . . . . . . . . . . . . . . . . . 18 ESD robustness according to LIN EMC test specification . . . . . . . . . . . . . . . . . . . . . . . 18 Hardware requirements for LIN interfaces in automotive applications . . . . . . . . . . . . . . . 19 Test information . . . . . . . . . . . . . . . . . . . . . . . . 19 Quality information . . . . . . . . . . . . . . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 15 16 16.1 16.2 16.3 16.4 17 18 19 19.1 19.2 19.3 19.4 20 21 Handling information . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Soldering of HVSON packages . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 21 21 22 23 24 25 25 25 25 26 26 27 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 July 2012 Document identifier: UJA1018