Data Sheet

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5646C
Rev.6, 02/2014
MPC5646C
MAPBGA–225
QFN12
208-pin LQFP
##_mm_x_##mm
256 15
MAPBGA
mm x 15 mm
(17 mm x 17 mm)
MPC5646C
Microcontroller Data Sheet
On-chip modules available within the family
include the following features:
• e200z4d dual issue, 32-bit core Power
Architecture compliant CPU
— Up to 120 MHz
— 4 KB, 2/4-Way Set Associative
Instruction Cache
— Variable length encoding (VLE)
— Embedded floating-point (FPU) unit
— Supports Nexus3+
• e200z0h single issue, 32-bit core Power
Architecture compliant CPU
— Up to 80 MHz
— Variable length encoding (VLE)
— Supports Nexus3+
• Up to 3 MB on-chip flash memory: flash
page buffers to improve access time
• Up to 256 KB on-chip SRAM
• 64 KB on-chip data flash memory to
support EEPROM emulation
• Up to 16 semaphores across all slave ports
• User selectable MBIST
• Low-power modes supported: STOP,
HALT, STANDBY
• 16 region Memory Protection Unit (MPU)
• Dual-core Interrupt Controller (INTC).
Interrupt sources can be routed to
SOT-343R
##_mm_x_##mm
176-pin LQFP
(24 mm x 24 mm)
TBD
PKG-TBD
## mm x ## mm
e200z4d, e200z0h, or both.
• Crossbar switch architecture for concurrent
access to peripherals, flash memory, and
SRAM from multiple bus masters
• 32 channel eDMA controller with
DMAMUX
• Timer supports input/output channels
providing 16-bit input capture, output
compare, and PWM functions (eMIOS)
• 2 analog-to-digital converters (ADC): one
10-bit and one 12-bit
• Cross Trigger Unit (CTU) to enable
synchronization of ADC conversions with a
timer event from the eMIOS or from the PIT
• Up to 8 serial peripheral interface (DSPI)
modules
• Up to 10 serial communication interface
(LINFlex) modules
• Up to 6 full CAN (FlexCAN) modules with
64 MBs each
• CAN Sampler to catch ID of CAN message
• 1 inter IC communication interface (I2C)
module
• Up to 177 (LQFP) or 199 (BGA)
configurable general purpose I/O pins
• 1 System Timer Module (STM) with four
32-bit compare channels
• Up to 8 periodic interrupt timers (PIT) with
32-bit counter resolution
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009-2014. All rights reserved.
(28 mm x 28 mm)
Table of Contents
2
3
4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Document Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Package pinouts and signal descriptions . . . . . . . . . . . . . . . .10
3.1 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.3 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .41
4.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.2.1 NVUSRO [PAD3V5V(0)] field description . . . . .42
4.2.2 NVUSRO [PAD3V5V(1)] field description . . . . .42
4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .42
4.4 Recommended operating conditions . . . . . . . . . . . . . .44
4.5 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .47
4.5.1 Package thermal characteristics . . . . . . . . . . . .47
4.5.2 Power considerations. . . . . . . . . . . . . . . . . . . . .48
4.6 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .48
4.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.6.2 I/O input DC characteristics . . . . . . . . . . . . . . . .49
4.6.3 I/O output DC characteristics. . . . . . . . . . . . . . .50
4.6.4 Output pin transition times . . . . . . . . . . . . . . . . .52
4.6.5 I/O pad current specification . . . . . . . . . . . . . . .53
4.7 RESET electrical characteristics. . . . . . . . . . . . . . . . . .55
4.8 Power management electrical characteristics. . . . . . . .57
4.8.1 Voltage regulator electrical characteristics . . . .57
4.8.2 VDD_BV options . . . . . . . . . . . . . . . . . . . . . . . .59
4.8.3 Voltage monitor electrical characteristics. . . . . .60
4.9 Low voltage domain power consumption . . . . . . . . . . .61
4.10 Flash memory electrical characteristics . . . . . . . . . . . .63
4.10.1 Program/Erase characteristics. . . . . . . . . . . . . .63
4.10.2 Flash memory power supply DC characteristics65
4.10.3 Flash memory start-up/switch-off timings . . . . .66
4.11 Electromagnetic compatibility (EMC) characteristics . .66
4.11.1 Designing hardened software to avoid noise
5
6
7
problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.11.2 Electromagnetic interference (EMI) . . . . . . . . . 67
4.11.3 Absolute maximum ratings (electrical sensitivity)67
4.12 Fast external crystal oscillator (4–40 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.13 Slow external crystal oscillator (32 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 73
4.15 Fast internal RC oscillator (16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.16 Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 76
4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.18 Fast Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . 87
4.18.1 MII Receive Signal Timing (RXD[3:0], RX_DV,
RX_ER, and RX_CLK) . . . . . . . . . . . . . . . . . . . 87
4.18.2 MII Transmit Signal Timing (TXD[3:0], TX_EN,
TX_ER, TX_CLK) . . . . . . . . . . . . . . . . . . . . . . . 87
4.18.3 MII Async Inputs Signal Timing (CRS and COL)88
4.18.4 MII Serial Management Channel Timing (MDIO and
MDC)89
4.19 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.19.1 Current consumption . . . . . . . . . . . . . . . . . . . . 91
4.19.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 93
4.19.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . 101
4.19.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . 103
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 105
5.1.1 176 LQFP package mechanical drawing . . . . 105
5.1.2 208 LQFP package mechanical drawing . . . . 108
5.1.3 256 MAPBGA package mechanical drawing . 113
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
MPC5646C Data Sheet, Rev.6
2
Freescale Semiconductor
Other Features
• System clocks sources
— 4–40 MHz external crystal oscillator
— 16 MHz internal RC oscillator
— FMPLL
— Additionally, there are two low power oscillators: 128 kHz internal RC oscillator, 32 kHz
external crystal oscillator
• Real Time Counter (RTC) with clock source from internal 128 kHz or 16 MHz oscillators or
external 4–40 MHz crystal
— Supports autonomous wake-up with 1 ms resolution with max timeout of 2 seconds
— Optional support from external 32 kHz crystal oscillator, supporting wake-up with 1 second
resolution and max timeout of 1 hour
• 1 Real Time Interrupt (RTI) with 32-bit counter resolution
• 1 Safety Enhanced Software Watchdog Timer (SWT) that supports keyed functionality
• 1 dual-channel FlexRay Controller with 128 message buffers
• 1 Fast Ethernet Controller (FEC)
• On-chip voltage regulator (VREG)
• Cryptographic Services Engine (CSE)
• Offered in the following standard package types:
— 176-pin LQFP, 24  24 mm, 0.5 mm Lead Pitch
— 208-pin LQFP, 28  28 mm, 0.5 mm Lead Pitch
— 256-ball MAPBGA, 17  17mm, 1.0 mm Lead Pitch
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
3
Introduction
1
Introduction
1.1
Document Overview
This document describes the features of the family and options available within the family members, and
highlights important electrical and physical characteristics of the MPC5646C device. To ensure a complete
understanding of the device functionality, refer also to the MPC5646C Reference Manual.
1.2
Description
The MPC5646C is a new family of next generation microcontrollers built on the Power Architecture
embedded category. This document describes the features of the family and options available within the
family members, and highlights important electrical and physical characteristics of the device.
The MPC5646C family expands the range of the MPC560xB microcontroller family. It provides the
scalability needed to implement platform approaches and delivers the performance required by
increasingly sophisticated software architectures. The advanced and cost-efficient host processor core of
the MPC5646C automotive controller family complies with the Power Architecture embedded category,
which is 100 percent user-mode compatible with the original Power Architecture user instruction set
architecture (UISA). It operates at speeds of up to 120 MHz and offers high performance processing
optimized for low power consumption. It also capitalizes on the available development infrastructure of
current Power Architecture devices and is supported with software drivers, operating systems and
configuration code to assist with users implementations.
MPC5646C Data Sheet, Rev.6
4
Freescale Semiconductor
Freescale Semiconductor
Table 1. MPC5646C family comparison1
Feature
MPC5644B
Package
MPC5644C
176
208
176
208
LQFP LQFP LQFP LQFP
CPU
Execution speed2
256
BGA
MPC5645B
176
208
176
208
LQFP LQFP LQFP LQFP
256
BGA
MPC5646B
MPC5646C
176
208
176
208
LQFP LQFP LQFP LQFP
256
BGA
e200z4d
e200z4d + e200z0h
e200z4d
e200z4d + e200z0h
e200z4d
e200z4d + e200z0h
Up to 120 MHz
(e200z4d)
Up to 120 MHz
(e200z4d)
Up to 80 MHz
(e200z0h)3
Up to 120 MHz
(e200z4d)
Up to 120 MHz
(e200z4d)
Up to 80 MHz
(e200z0h)3
Up to 120 MHz
(e200z4d)
Up to 120 MHz
(e200z4d)
Up to 80 MHz
(e200z0h)3
Code flash memory
1.5 MB
2 MB
Data flash memory
MPC5646C Data Sheet, Rev.6
SRAM
MPC5645C
3 MB
4 x16 KB
128 KB
192 KB
160 KB
256 KB
MPU
192 KB
256 KB
16-entry
4
32 ch
eDMA
10-bit ADC
dedicated5,6
27 ch
33 ch
27 ch
33 ch
27 ch
33 ch
shared with
12-bit ADC7
27 ch
33 ch
27 ch
33 ch
27 ch
33 ch
10 ch
5 ch
10 ch
5 ch
10 ch
19 ch
12-bit ADC
dedicated8
shared with
10-bit ADC7
CTU
Total timer
5 ch
10 ch
5 ch
10 ch
5 ch
10 ch
5 ch
19 ch
64 ch
I/O9
eMIOS
SCI (LINFlexD)
10
SPI (DSPI)
CAN (FlexCAN)
64 ch, 16-bit
8
10
6
Yes
STCU11
Yes
5
Introduction
FlexRay
6
Table 1. MPC5646C family comparison1 (continued)
Package
MPC5644B
MPC5644C
176
208
176
208
LQFP LQFP LQFP LQFP
Ethernet
No
MPC5645B
256
BGA
MPC5645C
176
208
176
208
LQFP LQFP LQFP LQFP
Yes
No
32 kHz oscillator (SXOSC)
Cryptographic Services
Engine (CSE)
MPC5646C
176
208
176
208
LQFP LQFP LQFP LQFP
No
256
BGA
Yes
1
I
Debug
256
BGA
Yes
2C
GPIO12
MPC5646B
Yes
147
177
147
JTAG
177
199
Nexus
3+
147
177
147
JTAG
177
199
Nexus
3+
147
177
147
JTAG
177
199
Nexus
3+
Optional
MPC5646C Data Sheet, Rev.6
NOTES:
1 Feature set dependent on selected peripheral multiplexing; table shows example.
2 Based on 125 C ambient operating temperature and subject to full device characterisation.
3 The e200z0h can run at speeds up to 80 MHz. However, if system frequency is >80 MHz (e.g., e200z4d running at 120 MHz) the e200z0h needs
to run at 1/2 system frequency. There is a configurable e200z0 system clock divider for this purpose.
4 DMAMUX also included that allows for software selection of 32 out of a possible 57 sources.
5 Not shared with 12-bit ADC, but possibly shared with other alternate functions.
6 There are 23 dedicated ANS plus 4 dedicated ANX channels on LQPF176. For higher pin count packages, there are 29 dedicated ANS plus 4
dedicated ANX channels.
7 16x precision channels (ANP) and 3x standard (ANS).
8 Not shared with 10-bit ADC, but possibly shared with other alternate functions.
9 As a minimum, all timer channels can function as PWM or Input Capture and Output Control. Refer to the eMIOS section of the device reference
manual for information on the channel configuration and functions.
10 CAN Sampler also included that allows ID of CAN message to be captured when in low power mode.
11 STCU controls MBIST activation and reporting.
12 Estimated I/O count for proposed packages based on multiplexing with peripherals.
Introduction
Feature
Freescale Semiconductor
Block diagram
2
Block diagram
Figure 1 shows the detailed block diagram of the MPC5646C.
FEC
CSE
Nexus Port
FlexRay
Nexus 3+
Nexus
Voltage
regulator
NMI0
e200z0h
NMI1
e200z4d
Instructions
(Master)
Data
(Master)
Instructions
(Master)
Data
(Master)
MPU
JTAG Port
64-bit 8 x 5 crossbar switch
JTAGC
SRAM
2  128 KB
Code Flash Data Flash
64 KB
2  1.5 MB
2  SRAM
controller
Flash memory
controller
(Slave)
Nexus 3+
NMI0
(Slave)
(Slave)
Interrupt requests
from peripheral
blocks
NMI1
Clocks
DMAMUX
MPU
registers
INTC
eDMA
CMU
16 x
Semaphores
CAN
Sampler
( Master)
FMPLL
STCU
8
RTC/API 4  STM
SWT
ECSM
MC_RGM MC_CGM MC_ME MC_PCU
PIT RTI
BAM
SSCM
WKPU
Peripheral Bridge
Interrupt
Request
10 ch(1)
1  12-bit
ADC
SIUL
Reset Control
External
Interrupt
Request
27 ch or 33 ch(2)
1  10-bit
ADC
CTU
2  32 ch
eMIOS
10 
LINFlexD
8
DSPI
I2C
6
FlexCAN
IMUX
GPIO &
Pad Control
(3)
(3)
I/O
Legend:
ADC
BAM
CSE
CAN
CMU
CTU
DMAMUX
DSPI
eDMA
FlexCAN
FEC
eMIOS
ECSM
FMPLL
FlexRay
I2C
IMUX
INTC
Notes:
1) 10 dedicated channels plus up to 19 shared channels. See the device-comparison table.
2) Package dependent. 27 or 33 dedicated channels plus up to 19 shared channels. See the device-comparison table.
3) 16 x precision channels (ANP) are mapped on input only I/O cells.
Analog-to-Digital Converter
Boot Assist Module
Cryptographic Services Engine
Controller Area Network (FlexCAN)
Clock Monitor Unit
Cross Triggering Unit
DMA Channel Multiplexer
Deserial Serial Peripheral Interface
enhanced Direct Memory Access
Controller Area Network controller modules
Fast Ethenet Controller
Enhanced Modular Input Output System
Error Correction Status Module
Frequency-Modulated Phase-Locked Loop
FlexRay Communication Controller
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
JTAGC
LINFlexD
MC_ME
MC_CGM
MC_PCU
MC_RGM
MPU
Nexus
NMI
PIT_RTI
RTC/API
SIUL
SRAM
SSCM
STM
SWT
STCU
WKPU
JTAG controller
Local Interconnect Network Flexible with DMA support
Mode Entry Module
Clock Generation Module
Power Control Unit
Reset Generation Module
Memory Protection Unit
Nexus Development Interface
Non-Maskable Interrupt
Periodic Interrupt Timer with Real-Time Interrupt
Real-Time Clock/ Autonomous Periodic Interrupt
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Self Test Control Unit
Wakeup Unit
Figure 1. MPC5646C block diagram
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
7
Block diagram
Table 2 summarizes the functions of the blocks present on the MPC5646C.
Table 2. MPC5646C series block summary
Block
Function
Analog-to-digital converter (ADC) Converts analog voltages to digital values
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock monitor unit (CMU)
Monitors clock source (internal and external) integrity
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Cryptographic Security Engine
(CSE)
Supports the encoding and decoding of any kind of data
Crossbar (XBAR) switch
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width
DMA Channel Multiplexer
(DMAMUX)
Allows to route DMA sources (called slots) to DMA channels
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices
(DSPI)
Error Correction Status Module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset status
register, wakeup control for exiting sleep modes, and optional features such as
information on memory errors reported by error-correcting codes
Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host processor
(eDMA)
via “n” programmable channels.
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol
FMPLL (frequency-modulated
phase-locked loop)
Generates high-speed system clocks and supports programmable frequency
modulation
FlexRay (FlexRay communication Provides high-speed distributed control for advanced automotive applications
controller)
Fast Ethernet Controller (FEC)
Ethernet Media Access Controller (MAC) designed to support both 10 and 100
Mbps Ethernet/IEEE 802.3 networks
Internal multiplexer (IMUX) SIUL
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of
data exchange between devices
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests for both
e200z0h and e200z4d cores
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
MPC5646C Data Sheet, Rev.6
8
Freescale Semiconductor
Block diagram
Table 2. MPC5646C series block summary (continued)
Block
Function
LinFlexD (Local Interconnect
Network Flexible with DMA
support)
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Memory protection unit (MPU)
Provides hardware access control for all memory references generated in a
device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the device
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and
modetransition sequences in all functional states; also manages the power
control unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Non-Maskable Interrupt (NMI)
Handles external events that must produce an immediate response, such as
power down detection
Nexus Development Interface
(NDI)
Provides real-time development capabilities for e200z0h and e200z4d core
processor
Periodic interrupt timer/ Real Time Produces periodic interrupts and triggers
Interrupt Timer (PIT_RTI)
Real-time counter (RTC/API)
A free running counter used for time keeping applications, the RTC can be
configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode). Supports autonomous
periodic interrupt (API) function to generate a periodic wakeup request to exit a
low power mode or an interrupt request
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status and configuration
module (SSCM)
Provides system configuration and status data (such as memory size and status,
device mode and security status), device identification data, debug status port
enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AutoSAR and operating
system tasks
Semaphores
Provides the hardware support needed in multi-core systems for sharing
resources and provides a simple mechanism to achieve lock/unlock operations
via a single write access.
Wake Unit (WKPU)
Supports external sources that can generate interrupts or wakeup events, of
which can cause non-maskable interrupt requests or wakeup events.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
9
Package pinouts and signal descriptions
3
Package pinouts and signal descriptions
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PB[2]
PC[8]
PC[13]
PC[12]
PI[0]
PI[1]
PI[2]
PI[3]
PE[7]
PE[6]
PH[8]
PH[7]
PH[6]
PH[5]
PH[4]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV_A
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PI[4]
PI[5]
PH[12]
PH[11]
PG[11]
PG[10]
PE[15]
PE[14]
PG[15]
PG[14]
PE[12]
The available LQFP pinouts and the MAPBGA ballmaps are provided in the following figures. For
functional port pin description, see Table 4.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176 LQFP
Top view
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV_B
VSS_HV
PG[0]
PG[1]
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PG[13]
PA[3]
PI[13]
PI[12]
PI[11]
VDD_LV
VSS_LV
PI[8]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
VDD_HV_ADC1
VSS_HV_ADC1
PB[11]
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
NOTE
1) VDD_HV_B supplies the IO voltage domain for the
pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7],
PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2],
PH[1], PH[0], PG[12], PG[13], and PA[3].
2)Availability of port pin alternate functions depends
on product selection.
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV_A
PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PJ[3]
PJ[2]
PJ[1]
PJ[0]
PI[15]
PI[14]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
VDD_HV_A
VSS_HV
PD[8]
PB[4]
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PB[3]
PC[9]
PC[14]
PC[15]
PJ[4]
VDD_HV_A
VSS_HV
PH[15]
PH[13]
PH[14]
PI[6]
PI[7]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV_A
VSS_HV
RESET
VSS_LV
VDD_LV
VRC_CTRL
PG[9]
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PF[9]
PF[8]
PF[12]
PC[6]
Figure 2. 176-pin LQFP configuration
MPC5646C Data Sheet, Rev.6
10
Freescale Semiconductor
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
PB[2]
PC[8]
PC[13]
PC[12]
PL[0]
PK[15]
PK[14]
PK[13]
PK[12]
PK[11]
PK[10]
PK[9]
PI[0]
PI[1]
PI[2]
PI[3]
PE[7]
PE[6]
PH[8]
PH[7]
PH[6]
PH[5]
PH[4]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV_A
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PI[4]
PI[5]
PH[12]
PH[11]
PG[11]
PG[10]
PE[15]
PE[14]
PG[15]
PG[14]
PE[12]
Package pinouts and signal descriptions
208 LQFP
Top view
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV_B
VSS_HV
PG[0]
PG[1]
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PG[13]
PA[3]
PI[13]
PI[12]
PI[11]
PI[10]
VDD_LV
VSS_LV
PI[9]
PI[8]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
VDD_HV_A
VSS_HV
PD[12]
VDD_HV_ADC1
VSS_HV_ADC1
PB[11]
PD[11]
PD[10]
PD[9]
PJ[5]
PJ[6]
PJ[7]
PJ[8]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PJ[12]
PJ[11]
PA[4]
PK[0]
PJ[15]
PJ[14]
PJ[13]
PA[13]
PJ[10]
PJ[9]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV_A
PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PJ[3]
PJ[2]
PJ[1]
PJ[0]
PI[15]
PI[14]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
VDD_HV_A
VSS_HV
PD[8]
PB[4]
PB[3]
PC[9]
PC[14]
PC[15]
PJ[4]
VDD_HV_A
VSS_HV
PH[15]
PH[13]
PH[14]
P[I6]
P[I7]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV_A
VSS_HV
RESET
VSS_LV
VDD_LV
VRC_CTRL
PG[9]
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PK[1]
PK[2]
PK[3]
PK[4]
PK[5]
PK[6]
PK[7]
PK[8]
PF[9]
PF[8]
PF[12]
PC[6]
NOTE
1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11],
PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3],
PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3].
2) Availability of port pin alternate functions depends on product selection.
Figure 3. 208-pin LQFP configuration
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
11
Package pinouts and signal descriptions
A
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PC[15]
PB[2]
PC[13]
PI[1]
PE[7]
PH[8]
PE[2]
PE[4]
PC[4]
PE[3]
PH[9]
PI[4]
PH[11]
PE[14]
PA[10]
PG[11]
PH[13]
PC[14]
PC[8]
PC[12]
PI[3]
PE[6]
PH[5]
PE[5]
PC[5]
PC[0]
PC[2]
PH[12]
PG[10]
PA[11]
PA[9]
PA[8]
PH[14]
VDD_HV
_A
PC[9]
PL[0]
PI[0]
PH[7]
PH[6]
VSS_LV
VDD_HV
_A
PA[5]
PC[3]
PE[15]
PG[14]
PE[12]
PA[7]
PE[13]
PG[5]
PI[6]
PJ[4]
PB[3]
PC[1]
PH[10]
PG[3]
PI[7]
PH[15]
PA[2]
PG[4]
PE[8]
C
D
E
F
G
H
J
K
L
M
N
P
R
T
PK[15]
PI[2]
PH[4]
VDD_LV
A
B
C
PA[6]
PI[5]
PG[15]
PF[14]
PF[15]
PH[2]
PG[2]
PG[0]
PG[1]
PH[0]
VDD_HV
_A
PA[1]
PE[1]
PH[1]
PH[3]
PG[12]
PG[13]
PE[0]
PE[10]
PA[0]
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VDD_HV
_B
PI[13]
PI[12]
PA[3]
PE[9]
VDD_HV
_A
PE[11]
PK[1]
VSS_LV
VSS_HV
VSS_HV
VSS_HV
VDD_HV
_A
VDD_LV
VSS_LV
PI[11]
VSS_HV
VRC_CT
RL
VDD_LV
PG[9]
VSS_LV
VSS_LV
VSS_HV
VSS_HV
PD[15]
PI[8]
PI[9]
PI[10]
RESET
VSS_LV
PG[8]
PC[11]
VSS_LV
VSS_LV
VSS_LV
VDD_LV
PD[14]
PD[13]
PB[14]
PB[15]
PC[10]
PG[7]
PB[0]
PK[2]
PD[12]
PB[12]
PB[13]
VDD_HV
_ADC1
L
PG[6]
PB[1]
PK[4]
PF[9]
PB[11]
PD[10]
PD[11]
VSS_HV
_ADC1
M
PK[3]
PF[8]
PC[6]
PC[7]
PJ[13]
VDD_HV
_A
PB[10]
PF[6]
VDD_HV
_A
PJ[1]
PD[2]
PJ[5]
PB[5]
PB[6]
PJ[6]
PD[9]
PF[12]
PF[10]
PF[13]
PA[14]
PJ[9]
PA[12]
PF[0]
PF[5]
PF[7]
PJ[3]
PI[15]
PD[4]
PD[7]
PD[8]
PJ[8]
PJ[7]
PF[11]
PA[15]
PJ[11]
PJ[15]
PA[13]
PF[2]
PF[3]
PF[4]
VDD_LV
PJ[2]
PJ[0]
PD[0]
PD[3]
PD[6]
VDD_HV
_ADC0
PB[7]
PJ[12]
PA[4]
PK[0]
PJ[14]
PJ[10]
PF[1]
XTAL
EXTAL
VSS_LV
PB[9]
PB[8]
PI[14]
PD[1]
PD[5]
VSS_HV
_ADC0
PB[4]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D
E
F
G
H
J
K
N
P
R
T
Notes:
1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0],
PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3].
2) Availability of port pin alternate functions depends on product selection.
MPC5646C Data Sheet, Rev.6
12
Freescale Semiconductor
Package pinouts and signal descriptions
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PC[15]
PB[2]
PC[13]
PI[1]
PE[7]
PH[8]
PE[2]
PE[4]
PC[4]
PE[3]
PH[9]
PI[4]
PH[11]
PE[14]
PA[10]
PG[11]
PH[13]
PC[14]
PC[8]
PC[12]
PI[3]
PE[6]
PH[5]
PE[5]
PC[5]
PC[0]
PC[2]
PH[12]
PG[10]
PA[11]
PA[9]
PA[8]
PH[14]
VDD_HV_
A
PC[9]
PL[0]
PI[0]
PH[7]
PH[6]
VSS_LV
VDD_HV_
A
PA[5]
PC[3]
PE[15]
PG[14]
PE[12]
PA[7]
PE[13]
PG[5]
PI[6]
PJ[4]
PB[3]
PK[15]
PI[2]
PH[4]
VDD_LV
PC[1]
PH[10]
PA[6]
PI[5]
PG[15]
PF[14]
PF[15]
PH[2]
PG[3]
PI[7]
PH[15]
PG[2]
VDD_LV
VSS_LV
PK[10]
PK[9]
PM[1]
PM[0]
PL[15]
PL[14]
PG[0]
PG[1]
PH[0]
VDD_HV_
A
PA[2]
PG[4]
PA[1]
PE[1]
PL[2]
PM[6]
PL[1]
PK[11]
PM[5]
PL[13]
PL[12]
PM[2]
PH[1]
PH[3]
PG[12]
PG[13]
PE[8]
PE[0]
PE[10]
PA[0]
PL[3]
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
PK[12]
VDD_HV_
B
PI[13]
PI[12]
PA[3]
PE[9]
VDD_HV_
A
PE[11]
PK[1]
PL[4]
VSS_LV
VSS_LV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
PK[13]
VDD_HV_
A
VDD_LV
VSS_LV
PI[11]
VSS_HV
VRC_CTR
L
VDD_LV
PG[9]
PL[5]
VSS_LV
VSS_LV
VSS_LV
VSS_HV
VSS_HV
VSS_HV
PK[14]
PD[15]
PI[8]
PI[9]
PI[10]
RESET
VSS_LV
PG[8]
PC[11]
PL[6]
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VDD_LV
VDD_LV
PM[3]
PD[14]
PD[13]
PB[14]
PB[15]
PC[10]
PG[7]
PB[0]
PK[2]
PL[7]
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VDD_LV
VDD_LV
PM[4]
PD[12]
PB[12]
PB[13]
VDD_HV_
ADC1
L
PG[6]
PB[1]
PK[4]
PF[9]
PK[5]
PK[6]
PK[7]
PK[8]
PL[8]
PL[9]
PL[10]
PL[11]
PB[11]
PD[10]
PD[11]
VSS_HV_
ADC1
M
PK[3]
PF[8]
PC[6]
PC[7]
PJ[13]
VDD_HV_
A
PB[10]
PF[6]
VDD_HV_
A
PJ[1]
PD[2]
PJ[5]
PB[5]
PB[6]
PJ[6]
PD[9]
PF[12]
PF[10]
PF[13]
PA[14]
PJ[9]
PA[12]
PF[0]
PF[5]
PF[7]
PJ[3]
PI[15]
PD[4]
PD[7]
PD[8]
PJ[8]
PJ[7]
PF[11]
PA[15]
PJ[11]
PJ[15]
PA[13]
PF[2]
PF[3]
PF[4]
VDD_LV
PJ[2]
PJ[0]
PD[0]
PD[3]
PD[6]
VDD_HV_
ADC0
PB[7]
PJ[12]
PA[4]
PK[0]
PJ[14]
PJ[10]
PF[1]
XTAL
EXTAL
VSS_LV
PB[9]
PB[8]
PI[14]
PD[1]
PD[5]
VSS_HV_
ADC0
PB[4]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
G
H
J
K
N
P
R
T
Notes:
1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0],
PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], PA[3], PM[3], and PM[4].
2)Availability of port pin alternate functions depends on product selection.
Figure 4. 256-pin BGA configuration
3.1
Pad types
In the device the following types of pads are available for system pins and functional port pins:
S = Slow1
M = Medium1, 2
1. See the I/O pad electrical characteristics in the device data sheet for details.
2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium. For example,
Fast/Medium pad will be Medium by default at reset. Similarly, Slow/Medium pad will be Slow by default. Only exception is PC[1]
which is in medium configuration by default (refer to PCR.SRC in the reference manual, Pad Configuration Registers
(PCR0—PCR198)).
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
13
Package pinouts and signal descriptions
F = Fast1, 2
I = Input only with analog feature1
A = Analog
3.2
System pins
The system pins are listed in Table 3.
Table 3. System pin descriptions
I/O
direction
Pad
type
RESET
config.
256 MAPBGA
Function
208 LQFP
Port pin
176 LQFP
Pin number
I/O
M
Input, weak
pull-up only
after
PHASE2
29
29
K1
RESET
Bidirectional reset with Schmitt-Trigger
characteristics and noise filter.
EXTAL
Analog input of the oscillator amplifier
circuit. Needs to be grounded if oscillator
bypass mode is used.
I
A1
—
58
74
T8
XTAL
Analog output of the oscillator amplifier
circuit, when the oscillator is not in bypass
mode.
Analog input for the clock generator when
the oscillator is in bypass mode.
I/O
A1
—
56
72
T7
NOTES:
1 For analog pads, it is not recommended to enable IBE if APC is enabled to avoid extra current in middle range
voltage.
3.3
Functional ports
The functional port pins are listed in Table 4.
MPC5646C Data Sheet, Rev.6
14
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
—
GPIO[0]
E0UC[0]
CLKOUT
E0UC[13]
WKPU[19]
CAN1RX
SIUL
eMIOS_0
MC_CGM
eMIOS_0
WKPU
FlexCAN_1
I/O
I/O
O
I/O
I
I
M/S
Tristate
24
24
G4
PCR[1]
AF0
AF1
AF2
AF3
—
—
—
GPIO[1]
E0UC[1]
—
—
WKPU[2]
CAN3RX
NMI[0]3
SIUL
eMIOS_0
—
—
WKPU
FlexCAN_3
WKPU
I/O
I/O
—
—
I
I
I
S
Tristate
19
19
F3
PA[2]
PCR[2]
AF0
AF1
AF2
AF3
—
—
GPIO[2]
E0UC[2]
—
MA[2]
WKPU[3]
NMI[1]3
SIUL
eMIOS_0
—
ADC_0
WKPU
WKPU
I/O
I/O
—
O
I
I
S
Tristate
17
17
F1
PA[3]
PCR[3]
AF0
AF1
AF2
AF3
—
—
—
GPIO[3]
E0UC[3]
LIN5TX
CS4_1
RX_ER_CLK
EIRQ[0]
ADC1_S[0]
SIUL
eMIOS_0
LINFlexD_5
DSPI_1
FEC
SIUL
ADC_1
I/O
I/O
O
O
I
I
I
M/S
Tristate
114
138
G16
PA[4]
PCR[4]
AF0
AF1
AF2
AF3
—
—
GPIO[4]
E0UC[4]
—
CS0_1
LIN5RX
WKPU[9]
SIUL
eMIOS_0
—
DSPI_1
LINFlexD_5
WKPU
I/O
I/O
—
I/O
I
I
S
Tristate
51
61
T2
PA[5]
PCR[5]
AF0
AF1
AF2
GPIO[5]
E0UC[5]
LIN4TX
SIUL
eMIOS_0
LINFlexD_4
I/O
I/O
O
M/S
Tristate
146
170
C10
PA[6]
PCR[6]
AF0
AF1
AF2
AF3
—
—
GPIO[6]
E0UC[6]
—
CS1_1
LIN4RX
EIRQ[1]
SIUL
eMIOS_0
—
DSPI_1
LINFlexD_4
SIUL
I/O
I/O
—
O
I
I
S
Tristate
147
171
D11
Port
pin
PCR
PA[0]
PCR[0]
PA[1]
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
15
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
—
—
GPIO[7]
E0UC[7]
LIN3TX
—
RXD[2]
EIRQ[2]
ADC1_S[1]
SIUL
eMIOS_0
LINFlexD_3
—
FEC
SIUL
ADC_1
I/O
I/O
O
—
I
I
I
M/S
Tristate
128
152
C15
PCR[8]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[8]
E0UC[8]
E0UC[14]
—
RXD[1]
EIRQ[3]
ABS[0]
LIN3RX
SIUL
eMIOS_0
eMIOS_0
—
FEC
SIUL
MC_RGM
LINFlexD_3
I/O
I/O
I/O
—
I
I
I
I
M/S
Input,
weak
pull-up
129
153
B16
PA[9]
PCR[9]
AF0
AF1
AF2
AF3
—
—
GPIO[9]
E0UC[9]
—
CS2_1
RXD[0]
FAB
SIUL
eMIOS_0
—
DSPI1
FEC
MC_RGM
I/O
I/O
—
O
I
I
M/S
Pulldown
130
154
B15
PA[10]
PCR[10]
AF0
AF1
AF2
AF3
—
—
—
GPIO[10]
E0UC[10]
SDA
LIN2TX
COL
ADC1_S[2]
SIN_1
SIUL
eMIOS_0
I2C
LINFlexD_2
FEC
ADC_1
DSPI_1
I/O
I/O
I/O
O
I
I
I
M/S
Tristate
131
155
A15
PA[11]
PCR[11]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[11]
E0UC[11]
SCL
—
RX_ER
EIRQ[16]
LIN2RX
ADC1_S[3]
SIUL
eMIOS_0
I2C
—
FEC
SIUL
LINFlexD_2
ADC_1
I/O
I/O
I/O
—
I
I
I
I
M/S
Tristate
132
156
B14
PA[12]
PCR[12]
AF0
AF1
AF2
AF3
—
—
GPIO[12]
—
E0UC[28]
CS3_1
EIRQ[17]
SIN_0
SIUL
—
eMIOS_0
DSPI1
SIUL
DSPI_0
I/O
—
I/O
O
I
I
S
Tristate
53
69
P6
Port
pin
PCR
PA[7]
PCR[7]
PA[8]
MPC5646C Data Sheet, Rev.6
16
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
GPIO[13]
SOUT_0
E0UC[29]
—
SIUL
DSPI_0
eMIOS_0
—
I/O
O
I/O
—
M/S
Tristate
52
66
R5
PCR[14]
AF0
AF1
AF2
AF3
—
GPIO[14]
SCK_0
CS0_0
E0UC[0]
EIRQ[4]
SIUL
DSPI_0
DSPI_0
eMIOS_0
SIUL
I/O
I/O
I/O
I/O
I
M/S
Tristate
50
58
P4
PA[15]
PCR[15]
AF0
AF1
AF2
AF3
—
GPIO[15]
CS0_0
SCK_0
E0UC[1]
WKPU[10]
SIUL
DSPI_0
DSPI_0
eMIOS_0
WKPU
I/O
I/O
I/O
I/O
I
M/S
Tristate
48
56
R2
PB[0]
PCR[16]
AF0
AF1
AF2
AF3
GPIO[16]
CAN0TX
E0UC[30]
LIN0TX
SIUL
FlexCAN_0
eMIOS_0
LINFlexD_0
I/O
O
I/O
I
M/S
Tristate
39
39
L3
PB[1]
PCR[17]
AF0
AF1
AF2
—
—
—
GPIO[17]
—
E0UC[31]
LIN0RX
WKPU[4]
CAN0RX
SIUL
—
eMIOS_0
LINFlexD_0
WKPU
FlexCAN_0
I/O
—
I/O
I
I
I
S
Tristate
40
40
M2
PB[2]
PCR[18]
AF0
AF1
AF2
AF3
GPIO[18]
LIN0TX
SDA
E0UC[30]
SIUL
LINFlexD_0
I2C
eMIOS_0
I/O
O
I/O
I/O
M/S
Tristate
176
208
A2
PB[3]
PCR[19]
AF0
AF1
AF2
AF3
—
—
GPIO[19]
E0UC[31]
SCL
—
WKPU[11]
LIN0RX
SIUL
eMIOS_0
I2C
—
WKPU
LINFlexD_0
I/O
I/O
I/O
—
I
I
S
Tristate
1
1
D4
PB[4]
PCR[20]
AF0
AF1
AF2
AF3
—
—
GPI[20]
—
—
—
ADC0_P[0]
ADC1_P[0]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
88
104
T16
Port
pin
PCR
PA[13]
PCR[13]
PA[14]
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
17
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
—
GPI[21]
—
—
—
ADC0_P[1]
ADC1_P[1]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
91
107
N13
PCR[22]
AF0
AF1
AF2
AF3
—
—
GPI[22]
—
—
—
ADC0_P[2]
ADC1_P[2]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
92
108
N14
PB[7]
PCR[23]
AF0
AF1
AF2
AF3
—
—
GPI[23]
—
—
—
ADC0_P[3]
ADC1_P[3]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
93
109
R16
PB[8]
PCR[24]
AF0
AF1
AF2
AF3
—
—
—
—
GPI[24]
—
—
—
ADC0_S[0]
ADC1_S[4]
WKPU[25]
OSC32k_XTAL4
SIUL
—
—
—
ADC_0
ADC_1
WKPU
SXOSC
I
—
—
—
I
I
I
I
I
—
61
77
T11
PB[9]5
PCR[25]
AF0
AF1
AF2
AF3
—
—
—
—
GPI[25]
—
—
—
ADC0_S[1]
ADC1_S[5]
WKPU[26]
OSC32k_EXTAL4
SIUL
—
—
—
ADC_0
ADC_1
WKPU
SXOSC
I
—
—
—
I
I
I
I
I
—
60
76
T10
PB[10]
PCR[26]
AF0
AF1
AF2
AF3
—
—
—
GPIO[26]
SOUT_1
CAN3TX
—
ADC0_S[2]
ADC1_S[6]
WKPU[8]
SIUL
DSPI_1
FlexCAN_3
—
ADC_0
ADC_1
WKPU
I/O
O
—
—
I
I
I
S
Tristate
62
78
N7
Port
pin
PCR
PB[5]
PCR[21]
PB[6]
MPC5646C Data Sheet, Rev.6
18
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
GPIO[27]
E0UC[3]
—
CS0_0
ADC0_S[3]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
I/O
I
S
Tristate
97
117
M13
PCR[28]
AF0
AF1
AF2
AF3
—
GPIO[28]
E0UC[4]
—
CS1_0
ADC0_X[0]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
S
Tristate
101
123
L14
PB[13]
PCR[29]
AF0
AF1
AF2
AF3
—
GPIO[29]
E0UC[5]
—
CS2_0
ADC0_X[1]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
S
Tristate
103
125
L15
PB[14]
PCR[30]
AF0
AF1
AF2
AF3
—
GPIO[30]
E0UC[6]
—
CS3_0
ADC0_X[2]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
S
Tristate
105
127
K15
PB[15]
PCR[31]
AF0
AF1
AF2
AF3
—
GPIO[31]
E0UC[7]
—
CS4_0
ADC0_X[3]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
S
Tristate
107
129
K16
PC[0]6
PCR[32]
AF0
AF1
AF2
AF3
GPIO[32]
—
TDI
—
SIUL
—
JTAGC
—
I/O
—
I
—
M/S
Input,
weak
pull-up
154
178
B10
PC[1]6
PCR[33]
AF0
AF1
AF2
AF3
GPIO[33]
—
TDO
—
SIUL
—
JTAGC
—
I/O
—
O
—
F/M
Tristate
149
173
D9
PC[2]
PCR[34]
AF0
AF1
AF2
AF3
—
GPIO[34]
SCK_1
CAN4TX
—
EIRQ[5]
SIUL
DSPI_1
FlexCAN_4
—
SIUL
I/O
I/O
O
—
I
M/S
Tristate
145
169
B11
Port
pin
PCR
PB[11]
PCR[27]
PB[12]
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
19
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
AF0
AF1
AF2
AF3
ALT4
—
—
—
GPIO[36]
E1UC[31]
—
SIUL
eMIOS_1
—
I/O
I/O
—
FR_B_TX_EN
SIN_1
CAN3RX
EIRQ[18]
Flexray
DSPI_1
FlexCAN_3
SIUL
O
I
I
I
256 MAPBGA
SIUL
DSPI_1
ADC_0
—
FlexCAN_1
FlexCAN_4
SIUL
208 LQFP
PCR[36]
GPIO[35]
CS0_1
MA[0]
—
CAN1RX
CAN4RX
EIRQ[6]
176 LQFP
PC[4]
AF0
AF1
AF2
AF3
—
—
—
RESET
config.
PCR[35]
Pad type
PC[3]
Function
I/O
direction2
PCR
Peripheral
Port
pin
Alternate
function1
Pin number
I/O
I/O
O
S
Tristate
144
168
C11
M/S
Tristate
159
183
A9
I
I
I
PC[5]
PCR[37]
AF0
AF1
AF2
AF3
ALT4
—
GPIO[37]
SOUT_1
CAN3TX
—
FR_A_TX
EIRQ[7]
SIUL
DSPI_1
FlexCAN_3
—
Flexray
SIUL
I/O
O
O
—
O
I
M/S
Tristate
158
182
B9
PC[6]
PCR[38]
AF0
AF1
AF2
AF3
GPIO[38]
LIN1TX
E1UC[28]
—
SIUL
LINFlexD_1
eMIOS_1
—
I/O
O
I/O
—
S
Tristate
44
52
N3
PC[7]
PCR[39]
AF0
AF1
AF2
AF3
—
—
GPIO[39]
—
E1UC[29]
—
LIN1RX
WKPU[12]
SIUL
—
eMIOS_1
—
LINFlexD_1
WKPU
I/O
—
I/O
—
I
I
S
Tristate
45
53
N4
PC[8]
PCR[40]
AF0
AF1
AF2
AF3
GPIO[40]
LIN2TX
E0UC[3]
—
SIUL
LINFlexD_2
eMIOS_0
—
I/O
O
I/O
—
S
Tristate
175
207
B3
PC[9]
PCR[41]
AF0
AF1
AF2
AF3
—
—
GPIO[41]
—
E0UC[7]
—
LIN2RX
WKPU[13]
SIUL
—
eMIOS_0
—
LINFlexD_2
WKPU
I/O
—
I/O
—
I
I
S
Tristate
2
2
C3
MPC5646C Data Sheet, Rev.6
20
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
GPIO[42]
CAN1TX
CAN4TX
MA[1]
SIUL
FlexCAN_1
FlexCAN_4
ADC_0
I/O
O
O
O
M/S
Tristate
36
36
L1
PCR[43]
AF0
AF1
AF2
AF3
—
—
—
GPIO[43]
—
—
MA[2]
CAN1RX
CAN4RX
WKPU[5]
SIUL
—
—
ADC_0
FlexCAN_1
FlexCAN_4
WKPU
I/O
—
—
O
I
I
I
S
Tristate
35
35
K4
PC[12]
PCR[44]
AF0
AF1
AF2
AF3
ALT4
—
—
GPIO[44]
E0UC[12]
—
—
FR_DBG[0]
SIN_2
EIRQ[19]
SIUL
eMIOS_0
—
—
Flexray
DSPI_2
SIUL
I/O
I/O
—
—
O
I
I
M/S
Tristate
173
205
B4
PC[13]
PCR[45]
AF0
AF1
AF2
AF3
ALT4
GPIO[45]
E0UC[13]
SOUT_2
—
FR_DBG[1]
SIUL
eMIOS_0
DSPI_2
—
Flexray
I/O
I/O
O
—
O
M/S
Tristate
174
206
A3
PC[14]
PCR[46]
AF0
AF1
AF2
AF3
ALT4
—
GPIO[46]
E0UC[14]
SCK_2
—
FR_DBG[2]
EIRQ[8]
SIUL
eMIOS_0
DSPI_2
—
Flexray
SIUL
I/O
I/O
I/O
—
O
I
M/S
Tristate
3
3
B2
PC[15]
PCR[47]
AF0
AF1
AF2
AF3
ALT4
GPIO[47]
E0UC[15]
CS0_2
—
FR_DBG[3]
EIRQ[20]
SIUL
eMIOS_0
DSPI_2
—
Flexray
SIUL
I/O
I/O
I/O
—
O
I
M/S
Tristate
4
4
A1
PD[0]
PCR[48]
AF0
AF1
AF2
AF3
—
—
—
GPI[48]
—
—
—
ADC0_P[4]
ADC1_P[4]
WKPU[27]
SIUL
—
—
—
ADC_0
ADC_1
WKPU
I
—
—
—
I
I
I
I
Tristate
77
93
R12
Port
pin
PCR
PC[10]
PCR[42]
PC[11]
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
21
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
—
—
GPI[49]
—
—
—
ADC0_P[5]
ADC1_P[5]
WKPU[28]
SIUL
—
—
—
ADC_0
ADC_1
WKPU
I
—
—
—
I
I
I
I
Tristate
78
94
T13
PCR[50]
AF0
AF1
AF2
AF3
—
—
GPI[50]
—
—
—
ADC0_P[6]
ADC1_P[6]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
79
95
N11
PD[3]
PCR[51]
AF0
AF1
AF2
AF3
—
—
GPI[51]
—
—
—
ADC0_P[7]
ADC1_P[7]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
80
96
R13
PD[4]
PCR[52]
AF0
AF1
AF2
AF3
—
—
GPI[52]
—
—
—
ADC0_P[8]
ADC1_P[8]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
81
97
P12
PD[5]
PCR[53]
AF0
AF1
AF2
AF3
—
—
GPI[53]
—
—
—
ADC0_P[9]
ADC1_P[9]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
82
98
T14
PD[6]
PCR[54]
AF0
AF1
AF2
AF3
—
—
GPI[54]
—
—
—
ADC0_P[10]
ADC1_P[10]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
83
99
R14
PD[7]
PCR[55]
AF0
AF1
AF2
AF3
—
—
GPI[55]
—
—
—
ADC0_P[11]
ADC1_P[11]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
84
100
P13
Port
pin
PCR
PD[1]
PCR[49]
PD[2]
MPC5646C Data Sheet, Rev.6
22
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
—
GPI[56]
—
—
—
ADC0_P[12]
ADC1_P[12]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
87
103
P14
PCR[57]
AF0
AF1
AF2
AF3
—
—
GPI[57]
—
—
—
ADC0_P[13]
ADC1_P[13]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
94
114
N16
PD[10]
PCR[58]
AF0
AF1
AF2
AF3
—
—
GPI[58]
—
—
—
ADC0_P[14]
ADC1_P[14]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
95
115
M14
PD[11]
PCR[59]
AF0
AF1
AF2
AF3
—
—
GPI[59]
—
—
—
ADC0_P[15]
ADC1_P[15]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
96
116
M15
PD[12]
PCR[60]
AF0
AF1
AF2
AF3
—
GPIO[60]
CS5_0
E0UC[24]
—
ADC0_S[4]
SIUL
DSPI_0
eMIOS_0
—
ADC_0
I/O
O
I/O
—
I
S
Tristate
100
120
L13
PD[13]
PCR[61]
AF0
AF1
AF2
AF3
—
GPIO[61]
CS0_1
E0UC[25]
—
ADC0_S[5]
SIUL
DSPI_1
eMIOS_0
—
ADC_0
I/O
I/O
I/O
—
I
S
Tristate
102
124
K14
PD[14]
PCR[62]
AF0
AF1
AF2
AF3
ALT4
—
GPIO[62]
CS1_1
E0UC[26]
—
FR_DBG[0]
ADC0_S[6]
SIUL
DSPI_1
eMIOS_0
—
Flexray
ADC_0
I/O
O
I/O
—
O
I
S
Tristate
104
126
K13
Port
pin
PCR
PD[8]
PCR[56]
PD[9]
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
23
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
ALT4
—
GPIO[63]
CS2_1
E0UC[27]
—
FR_DBG[1]
ADC0_S[7]
SIUL
DSPI_1
eMIOS_0
—
Flexray
ADC_0
I/O
O
I/O
—
O
I
S
Tristate
106
128
J13
PCR[64]
AF0
AF1
AF2
AF3
—
—
GPIO[64]
E0UC[16]
—
—
CAN5RX
WKPU[6]
SIUL
eMIOS_0
—
—
FlexCAN_5
WKPU
I/O
I/O
—
—
I
I
S
Tristate
18
18
G2
PE[1]
PCR[65]
AF0
AF1
AF2
AF3
GPIO[65]
E0UC[17]
CAN5TX
—
SIUL
eMIOS_0
FlexCAN_5
—
I/O
I/O
O
—
M/S
Tristate
20
20
F4
PE[2]
PCR[66]
AF0
AF1
AF2
AF3
ALT4
—
—
GPIO[66]
E0UC[18]
—
—
FR_A_TX_EN
SIN_1
EIRQ[21]
SIUL
eMIOS_0
—
—
Flexray
DSPI_1
SIUL
I/O
I/O
—
—
O
I
I
M/S
Tristate
156
180
A7
PE[3]
PCR[67]
AF0
AF1
AF2
AF3
—
—
GPIO[67]
E0UC[19]
SOUT_1
—
FR_A_RX
WKPU[29]
SIUL
eMIOS_0
DSPI_1
—
Flexray
WKPU
I/O
I/O
O
—
I
I
M/S
Tristate
157
181
A10
PE[4]
PCR[68]
AF0
AF1
AF2
AF3
ALT4
—
GPIO[68]
E0UC[20]
SCK_1
—
FR_B_TX
EIRQ[9]
SIUL
eMIOS_0
DSPI_1
—
Flexray
SIUL
I/O
I/O
I/O
—
O
I
M/S
Tristate
160
184
A8
PE[5]
PCR[69]
AF0
AF1
AF2
AF3
—
—
GPIO[69]
E0UC[21]
CS0_1
MA[2]
FR_B_RX
WKPU[30]
SIUL
eMIOS_0
DSPI_1
ADC_0
Flexray
WKPU
I/O
I/O
I/O
O
I
I
M/S
Tristate
161
185
B8
Port
pin
PCR
PD[15]
PCR[63]
PE[0]
MPC5646C Data Sheet, Rev.6
24
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
GPIO[70]
E0UC[22]
CS3_0
MA[1]
EIRQ[22]
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
O
O
I
M/S
Tristate
167
191
B6
PCR[71]
AF0
AF1
AF2
AF3
—
GPIO[71]
E0UC[23]
CS2_0
MA[0]
EIRQ[23]
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
O
O
I
M/S
Tristate
168
192
A5
PE[8]
PCR[72]
AF0
AF1
AF2
AF3
GPIO[72]
CAN2TX
E0UC[22]
CAN3TX
SIUL
FlexCAN_2
eMIOS_0
FlexCAN_3
I/O
O
I/O
O
M/S
Tristate
21
21
G1
PE[9]
PCR[73]
AF0
AF1
AF2
AF3
—
—
—
GPIO[73]
—
E0UC[23]
—
WKPU[7]
CAN2RX
CAN3RX
SIUL
—
eMIOS_0
—
WKPU
FlexCAN_2
FlexCAN_3
I/O
—
I/O
—
I
I
I
S
Tristate
22
22
H1
PE[10]
PCR[74]
AF0
AF1
AF2
AF3
—
GPIO[74]
LIN3TX
CS3_1
E1UC[30]
EIRQ[10]
SIUL
LINFlexD_3
DSPI_1
eMIOS_1
SIUL
I/O
O
O
I/O
I
S
Tristate
23
23
G3
PE[11]
PCR[75]
AF0
AF1
AF2
AF3
—
—
GPIO[75]
E0UC[24]
CS4_1
—
LIN3RX
WKPU[14]
SIUL
eMIOS_0
DSPI_1
—
LINFlexD_3
WKPU
I/O
I/O
O
—
I
I
S
Tristate
25
25
H3
PE[12]
PCR[76]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[76]
—
E1UC[19]
—
CRS
SIN_2
EIRQ[11]
ADC1_S[7]
SIUL
—
eMIOS_1
—
FEC
DSPI_2
SIUL
ADC_1
I/O
—
I/O
—
I
I
I
I
M/S
Tristate
133
157
C14
Port
pin
PCR
PE[6]
PCR[70]
PE[7]
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
25
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
GPIO[77]
SOUT_2
E1UC[20]
—
RXD[3]
SIUL
DSPI_2
eMIOS_1
—
FEC
I/O
O
I/O
—
I
M/S
Tristate
127
151
C16
PCR[78]
AF0
AF1
AF2
AF3
—
GPIO[78]
SCK_2
E1UC[21]
—
EIRQ[12]
SIUL
DSPI_2
eMIOS_1
—
SIUL
I/O
I/O
I/O
—
I
M/S
Tristate
136
160
A14
PE[15]
PCR[79]
AF0
AF1
AF2
AF3
GPIO[79]
CS0_2
E1UC[22]
SCK_6
SIUL
DSPI_2
eMIOS_1
DSPI_6
I/O
I/O
I/O
I/O
M/S
Tristate
137
161
C12
PF[0]
PCR[80]
AF0
AF1
AF2
AF3
—
GPIO[80]
E0UC[10]
CS3_1
—
ADC0_S[8]
SIUL
eMIOS_0
DSPI_1
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
63
79
P7
PF[1]
PCR[81]
AF0
AF1
AF2
AF3
—
GPIO[81]
E0UC[11]
CS4_1
—
ADC0_S[9]
SIUL
eMIOS_0
DSPI_1
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
64
80
T6
PF[2]
PCR[82]
AF0
AF1
AF2
AF3
—
GPIO[82]
E0UC[12]
CS0_2
—
ADC0_S[10]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
I/O
—
I
S
Tristate
65
81
R6
PF[3]
PCR[83]
AF0
AF1
AF2
AF3
—
GPIO[83]
E0UC[13]
CS1_2
—
ADC0_S[11]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
66
82
R7
PF[4]
PCR[84]
AF0
AF1
AF2
AF3
—
GPIO[84]
E0UC[14]
CS2_2
—
ADC0_S[12]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
67
83
R8
Port
pin
PCR
PE[13]
PCR[77]
PE[14]
MPC5646C Data Sheet, Rev.6
26
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
GPIO[85]
E0UC[22]
CS3_2
—
ADC0_S[13]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
68
84
P8
PCR[86]
AF0
AF1
AF2
AF3
—
GPIO[86]
E0UC[23]
CS1_1
—
ADC0_S[14]
SIUL
eMIOS_0
DSPI_1
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
69
85
N8
PF[7]
PCR[87]
AF0
AF1
AF2
AF3
—
GPIO[87]
—
CS2_1
—
ADC0_S[15]
SIUL
—
DSPI_1
—
ADC_0
I/O
—
O
—
I
S
Tristate
70
86
P9
PF[8]
PCR[88]
AF0
AF1
AF2
AF3
GPIO[88]
CAN3TX
CS4_0
CAN2TX
SIUL
FlexCAN_3
DSPI_0
FlexCAN_2
I/O
O
O
O
M/S
Tristate
42
50
N2
PF[9]
PCR[89]
AF0
AF1
AF2
AF3
—
—
—
GPIO[89]
E1UC[1]
CS5_0
—
CAN2RX
CAN3RX
WKPU[22]
SIUL
eMIOS_1
DSPI_0
—
FlexCAN_2
FlexCAN_3
WKPU
I/O
I/O
O
—
I
I
I
S
Tristate
41
49
M4
PF[10]
PCR[90]
AF0
AF1
AF2
AF3
GPIO[90]
CS1_0
LIN4TX
E1UC[2]
SIUL
DSPI_0
LINFlexD_4
eMIOS_1
I/O
O
O
I/O
M/S
Tristate
46
54
P2
PF[11]
PCR[91]
AF0
AF1
AF2
AF3
—
—
GPIO[91]
CS2_0
E1UC[3]
—
LIN4RX
WKPU[15]
SIUL
DSPI_0
eMIOS_1
—
LINFlexD_4
WKPU
I/O
O
I/O
—
I
I
S
Tristate
47
55
R1
PF[12]
PCR[92]
AF0
AF1
AF2
AF3
GPIO[92]
E1UC[25]
LIN5TX
—
SIUL
eMIOS_1
LINFlexD_5
—
I/O
I/O
O
—
M/S
Tristate
43
51
P1
Port
pin
PCR
PF[5]
PCR[85]
PF[6]
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
27
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
—
GPIO[93]
E1UC[26]
—
—
LIN5RX
WKPU[16]
SIUL
eMIOS_1
—
—
LINFlexD_5
WKPU
I/O
I/O
—
—
I
I
S
Tristate
49
57
P3
PCR[94]
AF0
AF1
AF2
AF3
ALT4
GPIO[94]
CAN4TX
E1UC[27]
CAN1TX
MDIO
SIUL
FlexCAN_4
eMIOS_1
FlexCAN_1
FEC
I/O
O
I/O
O
I/O
M/S
Tristate
126
150
D14
PF[15]
PCR[95]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[95]
E1UC[4]
—
—
RX_DV
CAN1RX
CAN4RX
EIRQ[13]
SIUL
eMIOS_1
—
—
FEC
FlexCAN_1
FlexCAN_4
SIUL
I/O
I/O
—
—
I
I
I
I
M/S
Tristate
125
149
D15
PG[0]
PCR[96]
AF0
AF1
AF2
AF3
ALT4
GPIO[96]
CAN5TX
E1UC[23]
—
MDC
SIUL
FlexCAN_5
eMIOS_1
—
FEC
I/O
O
I/O
—
O
F
Tristate
122
146
E13
PG[1]
PCR[97]
AF0
AF1
AF2
AF3
—
—
—
GPIO[97]
—
E1UC[24]
—
TX_CLK
CAN5RX
EIRQ[14]
SIUL
—
eMIOS_1
—
FEC
FlexCAN_5
SIUL
I/O
—
I/O
—
I
I
I
M
Tristate
121
145
E14
PG[2]
PCR[98]
AF0
AF1
AF2
AF3
GPIO[98]
E1UC[11]
SOUT_3
—
SIUL
eMIOS_1
DSPI_3
—
I/O
I/O
O
—
M/S
Tristate
16
16
E4
PG[3]
PCR[99]
AF0
AF1
AF2
AF3
—
GPIO[99]
E1UC[12]
CS0_3
—
WKPU[17]
SIUL
eMIOS_1
DSPI_3
—
WKPU
I/O
I/O
I/O
—
I
S
Tristate
15
15
E1
PG[4]
PCR[100]
AF0
AF1
AF2
AF3
GPIO[100]
E1UC[13]
SCK_3
—
SIUL
eMIOS_1
DSPI_3
—
I/O
I/O
I/O
—
M/S
Tristate
14
14
F2
Port
pin
PCR
PF[13]
PCR[93]
PF[14]
MPC5646C Data Sheet, Rev.6
28
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
—
GPIO[101]
E1UC[14]
—
—
WKPU[18]
SIN_3
SIUL
eMIOS_1
—
—
WKPU
DSPI_3
I/O
I/O
—
—
I
I
S
Tristate
13
13
D1
PCR[102]
AF0
AF1
AF2
AF3
GPIO[102]
E1UC[15]
LIN6TX
—
SIUL
eMIOS_1
LINFlexD_6
—
I/O
I/O
O
—
M/S
Tristate
38
38
M1
PG[7]
PCR[103]
AF0
AF1
AF2
AF3
—
—
GPIO[103]
E1UC[16]
E1UC[30]
—
LIN6RX
WKPU[20]
SIUL
eMIOS_1
eMIOS_1
—
LINFlexD_6
WKPU
I/O
I/O
I/O
—
I
I
S
Tristate
37
37
L2
PG[8]
PCR[104]
AF0
AF1
AF2
AF3
—
GPIO[104]
E1UC[17]
LIN7TX
CS0_2
EIRQ[15]
SIUL
eMIOS_1
LINFlexD_7
DSPI_2
SIUL
I/O
I/O
O
I/O
I
S
Tristate
34
34
K3
PG[9]
PCR[105]
AF0
AF1
AF2
AF3
—
—
GPIO[105]
E1UC[18]
—
SCK_2
LIN7RX
WKPU[21]
SIUL
eMIOS_1
—
DSPI_2
LINFlexD_7
WKPU
I/O
I/O
—
I/O
I
I
S
Tristate
33
33
J4
PG[10]
PCR[106]
AF0
AF1
AF2
AF3
—
GPIO[106]
E0UC[24]
E1UC[31]
—
SIN_4
SIUL
eMIOS_0
eMIOS_1
—
DSPI_4
I/O
I/O
I/O
—
I
S
Tristate
138
162
B13
PG[11]
PCR[107]
AF0
AF1
AF2
AF3
GPIO[107]
E0UC[25]
CS0_4
CS0_6
SIUL
eMIOS_0
DSPI_4
DSPI_6
I/O
I/O
I/O
I/O
M/S
Tristate
139
163
A16
PG[12]
PCR[108]
AF0
AF1
AF2
AF3
ALT4
GPIO[108]
E0UC[26]
SOUT_4
—
TXD[2]
SIUL
eMIOS_0
DSPI_4
—
FEC
I/O
I/O
O
—
O
M/S
Tristate
116
140
F15
Port
pin
PCR
PG[5]
PCR[101]
PG[6]
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
29
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
ALT4
GPIO[109]
E0UC[27]
SCK_4
—
TXD[3]
SIUL
eMIOS_0
DSPI_4
—
FEC
I/O
I/O
I/O
—
O
M/S
Tristate
115
139
F16
PCR[110]
AF0
AF1
AF2
AF3
—
GPIO[110]
E1UC[0]
LIN8TX
—
SIN_6
SIUL
eMIOS_1
LINFlexD_8
—
DSPI_6
I/O
I/O
O
—
I
S
Tristate
134
158
C13
PG[15]
PCR[111]
AF0
AF1
AF2
AF3
—
GPIO[111]
E1UC[1]
SOUT_6
—
LIN8RX
SIUL
eMIOS_1
DSPI_6
—
LINFlexD_8
I/O
I/O
O
—
I
M/S
Tristate
135
159
D13
PH[0]
PCR[112]
AF0
AF1
AF2
AF3
ALT4
—
GPIO[112]
E1UC[2]
—
—
TXD[1]
SIN_1
SIUL
eMIOS_1
—
—
FEC
DSPI_1
I/O
I/O
—
—
O
I
M/S
Tristate
117
141
E15
PH[1]
PCR[113]
AF0
AF1
AF2
AF3
ALT4
GPIO[113]
E1UC[3]
SOUT_1
—
TXD[0]
SIUL
eMIOS_1
DSPI_1
—
FEC
I/O
I/O
O
—
O
M/S
Tristate
118
142
F13
PH[2]
PCR[114]
AF0
AF1
AF2
AF3
ALT4
GPIO[114]
E1UC[4]
SCK_1
—
TX_EN
SIUL
eMIOS_1
DSPI_1
—
FEC
I/O
I/O
I/O
—
O
M/S
Tristate
119
143
D16
PH[3]
PCR[115]
AF0
AF1
AF2
AF3
ALT4
GPIO[115]
E1UC[5]
CS0_1
—
TX_ER
SIUL
eMIOS_1
DSPI_1
—
FEC
I/O
I/O
I/O
—
O
M/S
Tristate
120
144
F14
PH[4]
PCR[116]
AF0
AF1
AF2
AF3
GPIO[116]
E1UC[6]
SOUT_7
—
SIUL
eMIOS_1
DSPI_7
—
I/O
I/O
O
—
M/S
Tristate
162
186
D7
Port
pin
PCR
PG[13]
PCR[109]
PG[14]
MPC5646C Data Sheet, Rev.6
30
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
GPIO[117]
E1UC[7]
—
—
SIN_7
SIUL
eMIOS_1
—
—
DSPI_7
I/O
I/O
—
—
I
S
Tristate
163
187
B7
PCR[118]
AF0
AF1
AF2
AF3
GPIO[118]
E1UC[8]
SCK_7
MA[2]
SIUL
eMIOS_1
DSPI_7
ADC_0
I/O
I/O
I/O
O
M/S
Tristate
164
188
C7
PH[7]
PCR[119]
AF0
AF1
AF2
AF3
ALT4
GPIO[119]
E1UC[9]
CS3_2
MA[1]
CS0_7
SIUL
eMIOS_1
DSPI_2
ADC_0
DSPI_7
I/O
I/O
O
O
I/O
M/S
Tristate
165
189
C6
PH[8]
PCR[120]
AF0
AF1
AF2
AF3
GPIO[120]
E1UC[10]
CS2_2
MA[0]
SIUL
eMIOS_1
DSPI_2
ADC_0
I/O
I/O
O
O
M/S
Tristate
166
190
A6
PH[9]6
PCR[121]
AF0
AF1
AF2
AF3
—
GPIO[121]
—
—
—
TCK
SIUL
—
—
—
JTAGC
I/O
—
—
—
I
S
Input,
weak
pull-up
155
179
A11
PH[10]6 PCR[122]
AF0
AF1
AF2
AF3
—
GPIO[122]
—
—
—
TMS
SIUL
—
—
—
JTAGC
I/O
—
—
—
I
M/S
Input,
weak
pull-up
148
172
D10
PH[11]
PCR[123]
AF0
AF1
AF2
AF3
GPIO[123]
SOUT_3
CS0_4
E1UC[5]
SIUL
DSPI_3
DSPI_4
eMIOS_1
I/O
O
I/O
I/O
M/S
Tristate
140
164
A13
PH[12]
PCR[124]
AF0
AF1
AF2
AF3
GPIO[124]
SCK_3
CS1_4
E1UC[25]
SIUL
DSPI_3
DSPI_4
eMIOS_1
I/O
I/O
O
I/O
M/S
Tristate
141
165
B12
PH[13]
PCR[125]
AF0
AF1
AF2
AF3
GPIO[125]
SOUT_4
CS0_3
E1UC[26]
SIUL
DSPI_4
DSPI_3
eMIOS_1
I/O
O
I/O
I/O
M/S
Tristate
9
9
B1
Port
pin
PCR
PH[5]
PCR[117]
PH[6]
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
31
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
GPIO[126]
SCK_4
CS1_3
E1UC[27]
SIUL
DSPI_4
DSPI_3
eMIOS_1
I/O
I/O
O
I/O
M/S
Tristate
10
10
C1
PCR[127]
AF0
AF1
AF2
AF3
GPIO[127]
SOUT_5
—
E1UC[17]
SIUL
DSPI_5
—
eMIOS_1
I/O
O
—
I/O
M/S
Tristate
8
8
E3
PI[0]
PCR[128]
AF0
AF1
AF2
AF3
GPIO[128]
E0UC[28]
LIN8TX
—
SIUL
eMIOS_0
LINFlexD_8
—
I/O
I/O
O
—
S
Tristate
172
196
C5
PI[1]
PCR[129]
AF0
AF1
AF2
AF3
—
—
GPIO[129]
E0UC[29]
—
—
WKPU[24]
LIN8RX
SIUL
eMIOS_0
—
—
WKPU
LINFlexD_8
I/O
I/O
—
—
I
I
S
Tristate
171
195
A4
PI[2]
PCR[130]
AF0
AF1
AF2
AF3
GPIO[130]
E0UC[30]
LIN9TX
—
SIUL
eMIOS_0
LINFlexD_9
—
I/O
I/O
O
—
S
Tristate
170
194
D6
PI[3]
PCR[131]
AF0
AF1
AF2
AF3
—
—
GPIO[131]
E0UC[31]
—
—
WKPU[23]
LIN9RX
SIUL
eMIOS_0
—
—
WKPU
LINFlexD_9
I/O
I/O
—
—
I
I
S
Tristate
169
193
B5
PI[4]
PCR[132]
AF0
AF1
AF2
AF3
GPIO[132]
E1UC[28]
SOUT_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
O
—
M/S
Tristate
143
167
A12
PI[5]
PCR[133]
AF0
AF1
AF2
AF3
ALT4
GPIO[133]
E1UC[29]
SCK_4
CS2_5
CS2_6
SIUL
eMIOS_1
DSPI_4
DSPI_5
DSPI_6
I/O
I/O
I/O
O
O
M/S
Tristate
142
166
D12
PI[6]
PCR[134]
AF0
AF1
AF2
AF3
ALT4
GPIO[134]
E1UC[30]
CS0_4
CS0_5
CS0_6
SIUL
eMIOS_1
DSPI_4
DSPI_5
DSPI_6
I/O
I/O
I/O
I/O
I/O
S
Tristate
11
11
D2
Port
pin
PCR
PH[14]
PCR[126]
PH[15]
MPC5646C Data Sheet, Rev.6
32
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
ALT4
GPIO[135]
E1UC[31]
CS1_4
CS1_5
CS1_6
SIUL
eMIOS_1
DSPI_4
DSPI_5
DSPI_6
I/O
I/O
O
O
O
S
Tristate
12
12
E2
PCR[136]
AF0
AF1
AF2
AF3
—
GPIO[136]
—
—
—
ADC0_S[16]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
108
130
J14
PI[9]
PCR[137]
AF0
AF1
AF2
AF3
—
GPIO[137]
—
—
—
ADC0_S[17]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
—
131
J15
PI[10]
PCR[138]
AF0
AF1
AF2
AF3
—
GPIO[138]
—
—
—
ADC0_S[18]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
—
134
J16
PI[11]
PCR[139]
AF0
AF1
AF2
AF3
—
—
GPIO[139]
—
—
—
ADC0_S[19]
SIN_3
SIUL
—
—
—
ADC_0
DSPI_3
I/O
—
—
—
I
I
S
Tristate
111
135
H16
PI[12]
PCR[140]
AF0
AF1
AF2
AF3
—
GPIO[140]
CS0_3
CS0_2
—
ADC0_S[20]
SIUL
DSPI_3
DSPI_2
—
ADC_0
I/O
I/O
I/O
—
I
S
Tristate
112
136
G15
PI[13]
PCR[141]
AF0
AF1
AF2
AF3
—
GPIO[141]
CS1_3
CS1_2
—
ADC0_S[21]
SIUL
DSPI_3
DSPI_2
—
ADC_0
I/O
O
O
—
I
S
Tristate
113
137
G14
PI[14]
PCR[142]
AF0
AF1
AF2
AF3
—
—
GPIO[142]
—
—
—
ADC0_S[22]
SIN_4
SIUL
—
—
—
ADC_0
DSPI_4
I/O
—
—
—
I
I
S
Tristate
76
92
T12
Port
pin
PCR
PI[7]
PCR[135]
PI[8]
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
33
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
GPIO[143]
CS0_4
CS2_2
—
ADC0_S[23]
SIUL
DSPI_4
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
75
91
P11
PCR[144]
AF0
AF1
AF2
AF3
—
GPIO[144]
CS1_4
CS3_2
—
ADC0_S[24]
SIUL
DSPI_4
DSPI_2
—
ADC_0
I/O
O
O
—
I
S
Tristate
74
90
R11
PJ[1]
PCR[145]
AF0
AF1
AF2
AF3
—
—
GPIO[145]
—
—
—
ADC0_S[25]
SIN_5
SIUL
—
—
——
ADC_0
DSPI_5
I/O
—
—
—
I
I
S
Tristate
73
89
N10
PJ[2]
PCR[146]
AF0
AF1
AF2
AF3
—
GPIO[146]
CS0_5
CS0_6
CS0_7
ADC0_S[26]
SIUL
DSPI_5
DSPI_6
DSPI_7
ADC_0
I/O
I/O
I/O
I/O
I
S
Tristate
72
88
R10
PJ[3]
PCR[147]
AF0
AF1
AF2
AF3
—
GPIO[147]
CS1_5
CS1_6
CS1_7
ADC0_S[27]
SIUL
DSPI_5
DSPI_6
DSPI_7
ADC_0
I/O
O
O
O
I
S
Tristate
71
87
P10
PJ[4]
PCR[148]
AF0
AF1
AF2
AF3
GPIO[148]
SCK_5
E1UC[18]
—
SIUL
DSPI_5
eMIOS_1
—
I/O
I/O
I/O
—
M/S
Tristate
5
5
D3
PJ[5]
PCR[149]
AF0
AF1
AF2
AF3
—
GPIO[149]
—
—
—
ADC0_S[28]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
—
113
N12
PJ[6]
PCR[150]
AF0
AF1
AF2
AF3
—
GPIO[150]
—
—
—
ADC0_S[29]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
—
112
N15
Port
pin
PCR
PI[15]
PCR[143]
PJ[0]
MPC5646C Data Sheet, Rev.6
34
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
GPIO[151]
—
—
—
ADC0_S[30]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
—
111
P16
PCR[152]
AF0
AF1
AF2
AF3
—
GPIO[152]
—
—
—
ADC0_S[31]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
—
110
P15
PJ[9]
PCR[153]
AF0
AF1
AF2
AF3
—
GPIO[153]
—
—
—
ADC1_S[8]
SIUL
—
—
—
ADC_1
I/O
—
—
—
I
S
Tristate
—
68
P5
PJ[10]
PCR[154]
AF0
AF1
AF2
AF3
—
GPIO[154]
—
—
—
ADC1_S[9]
SIUL
—
—
—
ADC_1
I/O
—
—
—
I
S
Tristate
—
67
T5
PJ[11]
PCR[155]
AF0
AF1
AF2
AF3
—
GPIO[155]
—
—
—
ADC1_S[10]
SIUL
—
—
—
ADC_1
I/O
—
—
—
I
S
Tristate
—
60
R3
PJ[12]
PCR[156]
AF0
AF1
AF2
AF3
—
GPIO[156]
—
—
—
ADC1_S[11]
SIUL
—
—
—
ADC_1
I/O
—
—
—
I
S
Tristate
—
59
T1
PJ[13]
PCR[157]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[157]
—
CS1_7
—
CAN4RX
ADC1_S[12]
CAN1RX
WKPU[31]
SIUL
—
DSPI_7
—
FlexCAN_4
ADC_1
FlexCAN_1
WKPU
I/O
—
O
—
I
I
I
I
S
Tristate
—
65
N5
PJ[14]
PCR[158]
AF0
AF1
AF2
AF3
GPIO[158]
CAN1TX
CAN4TX
CS2_7
SIUL
FlexCAN_1
FlexCAN_4
DSPI_7
I/O
O
O
O
M/S
Tristate
—
64
T4
Port
pin
PCR
PJ[7]
PCR[151]
PJ[8]
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
35
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
GPIO[159]
—
CS1_6
—
CAN1RX
SIUL
—
DSPI_6
—
FlexCAN_1
I/O
—
O
—
I
M/S
Tristate
—
63
R4
PCR[160]
AF0
AF1
AF2
AF3
GPIO[160]
CAN1TX
CS2_6
—
SIUL
FlexCAN_1
DSPI_6
—
I/O
O
O
—
M/S
Tristate
—
62
T3
PK[1]
PCR[161]
AF0
AF1
AF2
AF3
—
GPIO[161]
CS3_6
—
—
CAN4RX
SIUL
DSPI_6
—
—
FlexCAN_4
I/O
O
—
—
I
M/S
Tristate
—
41
H4
PK[2]
PCR[162]
AF0
AF1
AF2
AF3
GPIO[162]
CAN4TX
—
—
SIUL
FlexCAN_4
—
—
I/O
O
—
—
M/S
Tristate
—
42
L4
PK[3]
PCR[163]
AF0
AF1
AF2
AF3
—
—
GPIO[163]
E1UC[0]
—
—
CAN5RX
LIN8RX
SIUL
eMIOS_1
—
—
FlexCAN_5
LINFlexD_8
I/O
I/O
—
—
I
I
M/S
Tristate
—
43
N1
PK[4]
PCR[164]
AF0
AF1
AF2
AF3
GPIO[164]
LIN8TX
CAN5TX
E1UC[1]
SIUL
LINFlexD_8
FlexCAN_5
eMIOS_1
I/O
O
O
I/O
M/S
Tristate
—
44
M3
PK[5]
PCR[165]
AF0
AF1
AF2
AF3
—
—
GPIO[165]
—
—
—
CAN2RX
LIN2RX
SIUL
—
—
—
FlexCAN_2
LINFlexD_2
I/O
—
—
—
I
I
M/S
Tristate
—
45
M5
PK[6]
PCR[166]
AF0
AF1
AF2
AF3
GPIO[166]
CAN2TX
LIN2TX
—
SIUL
FlexCAN_2
LINFlexD_2
—
I/O
O
O
—
M/S
Tristate
—
46
M6
Port
pin
PCR
PJ[15]
PCR[159]
PK[0]
MPC5646C Data Sheet, Rev.6
36
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
—
—
GPIO[167]
—
—
—
CAN3RX
LIN3RX
SIUL
—
—
—
FlexCAN_3
LINFlexD_3
I/O
—
—
—
I
I
M/S
Tristate
—
47
M7
PCR[168]
AF0
AF1
AF2
AF3
GPIO[168]
CAN3TX
LIN3TX
—
SIUL
FlexCAN_3
LINFlexD_3
—
I/O
O
O
—
M/S
Tristate
—
48
M8
PK[9]
PCR[169]
AF0
AF1
AF2
AF3
—
GPIO[169]
—
—
—
SIN_4
SIUL
—
—
—
DSPI_4
I/O
—
—
—
I
M/S
Tristate
—
197
E8
PK[10]
PCR[170]
AF0
AF1
AF2
AF3
GPIO[170]
SOUT_4
—
—
SIUL
DSPI_4
—
—
I/O
O
—
—
M/S
Tristate
—
198
E7
PK[11]
PCR[171]
AF0
AF1
AF2
AF3
GPIO[171]
SCK_4
—
—
SIUL
DSPI_4
—
—
I/O
I/O
—
—
M/S
Tristate
—
199
F8
PK[12]
PCR[172]
AF0
AF1
AF2
AF3
GPIO[172]
CS0_4
—
—
SIUL
DSPI_4
—
—
I/O
I/O
—
—
M/S
Tristate
—
200
G12
PK[13]
PCR[173]
AF0
AF1
AF2
AF3
—
GPIO[173]
CS3_6
CS2_7
SCK_1
CAN3RX
SIUL
DSPI_6
DSPI_7
DSPI_1
FlexCAN_3
I/O
O
O
I/O
I
M/S
Tristate
—
201
H12
PK[14]
PCR[174]
AF0
AF1
AF2
AF3
GPIO[174]
CAN3TX
CS3_7
CS0_1
SIUL
FlexCAN_3
DSPI_7
DSPI_1
I/O
O
O
I/O
M/S
Tristate
—
202
J12
PK[15]
PCR[175]
AF0
AF1
AF2
AF3
—
—
GPIO[175]
—
—
—
SIN_1
SIN_7
SIUL
—
—
—
DSPI_1
DSPI_7
I/O
—
—
—
I
I
M/S
Tristate
—
203
D5
Port
pin
PCR
PK[7]
PCR[167]
PK[8]
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
37
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
GPIO[176]
SOUT_1
SOUT_7
—
SIUL
DSPI_1
DSPI_7
—
I/O
O
O
—
M/S
Tristate
—
204
C4
PCR[177]
AF0
AF1
AF2
AF3
GPIO[177]
—
—
—
SIUL
—
—
—
I/O
—
—
—
M/S
Tristate
—
—
F7
PL[2]
PCR[178]7
AF0
AF1
AF2
AF3
GPIO[178]
—
MDO08
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
F5
PL[3]
PCR[179]
AF0
AF1
AF2
AF3
GPIO[179]
—
MDO1
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
G5
PL[4]
PCR[180]
AF0
AF1
AF2
AF3
GPIO[180]
—
MDO2
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
H5
PL[5]
PCR[181]
AF0
AF1
AF2
AF3
GPIO[181]
—
MDO3
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
J5
PL[6]
PCR[182]
AF0
AF1
AF2
AF3
GPIO[182]
—
MDO4
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
K5
PL[7]
PCR[183]
AF0
AF1
AF2
AF3
GPIO[183]
—
MDO5
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
L5
PL[8]
PCR[184]
AF0
AF1
AF2
AF3
—
GPIO[184]
—
—
—
EVTI
SIUL
—
—
—
Nexus
I/O
—
—
—
I
S
Pull-up
—
—
M9
PL[9]
PCR[185]
AF0
AF1
AF2
AF3
GPIO[185]
—
MSEO
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
M10
Port
pin
PCR
PL[0]
PCR[176]
PL[1]
MPC5646C Data Sheet, Rev.6
38
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
GPIO[186]
—
MCKO
—
SIUL
—
Nexus
—
I/O
—
O
—
F/S
Tristate
—
—
M11
PCR[187]
AF0
AF1
AF2
AF3
GPIO[187]
—
—
—
SIUL
—
—
—
I/O
—
—
—
M/S
Tristate
—
—
M12
PL[12]
PCR[188]
AF0
AF1
AF2
AF3
GPIO[188]
—
EVTO
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
F11
PL[13]
PCR[189]
AF0
AF1
AF2
AF3
GPIO[189]
—
MDO6
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
F10
PL[14]
PCR[190]
AF0
AF1
AF2
AF3
GPIO[190]
—
MDO7
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
E12
PL[15]
PCR[191]
AF0
AF1
AF2
AF3
GPIO[191]
—
MDO8
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
E11
PM[0]
PCR[192]
AF0
AF1
AF2
AF3
GPIO[192]
—
MDO9
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
E10
PM[1]
PCR[193]
AF0
AF1
AF2
AF3
GPIO[193]
—
MDO10
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
E9
PM[2]
PCR[194]
AF0
AF1
AF2
AF3
GPIO[194]
—
MDO11
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
F12
PM[3]
PCR[195]
AF0
AF1
AF2
AF3
GPIO[195]
—
—
—
SIUL
—
—
—
I/O
—
—
—
M/S
Tristate
—
—
K12
Port
pin
PCR
PL[10]
PCR[186]
PL[11]
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
39
Package pinouts and signal descriptions
Table 4. Functional port pin descriptions (continued)
Alternate
function1
Function
Peripheral
I/O
direction2
Pad type
RESET
config.
176 LQFP
208 LQFP
256 MAPBGA
Pin number
AF0
AF1
AF2
AF3
GPIO[196]
—
—
—
SIUL
—
—
—
I/O
—
—
—
M/S
Tristate
—
—
L12
PCR[197]
AF0
AF1
AF2
AF3
GPIO[197]
—
—
—
SIUL
—
—
—
I/O
—
—
—
M/S
Tristate
—
—
F9
PCR[198]
AF0
AF1
AF2
AF3
GPIO[198]
—
—
—
SIUL
—
—
—
I/O
—
—
—
M/S
Tristate
—
—
F6
Port
pin
PCR
PM[4]
PCR[196]
PM[5]
PM[6]
NOTES:
1 Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA =
000  AF0; PCR.PA = 001  AF1; PCR.PA = 010  AF2; PCR.PA = 011  AF3; PCR.PA = 100  ALT4. This is
intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’,
regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only
function is reported as “—”.
2 Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by
setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.
3 NMI[0] and NMI[1] have a higher priority than alternate functions. When NMI is selected, the PCR.PA field is
ignored.
4 SXOSC’s OSC32k_XTAL and OSC32k_EXTAL pins are shared with GPIO functionality. When used as crystal pins,
other functionality of the pin cannot be used and it should be ensured that application never programs OBE and
PUE bit of the corresponding PCR to "1".
5 If you want to use OSC32K functionality through PB[8] and PB[9], you must ensure that PB[10] is static in nature
as PB[10] can induce coupling on PB[9] and disturb oscillator frequency.
6
Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
It is up to the user to configure these pins as GPIO when needed.
7
When MBIST is enabled to run ( STCU Enable = 1), the application must not drive or tie PAD[178) (MDO[0]) to 0 V
before the device exits reset (external reset is removed) as the pad is internally driven to 1 to indicate MBIST
operation. When MBIST is not enabled (STCU Enable = 0), there are no restriction as the device does not internally
drive the pad.
8 These pins can be configured as Nexus pins during reset by the debugger writing to the Nexus Development
Interface "Port Control Register" rather than the SIUL. Specifically, the debugger can enable the MDO[7:0], MSEO,
and MCKO ports by programming NDI (PCR[MCKO_EN] or PCR[PSTAT_EN]). MDO[8:11] ports can be enabled by
programming NDI ((PCR[MCKO_EN] and PCR[FPM]) or PCR[PSTAT_EN]).
MPC5646C Data Sheet, Rev.6
40
Freescale Semiconductor
Electrical Characteristics
4
Electrical Characteristics
This section contains electrical characteristics of the device as well as temperature and power
considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However,
it is advisable to take precautions to avoid application of any voltage higher than the specified maximum
rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS_HV).
This could be done by the internal pull-up and pull-down, which is provided by the product for most
general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on
the system.
In the tables where the device logic provides signals with their respective timing characteristics, the
symbol “CC” for Controller Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to
the device, the symbol “SR” for System Requirement is included in the Symbol column.
4.1
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the classifications listed in Table 5 are used and the parameters are tagged
accordingly in the tables where appropriate.
Table 5. Parameter classifications
Classification tag
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
4.2
NVUSRO register
Portions of the device configuration, such as high voltage supply is controlled via bit values in the
Non-Volatile User Options Register (NVUSRO). For a detailed description of the NVUSRO register, see
MPC5646C Reference Manual.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
41
Electrical Characteristics
4.2.1
NVUSRO [PAD3V5V(0)] field description
Table 6 shows how NVUSRO [PAD3V5V(0)] controls the device configuration for VDD_HV_A domain.
Table 6. PAD3V5V(0) field description
Value1
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
NOTES:
1
'1' is delivery value. It is part of shadow flash memory, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V(0,1) bit value.
4.2.2
NVUSRO [PAD3V5V(1)] field description
Table 7 shows how NVUSRO [PAD3V5V(1)] controls the device configuration the device configuration
for VDD_HV_B domain.
Table 7. PAD3V5V(1) field description
Value1
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
NOTES:
1 '1' is delivery value. It is part of shadow flash memory, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V(0,1) bit value.
4.3
Absolute maximum ratings
Table 8. Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Unit
Min
Max
SR Digital ground on VSS_HV
pins
—
0
0
V
VDD_HV_A
SR Voltage on VDD_HV_A pins
with respect to ground
(VSS_HV)
—
–0.3
6.0
V
VDD_HV_B1
SR Voltage on VDD_HV_B pins
with respect to common
ground (VSS_HV)
—
–0.3
6.0
V
SR Voltage on VSS_LV (low
voltage digital supply) pins
with respect to ground
(VSS_HV)
—
VSS_HV  0.1
VSS_HV  0.1
V
VSS_HV
VSS_LV
MPC5646C Data Sheet, Rev.6
42
Freescale Semiconductor
Electrical Characteristics
Table 8. Absolute maximum ratings (continued)
Value
Symbol
Parameter
VRC_CTRL2
VSS_ADC
Conditions
Base control voltage for
external BCP68 NPN device
SR Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC
reference) pin with respect to
ground (VSS_HV)
VDD_HV_ADC0 SR Voltage on VDD_HV_ADC0
with respect to ground
(VSS_HV)
VDD_HV_ADC14 SR Voltage on VDD_HV_ADC1
with respect to ground
(VSS_HV)
Unit
Min
Max
Relative to VDD_LV
0
VDD_LV + 1
V
—
VSS_HV  0.1
VSS_HV + 0.1
V
–0.3
6.0
V
—
Relative to VDD_HV_A
3
VDD_HV_A 0.3 VDD_HV_A+0.3
—
–0.3
6.0
Relative to VDD_HV_A2
VDD_HV_A0.3
VDD_HV_A+0.3
VIN
SR Voltage on any GPIO pin with
respect to ground (VSS_HV)
Relative to
VDD_HV_A/HV_B
IINJPAD
SR Injected input current on any
pin during overload condition
—
–10
10
IINJSUM
SR Absolute sum of all injected
input currents during overload
condition
—
–50
50
IAVGSEG5
TSTORAGE
SR Sum of all the static I/O
current within a supply
segment
(VDD_HV_A or VDD_HV_B)
SR Storage temperature
VDD_HV_A/HV_B VDD_HV_A/HV_B
0.3
+0.3
VDD = 5.0 V ± 10%,
PAD3V5V = 0
70
VDD = 3.3 V ± 10%,
PAD3V5V = 1
64
—
–556
150
V
V
mA
mA
°C
NOTES:
1 V
DD_HV_B can be independently controlled from VDD_HV_A. These can ramp up or ramp down in any order. Design
is robust against any supply order.
2 This voltage is internally generated by the device and no external voltage should be supplied.
3
Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum
value is 6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V.
4
PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should
be within ±300 mV of VDD_HV_B when these channels are used for ADC_1.
5 Any temperature beyond 125 °C should limit the current to 50 mA (max).
6
This is the storage temperature for the flash memory.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
43
Electrical Characteristics
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of this specification are not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability. During overload conditions
(VIN > VDD_HV_A/HV_B or VIN < VSS_HV), the voltage on pins with respect
to ground (VSS_HV) must not exceed the recommended values.
4.4
Recommended operating conditions
Table 9. Recommended operating conditions (3.3 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS_HV
SR Digital ground on VSS_HV
pins
—
0
0
V
VDD_HV_A1
SR Voltage on VDD_HV_A pins
with respect to ground
(VSS_HV)
—
3.0
3.6
V
VDD_HV_B1
SR Voltage on VDD_HV_B pins
with respect to ground
(VSS_HV)
—
3.0
3.6
V
VSS_LV2
SR Voltage on VSS_LV (low
voltage digital supply) pins
with respect to ground
(VSS_HV)
—
VSS_HV  0.1
VSS_HV + 0.1
V
Relative to VDD_LV
0
VDD_LV + 1
V
—
VSS_HV  0.1
VSS_HV + 0.1
V
—
3.05
3.6
V
VRC_CTRL3
VSS_ADC
Base control voltage for
external BCP68 NPN device
SR Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC
reference) pin with respect to
ground (VSS_HV)
VDD_HV_ADC04 SR Voltage on VDD_HV_ADC0
with respect to ground
(VSS_HV)
VDD_HV_ADC17 SR Voltage on VDD_HV_ADC1
with respect to ground
(VSS_HV)
VIN
SR Voltage on any GPIO pin with
respect to ground (VSS_HV)
Relative to
VDD_HV_A6
—
Relative to
VDD_HV_A6
VDD_HV_A  0.1 VDD_HV_A + 0.1
3.0
3.6
V
VDD_HV_A  0.1 VDD_HV_A + 0.1
—
VSS_HV  0.1
—
Relative to
VDD_HV_A/HV_B
—
VDD_HV_A/HV_B
+ 0.1
V
MPC5646C Data Sheet, Rev.6
44
Freescale Semiconductor
Electrical Characteristics
Table 9. Recommended operating conditions (3.3 V) (continued)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
IINJPAD
SR Injected input current on any
pin during overload condition
—
5
5
IINJSUM
SR Absolute sum of all injected
input currents during overload
condition
—
50
50
SR VDD_HV_A slope to ensure
correct power up8
—
—
0.5
V/µs
—
0.5
—
V/min
–40
125
°C
40
150
TVDD
TA
SR Ambient temperature under
bias
TJ
SR Junction temperature under
bias
fCPU up to
120 MHz  2%
—
mA
NOTES:
1 100 nF EMI capacitance need to be provided between each VDD/VSS_HV pair.
2 100 nF EMI capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 10 µF bulk capacitance
needs to be provided as CREG on each VDD_LV pin. For details refer to the Power Management chapter of the
MPC5646C Reference Manual.
3 This voltage is internally generated by the device and no external voltage should be supplied.
4 100 nF capacitance needs to be provided between V
DD_ADC/VSS_ADC pair.
5 Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device
is reset.
6 Both the relative and the fixed conditions must be met. For instance: If V
DD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value
is 6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V.
7 PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from V
DD_HV_B domain hence VDD_HV_ADC1 should be
within ±100 mV of VDD_HV_B when these channels are used for ADC_1.
8 Guaranteed by the device validation.
Table 10. Recommended operating conditions (5.0 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS_HV
SR Digital ground on VSS_HV pins
—
0
0
V
VDD_HV_A1
SR Voltage on VDD_HV_A pins with
respect to ground (VSS_HV)
—
4.5
5.5
V
3.0
5.5
—
3.0
5.5
V
—
3.0
3.6
V
VDD_HV_B
SR Generic GPIO functionality
Ethernet/3.3 V functionality
(See the notes in all figures in
Section 3, ”Package pinouts and
signal descriptions” for the list of
channels operating in VDD_HV_B
domain)
Voltage
drop2
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
45
Electrical Characteristics
Table 10. Recommended operating conditions (5.0 V) (continued)
Value
Symbol
VSS_LV3
VRC_CTRL4
VSS_ADC
Parameter
SR Voltage on VSS_LV (Low voltage
digital supply) pins with respect to
ground (VSS_HV)
Base control voltage for external
BCP68 NPN device
SR Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC reference)
pin with respect to ground
(VSS_HV)
VDD_HV_ADC05 SR Voltage on VDD_HV_ADC0 with
respect to ground (VSS_HV)
VDD_HV_ADC17 SR Voltage on VDD_HV_ADC1 with
respect to ground (VSS_HV)
VIN
SR Voltage on any GPIO pin with
respect to ground (VSS_HV)
Conditions
Unit
Min
Max
—
VSS_HV – 0.1
VSS_HV + 0.1
V
Relative to
VDD_LV
0
VDD_LV + 1
V
—
VSS_HV – 0.1
VSS_HV + 0.1
V
—
4.5
5.5
V
Voltage drop(2)
3.0
5.5
Relative to
VDD_HV_A6
VDD_HV_A – 0.1
VDD_HV_A + 0.1
—
4.5
5.5
3.0
5.5
Relative to
VDD_HV_A6
VDD_HV_A  0.1
VDD_HV_A + 0.1
—
VSS_HV –0.1
—
Relative to
VDD_HV_A/HV_B
—
VDD_HV_A/HV_B
+ 0.1
(2)
Voltage drop
V
V
IINJPAD
SR Injected input current on any pin
during overload condition
—
–5
5
mA
IINJSUM
SR Absolute sum of all injected input
currents during overload condition
—
–50
50
TVDD
SR VDD_HV_A slope to ensure correct
power up8
—
—
0.5
V/µs
—
0.5
—
V/min
TA C-Grade Part SR Ambient temperature under bias
—
40
85
TJ C-Grade Part SR Junction temperature under bias
—
40
110
TA V-Grade Part SR Ambient temperature under bias
—
40
105
TJ V-Grade Part SR Junction temperature under bias
—
40
130
TA M-Grade Part SR Ambient temperature under bias
—
40
125
TJ M-Grade Part SR Junction temperature under bias
—
40
150
°C
NOTES:
1 100 nF EMI capacitance need to be provided between each VDD/VSS_HV pair.
2
Full device operation is guaranteed by design from 3.0 V–5.5 V. OSC functionality is guaranteed from the entire
range 3.0V–5.5 V, the parametrics measured are at 3.0V and 5.5V (extreme voltage ranges to cover the range of
operation). The parametrics might have some variation in the intermediate voltage range, but there is no impact to
functionality.
3 100 nF EMI capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 10 µF bulk capacitance
needs to be provided as CREG on each VDD_LV pin.
MPC5646C Data Sheet, Rev.6
46
Freescale Semiconductor
Electrical Characteristics
4
This voltage is internally generated by the device and no external voltage should be supplied.
100 nF capacitance needs to be provided between VDD_HV_(ADC0/ADC1)/VSS_HV_(ADC0/ADC1) pair.
6
Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum
value is 6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V.
7
PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1
should be within ±100 mV of VDD_HV_B when these channels are used for ADC_1.
8
Guaranteed by device validation.
5
NOTE
SRAM retention guaranteed to LVD levels.
4.5
Thermal characteristics
4.5.1
Package thermal characteristics
Table 11. LQFP thermal characteristics1
Symbol
C
CC
RJA
CC
RJA
D
D
Conditions2
Parameter
Thermal resistance,
junction-to-ambient
natural convection4
Single-layer
board—1s
Thermal resistance,
junction-to-ambient
natural convection7
Four-layer
board—2s2p7
Value3
Pin count
Unit
Min
Typ
Max
176
—
—
385
°C/W
208
—
—
416
°C/W
176
—
—
31
°C/W
208
—
—
34
°C/W
NOTES:
1 Thermal characteristics are targets based on simulation that are subject to change per device characterization.
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C.
3 All values need to be confirmed during device validation.
4
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
5
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6.
6 Junction-to-Ambient thermal resistance determined per JEDEC JESD51-2 and JESD51-6
7 Junction-to-Board thermal resistance determined per JEDEC JESD51-8.
Table 12. 256 MAPBGA thermal characteristics1
Symbol
RJA
CC
C
Parameter
— Thermal resistance, junction-to-ambient
natural convection
Conditions
Value
Unit
Single-layer board—1s
432
°C/W
Four-layer board—2s2p
263
NOTES:
1 Thermal characteristics are targets based on simulation that are subject to change per device characterization.
2 Junction-to-ambient thermal resistance determined per JEDEC JESD51-2 with the single layer board horizontal.
Board meets JESD51-9 specification.
3 Junction-to-ambient thermal resistance determined per JEDEC JESD51-6 with the board horizontal.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
47
Electrical Characteristics
4.5.2
Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1:
TJ = TA + (PD  RJA)
Eqn. 1
Where:
TA is the ambient temperature in °C.
RJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PI/O (PD = PINT + PI/O).
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power.
PI/O represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be
significant, if the device is configured to continuously drive external modules and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273 °C)
Eqn. 2
K = PD  (TA + 273 °C) + RJA  PD2
Eqn. 3
Therefore, solving equations 1 and 2:
Where:
K is a constant for the particular part, which may be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be
obtained by solving equations 1 and 2 iteratively for any value of TA.
4.6
4.6.1
I/O pad electrical characteristics
I/O pad types
The device provides four main I/O pad types depending on the associated alternate functions:
• Slow pads—These pads are the most common pads, providing a good compromise between
transition time and low electromagnetic emission.
• Medium pads—These pads provide transition fast enough for the serial communication channels
with controlled current to reduce electromagnetic emission.
• Fast pads—These pads provide maximum speed. These are used for improved Nexus debugging
capability.
• Input only pads—These pads are associated to ADC channels and 32 kHz low power external
crystal oscillator providing low input leakage.
• Low power pads—These pads are active in standby mode for wakeup source.
Also, medium/slow and fast/medium pads are available in design which can be configured to behave like
a slow/medium and medium/fast pads depending upon the slew-rate control.
MPC5646C Data Sheet, Rev.6
48
Freescale Semiconductor
Electrical Characteristics
Medium and fast pads can use slow configuration to reduce electromagnetic emission, at the cost of
reducing AC performance.
4.6.2
I/O input DC characteristics
Table 13 provides input DC electrical characteristics as described in Figure 5.
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1
(GPDI register of SIUL)
PDIx = ‘0’
Figure 5. I/O input DC electrical characteristics definition
Table 13. I/O input DC electrical characteristics
Symbol
C
Value2
Conditions1
Parameter
Unit
Min
Typ
Max
VIH
SR P Input high level CMOS (Schmitt
Trigger)
—
0.65VDD
—
VDD + 0.4
VIL
SR P Input low level CMOS (Schmitt
Trigger)
—
0.3
—
0.35VDD
—
0.1VDD
—
—
—
2
—
—
2
—
D
No injection TA = 40 °C
on adjacent
TA = 25 °C
pin
TA = 105 °C
—
12
500
P
TA = 125 °C
—
70
1000
—
—
—
404
ns
—
10004
—
—
ns
VHYS CC C Input hysteresis CMOS (Schmitt
Trigger)
ILKG CC P Digital input leakage
P
WFI
SR P Width of input pulse rejected by
analog filter3
WNFI SR P Width of input pulse accepted by
analog filter(3)
V
nA
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
49
Electrical Characteristics
2
VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. All values need to be confirmed during device validation.
Analog filters are available on all wakeup lines.
4
The width of input pulse in between 40 ns to 1000 ns is indeterminate. It may pass the noise or may not depending
on silicon sample to sample variation.
3
4.6.3
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
• Table 14 provides weak pull figures. Both pull-up and pull-down resistances are supported.
• Table 15 provides output driver characteristics for I/O pads when in SLOW configuration.
• Table 16 provides output driver characteristics for I/O pads when in MEDIUM configuration.
• Table 17 provides output driver characteristics for I/O pads when in FAST configuration.
Table 14. I/O pull-up/pull-down DC electrical characteristics
Symbol
|IWPU|
CC
C
P
C
P
|IWPD|
CC
P
C
P
Parameter
Value
Conditions1,2
Unit
Min
Typ
Max
10
—
150
10
—
250
10
—
150
10
—
150
10
—
250
10
—
150
Weak pull-up
VIN = VIL, VDD = PAD3V5V = 0
current absolute 5.0 V ± 10%
PAD3V5V = 13
value
VIN = VIL, VDD = PAD3V5V = 1
3.3 V ± 10%
Weak pull-down VIN = VIH, VDD = PAD3V5V = 0
current absolute 5.0 V ± 10%
PAD3V5V = 1
value
VIN = VIH, VDD = PAD3V5V = 1
3.3 V ± 10%
µA
µA
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 V
DD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3 The configuration PAD3V5 = 1 when V
DD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 15. SLOW configuration output buffer electrical characteristics
Symbol C
Parameter
VOH CC P Output high level
SLOW
configuration
C
P
Value
Conditions1,2
Unit
Min
Typ
Max
Push Pull IOH = 3 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
0.8VDD
—
—
IOH = 3 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 13
0.8VDD
—
—
—
—
VDD  0.8
IOH = 1.5 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
V
MPC5646C Data Sheet, Rev.6
50
Freescale Semiconductor
Electrical Characteristics
Table 15. SLOW configuration output buffer electrical characteristics (continued)
Symbol C
VOL CC P Output low level
SLOW
configuration
C
Value
Conditions1,2
Parameter
Unit
Min
Typ
Max
—
—
0.1VDD
IOL = 3 mA,
VDD = 5.0 V ± 10%, PAD3V5V =
1(3)
—
—
0.1VDD
IOL = 1.5 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
0.5
Push Pull IOL = 3 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
P
V
NOTES:
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 V
DD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3 The configuration PAD3V5 = 1 when V
DD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 16. MEDIUM configuration output buffer electrical characteristics
Symbol
VOH
VOL
CC
CC
C
Parameter
Value
Conditions1,2
Unit
Min
Typ
Max
Push Pull IOH = 3 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 0
0.8VDD
—
—
C
IOH = 1.5 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 13
0.8VDD
—
—
C
IOH = 2 mA,
VDD = 3.3 V ± 10%,
PAD3V5V = 1
VDD  0.8
—
—
Push Pull IOL = 3 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
0.2VDD
C
IOL = 1.5 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 1(3)
—
—
0.1VDD
C
IOL = 2 mA,
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
0.5
C
C
Output high level
MEDIUM
configuration
Output low level
MEDIUM
configuration
V
V
NOTES:
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 V
DD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
51
Electrical Characteristics
Table 17. FAST configuration output buffer electrical characteristics
Symbol
C
CC
VOH
VOL
CC
Value
Conditions1,2
Parameter
Unit
Min
Typ
Max
P
Output high level Push Pull IOH = 14 mA,
FAST
VDD = 5.0 V ± 10%,
PAD3V5V = 0
configuration
0.8VDD
—
—
C
IOH = 7 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 13
0.8VDD
—
—
C
IOH = 11 mA,
VDD = 3.3 V ± 10%,
PAD3V5V = 1
VDD  0.8
—
—
P
Output low level Push Pull IOL = 14 mA,
FAST
VDD = 5.0 V ± 10%,
configuration
PAD3V5V = 0
—
—
0.1VDD
C
IOL = 7 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 1(3)
—
—
0.1VDD
C
IOL = 11 mA,
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
0.5
V
V
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 V
DD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus outputs (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
4.6.4
Output pin transition times
Table 18. Output pin transition times
Symbol
Ttr
CC
C
D
T
D
Parameter
Value3
Conditions1,2
Output transition time CL = 25 pF
output pin4
CL = 50 pF
SLOW configuration
CL = 100 pF
D
CL = 25 pF
T
CL = 50 pF
D
CL = 100 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0
VDD = 3.3 V ± 10%,
PAD3V5V = 1
Unit
Min
Typ
Max
—
—
50
—
—
100
—
—
125
—
—
40
—
—
50
—
—
75
ns
MPC5646C Data Sheet, Rev.6
52
Freescale Semiconductor
Electrical Characteristics
Table 18. Output pin transition times (continued)
Symbol
Ttr
CC
C
D
T
D
Ttr
CC
Value3
1,2
Parameter
Conditions
Output transition time CL = 25 pF
output pin(4)
CL = 50 pF
MEDIUM
configuration
CL = 100 pF
D
CL = 25 pF
T
CL = 50 pF
D
CL = 100 pF
D
Output transition time CL = 25 pF
output pin(4)
CL = 50 pF
FAST configuration
CL = 100 pF
CL = 25 pF
CL = 50 pF
Unit
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF
Min
Typ
Max
—
—
10
—
—
20
—
—
40
—
—
12
—
—
25
—
—
40
—
—
4
—
—
6
—
—
12
—
—
4
—
—
7
—
—
12
ns
ns
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 V
DD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3 All values need to be confirmed during device validation.
4 C includes device and package capacitances (C
L
PKG < 5 pF).
4.6.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply is associated to a
VDD/VSS_HV supply pair as described in Table 19.
Table 20 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below
the IAVGSEG maximum value.
In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single
segment should remain below the IDYNSEG maximum value.
Table 19. I/O supplies
Package
I/O Supplies
256 MAPBGA
Equivalent to 208-pin LQFP segment pad distribution + G6, G11, H11, J11
208 LQFP
pin6
(VDD_HV_A)
pin7
(VSS_HV)
pin27
(VDD_HV_A)
pin28
(VSS_HV)
pin73
(VSS_HV)
pin75
(VDD_HV_A)
pin101
(VDD_HV_A)
pin102
(VSS_HV)
pin132
(VSS_HV)
pin133
(VDD_HV_A)
pin147
(VSS_HV)
pin148
(VDD_HV_B)
pin174
(VSS_HV)
pin175
(VDD_HV_A)
—
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
53
Electrical Characteristics
Table 19. I/O supplies (continued)
Package
176 LQFP
I/O Supplies
pin6
(VDD_HV_A)
pin7
(VSS_HV)
pin27
(VDD_HV_A)
pin28
(VSS_HV)
pin57
(VSS_HV)
pin59
(VDD_HV_A)
pin85
(VDD_HV_A)
pin86
(VSS_HV)
pin123
(VSS_HV)
pin124
(VDD_HV_B)
pin150
(VSS_HV)
pin151
(VDD_HV_A)
—
—
Table 20. I/O consumption
Symbol
ISWTSLW,4
ISWTMED(4)
ISWTFST(4)
IRMSSLW
C
CC D Peak I/O current for CL = 25 pF
SLOW configuration
CC D Peak I/O current for
MEDIUM
configuration
CL = 25 pF
CC D Peak I/O current for
FAST configuration
CL = 25 pF
CC D Root mean square
CL = 25 pF, 2 MHz
I/O current for SLOW
CL = 25 pF, 4 MHz
configuration
CL = 100 pF, 2 MHz
CL = 25 pF, 2 MHz
CL = 25 pF, 4 MHz
CC D Root mean square
I/O current for
MEDIUM
configuration
CL = 25 pF, 13 MHz
CL = 25 pF, 40 MHz
Typ
Max
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
19.9
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
15.5
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
28.8
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
16.3
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
113.5
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
52.1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
2.22
—
—
3.13
—
—
6.54
—
—
1.51
—
—
2.14
—
—
4.33
—
—
6.5
—
—
13.32
—
—
18.26
—
—
4.91
—
—
8.47
—
—
10.94
—
—
21.05 mA
—
—
33
—
—
55.77
—
—
14
—
—
20
—
—
34.89
VDD = 3.3 V ± 10%,
PAD3V5V = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CL = 100 pF, 13 MHz
CL = 25 pF, 13 MHz
CL = 25 pF, 40 MHz
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 13 MHz
IRMSFST
CC D Root mean square
CL = 25 pF, 40 MHz VDD = 5.0 V ± 10%,
I/O current for FAST
PAD3V5V = 0
CL = 25 pF, 64 MHz
configuration
CL = 100 pF, 40 MHz
CL = 25 pF, 40 MHz
CL = 25 pF, 64 MHz
Unit
Min
CL = 100 pF, 2 MHz
IRMSMED
Value3
Conditions1,2
Parameter
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 40 MHz
mA
mA
mA
mA
mA
MPC5646C Data Sheet, Rev.6
54
Freescale Semiconductor
Electrical Characteristics
Table 20. I/O consumption (continued)
Symbol
IAVGSEG
C
Parameter
SR D Sum of all the static
I/O current within a
supply segment
Value3
1,2
Conditions
VDD = 5.0 V ± 10%, PAD3V5V = 0
VDD = 3.3 V ± 10%, PAD3V5V = 1
Unit
Min
Typ
Max
—
—
70
—
4
—
65
mA
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2
VDD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3
All values need to be confirmed during device validation.
4 Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
4.7
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
VDD_HV_A
VDDMIN
RESET
VIH
VIL
device reset forced by RESET
device start-up phase
Figure 6. Start-up reset requirements
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
55
Electrical Characteristics
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
Figure 7. Noise filtering on reset signal
Table 21. Reset electrical characteristics
Symbol
C
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
VIH
SR P Input High Level CMOS
(Schmitt Trigger)
—
0.65VDD
—
VDD + 0.4
V
VIL
SR P Input low Level CMOS
(Schmitt Trigger)
—
0.3
—
0.35VDD
V
VHYS
CC C Input hysteresis CMOS
(Schmitt Trigger)
—
0.1VDD
—
—
V
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
V
Push Pull, IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 13
—
—
0.1VDD
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
VOL
CC P Output low level
MPC5646C Data Sheet, Rev.6
56
Freescale Semiconductor
Electrical Characteristics
Table 21. Reset electrical characteristics (continued)
Symbol
C
Value2
1
Parameter
Conditions
Unit
Min
Typ
Max
CL = 25 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
10
CL = 50 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
20
CL = 100 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
40
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
12
CL = 50 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
25
CL = 100 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
40
WFRST SR P Reset input filtered pulse
—
—
—
40
ns
WNFRST SR P Reset input not filtered
pulse
—
1000
—
—
ns
|IWPU| CC P Weak pull-up current
absolute value
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
—
150
µA
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
—
150
10
—
250
Ttr
CC D Output transition time
output pin4
MEDIUM configuration
VDD = 5.0 V ± 10%, PAD3V5V =
15
ns
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 V
DD as mentioned in the table is VDD_HV_A/VDD_HV_B. All values need to be confirmed during device validation.
3 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to the RGM module section
of the device Reference Manual).
4 C includes device and package capacitance (C
L
PKG < 5 pF).
5 The configuration PAD3V5 = 1 when V
=
5
V
is
only transient configuration during power-up. All pads but
DD
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
4.8
4.8.1
Power management electrical characteristics
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from
the high voltage supply VDD_HV_A. The following supplies are involved:
• HV: High voltage external power supply for voltage regulator module. This must be provided
externally through VDD_HV_A power pin.
• LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated
by the on-chip VREG with an external ballast (BCP68 NPN device). It is further split into four
main domains to ensure noise isolation between critical LV modules within the device:
— LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL
through double bonding.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
57
Electrical Characteristics
— LV_CFLA0/CFLA1: Low voltage supply for the two code Flash modules. It is shorted with
LV_COR through double bonding.
— LV_DFLA: Low voltage supply for data Flash module. It is shorted with LV_COR through
double bonding.
— LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
100 nf
VDD_LV
100 nf
VSS_LV VDD_LV
100 nf
VSS_LV VDD_LV
VSS_LV
40 f
(4  10 f)
PD0 (always on domain)
PD0 Logic
PD1 Switchable Domain
(FMPLL, Flash)
(CREGn)
32 KB
Split
56 KB
Split
8 KB
Split
CTRL
CTRL
CTRL
VDD_LV
HPVDD
VSS_LV
Off chip
BCP68
NPN driver
VRC_CTRL
sw1 (<0.1)
HPREG
LPVDD
10 f
LPREG
Chip Boundary
(CDEC2)
VDD_BV
VDD_HV_A
HPVDD
LPVDD
VSS_HV
100 nf
1) All VSS_LV pins must be grounded, as shown for VSS_HV pin.
Figure 8. Voltage regulator capacitance connection
The internal voltage regulator requires external bulk capacitance (CREGn) to be connected to the device to
provide a stable low voltage digital supply to the device. Also required for stability is the CDEC2 capacitor
at ballast collector. This is needed to minimize sharp injection current when ballast is turning ON. Apart
from the bulk capacitance, user should connect EMI/decoupling cap (CREGP) at each VDD_LV/VSS_LV pin
pair.
4.8.1.1
•
•
Recommendations
The external NPN driver must be BCP68 type.
VDD_LV should be implemented as a power plane from the emitter of the ballast transistor.
MPC5646C Data Sheet, Rev.6
58
Freescale Semiconductor
Electrical Characteristics
•
10 F capacitors should be connected to the 4 pins closest to the outside of the package and should
be evenly distributed around the package. For BGA packages, the balls should be used are D8,
H14, R9, J3–one cap on each side of package.
— There should be a track direct from the capacitor to this pin (pin also connects to VDD_LV
plane). The tracks ESR should be less than 100 m.
— The remaining VDD_LV pins (exact number will vary with package) should be decoupled with
0.1 F caps, connected to the pin as per 10 F.
(see Section 4.4, ”Recommended operating conditions”).
4.8.2
•
•
VDD_BV options
Option 1: VDD_BV shared with VDD_HV_A
VDD_BV must be star routed from VDD_HV_A from the common source. This is to eliminate ballast
noise injection on the MCU.
Option 2: VDD_BV independent of the MCU supply
VDD_BV > 2.6 V for correct functionality. The device is not monitoring this supply hence the
external component must meet the 2.6 V criteria through external monitoring if required.
Table 22. Voltage regulator electrical characteristics
Symbol
C
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
CREGn
SR — External ballast stability capacitance
—
40
—
60
F
RREG
SR — Stability capacitor equivalent serial
resistance
—
—
—
0.2

CREGP
SR — Decoupling capacitance (Close to
the pin)
VDD_HV_A/HV_B/VSS_HV
pair
100
—
nF
VDD_LV/VSS_LV pair
100
—
nF
CDEC2
SR — Stability capacitance regulator
VDD_BV/VSS_HV
supply (Close to the ballast collector)
10
—
40
F
VMREG
CC P Main regulator output voltage
—
1.32
—
V
1.20
1.28
—
—
—
350
mA
IMREG = 200 mA
—
—
2
mA
IMREG = 0 mA
—
—
1
1.21
1.27
—
V
—
—
50
mA
Before trimming
After trimming
TA = 25 °C
IMREG
IMREGINT
SR — Main regulator current provided to
VDD_LV domain
CC D Main regulator module current
consumption
—
VLPREG
CC P Low power regulator output voltage After trimming
TA = 25 °C
ILPREG
SR — Low power regulator current
provided to VDD_LV domain
—
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
59
Electrical Characteristics
Table 22. Voltage regulator electrical characteristics (continued)
Symbol
ILPREGINT
C
Parameter
IVREDLVD12
Unit
Min
Typ
Max
—
—
600
ILPREG = 0 mA;
TA = 55 °C
—
20
—
CC D Main LVDs and reference current
consumption (low power and main
regulator switched off)
TA = 55 °C
—
2
—
A
CC D Main LVD current consumption
(switch-off during standby)
TA = 55 °C
—
1
—
A
—
—
6003
mA
—
IDD_HV_A
Conditions
CC D Low power regulator module current ILPREG = 15 mA;
consumption
TA = 55 °C
IVREGREF
Value2
1
CC D In-rush current on VDD_BV during
power-up
—
A
NOTES:
1 V
DD_HV_A = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 All values need to be confirmed during device validation.
3 Inrush current is seen more like steps of 600 mA peak. The startup of the regulator happens in steps of 50 mV in
~25 steps to reach ~1.2 V VDD_LV. Each step peak current is within 600 mA
4.8.3
Voltage monitor electrical characteristics
The device implements a Power-on Reset module to ensure correct power-up initialization, as well as four
low voltage detectors to monitor the VDD_HV_A and the VDD_LV voltage while device is supplied:
• POR monitors VDD_HV_A during the power-up phase to ensure device is maintained in a safe reset
state
• LVDHV3 monitors VDD_HV_A to ensure device is reset below minimum functional supply
• LVDHV5 monitors VDD_HV_A when application uses device in the 5.0 V±10% range
• LVDLVCOR monitors power domain No. 1 (PD1)
• LVDLVBKP monitors power domain No. 0 (PD0). VDD_LV is same as PD0 supply.
NOTE
When enabled, PD2 (RAM retention) is monitored through LVD_DIGBKP.
MPC5646C Data Sheet, Rev.6
60
Freescale Semiconductor
Electrical Characteristics
VDDHV/LV
VLVDHVxH/LVxH
VLVDHVxL/LVxL
RESET
Figure 9. Low voltage monitor vs. Reset
Table 23. Low voltage monitor electrical characteristics
Symbol
C
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
VPORUP
SR P Supply for functional POR module
—
1.0
—
5.5
VPORH
CC P Power-on reset threshold
—
1.5
—
2.6
VLVDHV3H
CC T LVDHV3 low voltage detector high threshold
—
2.7
—
2.85
VLVDHV3L
CC T LVDHV3 low voltage detector low threshold
—
2.6
—
2.74
VLVDHV5H
CC T LVDHV5 low voltage detector high threshold
—
4.3
—
4.5
VLVDHV5L
CC T LVDHV5 low voltage detector low threshold
—
4.2
—
4.4
1.12
1.145
1.17
1.12
1.145
1.17
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
TA = 25 °C,
after trimming
V
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2
All values need to be confirmed during device validation.
4.9
Low voltage domain power consumption
Table 24 provides DC electrical characteristics for significant application modes. These values are
indicative values; actual consumption depends on the application.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
61
Electrical Characteristics
Table 24. Low voltage power domain electrical characteristics1
Symbol
C
IDDMAX5
CC D RUN mode maximum
average current
IDDRUN
CC P RUN mode typical average
current8
D
at 120 MHz
TA = 25 °C
Typ3
Max4
—
210
3006,7
mA
—
150
2009
mA
8
10
mA
TA = 25 °C
—
110
at 120 MHz
TA = 125 °C
—
180
270
mA
at 120 MHz
TA = 25 °C
—
20
27
mA
at 120 MHz
TA = 125 °C
—
35
113
mA
—
0.4
3
mA
—
16
95
mA
—
50
99
µA
—
630
3200
µA
—
40
94
µA
—
500
2500
µA
—
25
87
µA
TA = 125 °C
—
230
1250
µA
—
TA = 25 °C
—
—
5
µA
—
TA = 25 °C
—
—
3
mA
16 MHz IRC
—
TA = 25 °C
—
—
500
µA
128 KHz IRC
—
TA = 25 °C
—
—
5
µA
CC P HALT mode current
11
C
IDDSTOP
—
Unit
Min
at 80 MHz
C
IDDHALT
Value
Conditions2
Parameter
CC P STOP mode current
12
No clocks active TA = 25 °C
TA = 125 °C
C
IDDSTDBY3 CC P STANDBY3 mode
(96 KB RAM
current13
C
retained)
No clocks active TA = 25 °C
IDDSTDBY2 CC C STANDBY2 mode
(64 KB RAM
current14
C
retained)
No clocks active TA = 25 °C
IDDSTDBY1 CC C STANDBY1 mode
(8 KB RAM
current15
C
retained)
No clocks active TA = 25 °C
Adders in LP CC T 32 KHz OSC
mode
4–40 MHz OSC
TA = 125 °C
TA = 125 °C
150
NOTES:
1 Except for I
DDMAX, all the current values are total current drawn from VDD_HV_A.
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All temperatures are based on an
ambient temperature.
3
Target typical current consumption for the following typical operating conditions and configuration. Process = typical,
Voltage = 1.2 V.
4 Target maximum current consumption for mode observed under typical operating conditions. Process = Fast, Voltage
= 1.32 V.
5 Running consumption is given on voltage regulator supply (V
DDREG). It does not include consumption linked to I/Os
toggling. This value is highly dependent on the application. The given value is thought to be a worst case value with
all cores and peripherals running, and code fetched from code flash while modify operation on-going on data flash. It
is to be noticed that this value can be significantly reduced by application: switch-off not used peripherals (default),
reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode
when possible.
6
Higher current may sunk by device during power-up and standby exit. Please refer to in rush current in Table 22.
7
Maximum “allowed” current is package dependent.
8 Only for the “P” classification: Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPI as Master,
PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic
SW/WDG timer reset enabled. RUN current measured with typical application with accesses on both code flash and
RAM.
MPC5646C Data Sheet, Rev.6
62
Freescale Semiconductor
Electrical Characteristics
9
Subject to change, Configuration: 1  e200z4d + 4 kbit/s Cache, 1  e200z0h (1/2 system frequency), CSE,
1  eDMA (10 ch.), 6  FlexCAN (4  500 kbit/s, 2  125 kbit/s), 4  LINFlexD (20 kbit/s), 6  DSPI (2  2 Mbit/s,
3  4 Mbit/s, 1  10 Mbit/s), 16  Timed I/O, 16  ADC Input, 1  FlexRay (2 ch., 10 Mbit/s), 1  FEC (100 Mbit/s),
1  RTC, 4 PIT channels, 1  SWT, 1  STM. For lower pin count packages reduce the amount of timed I/O’s and ADC
channels. RUN current measured with typical application with accesses on both code flash and RAM.
10
This value is obtained from limited sample set.
11 Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz ON. 16 MHz XTAL clock.
FlexCAN: instances: 0, 1, 2 ON (clocked but no reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex:
instances: 0, 1, 2 ON (clocked but no reception or transmission), instance: 3-9 clocks gated. eMIOS: instance: 0 ON
(16 channels on PA[0]-PA[11] and PC[12]-PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0
(clocked but no communication, instance: 1-7 clocks gated). RTC/API ON. PIT ON. STM ON. ADC ON but no
conversion except 2 analog watchdogs.
12
Only for the “P” classification: No clock, FIRC 16 MHz OFF, SIRC128 kHz ON, PLL OFF, HPvreg OFF, LPVreg ON.
All possible peripherals off and clock gated. Flash in power down mode.
13
Only for the “P” classification: LPreg ON, HPVreg OFF, 96 KB RAM ON, device configured for minimum consumption,
all possible modules switched-off.
14 Only for the “P” classification: LPreg ON, HPVreg OFF, 64 KB RAM ON, device configured for minimum consumption,
all possible modules switched-off.
15 LPreg ON, HPVreg OFF, 8 KB RAM ON, device configured for minimum consumption, all possible modules switched
OFF.
4.10
Flash memory electrical characteristics
4.10.1
Program/Erase characteristics
Table 25 shows the code flash memory program and erase characteristics.
Table 25. Code flash memory—Program and erase specifications
Value
Symbol
C
Tdwprogram
T16Kpperase
C
T32Kpperase
T128Kpperase
Teslat
Parameter
Unit
Min
Typ1
Initial
max2
Max3
Double word (64 bits) program time4
—
18
50
500
µs
16 KB block pre-program and erase time
—
200
500
5000
ms
32 KB block pre-program and erase time
—
300
600
5000
ms
128 KB block pre-program and erase time
—
600
1300
5000
ms
—
—
30
30
µs
CC D Erase Suspend Latency
tESRT5
C Erase Suspend Request Rate
20
—
—
—
ms
tPABT
D Program Abort Latency
—
—
10
10
µs
tEAPT
D Erase Abort Latency
—
—
30
30
µs
NOTES:
1 Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3
The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4
Actual hardware programming times. This does not include software overhead.
5
It is Time between erase suspend resume and the next erase suspend request.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
63
Electrical Characteristics
Table 26 shows the data flash memory program and erase characteristics.
Table 26. Data flash memory—Program and erase specifications
Value
Symbol
C
Parameter
Unit
Min
Typ1
Initial
max2
Max3
Word (32 bits) program time4
—
30
70
500
µs
16 KB block pre-program and erase time
—
700
800
5000
ms
D Erase Suspend Latency
—
—
30
30
µs
C Erase Suspend Request Rate
10
—
—
—
ms
tPABT
D Program Abort Latency
—
—
12
12
µs
tEAPT
D Erase Abort Latency
—
—
30
30
µs
Twprogram
C
T16Kpperase
Teslat
CC
tESRT5
NOTES:
1 Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4
Actual hardware programming times. This does not include software overhead.
5
It is time between erase suspend resume and next erase suspend.
Table 27. Flash memory module life
Value
Symbol
C
Parameter
Conditions
Unit
Min
P/E
CC
Retention CC
Typ
C Number of program/erase cycles per
block for 16 Kbyte blocks over the
operating temperature range (TJ)
—
100,000
100,000 cycles
Number of program/erase cycles per
block for 32 Kbyte blocks over the
operating temperature range (TJ)
—
10,000
100,000 cycles
Number of program/erase cycles per
block for 128 Kbyte blocks over the
operating temperature range (TJ)
—
1,000
100,000 cycles
Blocks with 0–1,000 P/E
cycles
20
—
years
Blocks with 10,000 P/E
cycles
10
—
years
Blocks with 100,000 P/E
cycles
5
—
years
C Minimum data retention at 85 °C
average ambient temperature1
NOTES:
1 Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
MPC5646C Data Sheet, Rev.6
64
Freescale Semiconductor
Electrical Characteristics
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability
results. Some units will experience single bit corrections throughout the life of the product with no impact
to product reliability.
Table 28. Flash memory read access timing1
Conditions2
Symbol
CC
fREAD
C
Parameter
Code flash
memory
Data flash
memory
Frequency
range
P Maximum frequency for Flash reading 5 wait states
13 wait states
120 —100
C
4 wait states
11 wait states
100—80
D
3 wait states
9 wait states
80—64
C
2 wait states
7 wait states
64—40
C
1 wait states
4 wait states
40—20
C
0 wait states
2 wait states
20—0
Unit
MHz
NOTES:
1 Max speed is the maximum speed allowed including PLL frequency modulation (FM).
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
4.10.2
Flash memory power supply DC characteristics
Table 29 shows the flash memory power supply DC characteristics on external supply.
Table 29. Flash memory power supply DC electrical characteristics
Symbol
Value2
Conditions1
Parameter
Unit
Min
Typ
Max
ICFREAD3 CC Sum of the current consumption Flash memory module read Code flash
on VDD_HV_A on read access
fCPU = 120 MHz  2%4
memory
33
IDFREAD(3)
Data flash
memory
13
ICFMOD(3) CC Sum of the current consumption Program/Erase on-going
Code flash
while reading flash memory memory
on VDD_HV_A (program/erase)
registers
IDFMOD(3)
Data flash
fCPU = 120 MHz  2% (4)
memory
52
ICFLPW(3) CC Sum of the current consumption
on VDD_HV_A during flash
memory low power mode
Code flash
memory
1.1
mA
ICFPWD(3) CC Sum of the current consumption
on VDD_HV_A during flash
memory power down mode
IDFPWD(3)
Code flash
memory
150
µA
Data flash
memory
150
mA
mA
13
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified.
2
All values need to be confirmed during device validation.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
65
Electrical Characteristics
3
4
Data based on characterization results, not tested in production.
fCPU 120 MHz  2% can be achieved over full temperature 125 °C ambient, 150 °C junction temperature.
4.10.3
Flash memory start-up/switch-off timings
Table 30. Start-up time/Switch-off time
Symbol
TFLARSTEXIT
C
CC D Delay for flash memory module to exit
reset mode
Code flash
memory
—
Data flash
memory
TFLALPEXIT
CC T Delay for flash memory module to exit
low-power mode
Code flash
memory
—
TFLAPDEXIT
CC T Delay for flash memory module to exit
power-down mode
Code flash
memory
—
Code flash
memory
Unit
Min
Typ
Max
—
—
125
—
—
—
—
0.5
µs
Data flash
memory
TFLALPENTRY CC T Delay for flash memory module to enter
low-power mode
Value
Conditions1
Parameter
—
—
—
—
—
—
—
30
0.5
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
4.11
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.11.1
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application
environment and simplified MCU software. It should be noted that good EMC performance is highly
dependent on the user application and the software in particular.
Therefore it is recommended that the user apply EMC software optimization and pre-qualification tests in
relation with the EMC level requested for the application.
• Software recommendations The software flowchart must include the management of runaway
conditions such as:
— Corrupted program counter
— Unexpected reset
— Critical data corruption (control registers)
• Pre-qualification trials Most of the common failures (unexpected reset and program counter
corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins
for 1 second.
MPC5646C Data Sheet, Rev.6
66
Freescale Semiconductor
Electrical Characteristics
To complete these trials, ESD stress can be applied directly on the device. When unexpected
behavior is detected, the software can be hardened to prevent unrecoverable errors occurring.
4.11.2
Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms
to the IEC61967-1 standard, which specifies the general conditions for EMI measurements.
Table 31. EMI radiated emission measurement1,2
Value
Symbol
C
Parameter
Conditions
Unit
Min
—
SR — Scan range
Typ
Max
—
0.150
fCPU SR — Operating frequency
—
—
120
—
MHz
VDD_LV SR — LV operating voltages
—
—
1.28
—
V
No PLL frequency
VDD = 5 V, TA = 25 °C,
modulation
LQFP176 package
Test conforming to IEC 61967-2,
± 2% PLL frequency
fOSC = 40 MHz/fCPU = 120 MHz
modulation
—
—
18
dBµV
—
—
143 dBµV
SEMI CC T Peak level
1000 MHz
NOTES:
1 EMI testing and I/O port waveforms per IEC 61967-1, -2, -4.
2 For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your
local marketing representative.
3 All values need to be confirmed during device validation.
4.11.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed
in order to determine its performance in terms of electrical sensitivity.
4.11.3.1
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of
each sample according to each pin combination. The sample size depends on the number of supply pins in
the device (3 parts  (n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard.
Table 32. ESD absolute maximum ratings1,2
Conditions
Class
Max value3
Unit
VESD(HBM) Electrostatic discharge voltage
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C
2000
V
VESD(MM) Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
VESD(CDM) Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
Symbol
Ratings
750 (corners)
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
67
Electrical Characteristics
NOTES:
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
3 Data based on characterization results, not tested in production.
4.11.3.2
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
• A supply over-voltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 33. Latch-up results
Symbol
LU
4.12
Parameter
Static latch-up class
Conditions
TA = 125 °C
conforming to JESD 78
Class
II level A
Fast external crystal oscillator (4–40 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 10 describes a simple model of the internal
oscillator driver and provides an example of a connection for an oscillator or a resonator.
Table 34 provides the parameter description of 4 MHz to 40 MHz crystals used for the design simulations.
MPC5646C Data Sheet, Rev.6
68
Freescale Semiconductor
Electrical Characteristics
EXTAL
C1
Crystal
XTAL
XTAL
RD
C2
DEVICE
VDD
I
R
EXTAL
EXTAL
Resonator
DEVICE
XTAL
DEVICE
Figure 10. Crystal oscillator and resonator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
Table 34. Crystal description
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
xtalin/xtalout
C1 = C2
(pF)1
Shunt
capacitance
between
xtalout
and xtalin
C02 (pF)
Nominal
frequency
(MHz)
NDK crystal
reference
Crystal
equivalent
series
resistance
ESR 
4
NX8045GB
300
2.68
591.0
21
2.93
300
2.46
160.7
17
3.01
150
2.93
86.6
15
2.91
12
120
3.11
56.5
15
2.93
16
120
3.90
25.3
10
3.00
50
6.18
2.56
8
3.49
8
10
40
NX5032GA
NX5032GA
NOTES:
1
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing
includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2 The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,
package, etc.).
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
69
Electrical Characteristics
S_MTRANS bit (ME_GS register)
1
0
VXTAL
1/fMXOSC
VFXOSC
90%
VFXOSCOP
10%
TMXOSCSU
valid internal clock
Figure 11. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics
Table 35. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics
Symbol
fFXOSC
gmFXOSC
VFXOSC
VFXOSCOP
IFXOSC,4
TFXOSCSU
C
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
4.0
—
40.0
MHz
CC C Fast external crystal VDD = 3.3 V ± 10%
oscillator
VDD = 5.0 V ± 10%
transconductance
43
—
203
mA/V
43
—
203
CC T Oscillation
fOSC = 40 MHz
amplitude at EXTAL For both VDD = 3.3 V ±
10%, VDD = 5.0 V ±
10%
—
0.95
—
CC P Oscillation
operating point
—
1.8
CC T Fast external crystal VDD = 3.3 V ± 10%,
oscillator
fOSC = 40 MHz
consumption
VDD = 5.0 V ± 10%,
fOSC = 40 MHz
—
2
2.2
—
2.3
2.5
VDD = 3.3 V ± 10%,
fOSC = 16 MHz
—
1.3
1.5
VDD = 5.0 V ± 10%,
fOSC = 16 MHz
—
1.6
1.8
—
—
5
SR — Fast external crystal
oscillator frequency
—
—
CC T Fast external crystal fOSC = 40 MHz
oscillator start-up
For both VDD = 3.3 V ±
time
10%, VDD = 5.0 V ±
10%
V
V
mA
ms
MPC5646C Data Sheet, Rev.6
70
Freescale Semiconductor
Electrical Characteristics
Table 35. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics
Symbol
C
Parameter
Conditions
Value2
1
Unit
Min
Typ
Max
VIH
SR P Input high level
CMOS
(Schmitt Trigger)
Oscillator bypass
mode
0.65VDD_HV_A
—
VDD_HV_A + 0.4
V
VIL
SR P Input low level
CMOS
(Schmitt Trigger)
Oscillator bypass
mode
0.3
—
0.35VDD_HV_A
V
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2
All values need to be confirmed during device validation.
3
Based on ATE Cz
4 Stated values take into account only analog module consumption but not the digital contributor (clock tree and
enabled peripherals).
4.13
Slow external crystal oscillator (32 kHz) electrical characteristics
The device provides a low power oscillator/resonator driver.
OSC32K_EXTAL
OSC32K_EXTAL
Resonator
Crystal
C1
RP
OSC32K_XTAL
DEVICE
OSC32K_XTAL
C2
DEVICE
Figure 12. Crystal oscillator and resonator connection scheme
NOTE
OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive
external circuits.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
71
Electrical Characteristics
l
C0
C1
Crystal
Cm
C2
Rm
Lm
C1
C2
Figure 13. Equivalent circuit of a quartz crystal
Table 36. Crystal motional characteristics1
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
Lm
Motional inductance
—
—
11.796
—
KH
Cm
Motional capacitance
—
—
2
—
fF
—
18
—
28
pF
AC coupled @ C0 = 2.85 pF4
—
—
65
k
AC coupled @ C0 = 4.9
pF(4)
—
—
50
AC coupled @ C0 = 7.0
pF(4)
—
—
35
AC coupled @ C0 = 9.0 pF(4)
—
—
30
C1/C2 Load capacitance at OSC32K_XTAL and
OSC32K_EXTAL with respect to ground2
Rm3
Motional resistance
NOTES:
1 The crystal used is Epson Toyocom MC306.
2
This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to
ground. It includes all the parasitics due to board traces, crystal and package.
3 Maximum ESR (R ) of the crystal is 50 k
m
4
C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins.
MPC5646C Data Sheet, Rev.6
72
Freescale Semiconductor
Electrical Characteristics
OSCON bit (OSC_CTL register)
1
0
VOSC32K_XTAL
1/fLPXOSC32K
VLPXOSC32K
90%
10%
TLPXOSC32KSU
valid internal clock
Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics
Table 37. Slow external crystal oscillator (32 kHz) electrical characteristics
Symbol
C
Parameter
fSXOSC
SR — Slow external crystal oscillator
frequency
gmSXOSC
CC — Slow external crystal oscillator
transconductance
VSXOSC
Value2
Conditions1
Unit
Min
Typ
Max
32
32.768
40
kHz
VDD = 3.3 V ± 10%,
133
—
333
µA/V
VDD = 5.0 V ± 10%
153
—
353
—
1.2
1.4
1.7
V
—
1.2
—
4.4
µA
—
CC T Oscillation amplitude
ISXOSCBIAS CC T Oscillation bias current
ISXOSC
CC T Slow external crystal oscillator
consumption
—
—
—
7
µA
TSXOSCSU
CC T Slow external crystal oscillator
start-up time
—
—
—
24
s
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 All values need to be confirmed during device validation.
3
Based on ATE CZ
4 Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.
4.14
FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system
clock from the main oscillator driver.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
73
Electrical Characteristics
Table 38. FMPLL electrical characteristics
Symbol
C
Value2
Conditions1
Parameter
Unit
Min
Typ
Max
fPLLIN
SR — FMPLL reference clock3
—
4
—
64
MHz
PLLIN
SR — FMPLL reference clock duty
cycle(3)
—
40
—
60
%
—
16
—
120
MHz
fPLLOUT CC P FMPLL output clock
frequency
fCPU
SR — System clock frequency
—
—
—
120 + 2%4
MHz
fFREE
CC P Free-running frequency
—
20
—
150
MHz
tLOCK
CC P FMPLL lock time
40
100
µs
Stable oscillator (fPLLIN = 16
MHz)
tLTJIT CC — FMPLL long term jitter
IPLL
CC C FMPLL consumption
fPLLIN = 40 MHz (resonator),
fPLLCLK @ 120 MHz, 4000
cycles
—
—
6
(for < 1ppm)
ns
TA = 25 °C
—
—
3
mA
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2
All values need to be confirmed during device validation.
3 PLLIN clock retrieved directly from 4-40 MHz XOSC or 16 MIRC. Input characteristics are granted when oscillator
is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN.
4
fCPU 120 + 2% MHz can be achieved at 125 °C.
4.15
Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz main internal RC oscillator. This is used as the default clock at the power-up
of the device and can also be used as input to PLL.
Table 39. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol
C
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
16
—
CC P Fast internal RC oscillator high
frequency
SR —
TA = 25 °C, trimmed
—
—
12
IFIRCRUN3, CC T Fast internal RC oscillator high
frequency current in running
mode
TA = 25 °C, trimmed
—
—
200
µA
TA = 25 °C
—
—
100
nA
TA = 55 °C
—
—
200
nA
TA = 125 °C
—
—
1
µA
fFIRC
IFIRCPWD
CC D Fast internal RC oscillator high
frequency current in power
D
down mode
D
MHz
20
MPC5646C Data Sheet, Rev.6
74
Freescale Semiconductor
Electrical Characteristics
Table 39. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
sysclk = off
—
500
—
sysclk = 2 MHz
—
600
—
sysclk = 4 MHz
—
700
—
sysclk = 8 MHz
—
900
—
sysclk = 16 MHz
—
1250
—
VDD = 5.0 V ± 10%
—
—
2.0
VDD = 3.3 V ± 10%
—
—
5
—
TA = 125 °C VDD = 5.0 V ± 10%
—
—
2.0
—
VDD = 3.3 V ± 10%
—
—
5
+1
IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 °C
frequency and system clock
current in stop mode
TFIRCSU
Value2
1
CC C Fast internal RC oscillator
start-up time
—
TA = 55 °C
CC C Fast internal RC oscillator
precision after software
trimming of fFIRC
TA = 25 °C
1
—
FIRCTRIM CC C Fast internal RC oscillator
trimming step
TA = 25 °C
—
1.6
—
5
—
FIRCPRE
FIRCVAR
CC C Fast internal RC oscillator
variation over temperature and
supply with respect to fFIRC at
TA = 25 °C in high-frequency
configuration
µA
µs
%
%
+5
%
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 All values need to be confirmed during device validation.
3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
4.16
Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz low power internal RC oscillator. This can be used as the reference clock
for the RTC module.
Table 40. Slow internal RC oscillator (128 kHz) electrical characteristics
Symbol
fSIRC
ISIRC3,
C
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
CC P Slow internal RC oscillator low
frequency
SR —
TA = 25 °C, trimmed
—
128
—
untrimmed, across
temperatures
84
—
205
CC C Slow internal RC oscillator low
frequency current
TA = 25 °C, trimmed
—
—
5
kHz
µA
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
75
Electrical Characteristics
Table 40. Slow internal RC oscillator (128 kHz) electrical characteristics (continued)
Symbol
C
Parameter
Value2
1
Conditions
Unit
Min
Typ
Max
TSIRCSU
CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ± 10%
time
—
8
12
µs
SIRCPRE
CC C Slow internal RC oscillator precision
after software trimming of fSIRC
TA = 25 °C
2
—
+2
%
SIRCTRIM
CC C Slow internal RC oscillator trimming
step
—
—
2.7
—
SIRCVAR
CC C Variation in fSIRC across
temperature and fluctuation in
supply voltage, post trimming
—
10
—
+10
%
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 All values need to be confirmed during device validation.
3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
4.17
4.17.1
ADC electrical characteristics
Introduction
The device provides two Successive Approximation Register (SAR) analog-to-digital converters (10-bit
and 12-bit).
NOTE
Due to ADC limitations, the two ADCs cannot sample a shared channel at
the same time i.e., their sampling windows cannot overlap if a shared
channel is selected. If this is done, neither of the ADCs can guarantee their
conversion accuracies.
MPC5646C Data Sheet, Rev.6
76
Freescale Semiconductor
Electrical Characteristics
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
5
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error OSE
Figure 15. ADC_0 characteristic and error definitions
4.17.1.1
Input impedance and ADC accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC
impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device, can
be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to
attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase,
when the analog signal source is a high-impedance source. A real filter, can typically be obtained by using
a series resistance with a capacitor on the input pin (simple RC Filter). The RC filtering may be limited
according to the value of source impedance of the transducer or circuit supplying the analog signal to be
measured. The filter at the input pins must be designed taking into account the dynamic characteristics of
the input signal (bandwidth) and the equivalent input impedance of the ADC itself.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
77
Electrical Characteristics
In fact a current sink contributor is represented by the charge sharing effects with the sampling
capacitance: being CS and Cp2 substantially two switched capacitances, with a frequency equal to the
conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a
conversion rate of 1MHz, with CS+Cp2 equal to 3pF, a resistance of 330K is obtained (Reqiv = 1 /
(fc*(CS+Cp2)), where fc represents the conversion rate at the considered channel). To minimize the error
induced by the voltage partitioning between this resistance (sampled voltage on CS+Cp2) and the sum of
RS + RF, the external circuit must be designed to respect the following relation
Eqn. 4
RS + RF
V A  ---------------------  1
--- LSB
R EQ
2
The formula above provides a constraint for external network design, in particular on resistive path.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
VA
Filter
RF
Current Limiter
RL
CF
RS
RF
CF
RL
RSW
RAD
CP
CS
CP1
Channel
Selection
Sampling
RSW
RAD
CP2
CS
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
Pin Capacitance (two contributions, CP1 and CP2)
Sampling Capacitance
Figure 16. Input equivalent circuit (precise channels)
MPC5646C Data Sheet, Rev.6
78
Freescale Semiconductor
Electrical Characteristics
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
Filter
RS
Current Limiter
RF
RS
RF
CF
RL
RSW
RAD
CP
CS
Extended
Switch
Sampling
RSW1
RSW2
RAD
RL
CF
VA
Channel
Selection
CP1
CP3
CP2
CS
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance (two contributions RSW1 and RSW2)
Sampling Switch Impedance
Pin Capacitance (three contributions, CP1, CP2 and CP3)
Sampling Capacitance
Figure 17. Input equivalent circuit (extended channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances
CF, CP1 and CP2 initially charged at the source voltage VA (refer to the equivalent circuit reported in
Figure 16): when the sampling phase is started (A/D switch close), a charge sharing phenomena is
installed.
Voltage Transient on CS
VCS
VA
V <0.5 LSB
VA2
1
2
1 < (RSW + RAD) CS << TS
2 = RL (CS + CP1 + CP2)
VA1
TS
t
Figure 18. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
• A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling
capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case
(since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call
CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is
CP  CS
 1 =  R SW + R AD   --------------------CP + CS
Eqn. 5
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
79
Electrical Characteristics
This relation can again be simplified considering CS as an additional worst condition. In reality, transient
is faster, but the A/D converter circuitry has been designed to be robust also in very worst case: the
sampling time Ts is always much longer than the internal time constant.
Eqn. 6
 1   R SW + R AD   C S « T S
The charge of CP1 and CP2 is redistributed on CS,determining a new value of the voltage VA1 on the
capacitance according to the following equation
Eqn. 7
V A1   C S + C P1 + C P2  = V A   C P1 + C P2 
•
A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance)
through the resistance RL: again considering the worst case in which CP2 and CS were in parallel
to CP1 (since the time constant in reality would be faster), the time constant is:
Eqn. 8
 2  R L   C S + C P1 + C P2 
In this case, the time constant depends on the external circuit: in particular imposing that the transient is
completed well before the end of sampling time TS, a constraints on RL sizing is obtained:
Eqn. 9
8.5   = 8.5  R   C + C
2
L
S
P1 + C P2   TS
Of course, RL shall be sized also according to the current limitation constraints, in combination with RS
(source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the
final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. The following
equation must be respected (charge balance assuming now CS already charged at VA1):
Eqn. 10
VA2   C S + C P1 + C P2 + C F  = V A  C F + V A1   C P1 + C P2 + C S 
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF
filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal
source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The
filter is typically designed to act as anti-aliasing
MPC5646C Data Sheet, Rev.6
80
Freescale Semiconductor
Electrical Characteristics
Analog Source Bandwidth (VA)
TC 2 RFCF (Conversion Rate vs. Filter Pole)
fF  f0 (Anti-aliasing Filtering Condition)
Noise
2 f0 fC (Nyquist)
f0
f
Anti-Aliasing Filter (fF = RC Filter pole)
fF
Sampled Signal Spectrum (fC = conversion Rate)
f0
f
fC
f
Figure 19. Spectral representation of input signal
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the
anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at least 2f0; it
means that the constant time of the filter is greater than or at least equal to twice the conversion period
(TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it,
even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific
channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher
than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during
the time in which the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy
error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive
Equation 11 between the ideal and real sampled voltage on CS:
Eqn. 11
V A2
C P1 + C P2 + C F
------------ = ------------------------------------------------------VA
C P1 + C P2 + C F + C S
From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept
a maximum error of half a count, a constraint is evident on CF value:
ADC_0 (10-bit)
Eqn. 12
C F  2048  C S
ADC_1 (12-bit)
Eqn. 13
C F  8192  C S
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
81
Electrical Characteristics
4.17.1.2
ADC electrical characteristics
Table 41. ADC input leakage current
Value
Symbol C
Parameter
Conditions
Unit
Min
Typ
Max
ILKG CC C Input leakage current TA = 40 °C No current injection on adjacent pin
—
1
—
C
TA = 25 °C
—
1
—
C
TA = 105 °C
—
8
200
P
TA = 125 °C
—
45
400
nA
Table 42. ADC conversion characteristics (10-bit ADC_0)
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
VSS_ADC0 SR — Voltage on
VSS_HV_ADC0
(ADC_0 reference)
pin with respect to
ground (VSS_HV)2
—
0.1
—
0.1
V
VDD_ADC0 SR — Voltage on
VDD_HV_ADC0 pin
(ADC_0 reference)
with respect to
ground (VSS_HV)
—
VDD_HV_A  0.1
—
VDD_HV_A + 0.1
V
VAINx
SR — Analog input voltage3
—
VSS_ADC0  0.1
—
VDD_ADC0 + 0.1
V
fADC0
SR — ADC_0 analog
frequency
—
6
—
32 + 2%
MHz
—
—
—
1.5
µs
fADC = 32 MHz
500
—
ns
fADC = 32 MHz
0.625
—
µs
fADC = 30 MHz
0.700
—
tADC0_PU SR — ADC_0 power up
delay
tADC0_S CC T Sample time4
tADC0_C CC P Conversion
time5,6
CS
CC D ADC_0 input
sampling
capacitance
—
—
—
3
pF
CP1
CC D ADC_0 input pin
capacitance 1
—
—
—
3
pF
CP2
CC D ADC_0 input pin
capacitance 2
—
—
—
1
pF
CP3
CC D ADC_0 input pin
capacitance 3
—
—
—
1
pF
CC D Internal resistance of
analog source
—
—
—
3
k
RSW1
MPC5646C Data Sheet, Rev.6
82
Freescale Semiconductor
Electrical Characteristics
Table 42. ADC conversion characteristics (10-bit ADC_0) (continued)
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
RSW2
CC D Internal resistance of
analog source
—
—
—
2
k
RAD
CC D Internal resistance of
analog source
—
—
—
2
k
IINJ7
SR — Input current Injection Current
injection on
one ADC_0
input, different
from the
converted one
VDD =
3.3 V ± 10%
5
—
5
mA
VDD =
5.0 V ± 10%
5
—
5
| INL |
CC T Absolute value for
No overload
integral non-linearity
—
0.5
1.5
LSB
| DNL |
CC T Absolute differential No overload
non-linearity
—
0.5
1.0
LSB
| OFS |
CC T Absolute offset error
—
—
0.5
—
LSB
| GNE |
CC T Absolute gain error
—
—
0.6
—
LSB
TUEP
CC P Total unadjusted
Without current injection
error8 for precise
T
With current injection
channels, input only
pins
2
0.6
2
LSB
CC T Total unadjusted
Without current injection
error(8) for extended
T
With current injection
channel
3
TUEX
3
4
3
1
3
LSB
4
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 Analog and digital V
SS_HV must be common (to be tied together externally).
3 V
AINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
4 During the sample time the input capacitance C can be charged/discharged by the external source. The internal
S
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the
end of the sample time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC0_S depend on programming.
5 This parameter does not include the sample time t
ADC0_S, but only the time for determining the digital result and
the time to load the result's register with the conversion result
6 Refer to ADC conversion table for detailed calculations.
7
PB10 should not have any current injected. It can disturb accuracy on other ADC_0 pins.
8 Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
83
Electrical Characteristics
Offset Error OSE
Gain Error GE
4095
4094
4093
4092
4091
1 LSB ideal = AVDD / 4096
4090
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
5
(5)
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)
Offset Error OSE
Figure 20. ADC_1 characteristic and error definitions
MPC5646C Data Sheet, Rev.6
84
Freescale Semiconductor
Electrical Characteristics
Table 43. Conversion characteristics (12-bit ADC_1)
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
VSS_ADC1
SR
—
Voltage on
VSS_HV_ADC1
(ADC_1 reference)
pin with respect to
ground (VSS_HV)2
—
0.1
0.1
V
VDD_ADC13
SR
—
Voltage on
VDD_HV_ADC1
pin (ADC_1
reference) with
respect to ground
(VSS_HV)
—
VDD_HV_A  0.1
VDD_HV_A + 0.1
V
VAINx3,4
SR
—
Analog input
voltage5
—
VSS_ADC1  0.1
VDD_ADC1 + 0.1
V
fADC1
SR
—
ADC_1 analog
frequency
—
8 + 2%
32 + 2%
MHz
tADC1_PU
SR
—
ADC_1 power up
delay
—
tADC1_S
CC
T
Sample time6
VDD=5.0 V
—
440
Sample time(6)
VDD=3.3 V
—
530
Conversion time7, 8
VDD=5.0 V
fADC1 = 32 MHz
2
Conversion time(7),
fADC 1= 30 MHz
2.1
tADC1_C
CC
P
(6)
1.5
µs
ns
µs
VDD =5.0 V
Conversion time(7),
(6)
fADC 1= 20 MHz
3
fADC1 = 15 MHz
3.01
VDD=3.3 V
Conversion time(7),
(6)
VDD =3.3 V
CS
CC
D
ADC_1 input
sampling
capacitance
—
5
pF
CP1
CC
D
ADC_1 input pin
capacitance 1
—
3
pF
CP2
CC
D
ADC_1 input pin
capacitance 2
—
1
pF
CP3
CC
D
ADC_1 input pin
capacitance 3
—
1.5
pF
RSW1
CC
D
Internal resistance
of analog source
—
1
k
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
85
Electrical Characteristics
Table 43. Conversion characteristics (12-bit ADC_1) (continued)
Symbol
C
Value
Conditions1
Parameter
Unit
Min
Typ
Max
RSW2
CC
D
Internal resistance
of analog source
—
2
k
RAD
CC
D
Internal resistance
of analog source
—
0.3
k
IINJ
SR
—
Input current
Injection
mA
Current
injection
on one
ADC_1
input,
different
from the
converted
one
VDD = 3.3
V ± 10%
5
—
5
VDD = 5.0
V ± 10%
5
—
5
INLP
CC
T
Absolute Integral
non-linearity-Preci
se channels
No overload
1
3
LSB
INLS
CC
T
Absolute Integral
non-linearityStandard channels
No overload
1.5
5
LSB
DNL
CC
T
Absolute
Differential
non-linearity
No overload
0.5
1
LSB
OFS
CC
T
Absolute Offset
error
—
2
LSB
GNE
CC
T
Absolute Gain error —
2
LSB
TUEP9
CC
P
Total Unadjusted
Error for precise
channels, input
only pins
T
TUES(9)
CC
T
T
Without current
injection
6
6
LSB
With current injection
8
8
LSB
Total Unadjusted Without current
Error for standard injection
channel
With current injection
10
10
LSB
12
12
LSB
NOTES:
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2
Analog and digital VSS_HV must be common (to be tied together externally).
3 PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from V
DD_HV_B domain hence VDD_HV_ADC1 should be
within ±100 mV of VDD_HV_B when these channels are used for ADC_1.
4 VDD_HV_ADC1 can operate at 5V condition while V
DD_HV_B can operate at 3.3V provided that ADC_1 channels coming
from VDD_HV_B domain are limited in max swing as VDD_HV_B.
5 V
AINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
6 During the sample time the input capacitance C can be charged/discharged by the external source. The internal
S
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end of
the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tADC1_S depend on programming.
MPC5646C Data Sheet, Rev.6
86
Freescale Semiconductor
Electrical Characteristics
7
Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay.
Refer to ADC conversion table for detailed calculations.
9
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
8
4.18
Fast Ethernet Controller
MII signals use CMOS signal levels compatible with devices operating at 3.3 V. Signals are not TTL
compatible. They follow the CMOS electrical characteristics.
4.18.1
MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the system clock frequency must exceed four times the
RX_CLK frequency in 2:1 mode and two times the RX_CLK frequency in 1:1 mode.
Table 44. MII Receive Signal Timing
Spec
Characteristic
Min
Max
Unit
M1
RXD[3:0], RX_DV,
RX_ER to RX_CLK
setup
5
—
ns
M2
RX_CLK to
RXD[3:0], RX_DV,
RX_ER hold
5
—
ns
M3
RX_CLK pulse width
high
35%
65%
RX_CLK period
M4
RX_CLK pulse width
low
35%
65%
RX_CLK period
M3
RX_CLK (input)
M4
RXD[3:0] (inputs)
RX_DV
RX_ER
M1
M2
Figure 21. MII receive signal timing diagram
4.18.2
MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the system clock frequency must exceed four times the
TX_CLK frequency in 2:1 mode and two times the TX_CLK frequency in 1:1 mode.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
87
Electrical Characteristics
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising
or falling edge of TX_CLK, and the timing is the same in either case. This options allows the use of
non-compliant MII PHYs.
Refer to the Fast Ethernet Controller (FEC) chapter of the MPC5646C Reference Manual for details of this
option and how to enable it.
Table 45. MII transmit signal timing1
Spec
Characteristic
Min
Max
Unit
M5
TX_CLK to TXD[3:0],
TX_EN, TX_ER
invalid
5
—
ns
M6
TX_CLK to TXD[3:0],
TX_EN, TX_ER valid
—
25
ns
M7
TX_CLK pulse width
high
35%
65%
TX_CLK period
M8
TX_CLK pulse width
low
35%
65%
TX_CLK period
NOTES:
1 Output pads configured with SRE = 0b11.
M7
TX_CLK (input)
M5
M8
TXD[3:0] (outputs)
TX_EN
TX_ER
M6
Figure 22. MII transmit signal timing diagram
4.18.3
MII Async Inputs Signal Timing (CRS and COL)
Table 46. MII Async Inputs Signal Timing1
Spec
Characteristic
Min
Max
Unit
M9
CRS, COL minimum
pulse width
1.5
—
TX_CLK period
NOTES:
1 Output pads configured with SRE = 0b11.
MPC5646C Data Sheet, Rev.6
88
Freescale Semiconductor
Electrical Characteristics
CRS, COL
M9
Figure 23. MII async inputs timing diagram
4.18.4
MII Serial Management Channel Timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
Table 47. MII serial management channel timing1
Spec
Characteristic
Min
Max
Unit
M10
MDC falling edge to
MDIO output invalid
(minimum
propagation delay)
0
—
ns
M11
MDC falling edge to
MDIO output valid
(max prop delay)
—
25
ns
M12
MDIO (input) to MDC
rising edge setup
28
—
ns
M13
MDIO (input) to MDC
rising edge hold
0
—
ns
M14
MDC pulse width
high
40%
60%
MDC period
M15
MDC pulse width low
40%
60%
MDC period
NOTES:
1 Output pads configured with SRE = 0b11.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
89
Electrical Characteristics
M14
M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
M13
Figure 24. MII serial management channel timing diagram
MPC5646C Data Sheet, Rev.6
90
Freescale Semiconductor
Electrical Characteristics
4.19
On-chip peripherals
4.19.1
Current consumption
Table 48. On-chip peripherals current consumption1
Value2
Symbol
C
Parameter
Conditions
Unit
Typ
IDD_HV_A(CAN)
IDD_HV_A(eMIOS)
CC
CC
D CAN
500
(FlexCAN)
Kbps
supply current
125
on VDD_HV_A
Kbps
Total (static +
dynamic)
consumption:
FlexCAN in loop-back
mode
[email protected] MHz used
as CAN engine clock
source
Message sending
period is 580 µs
D eMIOS supply Static consumption:
current on
eMIOS channel OFF
VDD_HV_A
Global prescaler enabled
Dynamic consumption:
It does not change varying the
frequency (0.003 mA)
IDD_HV_A(SCI)
CC
D SCI (LINFlex) Total (static + dynamic)
supply current consumption:
on VDD_HV_A LIN mode
Baudrate: 20 Kbps
IDD_HV_A(SPI)
CC
D SPI (DSPI)
Ballast static consumption (only
supply current clocked)
on VDD_HV_A
Ballast dynamic consumption
(continuous communication):
Baudrate: 2 Mbit
Transmission every 8 µs
Frame: 16 bits
IDD_HV_A(ADC)
IDD_HV_ADC0
CC
CC
D ADC supply
current on
VDD_HV_A
7.652  fperiph + 84.73
µA
8.0743  fperiph + 26.757
28.7  fperiph
3
4.7804  fperiph + 30.946
1
16.3  fperiph
VDD =
5.5 V
Ballast static
consumption (no
conversion)
0.0409  fperiph
VDD =
5.5 V
Ballast dynamic
consumption
(continuous
conversion)
0.0049  fperiph
Analog static
consumption (no
conversion)
200
µA
Analog dynamic
consumption
(continuous
conversion)
4
mA
D ADC_0 supply VDD =
current on
5.5 V
VDD_HV_ADC0
mA
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
91
Electrical Characteristics
Table 48. On-chip peripherals current consumption1
Value2
Symbol
C
Parameter
Conditions
Unit
Typ
IDD_HV_ADC1
CC
D ADC_1 supply VDD =
current on
5.5 V
VDD_HV_ADC1
Analog static
consumption (no
conversion)
300  fperiph
µA
VDD =
5.5 V
Analog dynamic
consumption
(continuous
conversion)
6
mA
mA
IDD_HV(FLASH)
CC
D CFlash +
DFlash supply
current on
VDD_HV_ADC
VDD =
5.5 V
—
13.25
IDD_HV(PLL)
CC
D PLL supply
current on
VDD_HV
VDD =
5.5 V
—
0.0031  fperiph
NOTES:
1 Operating conditions: T = 25 °C, f
A
periph = 8 MHz to 120 MHz.
2 f
is
in
absolute
value.
periph
MPC5646C Data Sheet, Rev.6
92
Freescale Semiconductor
Electrical Characteristics
4.19.2
DSPI characteristics
Table 49. DSPI timing
Spec
Characteristic
Symbol
Unit
Min
Max
Refer
note1
—
ns
tCSC
—
115
ns
tASC
15
—
ns
1
DSPI Cycle Time
tSCK
—
Internal delay between pad associated to SCK and pad
associated to CSn in master mode for CSn1->0
—
Internal delay between pad associated to SCK and pad
associated to CSn in master mode for CSn1->1
2
CS to SCK Delay2
tCSC
7
—
ns
3
After SCK Delay3
tASC
15
—
ns
4
SCK Duty Cycle
tSDC
0.4  tSCK
0.6  tSCK
ns
—
Slave Setup Time
(SS active to SCK setup time)
tSUSS
5
—
ns
—
Slave Hold Time
(SS active to SCK hold time)
tHSS
10
—
ns
5
Slave Access Time
(SS active to SOUT valid)4
tA
—
42
ns
6
Slave SOUT Disable Time
(SS inactive to SOUT High-Z or invalid)
tDIS
—
25
ns
7
CSx to PCSS time
tPCSC
0
—
ns
8
PCSS to PCSx time
tPASC
0
—
ns
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
93
Electrical Characteristics
Table 49. DSPI timing (continued)
Spec
9
10
11
12
Characteristic
Symbol
Data Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)5
Master (MTFE = 1, CPHA = 1)
tSUI
Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)5
Master (MTFE = 1, CPHA = 1)
tHI
Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tSUO
Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tHO
Unit
Min
Max
36
5
36
36
—
—
—
—
ns
ns
ns
ns
0
4
0
0
—
—
—
—
ns
ns
ns
ns
—
—
—
—
12
37
12
12
ns
ns
ns
ns
06
9.5
07
08
—
—
—
—
ns
ns
ns
ns
NOTES:
1 This value of this parameter is dependent upon the external device delays and the other parameters mentioned in
this table.
2 The maximum value is programmable in DSPI_CTARn [PSSCK] and DSPI_CTARn [CSSCK]. For MPC5646C, the
spec value of tCSC will be attained only if TDSPI x PSSCK x CSSCK > tCSC.
3 The maximum value is programmable in DSPI_CTARn [PASC] and DSPI_CTARn [ASC]. For MPC5646C, the spec
value of tASC will be attained only if TDSPI x PASC x ASC > tASC.
4 The parameter value is obtained from t
SUSS and tSUO for slave.
5 This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b00.
6 For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 0) is 2 ns.
7
For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 0) is 2 n.
8 For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 1) is 2 ns.
MPC5646C Data Sheet, Rev.6
94
Freescale Semiconductor
Electrical Characteristics
2
3
CSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
SIN
10
First Data
Last Data
Data
12
SOUT
First Data
11
Data
Last Data
Note: Numbers shown reference Table 49.
Figure 25. DSPI classic SPI timing–master, CPHA = 0
CSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
SIN
Data
First Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Note: Numbers shown reference Table 49.
Figure 26. DSPI classic SPI timing–master, CPHA = 1
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
95
Electrical Characteristics
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
SOUT
First Data
9
SIN
12
11
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 49.
Figure 27. DSPI classic SPI timing–slave, CPHA = 0
MPC5646C Data Sheet, Rev.6
96
Freescale Semiconductor
Electrical Characteristics
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 49.
Figure 28. DSPI classic SPI timing–slave, CPHA = 1
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
97
Electrical Characteristics
3
CSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
SIN
First Data
10
Last Data
Data
12
SOUT
First Data
11
Data
Last Data
Note: Numbers shown reference Table 49.
Figure 29. DSPI modified transfer format timing–master, CPHA = 0
MPC5646C Data Sheet, Rev.6
98
Freescale Semiconductor
Electrical Characteristics
CSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
First Data
Data
12
SOUT
First Data
Data
Last Data
11
Last Data
Note: Numbers shown reference Table 49.
Figure 30. DSPI modified transfer format timing–master, CPHA = 1
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
99
Electrical Characteristics
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
First Data
SOUT
Data
6
Last Data
10
9
Data
First Data
SIN
12
11
5
Last Data
Note: Numbers shown reference Table 49.
Figure 31. DSPI modified transfer format timing–slave, CPHA = 0
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
12
First Data
SOUT
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 49.
Figure 32. DSPI modified transfer format timing–slave, CPHA = 1
MPC5646C Data Sheet, Rev.6
100
Freescale Semiconductor
Electrical Characteristics
8
7
PCSS
CSx
Note: Numbers shown reference Table 49.
Figure 33. DSPI PCS strobe (PCSS) timing
4.19.3
Nexus characteristics
Table 50. Nexus debug port timing1
Spec
Characteristic
Symbol
Min
Max
Unit
1
MCKO Cycle
Time2
tMCYC
16.3
—
ns
2
MCKO Duty Cycle
tMDC
40
60
%
3
MCKO Low to
MDO, MSEO,
EVTO Data Valid3
tMDOV
–0.1
0.25
tMCYC
4
EVTI Pulse Width
tEVTIPW
4.0
—
tTCYC
5
EVTO Pulse
Width
tEVTOPW
1
6
TCK Cycle Time4
tTCYC
40
—
ns
7
TCK Duty Cycle
tTDC
40
60
%
8
TDI, TMS Data
Setup Time
tNTDIS, tNTMSS
8
—
ns
9
TDI, TMS Data
Hold Time
tNTDIH, tNTMSH
5
—
ns
10
TCK Low to TDO
Data Valid
tJOV
0
25
ns
tMCYC
NOTES:
1 JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is
measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDDE = 4.0 – 5.5 V,
TA = TL to TH, and CL = 30 pF with SRC = 0b11.
2 MCKO can run up to 1/2 of full system frequency. It can also run at system frequency when it is <60 MHz.
3 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
4
The system clock frequency needs to be three times faster than the TCK frequency.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
101
Electrical Characteristics
1
2
MCKO
3
MDO
MSEO
EVTO
Output Data Valid
5
EVTI
4
Figure 34. Nexus output timing
MPC5646C Data Sheet, Rev.6
102
Freescale Semiconductor
Electrical Characteristics
6
7
TCK
8
9
TMS, TDI
10
TDO
Figure 35. Nexus TDI, TMS, TDO timing
4.19.4
JTAG characteristics
Table 51. JTAG characteristics
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tJCYC
CC
D TCK cycle time
64
—
—
ns
2
tTDIS
CC
D TDI setup time
10
—
—
ns
3
tTDIH
CC
D TDI hold time
5
—
—
ns
4
tTMSS
CC
D TMS setup time
10
—
—
ns
5
tTMSH
CC
D TMS hold time
5
—
—
ns
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
103
Electrical Characteristics
Table 51. JTAG characteristics (continued)
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
6
tTDOV
CC
D TCK low to TDO valid
—
—
33
ns
7
tTDOI
CC
D TCK low to TDO invalid
6
—
—
ns
—
tTDC
CC
D TCK Duty Cycle
40
—
60
%
—
tTCKRISE
CC
D TCK Rise and Fall Times
—
—
3
ns
TCK
2/4
DATA INPUTS
3/5
INPUT DATA VALID
6
DATA OUTPUTS
OUTPUT DATA VALID
7
DATA OUTPUTS
Note: Numbers shown reference Table 51.
Figure 36. Timing diagram - JTAG boundary scan
MPC5646C Data Sheet, Rev.6
104
Freescale Semiconductor
Package characteristics
5
Package characteristics
5.1
Package mechanical data
5.1.1
176 LQFP package mechanical drawing
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
105
Package characteristics
Figure 37. 176 LQFP mechanical drawing (Part 1 of 3)
MPC5646C Data Sheet, Rev.6
106
Freescale Semiconductor
Package characteristics
Figure 38. 176 LQFP mechanical drawing (Part 2 of 3)
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
107
Package characteristics
E
E
Figure 39. 176 LQFP mechanical drawing (Part 3 of 3)
5.1.2
208 LQFP package mechanical drawing
MPC5646C Data Sheet, Rev.6
108
Freescale Semiconductor
Package characteristics
Figure 40. 208 LQFP mechanical drawing (Part 1 of 3)
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
109
Package characteristics
Figure 41. 208 LQFP mechanical drawing (Part 2 of 3)
MPC5646C Data Sheet, Rev.6
110
Freescale Semiconductor
Package characteristics
Figure 42. 208 LQFP mechanical drawing (Part 3 of 3)
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
111
Package characteristics
MPC5646C Data Sheet, Rev.6
112
Freescale Semiconductor
Package characteristics
5.1.3
256 MAPBGA package mechanical drawing
Figure 43. 256 MAPBGA mechanical drawing (Part 1 of 2)
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
113
Package characteristics
Figure 44. 256 MAPBGA mechanical drawing (Part 2 of 2)
MPC5646C Data Sheet, Rev.6
114
Freescale Semiconductor
Ordering information
6
Ordering information
Example code:
M
PC
56
4
6
B
C
F0
M
LL
1
R
Qualification Status
Power Architecture
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Optional fields
Fab and mask indicator
Temperature spec.
Package Code
CPU Frequency
R = Tape & Reel (blank if Tray)
Product Version
B = Body
C = Gateway
Qualification Status
M = MC status
S = Auto qualified
P = PC status
Optional fields
C = CSE module available
Blank = none of these options available
PC = Power Architecture
Automotive Platform
56 = Power Architecture in 90 nm
Core Version
4 = e200z4d core version (highest core version in the case
of multiple cores)
Flash Memory Size
4 = 1.5 MB
5 = 2 MB
6 = 3 MB
Fab and mask version indicator
F = ATMC
0 = First version of the mask
Temperature spec.
C = –40 °C to 85 °C
V = –40 °C to 105 °C
M = –40 °C to 125 °C
Package Code
LU = 176 LQFP
LT = 208 LQFP
MJ = 256 MAPBGA
CPU Frequency
1 = e200z4d operates up to 120 MHz
8 = e200z4d operates up to 80 MHz
Shipping Method
R = Tape and reel
Blank = Tray
Note: Not all options are available on all devices. Refer to Table 1, which shows the orderable part numbers for
MPC564xx.
Figure 45. Orderable parts
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
115
Revision history
7
Revision history
Table 52 summarizes revisions to this document.
Table 52. Revision history
Revision
Date
1
15 April 2010
2
17 August 2010
Changes
Initial Release
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Editing and formatting updates throughout the document.
Updated Voltage regulator capacitance connection figure.
Added a new sub-section “VDD_BV Options”
Program and erase specifications:
-Updated Tdwprogram TYP to 22 us
-Updated T128Kpperase Max to 5000 ms
-Added tESUS parameter
Added 208 MAPBGA thermal characteristics
Added recommendation in the Voltage regulator electrical characteristics section.
Added Crystal description table in Fast external crystal oscillator (4 to 140 MHz)
electrical characteristics section and corrected the cross-reference to the same.
Added new sections - Pad types, System pins and functional ports
Updated TYP numbers in the Flash program and erase specifications table
Added a new table: Program and erase specifications (Data Flash)
Flash read access timing table: Added Data flash memory numbers
Flash power supply DC electrical characteristics table: Updated IDFREAD and
IDFMOD values for Data flash, Removed IDFLPW parameter
Updated feature list.
MPC5646C 3M family comparison table: Updated ADC channels and added ADC
footnotes.
MPC5646C 3M block diagram: Updated ADC channels and added legends.
MPC5646C 3M series block summary: Added new blocks.
Functional Port Pin Descriptions table: Added OSC32k_XTAL and
OSC32k_EXTAL function at PB8 and PB9 port pins.
Electrical Characteristics: Replaced VSS with VSS_HV throughout the section.
Absolute maximum ratings, Recommended operating conditions (3.3 V) and
Recommended operating conditions (5.0 V) tables: VRC_CTRL min is updated to
"0".
Recommended operating conditions (3.3 V) and Recommended operating
conditions (5.0 V) tables: Clarified VIN parameter, clarified footnote 2 in both
tables.
LQFP thermal characteristics section: Updated numbers for LQFP packages.
Low voltage power domain electrical characteristics table: Clarified footnotes
based upon review comments.
Code flash memory—Program and erase specifications: Updated tESRT to 20 ms.
ADC electrical characteristics section: Replace ADC0 with ADC_0 and ADC1 with
ADC_1 throughout the document.
DSPI characteristics section: Replaced PCSx with CSx in all figures and tables.
MPC5646C Data Sheet, Rev.6
116
Freescale Semiconductor
Revision history
Table 52. Revision history (continued)
Revision
Date
Changes
3
28 April 2011
• Replaced VIL min from –0.4 V to –0.3 V in the following tables:
- I/O input DC electrical characteristics
- Reset electrical characteristics
- Fast external crystal oscillator (4 to 40 MHz) electrical characteristics
• Updated Crystal oscillator and resonator connection scheme figure
• Specified NPN transistor as the recommended BCP68 transistor throughout the
document
• Code and Data flash memory—Program and erase specifications tables:
Renamed the parameter tESUS to Teslat
• Revised the footnotes in the “Functional port pin descriptions” table.
• In the “System pin descriptions” table, added a footnote to the A pads regarding
not using IBE.
For ports PB[12–15], changed ANX to ADC0_X.
• Revised the presentation of the ADC functions on the following ports:
PB[4–7]
PD[0–11]
• ADC conversion characteristics (10-bit ADC_0) table and Conversion
characteristics (12-bit ADC_1) table- Updated footnote 5 and 7 respectively for the
definition of the conversion time.
• Data flash memory—Program and erase specifications: Updated Twprogram to 500
µs and T16Kpperase to 500 µs. Corrected Teslat classification from “C” to “D”.
• Code flash memory—Program and erase specifications: Corrected Teslat
classification from “C” to “D”.
• Flash Start-up time/Switch-off time: Changed TFLARSTEXIT classification from “C”
to “D”.
• Functional port pin description: Added a footnote at the PB [9] port pin.
• Absolute maximum ratings table: Added footnote 1.
• Low voltage power domain electrical characteristics table: Updated IDDHALT,
IDDSTOP, IDDSTBY3, IDDSTDBY2, IDDSTDBY1.
• Slow external crystal oscillator (32 kHz) electrical characteristics table: Updated
gmSXOSC, VSXOSC, ISXOSCBIAS and ISXOSC.
• FMPLL electrical characteristics table: Updated tLTJIT.
• Fast internal RC oscillator (16 MHz) electrical characteristics table: Updated
TFIRCSU and IFIRCPWD.
• MII serial management channel timing table: Updated M12
• JTAG characteristics table: Updated tTDOV.
• Low voltage monitor electrical characteristics table: Updated VLVDHV3H,
VLVDHV3L, VLVDHV5H, VLVDHV5L.
• DSPI electricals table: Updated spec 1, 5, 6. Updated footnote 2 and 3. Added
tCSC, tASC, tSUSS, tHSS.
• IO consumption table: Updated all parameter values.
• DSPI electricals: Updated tCSC max to 115 ns.
• Low voltage power domain electrical characteristics table: Added footnote 9.
• ADC electrical characteristics: Added 2 notes above 10-bit and 12-bit conversion
tables.
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
117
Revision history
Table 52. Revision history (continued)
Revision
Date
Changes
4
23 June 2011
• Interchanged the denominator with numerator in Equation 11 of Input impedance
and ADC accuracy section
• Removed the note (All ADC conversion characteristics described in the table
below are applicable only for the precision channels. The data for semi-precision
and extended channels is awaited and same will be subsequently updated in later
revs.) in the ADC electrical characteristics section.
• In On-chip peripherals current consumption table, replaced IDD_HV_ADC with
IDD_HV_ADC0 and IDD_HV_ADC1 values as per ADC specs
• In ADC conversion characteristics (10-bit ADC_0) table, the minimum sample time
of ADC0 changed to 500 at 32 MHz
• In ADC conversion characteristics (10-bit ADC_0) table, removed the entry for
sample time at 30 MHz
• In Conversion characteristics (12-bit ADC_1)table, changed TUEX to TUES and
INLX to INLS (Extended channels are not supported by the device. So, changed
to standard channel.)
MPC5646C Data Sheet, Rev.6
118
Freescale Semiconductor
Revision history
Table 52. Revision history (continued)
Revision
Date
Changes
5
21 June 2012
• Updated the pins 23 and 24 of Figure 2.176-pin LQFP configuration
• Updated unit of measure in Table 43 Conversion characteristics (12-bit ADC_1)
• Modified the value to typical value in Table 48 On-chip peripherals current
consumption
• Added footnote to tESRT parameter in Table 25 Code flash memory—Program and
erase specifications
• Added footnote to tESRT parameter in Table 26 Data flash memory—Program and
erase specifications
• Updated Table 28 Flash memory read access timing.
• Updated Notes 2 and Notes 3 of Table 9 Recommended operating conditions
(3.3 V) and Table 10 Recommended operating conditions (5.0 V) respectively.
• Updated the footnote1 of Table 9 Recommended operating conditions (3.3 V) and
Table 10 Recommended operating conditions (5.0 V)
• Updated VDD_HV_A to VDD_BV for CDEC2 and IDD_HV_A in Table 22 Voltage
regulator electrical characteristics and deleted footnote3
• Updated the dedicated number of channels for 12-bit ADC in family comparison
tables
• Updated the values of fSIRC, parameters and conditions of SIRCVAR in Table 40
Slow internal RC oscillator (128 kHz) electrical characteristics
• Updated second footnote in Table 10, Recommended operating conditions (5.0 V)
• Updated the value of tADC0_PU in Table 42, ADC conversion characteristics (10-bit
ADC_0)
• Updated the IDD values in Table 24, Low voltage power domain electrical
characteristics
• Added footnote to Table 24, Low voltage power domain electrical characteristics
related to current drawn from VDD_HV_A and VDD_HV_B
• Updated entire Section 4.17.1.1, ”Input impedance and ADC accuracy”- Updated
the values of VLPREG in Table 22, Voltage regulator electrical characteristics.
• Updated the values of VLPREG in Table 22, Voltage regulator electrical
characteristics.
• Added TA = 25 °C, min and max values of VMREG in Table 22, Voltage regulator
electrical characteristics
• Added TA = 25 °C, min and max values of VLPREG in Table 22, Voltage regulator
electrical characteristics
• Updated the min, max and typical values of VLVDLVCORL and VLVDLVBKPL in
Table 23, Low voltage monitor electrical characteristics
• Updated values of gmFXOSC in Table 35, Fast external crystal oscillator (4 to 40
MHz) electrical characteristicsUpdated values of gmSXOSC in Table 37, Slow
external crystal oscillator (32 kHz) electrical characteristics
• Updated the footnote 5 for TADC0_C in Table 42, ADC conversion characteristics
(10-bit ADC_0)
• Updated the footnotes of Table 24, Low voltage power domain electrical
characteristics
5.1
15 Aug 2012
• Removed Footer: Preliminary tag
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
119
Revision history
Table 52. Revision history (continued)
Revision
Date
Changes
6
12 Feb 2014
• Removed occurrences of 208BGA from Table 3 System pin descriptions.
• Added PM[3] and PM[4] in the figure note 1 of Figure 4, 256-pin BGA
configuration.
• Added a table note in Table 19 I/O supplies.
• Updated Figure 8, Voltage regulator capacitance connection and added a note in
this figure.
• Removed max values of VLPREG and VMREG, changed min value of VLPREG to 1.21
V, and updated VMREG and VLPREG after trimming values in Table 22 Voltage
regulator electrical characteristics.
• Updated 1st footnote and updated max values for IDDRUN, IDDHALT, IDDSTOP,
IDDSTDBY3, IDDSTDBY2, IDDSTDBY1 and removed values at 85oC and 105oC in
Table 24 Low voltage power domain electrical characteristics.
• Added a footnote below Table 28 Flash memory read access timing.
• Updated the formula in Eq. 11 in Section 4.17.1.1, ”Input impedance and ADC
accuracy.
• Added Figure 17, Input equivalent circuit (extended channels).
• Updated tADC0_PU value to 1.5 as max and added footnote for IINJ in Table 42 ADC
conversion characteristics (10-bit ADC_0).
• Added Category column in Table 43 Conversion characteristics (12-bit ADC_1).
• Added the IDD_HV_ADC0 values in Table 48 On-chip peripherals current
consumption.
• Added a note in Figure 45, Orderable parts.
NOTE
This revision history uses clickable cross-references for ease of navigation.
The numbers and titles in each cross-reference are relative to the latest
published release.
MPC5646C Data Sheet, Rev.6
120
Freescale Semiconductor
Abbreviations
Appendix A
Abbreviations
Table 53 lists abbreviations used but not defined elsewhere in this document.
Table 53. Abbreviations
Abbreviation
CS
Meaning
Chip select
EVTO
Event out
MCKO
Message clock out
MDO
Message data out
MSEO
Message start/end out
MTFE
Modified timing format enable
SCK
Serial communications clock
SOUT
Serial data out
TBD
To be defined
TCK
Test clock input
TDI
Test data input
TDO
Test data output
TMS
Test mode select
MPC5646C Data Sheet, Rev.6
Freescale Semiconductor
121
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MPC5646C
Rev.6
02/2014
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