INTERSIL 5962F9860101VCC

ACS02MS
Data Sheet
November 1998
File Number
Radiation Hardened Quad 2-Input NOR Gate
Features
The Radiation Hardened ACS02MS is a Quad 2-Input NOR
Gate. For each gate, a HIGH level on either A or B input
results in a LOW level on the Y output. A LOW level on both
the A and B inputs results in a HIGH level on the Y output.
All inputs are buffered and the outputs are designed for
balanced propagation delay and transition times.
• QML Qualified Per MIL-PRF-38535 Requirements
The ACS02MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS02MS are
contained in SMD 5962-98601. A “hot-link” is provided
on our homepage with instructions for downloading.
www.intersil.com/data/sm/index.asp
4540
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under Any Conditions
- Total Dose. . . . . . . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si)
- SEU Immunity . . . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm2)
• Input Logic Levels. . . . VIL = (0.3)(VCC), VIH = (0.7)(VCC)
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . ±8mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . 100µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 12ns (Max)
Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
Ordering Information
INTERNAL MARKETING
NUMBER
ORDERING NUMBER
5962F9860101VCC
ACS02DMSR-03
ACS02D/SAMPLE-03
ACS02D/SAMPLE-03
5962F9860101VXC
ACS02KMSR-03
ACS02K/SAMPLE-03
5962F9860101V9A
TEMP. RANGE (oC)
PACKAGE
DESIGNATOR
-55 to 125
14 Ld SBDIP
CDIP2-T14
25
14 Ld SBDIP
CDIP2-T14
-55 to 125
14 Ld Flatpack
CDFP4-F14
ACS02K/SAMPLE-03
25
14 Ld Flatpack
CDFP4-F14
ACS02HMSR-03
25
Die
N/A
Pinouts
ACS02MS
(SBDIP)
TOP VIEW
ACS02MS
(FLATPACK)
TOP VIEW
1Y 1
14 VCC
1Y
1
14
VCC
A1 2
13 Y4
A1
2
13
Y4
B1 3
12 B4
B1
3
12
B4
Y2
4
11
A4
A2
5
10
Y3
B2
6
9
B3
GND
7
8
A3
11 A4
Y2 4
A2 5
10 Y3
B2 6
9 B3
GND 7
8 A3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
ACS02MS
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ±25µm (20.6 mils ±1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ±0.15µm
SPECIAL INSTRUCTIONS
METALLIZATION: AI
Bond VCC First
Metal 1 Thickness: 0.7µm ±0.1µm
Metal 2 Thickness: 1.0µm ±0.1µm
ADDITIONAL INFORMATION:
Worst Case Current Density: <2.0 x 105 A/cm2
Transistor Count: 108
SUBSTRATE POTENTIAL
Unbiased Insulator
Metallization Mask Layout
ACS02MS
A1
(2)
Y1
(1)
VCC
(14)
Y4
(13)
B1 (3)
(12) B4
Y2 (4)
(11) A4
NC
NC
A2 (5)
(10) Y3
(6)
B2
(7)
GND
(8)
A3
(9)
B3
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