Application Note AN-1162 Compensator Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier By: Amir M. Rahimi, Parviz Parto, and Peyman Asadi Table of Contents Page 1. Introduction to Synchronous Buck Converter ...................................2 2. Loop Gain of the System..................................................................5 3. Step by Step Compensator Design Procedure.................................6 4. Type II Compensator Design............................................................7 4.1 Design Example of Type II Compensator.......................................11 5. Type III Compensator.......................................................................13 5.1 Type III- A Compensator ................................................................14 5.2 Design Example of Type III-A Compensator ..................................16 5.3 Type III- B Compensator ................................................................19 5.4 Design Example of Type III-B Compensator ..................................20 6. Conclusion .......................................................................................23 Appendices: Designing the Power Stage of the Synchronous Buck Converter ........24 Some Special Cases of Compensator Design .....................................28 Loop Response Measurement .............................................................33 www.irf.com AN-1162 1 Compensator Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier Synchronous buck converters have received great attention in low voltage DC/DC converter applications because they can offer high efficiency; provide more precise output voltage and also meet the size requirement constraints. International Rectifier Inc. has developed a series of integrated buck regulators (SupIRBuckTM) to accommodate all the above. These regulators combine IR’s latest MOSFET technology with high performance process technology for IC controller. These regulators use a PWM voltage mode control scheme with external loop compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency can be programmed from 250kHz to above 1.5MHz to provide the capability of optimizing the design in terms of size and performance. In this application note stabilizing the buck converter with voltage-mode error amplifier is discussed. The goal is to highlight the advantage of this control scheme and illustrate how a high performance feedback loop that allows fast load transient response and accurate steady state output can be achieved. 1. Introduction to Synchronous Buck Converter with Voltage-Mode ErrorAmplifier A buck converter with voltage-mode control and voltage-mode error amplifier can be stabilized with a proportional-integral (PI) type of compensator. However, to have high performance a more sophisticated compensation network is required, especially when MLCC (Multi Layer Ceramic Capacitor) capacitors are used. MLCC capacitors are widely used at the output of low voltage DC/DC converters because of their low equivalent series resistance (ESR) and low equivalent series inductance (ESL). Low ESL, which results in high resonance frequency, makes the MLCC capacitors desirable at high switching frequencies. Besides, low ESL and low ESR make the output voltage switching ripple smaller which is very desirable. On the other hand, stabilizing a DC/DC converter www.irf.com AN-1162 2 with MLCC output capacitors requires more attention as compared to stabilizing a converter with electrolytic output capacitors. Depending on the type/size of the components of output filter which are used and the design parameters (switching frequency, bandwidth, etc), different compensation networks might be required. In addition, to achieve the desired performance, the parameters of the compensation network must be adjusted properly. This document provides guidelines to design appropriate compensation network in various conditions. In addition, the procedure of compensator design has been explained with examples. Figure 1 shows a typical synchronous buck converter with voltage-mode control and voltage-mode error-amplifier. Output Inductor Control FET + - RL Vout Lo Output Capacitor ESR Vin Sync FET RLoad Co Compensation Network Gate Drivers Vosc + - PWM Generator Ve + Vref Error Amplifier Figure 1 - Simplified circuit diagram of a synchronous buck converter with a voltagemode error-amplifier In Figure 1, RL is the inherent resistance of the output inductor and ESR is the equivalent series resistance of the output capacitor. To make the analysis simpler, the ESL of the output capacitors is neglected. The circuit shown in Figure 1 can be modeled with three blocks as presented in Figure 2. The power stage (Gp(s)) includes the switches, the drivers and the output inductor and capacitor. The model of the PWM generator is simply 1 / Vosc [2], where Vosc is the peak to peak amplitude of the oscillator voltage (saw-tooth) www.irf.com AN-1162 3 listed in the datasheet. The compensator block (H(s)) represents the error-amplifier with the compensation network. G(s) Compensator Ve Vref + H(s) - 1 Vosc d (duty cycle) GP(s) Vout Power Stage PWM Generator 1 k Figure 2 - The block diagram model of the synchronous buck converter The transfer function of the power stage can be simplified as follows: GP ( s ) Vout RLoad ( Co ESR s 1 ) (s) Vin 2 d Lo Co s ( RLoad ESR ) s ( Lo RLoad Co ESR ) RLoad (1) The ‘s’ indicates that the transfer function varies as a function of the frequency. For simplicity the transfer functions of the PWM generator and the power stage can be combined: G( s ) GP ( s ) 1 Vosc (2) Therefore, G(s) is usually referred to as the transfer function of the power stage. The roots of the polynomial in the denominator of (1) are called the poles of the transfer function of the power stage. Similarly the roots of the numerator of (1) are the zeros of the transfer function of the power stage. The transfer function of the power stage is a second order system with a double pole at the resonance frequency (of the LC filter) and a zero produced by the ESR of the output capacitor. The resonance frequency and the zero frequency associated with the ESR are given by (3) and (4). The approximate Bode plot of the power stage is sketched in Figure 3. The double pole causes the gain to fall with a slope of -40dB/dec up to the zero frequency ( FESR ) which compensates one of the poles. The zero frequency is a characteristic parameter of the output capacitor and is dependant on the type of the capacitor used. This frequency can be as low as a few kHz www.irf.com AN-1162 4 for an electrolytic capacitor to as high as a few MHz for a ceramic capacitor. More information about designing the power stage is provided in Appendix A. FLC FESR 1 (frequency of the double poles) 2 π Lo Co (3) 1 (frequency of the zero) 2 π ESR Co (4) n s ViVo FLC c -40dB Magnitude FESR -20dB 0 Phase -90° -180° Figure 3 - The bode plot of the power stage of the buck converter 2. Loop Gain of the system The loop gain of system is defined as the product of transfer functions along the closed control loop. Using Figure 2, the loop gain is defined as: M( s ) 1 1 1 H( s ) G P ( s ) H ( s ) G( s ) k Vosc k (5) Where 1 k represents the gain of the resistor divider which is used in the feedback loop when Vout Vref . For some configurations of compensation network, as the ones discussed in the next sections, this term ( 1 k ) is canceled out and does not appear in the loop-gain equation. The bode plots of power stage and desired loop gain is shown in Figure 4, where F0 is the zero crossover frequency defined as the frequency when loop gain equals unity. F0 is also called “the bandwidth of the loop” or “the bandwidth of the system”. www.irf.com AN-1162 5 Typically, F0 can be set to 1/10~1/5 of the switching frequency. The speed of the system response to load transients is determined by F0 . In other words, the higher the crossover frequency, the faster the load transient response would be. However, the crossover frequency should be low enough to allow attenuation of switching noise. The slope of the loop gain at F0 should be about –20dB in order to ensure a stable system. The phase margin should be greater than 45º for overall stability. n s ViVo c Figure 4 - Bode plot of the power stage, desired loop gain, and loop phase 3. Step by step compensator design procedure As mentioned in the Introduction, to have a stable closed loop buck converter with appropriate performance, a properly designed compensator is required. The typical procedure of compensator design is as follows: Step 1 - Collect system parameters such as input voltage, output voltage, maximum load/output current, switching frequency, input and output capacitance, and output inductance. Step 2 - Using (3) and (4) determine the power stage poles and zero Step 3 - Determine the zero crossover frequency of the loop, F0 . Usually this frequency is chosen equal to 1/10 to 1/5 of the switching frequency. www.irf.com AN-1162 6 F0 ( 1 / 10 ~ 1 / 5 ) FS (6) Step 4 - Determine the compensation type. The compensation type is determined by the location of zero crossover frequency and characteristics of the output capacitor as shown in Table 1. Step 5 - Determine the desired location of the poles and zeros of the selected compensator (this will be explained for each type of compensator). Step 6 - Calculate the real parameters (resistors and capacitors) for the selected compensator so that the desired poles/zeros are achieved. Choose the standard values for resistors and capacitors such that they are as close to the calculated values as possible. Table 1 - The compensation type and location of zero crossover frequency. Compensator Type Relative location of the crossover and power-stage frequencies Typical Output Capacitor Type II (PI) FLC FESR F0 FS / 2 Electrolytic, POS-Cap, SP-Cap Type III-A (PID) FLC F0 FESR FS / 2 POS-Cap, SP-Cap Type III-B (PID) FLC F0 FS / 2 FESR Ceramic 4. Type II Compensator Design Type II compensation is used for applications where the frequency of the zero caused by output capacitor and its ESR ( FESR ) is smaller than the closed loop bandwidth ( F0 ) as shown below: FLC FESR F0 FS / 2 (7) This condition is usually met when the output capacitor is of electrolytic type. The FESR (refer to (4)) for this type of capacitor is in the range of a few kHz. The schematic of the type II compensator is depicted in Figure 5. www.irf.com AN-1162 7 Zc Cc2 Vout Cc1 Rc1 Rf1 - E/A Rf2 Ve + Vref Figure 5 - Type II compensator Assuming the gain/band-width of the error-amplifier (E/A) is very high, the transfer function of this compensator is given by: H( s ) Ve (s) Vout 1 RC1 CC1 s C C Rf 1 s ( CC1 CC 2 ) ( RC1 C1 C 2 s 1 ) CC1 CC 2 (8) The capacitor CC 2 is chosen so that CC 2 CC1 . Therefore: H( s ) 1 RC1 CC1 s Rf 1 s CC1 ( RC1 CC 2 s 1 ) (9) The root of the numerator in (8) is the zero of compensator and the roots of the denominator are the poles of the compensator. Therefore, the compensator has a pole at the origin (an integrator) and another pole and one zero as given below: FZ 1 FP 2 1 2π RC1 CC1 (10) 1 (11) 2π RC1 CC 2 The approximate bode-plot of the power stage, the Type II compensator, and the desired loop gain has been drawn in Figure 6. www.irf.com AN-1162 8 Figure 6 - Bode plot of the buck converter power stage, desired loop gain, and Type II compensator Each pole makes the phase of the loop drop by 90º and each zero makes the phase rise by 90º. The phase change of a zero/pole starts at about 1 decade below the frequency of the zero/pole and ends about 1 decade above it. It should be noted that due to negative feedback (minus sign of H(s)) initially there is 180º phase-shift in the compensator. The phase change due to poles and zeros are added to this 180º. Hence, to have a stable system, the overall phase of the loop should never become 360º/0º (or close to it) when the gain is greater than 1 (0dB). Especially, at crossover frequency ( F0 ), the phase should be at least 45º (45º phase margin). Since the compensator has a pole at the origin, the zero of the compensator should be placed at a frequency lower than the double poles of the LC filter to make sure the phase of the loop does not drop close to 0º around FLC . Usually the following equation is used: FZ 1 0.75 FLC (12) The second pole of the compensator should be placed higher than the cross-over frequency so that its lagging phase (phase drop) does not decrease the phase margin of the loop. On the other hand, it should be placed lower than the switching frequency, so that enough attenuation at the switching ripple is obtained. The following equation gives a reasonable compromise: FP 2 FS / 2 www.irf.com (13) AN-1162 9 After FZ 1 and Fp 2 are selected the values of the components of the compensator can be calculated. There is one degree of freedom in calculating the values of the parameters of the compensator. The procedure can be started by selecting a reasonable value for Rf 1 . A value of a few kΩ should be a good starting point. Since Rf 1 and Rf2 are used to set the output voltage (Figure 5), Rf2 can be calculated using the following equation: Rf 2 Rf 1 Vref (14) ( Vout Vref ) The transfer function from the output of the error amplifier to the output voltage is: G(s) V R Load (C o ESR s 1) Vout ( s ) in 2 Ve Vosc Lo C o s ( R Load ESR ) s ( Lo R Load C o ESR ) R Load (15) In the above equation, Vosc is the amplitude of the saw-tooth/triangular modulator signal The amplitude of the loop-gain at crossover frequency is equal to one. Therefore, H ( s) G ( s) f F 1 (16) 0 Using the (9), (15), and (16) RC1 is calculated: RC1 Rf 1 FESR Vosc F0 2 Vin FLC (17) Since FZ 1 was chosen and RC1 was calculated, CC1 can be calculated: CC 1 1 1 2π RC1 FZ 1 1.5π RC1 FLC (18) Similarly, CC 2 can be calculated: CC 2 1 1 2π RC1 FP 2 π RC1 FS www.irf.com (19) AN-1162 10 4.1 Design example of Type II compensator For this design an IR3840 regulator is used. The schematic of the design is given in Figure 7. Vin =12 V Cin = 4 X 10 uF + 330 uF R1 49.9K 4.5 V< Vcc<5.5V R2 6.8K Enable CVcc RPG 10K Vin Boot C6 0. 1 uF Vcc SW PGood IR3840 Seq R OCSet 3.24k OCSet 4.7nF Rt 23.2k Cc1 Gnd Comp PGnd CSS 0. 1 uF 1.8V 7.15kΩ + - Rf1 1.2kΩ 1% Fb Rt SS / SD Vout Lo 1 uF PGood 530nH Rf2 768Ω 1% Co=2x470µF , 10mΩ each POSCAP Rc1 Cc2 68pF Figure 7 - Application of IR3840 with type II compensator for a 12A, 1.8V regulator Step 1 - Collect the system information such as input and output voltage and the switching frequency: Vin 12V Vout 1.8V Vref 0.7V Vosc 1.8V Lo 530nH C o 2 470 μF ESR(C o ) 10m each FS 600 KHz I o (max) 12 A Step 2 - Calculate the poles and zero of the power stage. Using (3), the double pole of the power stage is at: FLC 1 1 7.1KHz 2π Lo Co 2π 530nH 940 μF www.irf.com AN-1162 11 The zero caused by the ESR of the output capacitor can be calculated using (4): FESR 1 1 33.8kHz 2π ESR Co 2π 10m 470 μF Step 3 - Select crossover frequency to be 1/10 of the switching frequency: F0 60 KHz Step 4 - Select the type of compensator. Since FLC FESR F0 FS / 2 , Type II compensator is suitable for this application. Step 5 - Select the pole and zero of the compensator. Using (13) and (12): FZ 1 0.75 FLC 0.75 7.1kHz 5.33kHz FP 2 FS / 2 600kHz / 2 300kHz Step 6 - Calculate the parameters (resistors and capacitors) of the compensator. Select Rf 1 1.2 K . Rf 2 is calculated using (14): Rf 2 1.2k 0.7V 764 (1.8V 0.7V ) Select Rf 2 768 . Calculate RC1 using (17): RC1 1.2k 33.8kHz 1.8V 60kHz 7.24k 12V ( 7.1kHz )2 Choose RC1 7.15k . Calculate CC1 using (18): C C1 1 4.2nF 2π 7.15k 5.33kHz Choose CC1 4.7 nF . Calculate CC 2 using (19): CC 2 1 74 pF 2π 7.15k 300kHz Choose CC 2 68 pF . The experimentally measured Bode plot of the loop for this design is shown in Figure 8. The resulting crossover frequency is about 61kHz and the phase margin is about 54º. www.irf.com AN-1162 12 Figure 8 - The bode plot of the loop for the example with Type II compensator 5. Type III Compensator For a general solution for unconditional stability for any type of output capacitors, and a wide range of ESR values, local feedback should be implemented with a type III compensation network. Specially, when F0 FESR type II compensator is not useful and type III compensator must be used. The typically type III compensation network which is used for a voltage-mode PWM converter is shown in figure 9. Vout Zc Rf3 Rc1 Cc2 Cc1 Rf1 Cf3 Zf - E/A OUT Rf2 Ve + Vref Figure 9 - Type III compensator The transfer function of type III compensator is given by: H (s) Ve Z C Vout Zf www.irf.com (20) AN-1162 13 H (s) (1 s RC1 C C1 ) [1 s C f 3 ( Rf 1 Rf 3 )] C C s Rf 1 (C C1 C C 2 ) [1 s RC1 ( C1 C 2 )] (1 s Rf 3 C f 3 ) C C1 C C 2 (21) The pole which is generated by CC 2 and RC1 is usually set at a much higher frequency as compared with the frequency of the zero generated by CC1 and RC1 . This means: CC 2 CC1 . Therefore: H (s) (1 RC1 C C1 s ) [1 s C f 3 ( Rf 1 Rf 3 )] s Rf 1 C C1 ( RC1 C C 2 s 1) (1 s Rf 3 C f 3 ) (22) The compensator has two zeros and three poles as given below: FZ 1 1 2 RC1 C C1 (23) FZ 2 1 2 C f 3 ( Rf 1 Rf 3 ) (24) F p1 0 Fp 2 Fp3 (25) 1 2 C f 3 Rf 3 (26) 1 (27) 2 RC1 C C 2 Depending upon the relative location of FESR , type III compensator design is divided into two categories: Type III-A and Type III-B compensators. 5.1 Type III- A Compensator If the zero cased by the ESR is below half of the switching frequency, that is if (28) is valid, Type III-A compensation method is used. FLC F0 FESR FS / 2 (28) Condition (28) might happen when OSCON, POS-cap or SP-Cap types of capacitors are used at the output of the DC/DC converter. If this happens, the poles and zeros of the compensator will be placed as follows: www.irf.com AN-1162 14 FZ 2 FLC (29) FZ 1 0.75 FZ 2 0.75 FLC (30) F p 2 FESR (31) F p 3 FS / 2 (32) The approximate bode-plot of the power stage for the Type III-A compensator and the desired loop gain has been drawn in Figure 10. FLC Power Stage -40dB FESR Desired Loop Gain -20dB -20dB F0 -40dB Type III-A -20dB Compensator FZ1 FZ2 -20dB Fp2 Fp3=FS/2 Figure 10 - Bode plot of the buck converter power stage, desired loop gain, and Type III-A compensator The first zero of the compensator ( FZ 1 ) compensates the phase lag of the pole which is at the origin. The second zero ( FZ 2 ) is to compensate for one of the poles of the LC filter so that at F0 the slope of the bode plot of the loop is about -20dB/dec. The second pole of the compensator ( Fp 2 ) and the zero of the ESR of the capacitor ( FESR ) cancel each other and the third pole ( Fp 3 ) is to provide more attenuation for frequencies above FS / 2 . The parameters of the compensator can be calculated as follows. First a value for C f 3 is selected (2.2nF can be a good start). Using (26) Rf 3 is calculated: www.irf.com AN-1162 15 Rf 3 1 2 C f 3 F p 2 (33) Using (24) Rf 1 is calculated: Rf 1 1 Rf 3 2 C f 3 FZ 2 (34) Using (14), Rf 2 is calculated and RC1 is calculated using the following equation: RC1 2 F0 Lo C o Vosc Vin C f 3 (35) Using (23) calculate C C1 : C C1 1 2 RC1 FZ 1 (36) Using (27) calculate C C 2 : CC 2 1 2 RC1 F p 3 (37) 5.2 Design example of Type III-A compensator For this design, as shown in Figure 11, IR3840 regulator is used. Vin =12 V Cin = 4 X 10 uF + 330 uF R1 49.9K 4.5 V< Vcc<5.5V R2 6.8K Enable CVcc RPG 10K Vin Boot C6 0. 1 uF Lo 560nH Vcc Vout SW 1 uF PGood PGood IR3840 Seq Cf3 OCSet 2.2nF Rf3 3.24k R OCSet 402Ω Rf2 3.9nF Rt 23.2k Cc1 Gnd Comp PGnd CSS 0. 1 uF 2.94kΩ 1% 4.22kΩ + - 4.64kΩ 1% Fb Rt SS / SD Rf1 1.8V Co=2x100µF , 8mΩ each SP-Cap EEFSL0E101R Rc1 Cc2 120pF Figure 11 - Application of IR3840 with type III-A compensator for a 12A, 1.8V regulator www.irf.com AN-1162 16 Step 1 - Collect the system information such as input and output voltage and the switching frequency: Vin 12V VOut 1.8V Vref 0.7V Vosc 1.8V Lo 560nH Co 2 110 μF ESR( Co ) 8m each FS 600 KHz I o (max) 12 A Step 2 - Using (3) and (4) calculate the poles and zero of the power stage: FLC 1 14.34 KHz 2π 560nH 220 μF FESR 1 180kHz 2π (8m / 2) 220 μF Step 3 - Selected crossover frequency to be about 1/8 of the switching frequency: F0 80 KHz Step 4 - Select the type of compensator. Since FLC F0 FESR FS / 2 , Type III-A compensator is suitable for this application. Step 5 - Calculate the poles and zeros of the compensator. Using (29) to (32) the poles and zeros can be calculated: FZ 2 FLC 14.34kHz FZ 1 0.75 14.34kHz 10.8kHz Fp 2 FESR 180kHz Fp 3 600kHz / 2 300kHz Step 6 - Calculate the values of the parameters of the compensator. Choose C f 3 2.2nF . Using (33): Rf 3 1 401.9 2π 2.2nF 180kHz www.irf.com AN-1162 17 Choose Rf 3 402 . Use (34) to calculate Rf 1 : Rf 1 1 402 4.64 2π 2.2nF 14.34kHz Select Rf 1 4.64k . Using (14), Rf 2 can be calculated: Rf 2 4.64k 0.7V 2.95k ( 1.8V 0.7V ) Select Rf 2 2.94k . Use (35) to calculate RC1 : RC1 2π 80k 560nH 220 μF 1.8V 4.22k 12V 2.2nF Choose RC1 4.22k . Use (36) to calculate CC1 : CC 1 1 3.49nF 2π 4.22k 10.8k Choose CC1 3.9nF . Use (37) to calculate C C 2 : CC 2 1 125 pF 2π 4.22k 300k Choose CC 2 120 pF . The experimentally measured bode plot of the loop for this design is shown in Figure 12 which shows the loop crossover frequency is F0 77kHz and a phase-margin is about 53º. Figure 12 - The bode plot of the loop for the example with Type III-A compensator www.irf.com AN-1162 18 5.3 Type III- B compensator If the zero cased by the ESR is above half of the switching frequency, that is if (38) is valid, Type III-B compensation method is used. FLC F0 FS / 2 FESR (38) Condition (38) happens when MLCC capacitors are used at the output side of the converter. Sometimes, using POS-Cap or SP-Cap types of capacitors results in a type III-B system as well. If this happens, the poles and zeros of the compensator will be placed as follows: F p 3 FS / 2 (39) FZ 2 and Fp 2 pair (second pole and second zero of the compensator) are considered as a lead-compensator and are located so that the maximum phase lead of this pair results at crossover frequency ( F0 ). The following formulas can be used to locate FZ 2 and Fp 2 in order to get a maximum phase lead of θ at crossover frequency [3]: FZ 2 F0 1 Sinθ 1 Sinθ (40) F p 2 F0 1 Sinθ 1 Sinθ (41) θ is usually chosen to be 70º and this is about the maximum practical phase-lead obtainable from a lead compensator. The other zero of the compensator is chosen using the following formula: FZ 1 0.5 FZ 2 (42) The approximate bode-plot of the power stage, the desired loop gain and the type III-B compensator has been drawn in Figure 13. Sometimes, the value of Fp 2 calculated by (41) falls above Fp 3 . The order of the poles is not important, however, the important fact is that there are always two compensator poles above F0 as shown in Figure 13. FZ 1 compensates the phase lag of the pole which is at origin. FZ 2 and Fp 2 form a leadcompensator and provide their maximum leading phase at crossover frequency and Fp 3 provides further attenuation for frequencies above FS / 2 . www.irf.com AN-1162 19 Similar to the calculation for type III-A compensator, the parameters of the compensator can be calculated. That is, a value for C f 3 is selected and then using (33) to (37) the parameters of the compensator are calculated. Power Stage -40dB FESR FLC -20dB Desired Loop Gain -20dB F0 -40dB -20dB Type III-A -20dB Compensator FZ1 FZ2 Fp2 Fp3 Figure 13 - Bode plot of the buck converter power stage, desired loop gain, and Type III-B compensator 5.4 Design example of Type III-B compensator For this design, as shown in Figure 14, IR3842 regulator is used. Vin =12 V Cin = 2 X 10 uF + 330 uF R1 49.9K 4.5 V< Vcc<5.5V R2 6.8K Enable CVcc RPG 10K Vin C6 0. 1 uF Boot Lo 1.5µH Vcc Vout SW 1 uF PGood PGood IR3842 Seq Cf3 OCSet 2.2nF Rf3 1.87k ROCSet 127Ω Rf2 6.8nF Rt 23.2k Cc1 SS / SD Rf1 4.02kΩ 1% Fb Rt Gnd 1.8V Comp PGnd CSS 0. 1 uF 2.55kΩ 1% 2.74kΩ Co=4x22µF, 3mΩ each MLCC ECJ2FB0J226M Rc1 Cc2 180pF Figure 14 - Application of IR3842 with type III-B compensator for a 4A, 1.8V regulator www.irf.com AN-1162 20 Step 1 - Collect the system information such as input and output voltage and the switching frequency: Vin 12V VOut 1.8V Vref 0.7V Vosc 1.8V Lo 1.5 μH Co 4 10.8 μF ESR( Co ) 3m each FS 600kHz I o (max) 4 A It should be noted here that the value of the capacitance used in the compensator design must be the small signal value. Ceramic capacitors lose some portion of their capacitance as their biasing voltage increases. The MLCC capacitors which are used in this example have 22µF nominal capacitance. However, at the biasing voltage and 600kHz their capacitance drops to about 10.8µF. It is this value that must be used for all computations related to the compensation. The small signal value may be obtained from the manufacturer’s datasheets, design tools or SPICE models [4]. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency (FLC) and using equation (3) to compute the small signal value (refer to Appendix C). Step 2 - Using (3) and (4) calculate the poles and zero of the power stage: FLC 1 19.7kHz 2π 43.2 μF 1.5 μH FESR 1 4.9MHz 2π 3m 10.8 μF Step 3 - Selected crossover frequency to be 1/6 of the switching frequency: F0 100kHz Step 4 - Select the type of compensator. Since FLC F0 FS / 2 FESR , type III-B compensator is suitable for this application. Step 5 - Calculate the poles and zeros of the compensator. Using (40) and (41): www.irf.com AN-1162 21 FZ 2 100kHz 1 Sin70 17.6kHz 1 Sin70 Fp 2 100kHz 1 Sin70 567 kHz 1 Sin70 Using (42): FZ 1 0.5 17.6kHz 8.8kHz Using (39): Fp 3 600kHz / 2 300kHz Step 6 - Calculate the values of the parameters of the compensator. Choose C f 3 2.2nF . Using (33): Rf 3 1 127.6 2π 2.2nF 567k Choose Rf 3 127 . Use (34) to calculate Rf 1 : Rf 1 1 127 3.98k 2π 2.2n 17.6k Select Rf 1 4.02k . Using (14), Rf 2 can be calculated: Rf 2 4.02k 0.7V 2.56k ( 1.8V 0.7V ) Choose Rf2 2.55k . Use (35) to calculate RC1 : RC1 2π 100k 1.5 μ 43.2 μ 1.8 2.77k 12 2.2n Choose RC1 2.74k . Use (36) to calculate CC1 : CC 1 1 6.6nF 2π 2.74k 8.8k Choose C C1 6.8nF . Use (37) to calculate C C 2 : CC 2 1 193 pF 2π 2.74k 300k Choose CC 2 180 pF . The bode plot of the loop has been sketched in Figure 8 which shows the closed loop system has a crossover frequency of F0 105kHz and the phasemargin of about 51º. www.irf.com AN-1162 22 Figure 8 - The bode plot of the loop for the example with Type III-B compensator 6. Conclusion The control loop design based on regular voltage-mode error-amplifier was discussed for synchronous buck converter. When electrolytic capacitor or low performance tantalum capacitors are used a simple type II compensator can be employed. For ceramic, or high performance POS-cap or SP-Cap output capacitors, a type III compensator is usually required. Although IR3840 and IR3842 regulators were taken as examples in this application note, the proposed design method also applies to applications using other types of buck regulator/control ICs which utilize a voltage-mode error-amplifier. References [1] M. Qiao, P. Parto, and R. Amirani, “Stabilize the Buck Converter with Transconductance Amplifier,” IR-application note AN-1043, 2002. [2] Ned Mohan, Tore M. Undeland, and William P. Robbins, Power Electronics: Converters, Applications, and Design, New York: John Wiley & Sons, ISBN: 0-471-22693-9, 2003. [3] R. W. Erickson, D. Maksimovic, Fundamentals of Power Electronics, New York: Springer Science + Business Media, ISBN: 978-0-7923-7270-7, 2001. [4] P. Asadi, Y. Chen, P. Parto, “Optimal Utilization of Multi Layer Ceramic Capacitors for Synchronous Buck Converters in Point of Load Applications”, PCIM China, Shanghai, China, June 2010, pp. 233-237. www.irf.com AN-1162 23 Appendix A: Designing the Power Stage of the Synchronous Buck Converter The first step in designing a switching DC/DC converter is designing the power stage. The power stage includes the output LC filter of the converter as well as the switches and their drivers. Many factors are involved in designing the power stage including, efficiency, cost, space, EMI, acceptable output voltage ripple, transient response requirement, etc. The design requirements usually compete with each other. For example, to decrease the output voltage ripple the designer might increase the value of the inductor and/or capacitor. Increasing the value of the capacitor increases the cost and increasing the value of the inductor can decrease the efficiency and can make the transient response slower. On the other hand, the output voltage ripple can be decreased by increasing the switching frequency. However, higher switching frequency may result in less efficiency due to increased switching losses. Therefore, the designer has to find a trade off between different design requirements by going through a few design iterations. Switching frequency is usually the first parameter which is selected. In selecting the switching frequency different factors including efficiency, EMI requirements, required closed-loop bandwidth, etc are involved. The switching frequency might even be dictated by the system that the converter is going to be a part of. In this appendix the procedure of designing the power stage is briefly discussed with an example. Suppose that the switching frequency as well as the maximum output current and the input and output voltages are given. Depending on the maximum output current the appropriate switching regulator is selected. The list of IR’s integrated switching regulators and their specifications can be found on IR’s website. Among the design requirements, usually the inductor ripple current is given. If not, starting with a 40% current ripple is reasonable: I Lripple 40% I Load _ Max (A1) The inductor value can be calculated using the following equation: Lo Vin Vout Vout 1 I Lripple Vin FS www.irf.com (A2) AN-1162 24 The amplitude of the overshoot/undershoot of the transient response of the converter as well as the output voltage ripple determine the value of the output capacitor. The amplitude of the switching ripple is usually much smaller than the permissible value if an appropriate output capacitor combination is utilized. The minimum required amount of output capacitor is given by the following equation: Co _ Min Lo I Load _ Step 2 (A3) 2 Vout Vout _ Max where I Load _ Step is the maximum step load in Amps and Vout _ Max is the maximum permissible output voltage change due to transients/switching. Equation (A3) is based on having ideal output capacitors (no ESR) and infinite control-loop band-width. The required amount of output capacitance is usually higher than the value given by (A3) especially when the output capacitors have a considerable amount of ESR. However, the value calculated by (A3) is a good starting point to choose the output capacitor. Suppose the designer intends to use a type of capacitor with the value of C E . If the ESR of the capacitor could be neglected, the number of capacitors which is required would have been: N Min ( ESR 0 ) Co _ Min C E (A4) However, if each capacitor has an ESR equal to ESRE , the minimum number of required capacitors to have a satisfactory transient response is: N Min L I Vout ESRE I Load _ Step ( o Load _ Step ESRE C E )2 2 C E Lo Vout _ Max Vout _ Max Vout (A5) Usually the first integer which is greater than the value given by (A5) should be considered. For more information about (A5) refer to [A1]. The input capacitor of the converter should be able to handle the input current ripple: I in _ ripple I Load _ Max D ( 1 D ) (A6) where D is the duty cycle of the converter. If the input capacitor is comprised of multiple capacitors connected in parallel, we have: Cin N in C E _ in www.irf.com (A7) AN-1162 25 If the current ripple that each of the capacitors can handle is given by I C _ ripple _ max , then the number of capacitors which should be parallel to form Cin are: N in I in _ ripple (A8) I C _ ripple _ max It is worth mentioning that values of capacitors change as temperature, bias voltage, and operating frequency change. For example MLCC capacitors lose a considerable portion of their capacitance as their bias voltage is increased. Therefore, in all calculations throughout this document the effective value of the capacitors at the given operating condition should be considered. Design example of power stage Consider the following data is given: Vin 12V Vout 1.8V FS 600 KHz I Load _ Max 12 A (A9) I Load _ Step 6 A Vout _ Max 54mV I Lripple 4.55 A Using (A2) the value of the inductor is calculated: Lo 12 1.8 1.8 1 560nH 4.55 12 600 K (A10) Using (A3) the minimum required output capacitance is calculated: Co _ Min 560n 6 2 103 μF 2 1.8 54m (A11) Suppose the following capacitors are going to be used: C E 330 μF (A12) ESRE 12m Since C E Co _ Min , it seems that one capacitor should be enough, however using (A5) suggests: www.irf.com AN-1162 26 N Min 12m 1.8 560n 6 6 ( 12m 330 μ) 2 1.7 54m 2 330 μ 560n 54m 1.8 (A13) Therefore, 2 capacitors with the specifications given in (A12) should be used: Co 2 330 μF 660 μF ESR (A14) 12m 6m 2 Suppose the capacitors which are going to be used in input side are 3.3µF capacitors which can handle a maximum of 1.3A. The input current ripple is: I in _ ripple 12 1.8 / 12 ( 1 1.8 / 12 ) 4.28 Arms (A15) N in 4.28 / 1.4 3.3 (A16) Therefore, the minimum numbers of capacitors which should be paralleled at the input are 4 capacitors. References: [A1] C. Qiao, J. Zhang, P. Parto, and D. Jauregui, “Output Capacitor Comparison for Low Voltage High Current Applications,” in Proc. IEEE 35th Power Electronics Specialists Conference, Aachen, Germany, June 2004, pp. 622-628. www.irf.com AN-1162 27 Appendix B: Some Special Cases of Compensator Design The guidelines provided earlier in this document on compensator design are general guidelines which result in appropriate values for the compensator parameters in most cases. However, sometimes fine tuning might be desirable. That is, the designer might want to adjust the locations of the zeros and poles of the compensator (by a few design iterations) to get better/optimized results. There might be extreme conditions where fine tuning is necessary. In this appendix, one extreme condition in which the designer must adjust the compensation is discussed by an example. In some extreme conditions, the values of inductor and capacitor in the power stage may become too large so that the resonance frequency, FLC , becomes too low compared to the cross over frequency ( F0 ). In such conditions, if the compensator type III-B is used, the resulting bode-plot of the loop might not be appropriate. Therefore, some modifications in the design procedure are required. Such cases are demonstrated by an example. Consider a synchronous buck converter with the parameters given by (B1). The designer has been conservative in keeping the inductor current ripple and output voltage ripple/transient very low. Vin 16V Vout 2.5V Vref 0.7V Vosc 1.8V Lo 4.7 μH RLo 13m (B1) Co 9 47 μF ESR( Co ) 3m each FS 600 KHz I O _ Max 2 A F0 100kHz At the specified output voltage, the effective value of each output capacitor is about 16µF. Therefore: www.irf.com AN-1162 28 FLC 1 6.12kHz 2π 4.7 μH 9 16 μF (B2) FESR 1 3.3M 2π 16 μF 3m (B3) Since FLC F0 FS / 2 FESR , type III-B compensator is used. Using (39)-(42) the poles and zeros of the compensator are calculated as follows: FZ 2 100kHz 1 Sin70 17.6kHz 1 Sin70 (B4) Fp 2 100kHz 1 Sin 70 567 kHz 1 Sin70 (B5) FZ 1 0.5 17.6kHz 8.8kHz (B6) Fp 3 600kHz / 2 300kHz (B7) Now the values of the parameters of the compensator are calculated. If the value of 2.2nF is selected for Cf 3 , the following values are resulted: Rf 3 1 127 2π 2.2nF 567k (B8) Rf 1 1 127 4.02k 2π 2.2n 17.6k (B9) RC1 2π 100k 4.7 μ 144 μ 1.8 21.5k 16 2.2n (B10) CC 1 1 0.82nF 2π 8.8k 21.5k (B11) CC 2 1 24 pF 2π 21.5k 300k (B12) It is noticed that the value of RC1 is relatively large (>20kΩ) whereas CC1 and CC 2 are relatively small. If a larger value for C f 3 had been chosen, more reasonable values for RC1 , CC1 , and CC 2 would have been resulted. Apart from this, considering the bode plot of the loop, which is obtained by simulation and is presented in Figure B1, it is clear that the behavior of the phase of the loop is not appropriate. The phase drops to below 0º at about 9kHz which makes the system conditionally stable. www.irf.com AN-1162 29 It should be noted that the bode-plot sketched in Figure B1 is based on the average model for the buck converter. Therefore, it is valid only up to half of the switching frequency. 80 180 70 150 60 120 50 60 Gain (db) 30 20 30 10 0 0 -30 -10 -60 -20 -90 -30 -120 -40 -50 -60 100 Phase (Degree) 90 40 -150 95,700 1,000 10,000 100,000 -180 1,000,000 Frequency (Hz) Figure B1 - The bode plot of the loop for the example with Type III-B compensator shows a bandwidth of 95.7kHz and a phase margin of 50º The reason for the phase drop at about 9kHz is that the pole and zero selection has been done to secure enough phase-margin at the loop cross-over frequency. The cross-over frequency is much higher than the resonance frequency ( FLC or double-pole frequency). Consequently, both zeros of the compensator are above the resonance frequency where the double pole causes 180 degrees phase-drop. Technically, it is required to have the zeros at about FLC or even at lower frequencies. Therefore, when the procedure of type III-B compensator design is followed, if the calculated zeros of the compensator are both above FLC , modifications in the procedure are required as follows: - Design for lower loop Bandwidth (1/10 of the switching frequency). - Place the zeros of the compensator according to type III-A compensator design procedure. There are two reasons to design for lower loop bandwidth. First, due to relatively large value of the selected output capacitors, usually there is no need to design for a high loop www.irf.com AN-1162 30 bandwidth to achieve satisfactory transient response. Second, when the resonance frequency of the regulator is much lower than the designed loop bandwidth, a relatively high gain-bandwidth is demanded from the error amplifier. Therefore, to avoid running into the gain-bandwidth-product limitation of the error amplifier, it is recommended to design for a lower loop bandwidth. In this case, we design the loop for a BW of 60kHz. Placing the zeros of the compensator according to the type III-A compensator design procedure, moves the zeros to lower frequencies. This, in turn, reduces the gain at low frequencies. However, according to Figure B1, the low-frequency gain is relatively large (G(100Hz)>60dB), therefore, reducing the low-frequency gain is acceptable. Equations (B5) or (41) can still be used to calculate the location of the second pole of the compensator. The poles and zeros of the compensator which is going to be designed are: FZ 2 6.2kHz (B13) Fp 2 340kHz (B14) FZ 1 0.75 6.2kHz 4.65kHz (B15) Fp 3 600kHz / 2 300kHz (B16) The design procedure is started with Cf 3 2.2nF . Now, the values of the components can be calculated: C f 3 2.2nF R f 3 215 R f 1 11.5k R f 2 4.42k (B17) RC1 12.4k CC1 2.7 nF CC 2 43 pF With the above component values for the compensator, the bode plot of the loop is measured and presented in Figure B2. The bode plot shows that the phase-dip around 9kHz does not go below 45º and the phase margin has increased by 9º. www.irf.com AN-1162 31 Figure B2 - The bode plot of the loop for the example with modified Type III compensator shows a bandwidth of 62kHz and a phase margin of 59º www.irf.com AN-1162 32 Appendix C: Loop Response Measurement A properly measured loop response will allow measurement of control bandwidth and phase margin. In addition, it allows estimation of actual or effective output capacitance in a circuit. Control bandwidth indicates the speed of the system in responding to load transients and phase margin is a very important indication of robustness of stability of the closed loop system. A PWM DC-DC converter exhibits time-varying effects above half of the switching frequency and any measurements at such frequencies have no basis for comparison with averaged model designs and predictions which do not account for the time-varying effects. This implies that it does not serve any purpose to measure the loop response at frequencies approaching or exceeding half of the switching frequency. At very low frequencies and at very high frequencies, the measurement is susceptible to noise, because of the very high and very low loop gains respectively. For typical values of L and C used in POL designs, the LC resonant poles lie between 1 kHz and 30 kHz, and any loop measurement must clearly show this region. For a switching frequency of 600 kHz, used in IR’s integrated buck regulator designs (SupIRBuckTM) for most POL applications, loop response measurement in the range of 1kHz -150 kHz is sufficient. Figure C1 shows the general schematic for a family of SupIRBucks. This schematic is used to show how the loop response in measured. The measurement technique can similarly be used for any other IR’s SupIRBucks. The three test points (A, B, and C) which are used for loop-response measurement have been indicated by solid circles. To measure the loop response the following steps should be taken: • Using a network analyzer, apply a 15mV-30mV perturbation signal between test points A and B. • Set up the network analyzer to measure v(B)/v(A). • Set the frequency range of measurement between 1 kHz and 150 kHz. • Measure the control bandwidth as the frequency at which the loop gain response crosses 0 dB. www.irf.com AN-1162 33 • Measure the phase margin as the loop phase response at the loop gain crossover frequency. C VCC R19 1 R14 C7 0.1uF 4 5 R9 6 Vcc- C10 Vcc+ 13 14 Boot Enable IR384x/3x AGnd1 Rt SS VCC 1 + Vin 2 C30 C29 C28 C27 C20 C19 C18 10 PGnd R12 C13 0.1uF 1 1 VCC COMP AGnd2 R3 C1 + C21 C17 C16 C15 C14 0.1uF Vout + C22 15 C31 0.1uF C2 L1 11 SW PGood 3 C3 12 Vin FB 8 C26 R1 C4 0 Vcc 2 9 C11 U1 Seq/Vp OCset 1 7 R28 C5 C24 R10 R4 C6 C25 R16 C8 R2 R15 R18 Seq./VDDQ Q1 R17 C9 R6 A B Figure C1 - The typical schematic of a family of IR’s SupIRBucks and the associated test points which are used for frequency response measurements. Figure C2 shows the result of a typical frequency response measurement. The figure shows that the control loop bandwidth is 100.98kHz and the phase-margin is 47.975º. Control bandwidth=100.98 kHz Phase margin =47.9750 Figure C2 - The result of loop frequency-response measurement for a typical POL application which is the amplitude and phase of v(B)/v(A) versus frequency www.irf.com AN-1162 34 Ideally the loop frequency response should not depend on the output current of the rail. However, due to the dead-times of the switches and some other factors, the frequency response changes with load current to some extent. Usually the loop response should be measured at nominal current of the rail. In addition, at the current that the loop response is measured the converter must operate without jitter. Another frequency response which provides useful information is the power stage frequency response. To measure the frequency response of the power stage the following procedure should be followed: Using a network analyzer, apply a 15mV-30mV perturbation signal between test • points A and B. • Set up the network analyzer to measure v(B)/v(C). • Set the frequency range of measurement between 1 kHz and 150 kHz. • Measure the resonant frequency fLC of the LC output filter. • Measure the amplitude of the frequency response at low frequencies (G_Power_Stage_DC). This value is measured in dB scale. • With L known, compute the effective value of output capacitance using (C1). • Use (C2) to estimate the amplitude of the ramp signal in the modulator. Co 1 2 4π f LC L (C1) 2 Vin Vosc 10 (C2) G _ Power _ Stage _ DC ( ) 20 Using (C1) the effective / small-signal value of the output capacitance is obtained. This value should be used in all computations related to compensator design. Obtaining the effective value of the output capacitance is especially important when ceramic capacitors are used, since ceramic capacitors considerably loose their capacitance as bias voltage is increased. The small signal value of the output capacitors may also be obtained from the manufacturer’s datasheets and design tools. The amplitude of the ramp signal, Vosc , is also required in the process of compensator design. This value can be obtained from the datasheet as well. Figure C3 shows the frequency response of a typical power stage. www.irf.com AN-1162 35 Figure C3 - The frequency response of a typical power stage showing the resonance frequency If, for instance, a 1µH inductor is used, the effective value of the output capacitance is: Co 1 104 μF 4π (15.61kHz) 21μH (C3) 2 Figure C3 shows that at low frequencies the gain of the power stage is about 16.98dB. Therefore, assuming the input voltage is 12V, the amplitude of the ramp signal will be: Vosc 12 10 ( 16.98 ) 20 www.irf.com 1.7V (C4) AN-1162 36