DATASHEET 40V Radiation Hardened and SET Enhanced Precision Low Power Operational Amplifier ISL70219ASEH, ISL70419ASEH Features The ISL70219ASEH and ISL70419ASEH are a family of very high precision amplifiers featuring the perfect combination of low noise vs power consumption. Low offset voltage, low IBIAS current and low temperature drift making them the ideal choice for applications requiring both high DC accuracy and AC performance. The combination of high precision, low noise, low power and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. • Electrically screened to DLA SMD# 5962-14226 Applications for these amplifiers include precision active filters, medical and analytical instrumentation, precision power supply controls and industrial controls. The ISL70219ASEH is offered in a 10 lead hermetic ceramic flatpack. The ISL70419ASEH is offered in a 14 lead hermetic ceramic flatpack package. The devices are packaged in industry standard pin configurations and operate across the extended temperature range from -55°C to +125°C. Related Literature • UG007, “ISL70219ASEH Evaluation Board User Guide” • TR002, “Single Event Effects (SEE) Testing of the ISL70219ASEH Dual Operational Amplifier” • ISL70219ASEH SMD 5962-14226 • Low input offset voltage. . . . . . . . . . . . . . . . . . . .±110µV, max • Superb offset temperature coefficient. . . . . . . . 1µV/°C, max • Input bias current . . . . . . . . . . . . . . . . . . . . . . . . . .±15nA, max • Input bias current TC . . . . . . . . . . . . . . . . . . . . ±5pA/°C, max • Low current consumption . . . . . . . . . . . . . . . . . . . . . . . 440µA • Voltage noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8nV/√Hz • Wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 36V • Operating temperature range. . . . . . . . . . . .-55°C to +125°C • Radiation environment - SEB LETTH (VS = ±18V) . . . . . . . . . . . . . .86.4 MeV•cm2/mg - SET recovery time . . . . . . . . . . . ≤10µs at 60 MeV•cm2/m - SEL immune (SOI process) - Total dose HDR (50 to 300rad(Si)/s). . . . . . . . 300krad(Si) - Total dose LDR (10mrad(Si)/s) . . . . . . . . . . . 100krad(Si) * * Product capability established by initial characterization. The EH version is acceptance tested on a wafer-by-wafer basis to 50krad(Si) at low dose rate. Applications • ISL70219ASEH Radiation Test Report • Precision instrumentation • Spectral analysis equipment • Active filter blocks, thermocouples and RTD reference buffers • Data acquisition and power supply control 16 C1 14 V+ R1 R2 1.84k 4.93k ISL70X19ASEH VIN OUTPUT + 3.3nF SET DURATION (µs) 8.2nF 12 10 8 6 4 2 C2 V- 0 -8 -6 -4 -2 0 2 4 SET EXTREME DEVIATION (V) FIGURE 1. TYPICAL APPLICATION: SALLEN-KEY LOW PASS FILTER (FC = 10kHz) October 27, 2014 FN8459.0 1 FIGURE 2. SET DEVIATION vs DURATION FOR LET = 60 MeV•cm2/mg (VS = ±18V) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL70219ASEH, ISL70419ASEH Pin Configurations ISL70419ASEH6 (14 LD FLATPACK) TOP VIEW ISL70219ASEH (10 LD FLATPACK) TOP VIEW V+ 1 10 -INA 2 9 OUTB +INA 3 8 -INB NC 4 7 +INB V- 5 6 LID OUTA A - + B + - 14 OUTD 13 -IND 3 12 +IND V+ 4 11 V- +INB 5 10 +INC 9 -INC 8 OUTC OUTA 1 -INA 2 +INA -INB 6 OUTB 7 A - + D + - - + B + C Pin Descriptions 10 LD PIN NUMBER 14 LD PIN NUMBER PIN NAME EQUIVALENT ESD CIRCUIT 1 1 OUTA Circuit 2 Amplifier A output 2 2 -INA Circuit 1 Amplifier A inverting input 3 3 +INA Circuit 1 Amplifier A noninverting input 10 4 V+ Circuit 3 Positive power supply 7 5 +INB Circuit 1 Amplifier B noninverting input 8 6 -INB Circuit 1 Amplifier B inverting input 9 7 OUTB Circuit 2 Amplifier B output - 8 OUTC Circuit 2 Amplifier C output - 9 -INC Circuit 1 Amplifier C inverting input - 10 +INC Circuit 1 Amplifier C noninverting input 5 11 V- Circuit 3 Negative power supply - 12 +IND Circuit 1 Amplifier D noninverting input - 13 -IND Circuit 1 Amplifier D inverting input - 14 OUTD Circuit 2 Amplifier D output - E-Pad E-Pad None 4 - NC - 6 - LID NA E-Pad under package (unbiased, tied to package lid) No connect Unbiased, tied to package lid V+ 500Ω V+ 500Ω IN- IN+ Submit Document Feedback VCIRCUIT 2 2 V+ CAPACITIVELY COUPLED ESD CLAMP OUT V- CIRCUIT 1 DESCRIPTION V- CIRCUIT 3 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Ordering Information ORDERING/SMD NUMBER (Note 2) PART NUMBER (Note 1) TEMP RANGE (°C) PACKAGE (RoHS Compliant) 5962F1422602VYC ISL70219ASEHVF -55 to +125 10 Ld Flatpack 5962F1422602V9A ISL70219ASEHVX -55 to +125 Die ISL70219ASEHF/PROTO ISL70219ASEHF/PROTO -55 to +125 10 Ld Flatpack ISL70219ASEHF/SAMPLE ISL70219ASEHVX/SAMPLE -55 to +125 Die 5962F1422603VXC (Coming Soon) ISL70419ASEHVF -55 to +125 14 Ld Flatpack 5962F1422603V9A (Coming Soon) ISL70419ASEHVX -55 to +125 Die ISL70419ASEHF/PROTO (Coming Soon) ISL70419ASEHF/PROTO -55 to +125 14 Ld Flatpack ISL70419ASEHF/SAMPLE (Coming Soon) ISL70419ASEHVX/SAMPLE -55 to +125 Die ISL70219ASEHEV1Z ISL70219ASEHEV1Z Evaluation Board ISL70419ASEHEV1Z (Coming Soon) ISL70419ASEHEV1Z Evaluation Board PKG. DWG. # K10.A K10.A K14.C K14.C NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the “Ordering Information” table must be used when ordering. Submit Document Feedback 3 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Absolute Maximum Ratings Thermal Information Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Supply Voltage (Note 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V Max/Min Input Current for Input Voltage >V+ or <V - . . . . . . . . . . . . . . . ±20mA Output Short-Circuit Duration (1 output at a time). . . . . . . . . . . . . . . . Indefinite ESD Rating Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 2kV Machine Model (Tested per EIA/JESD22-A115-A) . . . . . . . . . . . . . . 200V Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 10 Ld Flatpack Package (Notes 3, 4). . . . . 40 8 14 Ld Flatpack Package (Notes 3, 4). . . . . 35 8 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Recommended Operating Conditions Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 36.0V Split Rail Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2.25V to ±18V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 4. For JC, the “case temp” location is the center of the package underside. 5. Tested in a heavy ion environment at LET = 86.4MeV•cm2/mg at +125°C (TC) for SEB. Refer to Single Event Effects Test Report for more information. Electrical Specifications VS = ±18.0V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s or over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s, unless otherwise noted. PARAMETER VOS DESCRIPTION TEST CONDITIONS Input Offset Voltage TCVOS Offset Voltage Drift (Note 7) IB Input Bias Current TA = +25°C TA = -55°C, +125°C TA = +25°C, post HDR/LDR Rad TCIB Input Bias Current Temperature Coefficient (Note 7) IOS Input Offset Current TA = +25°C TCIOS VCM CMRR PSRR MIN (Note 6) TYP MAX (Note 6) UNITS - 10 85 µV - - 110 µV - 0.1 1 µV/°C -2.5 0.08 2.5 nA -5 - 5 nA -15 - 15 nA -5 1 5 pA/°C -2.5 0.08 2.5 nA TA = -55°C, +125°C -3 - 3 nA TA = +25°C, post HDR/LDR Rad -10 - 10 nA Input Offset Current Temperature Coefficient (Note 7) -3 0.42 3 pA/°C Input Voltage Range Guaranteed by CMRR test -16 - 16 V Common-Mode Rejection Ratio VCM = -16V to +16V 120 145 - dB 120 - - dB 120 145 - dB 120 - - dB 3,000 14,000 - V/mV 16.5 16.7 - V 16.2 - - V 16.3 16.5 - V 16.0 - - V Power Supply Rejection Ratio VS = ±2.25V to ±20V AVOL Open-loop Gain VO = -16V to +16V, RL = 10kΩ to ground VOH Output Voltage High RL = 10kΩ to ground RL = 2kΩ to ground Submit Document Feedback 4 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Electrical Specifications VS = ±18.0V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s or over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s, unless otherwise noted. (Continued) PARAMETER VOL DESCRIPTION Output Voltage Low MIN (Note 6) TYP MAX (Note 6) UNITS - -16.7 -16.5 V - - -16.2 V - -16.5 -16.3 V - - -16.0 V - 0.49 0.725 mA - - 0.85 mA Sourcing: VIN = 0V, VOUT = -16V (Note 7) - 41 - mA Sinking: VIN = 0V, VOUT = +16V (Note 7) - -42 ±2.25 - ±20 V TEST CONDITIONS RL = 10kΩ to ground RL = 2kΩ to ground IS ISC VSUPPLY Supply Current/Amplifier Output Short-circuit Current Supply Voltage Range Guaranteed by PSRR mA AC SPECIFICATIONS GBWP Gain Bandwidth Product AV = 1k, RL = 2kΩ (Note 7) - 1.5 - MHz enVp-p Voltage Noise VP-P 0.1Hz to 10Hz (Note 7) - 0.25 - µVP-P en Voltage Noise Density f = 10Hz (Note 7) - 10 - nV/√Hz en Voltage Noise Density f = 100Hz (Note 7) - 8.2 - nV/√Hz en Voltage Noise Density f = 1kHz (Note 7) - 8 - nV/√Hz en Voltage Noise Density f = 10kHz (Note 7) - 8 - nV/√Hz in Current Noise Density f = 1kHz (Note 7) - 0.1 - pA/√Hz 0.3 0.5 - V/µs 0.2 - - V/µs 130 450 ns TRANSIENT RESPONSE SR tr, tf, Small Signal ts tOL OS+ OS- Slew Rate, VOUT 20% to 80% AV = 1, RL = 2kΩVO = 4VP-P Rise Time 10% to 90% of VOUT AV = 1, VOUT = 50mVP-P, RL = 10kΩto VCM - - 625 ns Fall Time 90% to 10% of VOUT AV = 1, VOUT = 50mVP-P, RL = 10kΩto VCM - 130 600 ns - - 700 ns Settling Time to 0.1% 10V Step; 10% to VOUT AV = -1, VOUT = 10VP-P, RL = 5kΩto VCM (Note 7) - 21 - µs Settling Time to 0.01% 10V Step; 10% to VOUT AV = -1, VOUT = 10VP-P, RL = 5kΩto VCM (Note 7) - 24 - µs Settling Time to 0.1% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, RL = 5kΩto VCM (Note 7) - 13 - µs Settling Time to 0.01% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, RL = 5kΩto VCM (Note 7) - 18 - µs Output Positive Overload Recovery Time AV = -100, VIN = 0.2VP-P, RL = 2kΩto VCM (Note 7) - 5.6 - µs Output Negative Overload Recovery Time AV = -100, VIN = 0.2VP-P, RL = 2kΩto VCM (Note 7) - 10.6 - µs Positive Overshoot AV = 1, VOUT = 10VP-P, Rf = 0Ω RL = 2kΩto VCM - 15 - % - - 33 % AV = 1, VOUT = 10VP-P, Rf = 0Ω RL = 2kΩto VCM - 15 - % - - 33 % Negative Overshoot Submit Document Feedback 5 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Electrical Specifications VS = ±5.0V, VCM = VO = 0V, RL = Open, TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s or over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s, unless otherwise noted. MIN (Note 6) TYP MAX (Note 6) UNITS - 10 150 µV - - 250 µV - 0.1 1 µV/°C -2.5 0.08 2.5 nA TA= -55°C, +125°C -5 - 5 nA TA= +25°C, post HDR/LDR Rad -15 - 15 nA -5 1 5 pA/°C -2.5 0.3 2.5 nA TA= -55°C, +125°C -3 - 3 nA TA= +25°C, post HDR/LDR Rad -10 - 10 nA Input Offset Current Temperature Coefficient (Note 7) -3 0.42 3 pA/°C Input Voltage Range Guaranteed by CMRR test -3 3 V Common-mode Rejection Ratio VCM = -3V to +3V PARAMETER VOS DESCRIPTION TEST CONDITIONS Input Offset Voltage TCVOS Offset Voltage Drift (Note 7) IB Input Bias Current TA= +25°C TCIB Input Bias Current Temperature Coefficient (Note 7) IOS Input Offset Current TA= +25°C TCIOS VCM CMRR 120 145 dB 120 PSRR Power Supply Rejection Ratio VS = ±2.25V to ±5V 120 AVOL Open-loop Gain VO = -3.0V to +3.0V RL = 10kΩ to ground VOH Output Voltage High RL = 10kΩ to ground dB 145 dB 3,000 14,000 V/mV 3.5 3.7 V 120 dB 3.2 RL = 2kΩ to ground 3.3 V 3.55 V 3.0 VOL Output Voltage Low RL = 10kΩ to ground -3.7 RL = 2kΩ to ground IS V -3.55 Supply Current/Amplifier 0.47 -3.5 V -3.2 V -3.3 V -3.0 V 0.675 mA 0.8 mA AC SPECIFICATIONS GBWP Gain Bandwidth Product AV = 1k, RL = 2kΩ (Note 7) enVp-p Voltage Noise VP-P 0.1Hz to 10Hz (Note 7) - 0.25 - µVP-P en Voltage Noise Density f = 10Hz (Note 7) - 12 - nV/√Hz en Voltage Noise Density f = 100Hz (Note 7) - 8.6 - nV/√Hz en Voltage Noise Density f = 1kHz (Note 7) - 8 - nV/√Hz en Voltage Noise Density f = 10kHz (Note 7) - 8 - nV/√Hz in Current Noise Density f = 1kHz (Note 7) - 0.1 - pA/√Hz Submit Document Feedback 6 1.5 MHz FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Electrical Specifications VS = ±5.0V, VCM = VO = 0V, RL = Open, TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s or over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s, unless otherwise noted. (Continued) PARAMETER DESCRIPTION TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS TRANSIENT RESPONSE SR Slew Rate, VOUT 20% to 80% AV = 1, RL = 2kΩVO = 4VP-P (Note 7) - 0.5 - V/µs Rise Time 10% to 90% of VOUT AV = 1, VOUT = 50mVP-P, RL = 10kΩto VCM (Note 7) - 130 - ns Fall Time 90% to 10% of VOUT AV = 1, VOUT = 50mVP-P, RL = 10kΩto VCM (Note 7) - 130 - ns Settling Time to 0.1% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, RL = 5kΩto VCM (Note 7) - 12 - µs Settling Time to 0.01% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, RL = 5kΩto VCM (Note 7) - 19 - µs Output Positive Overload Recovery Time AV = -100, VIN = 0.2VP-P, RL = 2kΩto VCM (Note 7) - 7 - µs Output Negative Overload Recovery Time AV = -100, VIN = 0.2VP-P, RL = 2kΩto VCM (Note 7) - 5.8 - µs OS+ Positive Overshoot AV = 1, VOUT = 10VP-P, Rf = 0Ω RL = 2kΩto VCM (V) - 15 - % OS- Negative Overshoot AV = 1, VOUT = 10VP-P, Rf = 0Ω RL = 2kΩto VCM (Note 7) - 15 - % tr, tf, Small Signal ts tOL Electrical Specifications VS = ±2.25V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s or over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s, unless otherwise noted. VOS MAX (Note 6) UNITS 10 150 µV 250 µV 0.1 1 µV/°C -2.5 0.18 2.5 nA TA = -55°C, +125°C -5 - 5 nA TA = +25°C, post HDR/LDR Rad -15 - 15 nA -5 1 5 pA/°C -2.5 0.3 2.5 nA TA = -55°C, +125°C -3 - 3 nA TA = +25°C, post HDR/LDR Rad -10 - 10 nA Input Offset Current Temperature Coefficient (Note 7) -3 0.42 3 pA/°C Input Voltage Range Guaranteed by CMRR Test 0.25 V Common-mode Rejection Ratio VCM = -0.25V to +0.25V DESCRIPTION TEST CONDITIONS Input Offset Voltage TCVOS Offset Voltage Drift (Note 7) IB Input Bias Current TA = +25°C TCIB Input Bias Current Temperature Coefficient (Note 7) IOS Input Offset Current TA = +25°C TCIOS VCM CMRR MIN (Note 6) TYP PARAMETER -0.25 90 90 Submit Document Feedback 7 110 dB dB FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Electrical Specifications VS = ±2.25V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s or over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s, unless otherwise noted. PARAMETER VOH DESCRIPTION Output Voltage High TEST CONDITIONS RL = 10kΩ to ground MIN (Note 6) TYP 0.8 1.03 MAX (Note 6) V 0.5 RL = 2kΩ to ground 0.75 V 0.98 V 0.45 VOL Output Voltage High RL = 10kΩ to ground RL = 2kΩ to ground UNITS V -1.03 -0.98 -0.8 V -0.5 V -0.75 V -0.45 V NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. Guaranteed by characterization, not tested. Submit Document Feedback 8 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. 40 40 20 20 OFFSET VOLTAGE (µV) OFFSET VOLTAGE (µV) Typical Performance Curves 0 -20 -40 -60 -20 -40 -60 -80 -80 -100 -75 0 -25 25 75 125 -100 -75 175 -25 TEMPERATURE (°C) FIGURE 3. VOS vs TEMPERATURE (±18V) 125 175 0.05 0 20 -0.05 0 BIAS CURRENT (nA) OFFSET VOLTAGE (µV) 75 FIGURE 4. VOS vs TEMPERATURE (±5V) 40 -20 -40 -60 -0.10 -0.15 -0.20 -0.25 -0.30 -80 -100 -75 -0.35 -25 25 75 125 -0.4 -75 175 -25 TEMPERATURE (°C) 25 75 125 175 TEMPERATURE (°C) FIGURE 5. VOS vs TEMPERATURE (±2.5V) FIGURE 6. IBIAS vs TEMPERATURE 0.4 0.35 0.30 BIAS CURRENT (nA) 0.3 0.25 BIAS CURRENT (nA) 25 TEMPERATURE (°C) 0.20 0.15 0.10 0.05 0 0.2 0.1 0 -0.1 -0.05 -0.1 -75 -0.2 -25 25 75 125 TEMPERATURE (°C) FIGURE 7. IBIAS vs TEMPERATURE (±5V) Submit Document Feedback 9 175 -75 -25 25 75 125 175 TEMPERATURE (°C) FIGURE 8. IBIAS vs TEMPERATURE (±2.5V) FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 1.4 0.80 ±2.5V 1.2 ±5.0V SUPPLY CURRENT (mA) OFFSET CURRENT (nA) 0.75 0.70 0.65 ±18V 0.60 0.55 ±5.0V 1.0 ±18V 0.8 ±2.5V 0.6 0.4 0.2 0.5 -75 -25 25 75 125 0 -75 175 -25 25 125 175 FIGURE 10. SUPPLY CURRENT vs TEMPERATURE FIGURE 9. OFFSET CURRENT vs TEMPERATURE 25000 -135 20000 PSRR (dB) AVOL (V/mV) 75 TEMPERATURE (°C) TEMPERATURE (°C) -140 15000 10000 -75 -50 -25 0 25 50 75 100 125 -145 -70 150 -50 -30 -10 TEMPERATURE (°C) 10 30 50 70 90 110 130 TEMPERATURE (°C) FIGURE 11. AVOL vs TEMPERATURE (VO = ±13V) FIGURE 12. PSRR vs TEMPERATURE (±2.25V TO ±20V) -130 70 -135 60 SUPPLY CURRENT (mA) ±2.5V CMRR (dB) -140 -145 -150 -155 -160 -75 50 ±5.0V 40 ±18V 30 20 10 -50 -25 0 25 50 75 100 TEMPERATURE (°C) FIGURE 13. CMRR vs TEMPERATURE Submit Document Feedback 10 125 150 0 -75 -25 25 75 125 175 TEMPERATURE (°C) FIGURE 14. ISC vs TEMPERATURE FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 100 2.0 80 1.8 -55°C 60 ±5.0V 1.4 20 +25°C 0 -20 1.2 1.0 -60 0.4 -80 0.2 0 5 10 15 ±2.5V 0.8 0.6 +125°C -40 -100 ±18V 1.6 40 VOH (V) OFFSET VOLTAGE (µV) Typical Performance Curves 20 25 30 35 0 -75 40 -25 2.0 175 ±5.0V 1.4 ±5.0V 1.4 ±18V 1.6 ±18V 1.6 1.2 VOH (V) 1.2 VOH (V) 125 1.8 1.8 1.0 ±2.5V 0.8 1.0 ±2.5V 0.8 0.6 0.6 0.4 0.4 0.2 0.2 -25 25 75 125 0 -75 175 -25 25 75 125 175 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 17. VOH vs TEMPERATURE (RL = 5k) FIGURE 18. VOH vs TEMPERATURE (RL = 10k) 2.5 2.0 1.8 2.0 ±5.0V 1.4 ±5.0V 1.5 ±18V 1.6 ±18V VOL (V) VOL (V) 75 FIGURE 16. VOH vs TEMPERATURE (RL = 2k) FIGURE 15. VOS vs VCM (±18V) 0 -75 25 TEMPERATURE (°C) COMMON MODE VOLTAGE (V) 1.0 ±2.5V 1.2 1.0 ±2.5V 0.8 0.6 0.5 0.4 0.2 0 -75 -25 25 75 125 TEMPERATURE (°C) FIGURE 19. VOL vs TEMPERATURE (RL = 2k) Submit Document Feedback 11 175 0 -75 -25 25 75 TEMPERATURE (°C) 125 175 FIGURE 20. VOL vs TEMPERATURE (RL = 5k) FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 250 1.8 1.6 200 INPUT NOISE VOLTAGE (nV) ±18V ±5.0V 1.4 VOL (V) 1.2 1.0 ±2.5V 0.8 0.6 0.4 0.2 0 -75 -25 25 75 125 150 100 50 0 -50 -100 -150 V+ = 36.4V -200 Rg = 10, Rf = 100k -250 175 AV = 10,000 0 1 2 3 4 7 8 9 10 1 VS = ±18.2V AV = 1 10 1 10 100 1k 10k 0.1 100k FREQUENCY (Hz) GAIN 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 25. OPEN-LOOP GAIN, PHASE vs FREQUENCY (RL = 10kΩ CL = 10pF) Submit Document Feedback 12 10 100 1k 10k 100k FIGURE 24. INPUT NOISE CURRENT SPECTRAL DENSITY OPEN LOOP GAIN (dB)/PHASE (°) PHASE 10 1 FREQUENCY (Hz) FIGURE 23. INPUT NOISE VOLTAGE SPECTRAL DENSITY 200 180 160 140 120 100 80 60 40 20 0 -20 -40 RL = 10k -60 CL = 10pF -80 SIMULATION -100 0.1m 1m 10m 100m 1 VS = ±18.2V AV = 1 INPUT NOISE CURRENT (pA/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) 100 OPEN LOOP GAIN (dB)/PHASE (°) 6 FIGURE 22. INPUT NOISE VOLTAGE (0.1Hz TO 10Hz) FIGURE 21. VOL vs TEMPERATURE (RL = 10k) 1 5 TIME (s) TEMPERATURE (°C) 200 180 160 140 120 100 80 60 40 20 0 -20 -40 RL = 10k -60 CL = 100pF -80 SIMULATION -100 0.1m 1m 10m 100m 1 PHASE GAIN 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 26. OPEN LOOP FREQUENCY RESPONSE (RL = 10kΩ, CL = 100pF) FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 0 0 -10 ±2.5 -20 -20 -30 PSRR (dB) -40 CMRR (dB) ±5V -40 -50 -60 -80 -60 -80 ±5V -70 ±18V -100 ±18V -90 -100 ±2.5 1 10 100 1k 10k 100k 1M -120 10M 1 10 100 FREQUENCY (Hz) FIGURE 27. CMRR vs SUPPLY VOLTAGE (+25°C) 10k 100k 1M 10M FIGURE 28. PSRR vs SUPPLY VOLTAGE (+25°C) 80 80 ACL1000 ACL1000 60 60 ACL100 ACL100 40 GAIN (dB) 40 GAIN (dB) 1k FREQUENCY (Hz) 20 0 ACL10 -20 20 0 ACL10 -20 ACL1 ACL1 -40 -40 -60 100 1k 10k 100k 1M -60 100 10M 1k 10k FREQUENCY (Hz) 100k 1M 10M FREQUENCY (Hz) FIGURE 29. FREQUENCY RESPONSE vs ACL (±2.5V) FIGURE 30. FREQUENCY RESPONSE vs ACL (±5.0V) 80 4 ACL1000 60 2 NORMALIZED GAIN (dB) ACL100 GAIN (dB) 40 20 0 ACL10 -20 ACL1 -40 RF = RG = 100k RF = RG = 10k 0 RF = RG = 100 -2 RF = RG = 1k -4 -6 -8 -60 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 31. FREQUENCY RESPONSE vs ACL (±18.0V) Submit Document Feedback 13 10M -10 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 32. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE (±2.5V) FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Typical Performance Curves 4 Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 4 RF = RG = 100k 2 RF = RG = 10k 0 -2 RF = RG = 1k -4 RF = RG = 100 -6 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 2 -8 -10 RF = RG = 100k RF = RG = 10k 0 -2 RF = RG = 1k -4 RF = RG = 100 -6 -8 1k 10k 100k 1M -10 1k 10M 10k FREQUENCY (Hz) FIGURE 33. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE (±5.0V) 4 RL = 5kΩ RL = 10kΩ 2 RL = 1kΩ RL = 1kΩ 0 GAIN (dB) GAIN (dB) 10M RL = 5kΩ RL = 10kΩ 2 0 RL = 500Ω -2 -4 -6 -2 RL = 500Ω -4 RL=100Ω -6 RL = 100Ω -8 -8 1k 10k 100k 1M -10 1k 10M 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 35. FREQUENCY RESPONSE vs RL (±2.5V) FIGURE 36. FREQUENCY RESPONSE vs RL (±5.0V) 10 4 RL = 5kΩ 2 RL = 1kΩ RL = 10kΩ 0 8 CL = 1000pF 6 CL = 470pF 4 -2 GAIN (dB) GAIN (dB) 1M FIGURE 34. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE (±18.0V) 4 -10 100k FREQUENCY (Hz) RL = 500Ω -4 RL = 100Ω -6 CL = 43pF CL = 220pF CL = 150pF 2 0 -2 CL = 4pF -4 -6 -8 -8 -10 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 37. FREQUENCY RESPONSE vs RL (±18.0V) Submit Document Feedback 14 -10 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 38. FREQUENCY RESPONSE vs CL (±2.5V) FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 10 10 CL = 1000pF 8 CL = 470pF 6 4 2 0 CL = 4pF -2 CL = 1000pF 6 CL = 470pF CL = 43pF CL = 220pF 2 0 CL = 4pF -2 -4 -4 -6 -6 CL = 150pF CL = 150pF -8 -8 -10 8 4 CL = 220pF GAIN (dB) GAIN (dB) CL = 43pF 1k 10k 100k 1M -10 10M 1k 10k 100k FREQUENCY (Hz) 10M FIGURE 40. FREQUENCY RESPONSE vs CL (±18.0V) FIGURE 39. FREQUENCY RESPONSE vs CL (±5.0V) 2 1M FREQUENCY (Hz) VS = ±2.25V 180 VS = ±5V 160 0 140 GAIN (dB) -2 VS = ±16.2V VS = ±18V VS = ±4.5V CROSSTALK (dB) VS = ±19.8V VS = ±5.5V -4 -6 VS = ±2.5V 120 100 80 60 40 -8 20 -10 VS = ±2.75V 1k 10k 100k 100M FREQUENCY (Hz) VS = ±15V RL-DRIVER CH. = OPEN RL-RECEIVING CH. = 10k CL = 4pF AV = +1 VSOURCE = 1VP-P 0 10 10M 100 60 50 40 VS =±5, ±18V 30 RL = 10k CL = 4pF AV = +1 VOUT = 50mVP-P 20 10 0 -10 0 5 10 15 20 25 TIME (µs) 30 35 FIGURE 43. SMALL SIGNAL TRANSIENT RESPONSE (+25°C) Submit Document Feedback 15 40 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 42. CROSSTALK (+25°C) LARGE SIGNAL TRANSIENT RESPONSE (V) SMALL SIGNAL TRANSIENT RESPONSE (mV) FIGURE 41. FREQUENCY RESPONSE vs SUPPLY VOLTAGE (+25°C) 1k 2.4 2.0 1.6 VS = ±18V, RL = 2k, 10k 1.2 0.8 0.4 0 VS = ±5V, RL = 2k, 10k -0.4 -0.8 CL = 4pF AV = +1 VOUT = 4VP-P -1.2 -1.6 -2.0 -2.4 0 10 20 30 40 50 60 TIME (µs) 70 80 90 100 FIGURE 44. LARGE SIGNAL TRANSIENT RESPONSE (+25°C) FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 0.8 0.8 0.7 0.7 POSITIVE SLEW RATE POSITIVE SLEW RATE 0.6 SLEW RATE (V/µs) SLEW RATE (V/µs) 0.6 0.5 NEGATIVE SLEW RATE 0.4 0.3 0.2 0.5 0.4 NEGATIVE SLEW RATE 0.3 0.2 0.1 0.1 0.0 -75 -50 -25 0 25 50 75 100 125 0.0 -75 150 -50 -25 0 TEMPERATURE (°C) FIGURE 45. SLEW RATE vs TEMPERATURE VS = ±2.5 75 100 125 150 60 0.7 OVERSHOOT+ (%) 0.5 ±5V 50 POSITIVE SLEW RATE 0.6 NEGATIVE SLEW RATE 0.4 0.3 40 ±2.5V 30 20 0.2 ±18V 10 0.1 0 50 FIGURE 46. SLEW RATE vs TEMPERATURE VS = ±5V 0.8 SLEW RATE (V/µs) 25 TEMPERATURE (°C) -75 -50 -25 0 25 50 75 100 125 0 150 1 10 TEMPERATURE (°C) 100 1k TEMPERATURE (°C) FIGURE 47. SLEW RATE vs TEMPERATURE VS = ±18V FIGURE 48. OVERSHOOT + vs CAPACITANCE 60 6 5 50 4 VIN AND VOUT (V) OVERSHOOT+ (%) 3 40 ±2.5V 30 ±5V 20 2 VOUT AT -55°C 1 0 -1 -3 ±18V 10 VOUT AT +25°C -4 VOUT AT +125°C -5 0 1 10 100 TEMPERATURE (°C) FIGURE 49. OVERSHOOT - vs CAPACITANCE Submit Document Feedback 16 1k RL = 10k CL = 7pF AV = 1 VIN = ±5.9VP-P -2 -6 VS = ±5V VIN 0 0.2 0.4 0.6 0.8 1.0 1.2 TIME (ms) 1.4 1.6 1.8 2.0 FIGURE 50. OUTPUT OVERDRIVE RESPONSE vs TEMPERATURE FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 0.24 0.08 INPUT 0 -0.04 -55°C -0.08 -0.12 +25°C -0.16 -0.20 -0.24 +125°C 0 10 20 30 40 +125°C 0.20 INPUT VOLTAGE LEVEL (V) INPUT VOLTAGE LEVEL (V) 0.04 +25°C 0.16 0.12 0.08 -55°C INPUT 0.04 0 -0.04 50 60 70 80 -0.08 90 0 10 20 30 FIGURE 51. ±18V POSITIVE SATURATION RECOVERY TIME (+25°C) 0.04 0.24 -0.04 INPUT VOLTAGE LEVEL (V) INPUT VOLTAGE LEVEL (V) 60 70 80 90 0.28 0 INPUT -0.08 -55°C -0.12 +25°C -0.20 INPUT 0.20 -55°C 0.16 0.12 0.08 +25°C +125°C 0.04 0 -0.24 -0.28 0 50 FIGURE 52. ±18V NEGATIVE SATURATION RECOVERY TIME (+25°C) +125°C -0.16 40 TIME (µs) TIME (µs) 10 20 30 40 50 TIME (µs) 60 70 80 90 FIGURE 53. ±5V POSITIVE SATURATION RECOVERY TIME (+25°C) Submit Document Feedback 17 -0.04 0 10 20 30 40 50 TIME (µs) 60 70 80 90 FIGURE 54. ±5V NEGATIVE SATURATION RECOVERY TIME (+25°C) FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Post High Dose Rate Radiation Characteristics Unless otherwise specified, VS ± 19.8V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a high dose rate of 50 to 300rad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed. 6 5 0.02 OFFSET VOLTAGE (µV) SUPPLY CURRENT (mA) 0.03 0.01 0.00 BIAS -0.01 GND -0.02 4 3 BIAS 2 1 0 GND -1 -2 -0.03 0 50 100 150 200 250 -3 300 0 50 100 krad(Si) FIGURE 55. SUPPLY CURRENT SHIFT vs HDR RADIATION 250 300 0.50 0.40 0.45 0.35 0.40 BIAS 0.30 0.35 0.25 0.30 0.20 IB- (nA) IB+ (nA) 200 FIGURE 56. OFFSET VOLTAGE SHIFT vs HDR RADIATION 0.45 GND 0.15 BIAS 0.25 0.20 GND 0.15 0.10 0.10 0.05 0.00 150 krad(Si) 0.05 0 50 100 150 200 250 0.00 300 0 50 100 krad(Si) FIGURE 57. POSITIVE INPUT BIAS CURRENT SHIFT vs HDR RADIATION 150 krad(Si) 200 250 300 FIGURE 58. NEGATIVE INPUT BIAS CURRENT SHIFT vs HDR RADIATION 0.10 0.08 0.06 IOS (nA) 0.04 BIAS 0.02 0.00 -0.02 GND -0.04 -0.06 -0.08 -0.10 0 50 100 150 200 250 300 krad(Si) FIGURE 59. INPUT OFFSET CURRENT SHIFT vs HDR RADIATION Submit Document Feedback 18 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Post Low Dose Rate Radiation Characteristics Unless otherwise specified, VS ± 19.8V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed. 15 0.10 10 0.06 0.04 OFFSET VOLTAGE (µV) SUPPLY CURRENT (mA) 0.08 GND 0.02 0.00 -0.02 BIASED -0.04 -0.06 BIASED 5 0 GND -5 -10 -0.08 -0.10 0 10 20 30 40 50 60 70 80 90 -15 100 0 10 20 30 40 krad(Si) FIGURE 60. SUPPLY CURRENT SHIFT vs LDR RADIATION 70 80 90 100 15 10 10 BIASED BIASED 5 5 IB+ (nA) IB+ (nA) 60 FIGURE 61. OFFSET VOLTAGE SHIFT vs LDR RADIATION 15 0 GND 0 GND -5 -5 -10 -10 -15 50 krad(Si) 0 10 20 30 40 50 60 70 80 90 -15 100 0 10 20 30 40 krad(Si) 50 60 70 80 90 100 krad(Si) FIGURE 62. POSITIVE INPUT BIAS CURRENT SHIFT vs LDR RADIATION FIGURE 63. NEGATIVE INPUT BIAS CURRENT SHIFT vs LDR RADIATION 1.00 0.80 0.60 IOS (nA) 0.40 GND 0.20 0.00 -0.20 BIASED -0.40 -0.60 -0.80 -1.00 0 10 20 30 40 50 60 70 80 90 100 krad(Si) FIGURE 64. INPUT OFFSET CURRENT SHIFT vs LDR RADIATION Submit Document Feedback 19 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Applications Information V+ Functional Description The ISL70219ASEH and ISL70419ASEH are dual and quad, low noise precision op amps. These devices are fabricated in a new precision 40V complementary bipolar DI process. A super-beta NPN input stage with input bias current cancellation provides low input bias current (180pA typical), low input offset voltage (13µV typical), low input noise voltage (8nV/√Hz), and low 1/f noise corner frequency (~8Hz). These amplifiers also feature high open loop gain (14kV/mV) for excellent CMRR (145dB) and THD+N performance (0.0005% at 3.5VRMS, 1kHz into 2kΩ). A complementary bipolar output stage enables high capacitive load drive without external compensation. Operating Voltage Range The devices are designed to operate across the 4.5V (±2.25V) to 40V (±20V) voltage range and are fully characterized at 10V (±5V) and 36V (±18V). The Power Supply Rejection Ratio typically exceeds 140dB across the full operating voltage range and 120dB minimum across the -55°C to +125°C temperature range. The worst case common mode input voltage range over-temperature is 2V to each rail. With ±18V supplies, CMRR performance is typically >130dB over-temperature. The minimum CMRR performance across the -55°C to +125°C temperature range is >120dB for power supply voltages from ±5V (10V) to ±18V (36V). Input Performance The super-beta NPN input pair provides excellent frequency response while maintaining high input precision. High NPN beta (>1000) reduces input bias current while maintaining good frequency response, low input bias current and low noise. Input bias cancellation circuits provide additional bias current reduction to <5nA, and excellent temperature stabilization. Figures 6 through 8 show the high degree of bias current stability at ±5V and ±18V supplies that is maintained across the -55°C to +125°C temperature range. The low bias current TC also produces very low input offset current TC, which reduces DC input offset errors in precision, high impedance amplifiers. The +25°C maximum input offset voltage (VOS) is 85µV at ±18V supplies. Input offset voltage temperature coefficients (VOSTC) is a maximum of ±1.0µV/°C. The VOS temperature behavior is smooth (Figures 3 through 5) maintaining constant TC across the entire temperature range. Input ESD Diode Protection 500Ω - VOUT VIN + 500Ω RL V- FIGURE 65. INPUT ESD DIODE CURRENT LIMITING - UNITY GAIN The series resistors limit the high feed-through currents that can occur in pulse applications when the input dV/dt exceeds the 0.5V/µs slew rate of the amplifier. Without the series resistors, the input can forward-bias the antiparallel diodes causing current to flow to the output resulting in severe distortion and possible diode failure. Figure 36 provides an example of distortion free large signal response using a 4VP-P input pulse with an input rise time of <1ns. The series resistors enable the input differential voltage to be equal to the maximum power supply voltage (40V) without damage. In applications where one or both amplifier input terminals are at risk of exposure to high voltages beyond the power supply rails, current limiting resistors may be needed at the input terminal to limit the current through the power supply ESD diodes to 20mA maximum. Output Current Limiting The output current is internally limited to approximately ±45mA at +25°C and can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only 1 amplifier at a time for the dual/quad op amp. Continuous operation under these conditions may degrade long term reliability. Figure 14 shows the current limit variation with temperature. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL70219ASEH and ISL70419ASEH are immune to output phase reversal, even when the input voltage is 1V beyond the supplies. The input terminals (IN+ and IN-) have internal ESD protection diodes to the positive and negative supply rails, series connected 500Ω current limiting resistors and an antiparallel diode pair across the inputs (Figure 65). Submit Document Feedback 20 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: (EQ. 1) T JMAX = T MAX + JA PD MAXTOTAL where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S I qMAX + V S - V OUTMAX ---------------------------R L (EQ. 2) where: • TMAX = Maximum ambient temperature • JA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application Submit Document Feedback 21 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH ISL70219ASEH Die Characteristics Assembly Related Information Die Dimensions SUBSTRATE POTENTIAL Floating 2406µm x 2935µm (95mils x 116mils) Thickness: 483µm ± 25µm (19mils ± 1 mil) ADDITIONAL INFORMATION Interface Materials WORST CASE CURRENT DENSITY GLASSIVATION < 2 x 105 A/cm2 Type: Silicon Nitride/Silicon Dioxide Sandwich Thickness: 15kÅ TRANSISTOR COUNT 466 TOP METALLIZATION Weight of Packaged Device Type: AlCu (99.5%/0.5%) Thickness: 30kÅ 0.3958 grams (Typical) Lid Characteristics BACKSIDE FINISH Silicon Finish: Gold Potential: Unbiased, tied to package pin 6 Case Isolation to Any Lead: 20 x 109Ω (min) PROCESS PR40 (DI) Metallization Mask Layout -INA OUTA +INA V+ OUTB V- +INB -INB Submit Document Feedback 22 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH TABLE 1. ISL70219ASEH DIE LAYOUT X-Y COORDINATES PAD NAME PAD NUMBER X (µm) Y (µm) dX (µm) dY (µm) BOND WIRES PER PAD OUTB 1 2195.0 1418.0 70 70 1 V+ 2 2195.0 2510.0 70 70 1 OUTA 3 709.0 2727.0 70 70 1 -INA 4 339.0 2727.0 70 70 1 +INA 5 114.0 2510.0 70 70 1 V- 6 114.0 336.0 70 70 1 +INB 7 2195.0 336.0 70 70 1 -INB 8 1970.0 110.0 70 70 1 NOTE: 8. Origin of coordinates is the bottom left corner of the die. Submit Document Feedback 23 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH ISL70419ASEH Die Characteristics Assembly Related Information Die Dimensions SUBSTRATE POTENTIAL Floating 2406µm x 2935µm (95mils x 116mils) Thickness: 483µm ± 25µm (19mils ± 1 mil) ADDITIONAL INFORMATION Interface Materials WORST CASE CURRENT DENSITY GLASSIVATION < 2 x 105 A/cm2 Type: Silicon Nitride/Silicon Dioxide Sandwich Thickness: 15kÅ TRANSISTOR COUNT 482 TOP METALLIZATION Weight of Packaged Device Type: AlCu (99.5%/0.5%) Thickness: 30kÅ 0. 6043 grams (Typical) Lid Characteristics BACKSIDE FINISH Silicon Finish: Gold Potential: Unbiased, tied to package E-pad Case Isolation to Any Lead: 20 x 109 Ω (min) PROCESS PR40 (DI) Metallization Mask Layout ͲINA OUTA OUTD ͲIND +INA +IND VͲ V+ +INB +INC ͲINB Submit Document Feedback 24 OUTB OUTC ͲINC FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH TABLE 2. ISL70419ASEH DIE LAYOUT X-Y COORDINATES PAD NAME PAD NUMBER X (µm) Y (µm) dX (µm) dY (µm) BOND WIRES PER PAD OUTA 3 709.0 2727.0 70 70 1 -INA 4 339.0 2727.0 70 70 1 +INA 5 114.0 2501.0 70 70 1 V+ 9 114.0 1419.0 70 70 1 -INB 13 339.0 110.0 70 70 1 +INB 14 114.0 327.0 70 70 1 OUTB 15 709.0 110.0 70 70 1 OUTC 16 1600.0 110.0 70 70 1 -INC 17 1970.0 110.0 70 70 1 +INC 18 2195.0 327.0 70 70 1 V- 22 2195.0 1419.0 70 70 1 -IND 26 1970.0 2727.0 70 70 1 +IND 1 2195.0 2501.0 70 70 1 OUTD 2 1600.0 2727.0 70 70 1 NOTE: 9. Origin of coordinates is the bottom left corner of die. Submit Document Feedback 25 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION October 27, 2014 FN8459.0 CHANGE Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 26 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Ceramic Metal Seal Flatpack Packages (Flatpack) K10.A MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B) 10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE e A INCHES A -A- D -BPIN NO. 1 ID AREA b E1 0.004 M H A-B S Q D S S1 0.036 M H A-B S D S C E -D- A -C- -HL E2 E3 SEATING AND BASE PLANE c1 L E3 (c) b1 M M (b) SECTION A-A MIN MILLIMETERS MAX MIN MAX NOTES A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.290 - 7.37 3 E 0.240 0.260 6.10 6.60 - E1 - 0.280 - 7.11 3 E2 0.125 - 3.18 - - E3 0.030 - 0.76 - 7 2 e LEAD FINISH BASE METAL SYMBOL 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 L 0.250 0.370 6.35 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.005 - 0.13 - 6 M - 0.0015 - 0.04 - N 10 10 Rev. 0 3/07 NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. Submit Document Feedback 27 FN8459.0 October 27, 2014 ISL70219ASEH, ISL70419ASEH Package Outline Drawing K14.C 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE Rev 0, 9/12 A A 0.050 (1.27 BSC) PIN NO. 1 ID AREA 0.390 (9.91) 0.376 (9.55) 1 TOP VIEW 0.022 (0.56) 0.005 (0.13) MIN 3 0.015 (0.38) 0.115 (2.92) 0.009 (0.23) 0.045 (1.14) 0.085 (2.16) 0.026 (0.66) 5 0.260 (6.60) 0.248 (6.30) -C- BOTTOM METAL 0.183 (4.65) 0.370 (9.40) 0.167 (4.24) 0.270 (6.86) -H- 0.03 (0.76) MIN 6 SEATING AND BASE PLANE 0.004 (0.10) -D- SIDE VIEW BOTTOM METAL 0.005 (0.127) REF. OFFSET FROM CERAMIC EDGE OPTIONAL PIN 1 INDEX BOTTOM VIEW NOTES: 0.006 (0.15) 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. LEAD FINISH 0.004 (0.10) 2. The maximum limits of lead dimensions (section A-A) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. BASE METAL 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) MAX 28 4. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 6. The bottom of the package is a solderable metal surface. 2 Submit Document Feedback 3. Measure dimension at all four corners. 5. Dimension shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 0.022 (0.56) 0.015 (0.38) SECTION A-A 0.009 (0.23) 0.004 (0.10) 7. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 8. Dimensions: INCH (mm). Controlling dimension: INCH. FN8459.0 October 27, 2014