an9331

No. AN9331.1
Application Note
January 1994
Using the HI1175 Evaluation Board
Author: Phil Louzon
Description
by individual clean linear regulated supplies. They can be
hooked up with external 16 gauge wires to the holes marked
+5V, +12V, -12V, and GND on the prototype area. Do not tie
the supply grounds together back at the supplies as this will
create a ground loop and create additional noise.
The HI1175 evaluation board can be used to evaluate the performance of the HI1175 8-bit 20MSPS analog-to-digital converter (ADC). The board includes clock driver circuitry a
reference voltage generator, and a choice of input drive circuitry.
Table 1 lists the operating conditions for the power supplies.
HI1175 Theory of Operation
TABLE 1. POWER SUPPLIES
As illustrated in the functional block diagram of the HI1175,
the part is a 2-step ADC converter featuring a 4-bit upper
comparator group and two lower comparator groups of 4-bits
each. The reference voltage can be obtained from the
onboard bias generator or be supplied externally. This IC uses
an offset canceling type CMOS comparator that operates synchronously with the external clock. The operating modes of
the part are input sampling (S), hold (H), and compare (C).
The operation of the part is depicted in the timing diagram of
Figure 1. A reference voltage that between VRT and VRB is
constantly applied to the upper 4-bit comparator group. The
analog input is sampled, VI(1), with the falling edge of the first
clock by the upper comparator group. The lower block A also
samples the analog input, VI(1), on the same edge. The upper
comparator block finalizes comparison data MD(1) with the
rising edge of the first clock. Simultaneously the reference
supply generates a reference voltage RV(1) that corresponds
to the upper results and applies it to the lower comparator
block A. The lower comparator block finalizes comparison
data LD(1) with the rising edge of the second clock. MD(1)
and LD(1) are combined and output as OUT(1) with the rising
edge of the third clock. There is a 2.5 cycle clock delay from
the analog input sampling point to the corresponding digital
output data. The lower comparator blocks A and B alternate
generating the lower data in order to increase the overall ADC
sampling rate.
POWER
SUPPLY
MIN
TYP
MAX
TYP
CURRENT
+5V
+4.75V
+5.0V
+5.25V
60mA
+12V
-
+12.0V
-
21mA
-12V
-
-12.0V
-
11mA
Reference Circuit
For the following discussion, refer to the board schematic
and the board layout drawing.
The HI1175 requires two reference voltages: VRT and VRB.
The evaluation board provides the user with two options for
supplying these voltages. First, by installing jumpers JP3
and JP5, the internal bias generators on the part can be
used to generate a VRT of about 2.6V and a VRB of about
0.6V. These generators are resistors to VDD and VSS which
in combination with the internal reference resistor string generates the desired voltages.
The evaluation board also provides an external reference
that can be applied to the part by installing jumpers JP4 and
JP6. In this case an ICL8069 reference diode generates a
1.2V that is gained up by an op-amp to the reference voltage
VRT for the ADC. VRT should be kept below 2.8V. R2 is
adjusted at the factory for a VRT reference voltage of +2V
±2mV. VRB is set to GND through JP6.
Layout and Power Supplies
The HI1175 evaluation board is a three layer board with a layout optimized for the best performance for the ADC. Figure 8
through Figure 12 include a schematic of the board, a board
layout, and the various board layers. The user should feel free
to copy the layout in their application.
Analog Input
The analog input to the HI1175 can be configured in various
ways depending on the input signal and the required level of
performance. A signal voltage with a maximum span of VRT VRB can be AC coupled to the HI1175 through the VIN2 BNC
and applied to the ADC by installing jumper JP2. R11 should
be adjusted to center the signal in the range of the HI1175.
In order to avoid latchup of the HI1175 at power up, it is necessary that AVDD and DVDD to the converter be driven from
the same supply. The supplies to the board should be driven
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
92
Application Note 9331
Evaluation Board Block Diagram
CLK
CLOCK OUT
1.2V REF
CLK
GAIN
+2
VRT
VRTS
VRB
VRBS
OFFSET
VIN1
8
DOUT
DATA OUT
VIN
-2
VIN2
HI1175
+12V
+12V
-12V
+5V
Functional Block Diagram
HI1175
OE
1
DVSS
2
D0 (LSB)
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
24 DVSS
REFERENCE VOLTAGE
22
LOWER
DATA
LATCHES
UPPER
DATA
LATCHES
D7 (MSB) 10
LOWER
ENCODER
(4-BIT)
LOWER
COMPARATORS
WITH S/H (4-BIT)
VRBS
(TYP. 0.6V)
21 AVSS
20 AVSS
LOWER
ENCODER
(4-BIT)
LOWER
COMPARATORS
WITH S/H (4-BIT)
UPPER
ENCODER
(4-BIT)
UPPER
COMPARATORS
WITH S/H (4-BIT)
19 VIN
18 AVDD
17 VRT
16
VRTS
(TYP. 2.6V)
15 AVDD
DVDD 11
CLK 12
23 VRB
14 AVDD
13 DVDD
CLOCK GENERATOR
93
Application Note 9331
Timing Diagrams
VI(1)
VI(2)
VI(3)
VI(4)
ANALOG INPUT
EXTERNAL CLOCK
UPPER COMPARATOR BLOCK
S (1)
S (1)
DIGITAL OUTPUT
S (3)
C (3)
MD (2)
RV (1)
H (1)
H (0)
C (0)
C (1)
LD (-2)
MD (3)
RV (3)
S (3)
H (3)
H (2)
C (2)
LD (0)
OUT (-1)
FIGURE 1.
94
C (4)
C (3)
LD (1)
S (2)
OUT (-2)
S (4)
RV (2)
LD (-1)
LOWER DATA A
LOWER DATA B
C (2)
MD (1)
RV (0)
LOWER REFERENCE VOLTAGE
LOWER COMPARATOR BLOCK B
S (2)
MD (0)
UPPER DATA
LOWER COMPARATOR BLOCK A
C (1)
S (4)
H (4)
LD (2)
OUT (0)
OUT (1)
Application Note 9331
An HA5020 buffer is also provided that can be used to drive
the part by inserting JP1. Using Figure 2, the gain of the circuit can be calculated from:
V
R3
R


 R9 
9
=  – -------  × V –  -------------------------  × V
.
OFFSET
IN  R + R 
OUT
 R7 
6
15
R4
VIN
R14
–
0.1µF
The signal gain has been set to about negative two. R15 has
been adjusted at the factory so that for +0.5V on VIN1 the
input to the ADC will be at 0V ±2mV.
+
VIN
VOUT
R2
R1
VOFFSET
R6 + R15
FIGURE 3. MODIFIED BUFFER
R9
VOFFSET
The HI1175 could latchup if the analog input exceeds the
absolute max input voltage rating. To avoid this resistor R14
should be increased to limit the input current to less then
15mA. However, increasing R14 beyond what is presently in
the evaluation board might sacrifice some AC performance.
R7
VIN
R14
–
+
VIN
The combination of the buffer and the external reference will
give the best performance for the HI1175 and allow the most
flexibility when dealing with various types of input signals. If
an application is extremely cost sensitive then the internal
bias generators along with the AC coupled version of the
input circuit can be used.
VOUT
FIGURE 2. INVERTING AMPLIFIER
The circuit in Figure 3 could be used if a negative voltage is
not available to provide the offset voltage. VOFFSET could be
generated from the 1.2V reference voltage. The gain can be
calculated from:
V
Increased Accuracy
Further calibration of the ADC can be done when using the
external reference and input buffer circuit. First, a precision
voltage equal to the ideal VIN-FS + 0.5 LSB is applied at
VIN1. R15 is then adjusted until the 0 to 1 transition occurs
on the digital output. Finally, a voltage equal to the ideal
VIN+FS - 1.5 LSB is applied at VIN1. R2 is then adjusted until
the 255 to 256 transition occurs on the digital output.
R   R
 R3 

1 
3
= –  -------  × V +  1 + -------  ×  --------------------  × V
OUT
IN 
OFFSET
R  R +R 
 R4 
4
1
2
CLK1
INPUT
tPD1
HI1175 CLOCK
INPUT
tOD
HI1175 D0 - D7
OUTPUT
DATA
DATA
tPD2
CLK OUT
(74ACT04)
tPD3
DOUT0-7
(74ACT541)
DATA
FIGURE 4. INPUT-TO-OUTPUT TIMING
95
DATA
Application Note 9331
Input Clock Driver and Timing
Where:
The input clock to the HI1175 evaluation board is a standard
TTL clock applied to the CLK1 BNC. U4 (75ACT04) will
buffer the clock and convert it to the CMOS levels necessary
to drive the HI1175. For optimum performance of the HI1175
the duty cycle of the clock should be kept at 50%. U5
(74ACT541) will buffer the output bits and keep the power
transients caused by charging a large buss capacitance off
the supplies to the ADC.
FS = sampling frequency of the ADC.
FSR = full scale range of the ADC.
k = desired test resolution (number of conversions per LSB).
m = desired number of steps (LSBs) per ramp period.
n = number of bits of the ADC.
For example, if k = 10, n = 8, m = 16, FS = 20MSPS, and
FSR = 1V then the input ramp would have a VP-P of 62.5mV
and a period (T) of 8µs. To view the reconstructed output,
connect the X axis of an o’scope to the ramp input and the Y
axis would be connected to the reconstruction DAC output.
Another o’scope could be used to probe the bits to verify the
codes that are being tested.The analog input should be low
pass filtered to remove as much noise as possible. Notice
that the input ramp is only covering m steps out a possible 2n
possible for the ADC. Therefore, the generator used for this
test will have to be able to offset the input through the range
of the converter so all the codes for the ADC can be
inspected.
TABLE 2. TIMING SPECS
PARAMETER
DESCRIPTION
MIN
TYP
MAX
-
18ns
30ns
tOD
HI1175 Data Delay
tPD1
74ACT04 Prop Delay
2.4ns
-
8.5ns
tPD2
74ACT04 Prop Delay
2.4ns
-
8.5ns
tPD3
74ACT541 Prop Delay
2.1ns
-
7.5ns
Figure 4 shows the timing for the evaluation board. The data
corresponding to a particular sample will be available at the
output of the HI1175 after the required data latency (2.5
cycles) plus an output delay. Table 2 lists the values that can
be expected for the various timing delays. Refer to the
datasheet for additional timing information.
Figure 6 shows what an ideal reconstructed output would
look like with and without various errors. For an ideal ADC
and an ideal ramp input, the digital output code will change
state by 1 LSB every kth conversion for an 1 LSB change on
the input. ADC errors will make the codes change before or
after the kth conversion and will translate to a larger or
smaller step width. The actual step width size would be compared with the ideal LSB size to determine errors. Since this
is a visual comparison it will tend not to be very precise.
HI1175 Characterization
Various tests can be used to characterize the performance
of the HI1175. The integral nonlinearity (INL) and differential
nonlinearity (DNL) specs are considered a measure of the
low frequency characteristics of the ADC. These parameters
are evaluated at the factory using a histogram approach with
a low frequency ramp input.
Further dynamic testing is used to evaluate the HI1175 performance as the input starts to approach nyquist (FS/2).
Among these tests are Signal-to-Noise Ratio (SNR), Signalto-Noise And Distortion (SINAD), and Total Harmonic Distortion (THD).
A three bit reconstruction DAC, as shown in Figure 5, can be
constructed to do a rough evaluation of HI1175 for DNL,
missing codes, and transition noise.
Coherent testing is recommended in order to avoid the inaccuracies due to windowing. Coherent sampling is governed
by the following relationship: FT/FS = M/N. Where FT is the
frequency of the input tone, FS is the sampling frequency, N
is the number of samples, and M is the number of cycles
over which the samples are taken. By making M an integer
and prime (1,3,5...) the samples are assured of being nonrepetitive.
1k
DOUT2
2k
DOUT1
4k
O’SCOPE
DOUT0
FIGURE 5. THREE BIT RECONSTRUCTION DAC
Figure 7 shows the test system used to do dynamic testing on
the HI1175. The clock (CLK) and analog input (AIN) signal
sources are derived from low phase noise HP8662A generators that are phase locked to each other to ensure coherence.
The output of the generator that drives the analog input to the
evaluation board is first passed through a bandpass filter to
improve the spectral purity of the signal. The ADC data is captured by a logic analyzer and then transferred over the GPIB
bus to the PC. The PC has all the software to perform the Fast
Fourier (FFT) and do the required data analysis.
The input frequency is set so that the input will changes by 1
LSB for every k conversions of the ADC. The p-to-p voltage
of the staircase is then determined by the number of LSB
steps within one period of the input ramp.The following
equations can be used:
V
p–p
m × FSR
= -----------------------2n
m×k
T = -------------F
s
A 12-bit accurate DAC is used to do the bandwidth testing.
The input sine wave has a peak-to-peak amplitude equal to
the reference voltage. The CLK and analog input frequencies are set up so a 1kHz beat frequency is generated on the
96
Application Note 9331
output of the DAC. Full power bandwidth is the frequency at
which the amplitude of the digitally reconstructed output is
3dB down from the low frequency value.
HP8662A
HP8662A
LOCK
Refer to the HI1175 datasheet for a complete list of test definitions and the results that can be expected using the evaluation board.
EH PULSE
GENERATOR
BAND-PASS
FILTER
RAMP INPUT
AIN
LAST THREE LSB CODES
CLK
HI1175
DIG OUT
111
110
8
HI1175 EVALUATION BOARD
B
101
A
100
011
C
010
ERRORS
001
000
1 LSB
DAC
DAS LOGIC
ANALYZER
GPIB
(A) is Major Transition Noise of 1 LSB.
(B) is a Missing Code.
(C) is a DNL Error of -1/2 LSB.
O’SCOPE
FIGURE 6. THREE BIT RECONSTUCTION DAC WAVEFORMS
PC
FIGURE 7. TEST SYSTEM
FIGURE 8. PARTS LAYOUT
97
Application Note 9331
FIGURE 9. COMPONENT SIDE
FIGURE 10. SOLDER SIDE
98
Application Note 9331
FIGURE 11. GROUND LAYER
+5V
R1
6.8K
+
+12V
R2
GAIN
C22
10µF
D1
ICL8069
U1
7
3
10K
2 +
-
6
VRTS
R3
JP3
VRT
JP4
C7
0.1µF
100
CA3193
4
-12V
R5
R4
10K
10K
VRBS
JP5
VRB
JP6
C8
0.1µF
+12V
OFFSET
7
3
+
2 -
R6
-12V
1.8K
4
R15
5K
6
JP1
HA5020
JP2
-12V
VIN1
BNC
R8
68
VIN2
BNC
R7
R9
221
471
C6
R13
51
+
10µ
R10
R12
+12V
1K
R11
2K
11K
FIGURE 12. HI1175 EVALUATION BOARD
99
R14
24
VIN
Application Note 9331
P1
+12V
-12V
FB1
+5VD
+5V
+5V
+ C19
10µF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
+12V
+12V
C10
0.1µF
GND
+ C11
10µF
C12
0.1µF
+ C13
10µF
C14
0.1µF
CLK
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
GND
-12V
-12V
+5V
OE
U4A
1
R17
2 CLK
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
51
CD74ACT04
U4B
CLK1
BNC
3
R16
51
U3
4
CD74ACT04
VIN
19
OE
1
VRT
12
VRT
VRTS
VRB
VRBS
17
16
23
22
14
15
18
20
21
+5V
U4C
5
U4E
6
11
10
U5
D7
D8
D7
D6
D5
D4
D3
D2
VIN
OE
CLK
VRT
VRTS
VRB
VRBS
10
9
8
7
6
5
4
3
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
1
DVDD
DVDD
DVSS
DVSS
13
11
24
2
19
G1
G2
CD74ACT541
HI1175
-12V
CD74ACT04
U4D
9
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
+5V
AVDD
AVDD
AVDD
AVSS
AVSS
+12V
CD74ACT04
A1
A2
A3
A4
A5
A6
A7
A8
U4F
8
CD74ACT04
13
C2
0.1µF
U1
12
C4
0.1µF
U2
CD74ACT04
C3
0.1µF
U1
C5
0.1µF
U2
+5V
C15
0.1µF
U3
C16
0.1µF
U3
C17
0.1µF
U3
C18
0.1µF
U4
FIGURE 12. HI1175 EVALUATION BOARD (Continued)
100
C19
0.1µF
U3
C20
0.1µF
U3
C21
0.1µF
U5
Application Note 9331
Parts List for HI1175 Evaluation Board
DESIGNATOR
QUANTITY
DESCRIPTION
DESIGNATOR
QUANTITY
DESCRIPTION
C15-C17, C7, C8,
C20, C21
7
0.1µF 1206 CHIPS
VIN1, VIN2, CLK1
3
BNC STRAIGHT
FEM
C6, C9, C12, C13,
C22
5
10µF TANT. 35WV
51
1
8 PIN SOCKET
53
1
14 PIN SOCKET
C2-C5, C10, C12,
C14-C18, C20-21
14
0.1µF CKO5BX104K
54
1
20 PIN SOCKET
C1
-
NOT INSTALLED
J1-J6
6
SHUNTS
R1, R4, R5, R10
4
1K CARBON 1/8W
J1-J6
6
HEADERS
R11
1
2K BOURNS POT
A/R
32
MINI SPRING SKT
R12
1
11K CARBON 1/8W
P1
1
50 PIN HEADER
R13, R16, R17
3
51 CARBON 1/8W
FB1
1
FERRITE BEAD
R14
1
22 CARBON 1/8W
D1
1
ICL8069DCSQ
R15
1
5K BOURNS POT
U1
1
CA3193E
R2
2
10K BOURNS POT
U2
1
HA3-5020-5
R3
1
100 CARBON 1/8W
U3
1
HI1175JCP
R6
1
1.8K CARBON 1/8W
U4
1
CD74ACT04E
R7
1
221 METAL 1/4W 1%
U5
1
CD74ACT541E
R8
1
68 CARBON 1/8W
R9
1
471 1206 CHIP
R18
-
NOT INSTALLED
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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101
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