DATASHEET

ISL54225
Features
The Intersil ISL54225 is a single supply dual 2:1
multiplexer that can operate from a single 2.7V to 5.25V
supply. It contains two SPDT (Single Pole/Double
Throw) switches configured as a DPDT. The part was
designed for switching or routing of USB High-Speed
signals and/or USB Full-speed signals in portable
battery powered products.
• High-Speed (480Mbps) and Full-Speed (12Mbps)
Signaling Capability per USB 2.0
The 6.5Ω switches were specifically designed to pass
USB high speed/full speed data signals. They have high
bandwidth and low capacitance to pass USB high speed
data signals with minimal DISTORTION.
• D-/D+ Pins Overvoltage Protection for +5.25V and
-5V Fault Voltages
The ISL54225 has OVP circuitry on the D-/D+ COM pins
that opens the USB in-line switches when the voltage at
these pins exceeds 3.8V (typ) or goes negative by -0.5V
(typ). It isolates fault voltages up to +5.25V or down to
-5V from getting passed to the other-side of the switch,
thereby protecting the USB transceivers.
• Low ON-Resistance . . . . . . . . . . . . . . . . . . . . 6.5Ω
The digital logic inputs are 1.8V logic compatible when
operated with a 2.7V to 3.6V supply. The ISL54225 has
an output enable pin to open all the switches. It can be
used to facilitate proper bus disconnect and connection
when switching between the USB sources.
The ISL54225 is available in 10 Ld 1.8mmx1.4mm
µTQFN and 10 Ld TDFN packages. It operates over a
temperature range of -40°C to +85°C.
• 1.8V Logic Compatible (2.7V to +3.6V Supply)
• Enable Pin to Open all Switches
• Low Power Mode
• Power OFF Protection
• -3dB Frequency . . . . . . . . . . . . . . . . . . . . 780MHz
• Low ON Capacitance @ 240MHz . . . . . . . . . . 3.3pF
• Single Supply Operation (VDD) . . . . . 2.7V to 5.25V
• Available in µTQFN and TDFN Packages
• Pb-Free (RoHS Compliant)
• Compliant with USB 2.0 Short Circuit and
Overvoltage Requirements Without Additional
External Components
Applications*(see page 16)
• MP3 and other Personal Media Players
• Cellular/Mobile Phones
• PDA’s
• Digital Cameras and Camcorders
• USB Switching
Typical Application
USB 2.0 HS Eye Pattern With
Switches in the Signal Path
3.3V
VDD
USB CONNECTOR
LOGIC
CONTROL
VBUS
D-
OE
SEL
HSD1-
D-
HSD1+
D+
OVP
D+
HSD2HSD2+
GND
ISL54225
µP
USB
TRANSCEIVER
USB
TRANSCEIVER
VOLTAGE SCALE (0.1V/DIV)
500Ω
GND
TIME SCALE (0.2ns/DIV)
July 2, 2010
FN7627.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54225
High-Speed USB 2.0 (480Mbps) Multiplexer with
Overvoltage Protection (OVP)
ISL54225
Pin Configuration
ISL54225
(10 LD 3X3 TDFN)
TOP VIEW
ISL54225
(10 LD 1.8X1.4 µTQFN)
TOP VIEW
HSD1+ HSD17
LOGIC
CONTROL
VDD 9
SEL 10
PD
6
OE 8
OVP
1
5
D-
4
GND
3
D+
LOGIC
CONTROL
SEL 1
10 VDD
HSD2- 2
9
OE
HSD2+ 3
8
HSD1+
D+ 4
7
HSD1-
6
D-
2
HSD2- HSD2+
GND 5
OVP
NOTE:
1. Switches Shown for SEL = Logic “1” and OE = Logic “0”.
Pin Descriptions
PIN
NAME
Truth Table
OE
SEL
HSD1-,
HSD1+
HSD2-,
HSD2+
STATE
HSD2- USB Data Port Channel 2
0
0
ON
OFF
Normal
HSD2+ USB Data Port Channel 2
0
1
OFF
ON
Normal
USB Data COM Port
1
0
OFF
OFF
Low Power
GND
Ground Connection
1
1
OFF
OFF
Normal
D-
USB Data COM Port
µTQFN
TDFN
DESCRIPTION
1
2
2
3
3
4
D+
4
5
5
6
6
7
HSD1- USB Data Port Channel 1
7
8
HSD1+ USB Data Port Channel 1
8
9
OE
9
10
VDD
Power Supply
10
1
SEL
Select Logic Control Input
-
PD
PD
Thermal Pad. Tie to Ground or
Float
Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a 2.7V to
3.6V Supply.
Note: In Low Power mode there is no persistence checking
when in OVP condition.
Bus Switch Enable
TABLE 1. USB - OVP POSSIBLE SITUATIONS AND TRIP POINT VOLTAGE
TRIP POINT
CODEC SUPPLY
SWITCH SUPPLY (VDD)
COMs SHORTED TO
PROTECTED
MIN
MAX
2.7V to 3.3V
2.7V to 5.25V
VBUS
Yes
3.63V
3.95V
2.7V to 3.3V
2.7V to 5.25V
-5V
Yes
-0.76V
-0.29V
2
FN7627.0
July 2, 2010
ISL54225
Ordering Information
PART
NUMBER
PART
MARKING
TEMP. RANGE
(°C)
ISL54225IRUZ-T (Notes 2, 3)
U0
-40 to +85
10 Ld 1.8x1.4mm µTQFN (Tape and Reel)
L10.1.8x1.4A
ISL54225IRUZ-T7A (Notes 2, 3)
U0
-40 to +85
10 Ld 1.8x1.4mm µTQFN (Tape and Reel)
L10.1.8x1.4A
ISL54225IRTZ (Note 4)
4225
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL54225IRTZ-T (Notes 2, 4)
4225
-40 to +85
10 Ld 3x3 TDFN (Tape and Reel)
L10.3x3A
ISL54225IRTZEVAL1Z
PACKAGE
(Pb-Free)
PKG.
DWG. #
Evaluation Board
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials
and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54225. For more information on MSL please
see techbrief TB363.
3
FN7627.0
July 2, 2010
ISL54225
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
VDD to Dx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5V
Dx to HSD1x, HSD2x . . . . . . . . . . . . . . . . . . . . . . . . .8.6V
Input Voltages
HSD2x, HSD1x . . . . . . . . . . . . . . . . . . . . . - 0.3V to 6.5V
SEL, OE . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Output Voltages
D+, D- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 6.5V
Continuous Current (HSD2x, HSD1x) . . . . . . . . . . . .±40mA
Peak Current (HSD2x, HSD1x)
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . ±100mA
ESD Rating:
Human Body Model (Tested per JESD22-A114-F) . . . >5.5kV
Machine Model (Tested per JESD22-A115-A). . . . . . . >250V
Charged Device Model (Tested per JESD22-C101-D) . . >2kV
Latch-up Tested per JEDEC; Class II Level A . . . . . at +85°C
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
10 Ld µTQFN Package (Note 6, 7) .
210
165
10 Ld TDFN Package (Notes 8, 9). .
58
22
Maximum Junction Temperature (Plastic Package). . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range . . . . . .
VDD Supply Voltage Range .
Logic Control Input Voltage
Analog Signal Range
VDD = 2.7V to 5.25V . . .
. . . . . . . . . . . . -40°C to +85°C
. . . . . . . . . . . . . 2.7V to 5.25V
. . . . . . . . . . . . . . . 0V to 5.25V
. . . . . . . . . . . . . . . . 0V to 3.6V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
7. For θJC, the “case temp” location is taken at the package top center.
8. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
9. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V,
VSELL = 0.5V, VOEH = 1.4V, VOEL = 0.5V, (Note 10), Unless
Otherwise Specified. Boldface limits apply over the operating
temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-Resistance, rON
(High-Speed)
VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V,
IDx = 17mA, VHSD1x or VHSD2x = 0V to 400mV
(see Figure 3, Note 15)
rON Matching Between
Channels, ΔrON
(High-Speed)
VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V,
IDx = 17mA, VHSD1x or VHSD2x = Voltage at
max rON, (Notes 14, 15)
rON Flatness, RFLAT(ON)
(High-Speed)
VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V,
IDx = 17mA, VHSD1x or VHSD2x = 0V to 400mV,
(Notes 13, 15)
ON-Resistance, rON
VDD = 3.3V, SEL = 0.5V or 1.4V, OE = 0.5V,
ICOMx = 17mA, VD+ or VD-= 3.3V (See Figure 4,
Note 15)
OFF Leakage Current,
IHSD1x(OFF)
VDD = 5.25V, SEL = VDD and OE = VDD or
OE = 0V, VDx = 0.3V, 3.3V, VHSD1x = 3.3V,
0.3V, VHSD2x = 0.3V, 3.3V
ON Leakage Current,
IHSD1x(ON)
VDD = 5.25V, SEL = OE = 0V, VDx = 0.3V, 3.3V,
VHSD1X = 0.3V, 3.3V, VHSD2x = 3.3V, 0.3V
OFF Leakage Current,
IHSD2x(OFF)
VDD = 5.25V, SEL = OE = 0V or OE = VDD,
VDx = 3.3V, 0.3V, VHSD2x = 0.3V, 3.3V,
VHSD1X = 3.3V, 0.3V
4
25
-
6.5
8
Ω
Full
-
-
10
Ω
25
-
0.2
0.45
Ω
Full
-
-
0.5
Ω
25
-
0.3
0.5
Ω
Full
-
-
1
Ω
25
-
12
20
Ω
Full
-
-
25
Ω
25
-20
1
20
nA
Full
-
30
-
nA
25
-
2
3
µA
Full
-
-
4
µA
25
-20
1
20
nA
Full
-
30
-
nA
FN7627.0
July 2, 2010
ISL54225
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V,
VSELL = 0.5V, VOEH = 1.4V, VOEL = 0.5V, (Note 10), Unless
Otherwise Specified. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
ON Leakage Current,
IHSD2x(ON)
VDD = 5.25V, SEL = VDD, OE = 0V, VDx = 0.3V,
3.3V, VHSD2x = 0.3V, 3.3V, VHSD1x = 3.3V, 0.3V
Power OFF Leakage
Current, ID+, IDPower OFF Logic Current,
ISEL, IOE
TEMP
MIN
MAX
(°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS
25
-
2
3
µA
Full
-
-
4
µA
VDD = 0V, VD+ = 5.25V, VD-= 5.25V,
SEL = OE = VDD
25
-
5
13
µA
VDD = 0V, SEL = OE = 5.25V
25
-
19
26
µA
25
-
0.05
1
µA
Power OFF D+/D- Current, VDD = 0V, SEL = OE = VDD,
IHSDX+, IHSDXVHSDX+ = VHSDX- = 5.25V
OVERVOLTAGE PROTECTION DETECTION
Positive Fault-Protection
Trip Threshold, VPFP
VDD = 2.7V to 5.25V, SEL = 0V or VDD, OE = 0V
See Table 1 on page 2
25
3.63
3.8
3.95
V
Negative Fault-Protection
Trip Threshold, VNFP
VDD = 2.7V to 5.25V, SEL = 0V or VDD, OE = 0V
See Table 1 on page 2
25
-0.76
-0.5
-0.29
V
OFF Persistence Time
Fault Protection Response
Time
Negative OVP Response: VDD = 2.7V, SEL = 0V
or VDD, OE = 0V, VDx = 0V to -5V, RL = 15kΩ
25
-
1
-
µs
Positive OVP Response: VDD = 2.7V, SEL = 0V
or VDD, OE = 0V, VDx = 0V to 5.25V, RL = 15kΩ
25
-
2
-
µs
ON Persistence Time
Fault Protection Recovery
Time
VDD = 2.7V, SEL = 0V or VDD, OE = 0V, VDx = 0V
to 5.25V or 0V to -5V, RL = 15kΩ
25
-
40
-
µs
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VDD = 3.3V, VINPUT = 3V, RL = 50Ω, CL = 50pF
(see Figure 1)
25
-
110
-
ns
Turn-OFF Time, tOFF
VDD = 3.3V, VINPUT = 3V, RL = 50Ω, CL = 50pF
(see Figure 1)
25
-
70
-
ns
Break-Before-Make Time
Delay, tD
VDD = 3.3V, RL = 50Ω, CL = 50pF (see Figure 2)
25
-
40
-
ns
Turn-ON Enable Time,
tENABLE
VDD = 3.3V, VINPUT = 3V, RL = 15kΩ,
CL = 50pF, Time out of All-Off state
25
-
90
-
ns
Turn-OFF Disable Time,
tDISABLE
VDD = 3.3V, VINPUT = 3V, RL = 15kΩ,
CL = 50pF, Time into All-Off state, Time is
highly dependent on the load (RL , CL) time
constant.
25
-
120
-
ns
Skew, (tSKEWOUT - tSKEWIN) VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45Ω,
CL = 10pF, tR = tF = 500ps at 480Mbps, (Duty
Cycle = 50%) (see Figure 6)
25
-
50
-
ps
Rise/Fall Degradation
(Propagation Delay), tPD
VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45Ω,
CL = 10pF (see Figure 6)
25
-
250
-
ps
Crosstalk
VDD = 3.3V, RL = 50Ω, f = 240MHz (see Figure 5)
25
-
-32
-
dB
OFF-Isolation
VDD = 3.3V, OE = 3.3V, RL = 50Ω, f = 240MHz
25
-
-30
-
dB
-3dB Bandwidth
Signal = 0dBm, 0.2VDC offset, RL = 50Ω
25
-
780
-
MHz
OFF Capacitance, CHSxOFF f = 1MHz, VDD = 3.3V, SEL = 0V or 3.3V,
OE = VDD (see Figure 4)
25
-
2.5
-
pF
COM ON Capacitance,
CDX(ON)
25
-
5.4
-
pF
f = 1MHz, VDD = 3.3V, SEL = 0V or 3.3V,
OE = 0V (see Figure 4)
5
FN7627.0
July 2, 2010
ISL54225
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V,
VSELL = 0.5V, VOEH = 1.4V, VOEL = 0.5V, (Note 10), Unless
Otherwise Specified. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
PARAMETER
COM ON Capacitance,
CDX(ON)
TEST CONDITIONS
f = 240MHz, VDD = 3.3V, SEL = 0V or 3.3V,
OE = 0V (see Figure 4)
TEMP
MIN
MAX
(°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS
25
-
Power Supply Range, VDD
Full
2.7
Positive Supply Current, IDD VDD = 5.25V, SEL = 0V or VDD, OE = 0V
25
-
Full
3.3
-
pF
5.25
V
45
58
µA
-
-
66
µA
25
-
23
30
µA
Full
-
-
35
µA
25
-
5
6
µA
Full
-
-
10
µA
25
-
35
45
µA
Full
-
-
52
µA
25
-
25
32
µA
Full
-
-
38
µA
VDD = 2.7V to 3.6V
Full
-
-
0.5
V
Input Voltage High, VSELH, VDD = 2.7V to 3.6V
VOEH
Full
1.4
-
5.25
V
Input Voltage Low, VSELL,
VOEL
Full
-
-
0.7
V
Input Voltage High, VSELH, VDD = 3.7V to 4.2
VOEH
Full
1.7
-
5.25
V
Input Voltage Low, VSELL,
VOEL
VDD = 4.3V to 5.25V
Full
-
-
0.8
V
Input Voltage High, VSELH, VDD = 4.3V to 5.25V
VOEH
Full
2.0
-
5.25
V
Input Current, ISELL, IOEH VDD = 5.25V, SEL = 0V, OE = 5.25V
Full
-
3.3
-
nA
Input Current, ISELH
VDD = 5.25V, SEL = 5.25V, 4MΩ pull-down
resistor
Full
-
1.4
-
µA
Input Current, IOEL
VDD = 5.25V, OE = 0V, 4MΩ pull-up resistor
Full
-
1.4
-
µA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, IDD VDD = 3.6V, SEL = 0V or VDD, OE = 0V
Positive Supply Current,
IDD (Low Power State)
VDD = 3.6V, SEL = 0V, OE = VDD
Positive Supply Current, IDD VDD = 4.3V, SEL = 2.6V, OE = 0V or 2.6V
Positive Supply Current, IDD VDD = 3.6V, SEL = 1.4V, OE = 0V or 1.4V
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VSELL,
VOEL
VDD = 3.7V to 4.2V
NOTES:
10. VLOGIC = Input voltage to perform proper function.
11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
13. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal
range.
14. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with
lowest max rON value, between HSD2+ and HSD2- or between HSD1+ and HSD1-.
15. Limits established by characterization and are not production tested.
6
FN7627.0
July 2, 2010
ISL54225
Test Circuits and Waveforms
VDD
LOGIC
INPUT
VDD
tr < 20ns
tf < 20ns
50%
0V
VINPUT
tOFF
SWITCH
INPUT VINPUT
SWITCH
INPUT
VOUT
HSDxx
Dx
SEL
VOUT
90%
SWITCH
OUTPUT
C
90%
VIN
CL
RL
OE
GND
0V
tON
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
----------------------V OUT = V
(INPUT) R + r
L
ON
Logic input waveform is inverted for switches that have the
opposite logic sense.
FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
VDD
C
VDD
LOGIC
INPUT
HSD2x
VINPUT
0V
RL
50Ω
SEL
SWITCH
OUTPUT
VOUT
VOUT
Dx
HSD1x
CL
10pF
90%
GND
VIN
0V
OE
tD
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. BREAK-BEFORE-MAKE TIME
VDD
C
rON = V1/17mA
HSDx
VHSDx
SEL
V1
17mA
0V OR VDD
Dx
GND
OE
Repeat test for all switches.
FIGURE 3. rON TEST CIRCUIT
7
FN7627.0
July 2, 2010
ISL54225
Test Circuits and Waveforms (Continued)
VDD
VDD
C
C
HSDxx
SIGNAL
GENERATOR
HSD1x
50Ω
Dx
SEL
SEL
IMPEDANCE
ANALYZER
0V OR
VDD
Dx
GND
VIN
OE
HSD2x
Dx
ANALYZER
GND
NC
OE
RL
Repeat test for all switches.
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 5. CROSSTALK TEST CIRCUIT
FIGURE 4. CAPACITANCE TEST CIRCUIT
VDD
C
tri
90%
DIN+
DIN-
10%
50%
VIN
tskew_i
90%
SEL
15.8Ω
COMD2
DIN+
50%
143Ω
10%
DIN-
tfi
tro
15.8Ω
OUT+
D2
45Ω
CL
COMD1
OE
143Ω
OUT-
D1
45Ω
CL
90%
OUT+
OUT-
10%
50%
GND
tskew_o
50%
90%
10%
tf0
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals.
|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals.
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
FIGURE 6A. MEASUREMENT POINTS
FIGURE 6B. TEST CIRCUIT
FIGURE 6. SKEW TEST
8
FN7627.0
July 2, 2010
ISL54225
Application Block Diagram
500Ω
ISL54225
USB CONNECTOR
VDD
4MΩ
SEL
VBUS
µCONTROLLER
VDD
LOGIC CIRCUITRY
OE
4MΩ
D-
D-
D+
D+
HSD1HSD1+
OVP
HSD2HSD2+
GND
GND
USB
HIGH-SPEED
OR
FULL-SPEED
TRANSCEIVER
#1
USB
HIGH_SPEED
OR
FULL-SPEED
TRANSCEIVER
#2
PORTABLE MEDIA DEVICE
Detailed Description
The ISL54225 device is a dual single pole/double throw
(SPDT) analog switch configured as a DPDT that operates
from a single DC power supply in the range of 2.7V to
5.25V.
It was designed to function as a dual 2-to-1 multiplexer
to select between two USB high-speed differential data
signals in portable battery powered products. It is offered
in a TDFN, and a small µTQFN packages for use in MP3
players, cameras, PDAs, cellphones, and other personal
media players. The device has an enable pin to open all
switches and put the part in a low power state.
The part contains special overvoltage detection and
protection (OVP) circuitry on the D-/D+ COM pins. This
circuitry acts to open the USB in-line switches when the
part senses a voltage on the COM pins that is >3.8V
(typ) or < -0.5V (typ). It isolates voltages up to 5.25V
and down to -5V from getting through to the other side
of the switch to protect the USB transceivers connected
at the signal pins (HSD1-, HSD1+, HSD2-, HSD2+).
The part consists of four 6.5Ω high speed (HSx) switches.
These switches have high bandwidth and low capacitance
to pass USB high-speed (480Mbps) differential data signals
with minimal edge and phase distortion. They can also
swing from 0V to 3.6V to pass USB full speed (12Mbps)
differential data signals with minimal distortion.
The ISL54225 was designed for MP3 players, cameras,
cellphones, and other personal media player applications
that have multiple high-speed or full-speed transceivers
sections and need to multiplex between these USB
sources to a single USB host (computer). A typical
application block diagram of this functionality is
previously shown.
9
A detailed description of the HS switches is provided in
the following section.
High-Speed (HSx) Data Switches
The HSx switches (HSD1-, HSD1+, HSD2-, HSD2+) are
bi-directional switches that can pass USB high-speed and
USB full-speed signals when VDD is in the range of 2.7V
to 5.25V.
When powered with a 2.7V supply, these switches have a
nominal rON of 6.5Ω over the signal range of 0V to
400mV with a rON flatness of 0.3Ω. The rON matching
between the HSD1x switches and HSD2x switches over
this signal range is only 0.2Ω, ensuring minimal impact
by the switches to USB high-speed signal transitions. As
the signal level increases, the rON switch resistance
increases. At signal level of 3.3V, the switch resistance is
nominally 12Ω. See Figures 9, 10, 11, 12, 13, 14, 15 and
16 in the “Typical Performance Curves” beginning on
page 12.
The HSx switches were specifically designed to pass
USB 2.0 high-speed (480Mbps) differential signals in
the range of 0V to 400mV. They have low capacitance
and high bandwidth to pass the USB high-speed
signals with minimum edge and phase distortion to
meet USB 2.0 high speed signal quality specifications.
See Figure 21 in the “Typical Performance Curves” on
page 14 for USB High-speed Eye Pattern taken with
switch in the signal path.
The HSx switches can also pass USB full-speed signals
(12Mbps) with minimal distortion and meet all the USB
requirements for USB 2.0 full-speed signaling. See
Figure 22 in the “Typical Performance Curves” on
page 14 for USB Full-speed Eye Pattern taken with
switch in the signal path.
FN7627.0
July 2, 2010
ISL54225
The HS1 channel switches are active (turned ON)
whenever the SEL voltage is logic “0”(Low) and the OE
voltage is logic “0”(Low).
VSUPPLY
PROTECTION
RESISTOR
100Ω to 1kΩ
The HS2 channel switches are active (turned ON)
whenever the SEL voltage is logic “1” (High) and the OE
voltage is logic “0” (Low).
External VDD Series Resistor to Limit IDD Current
during Negative OVP Condition
A 100Ω to 1kΩ resistor in series with the VDD pin (see
Figure 7) is required to limit the IDD current draw from the
system power supply rail during a negative OVP fault event.
With a negative -5V fault voltage at both COM pins, the
graph in Figure 8 shows the IDD current draw for
different external resistor values for supply voltages of
2.7V, 3.6V, and 5.25V. With a 500Ω resistor, the current
draw is limited to around 5mA. When the negative fault
voltage is removed, the IDD current will return to it’s
normal operation current of 25µA to 45µA.
The series resistor also provides improved ESD and
latch-up immunity. During an overvoltage transient
event (such as occurs during system level IEC 61000
ESD testing), substrate currents can be generated in
the IC that can trigger parasitic SCR structures to turn
ON, creating a low impedance path from the VDD
power supply to ground. This will result in a significant
amount of current flow in the IC, which can potentially
create a latch-up state or permanently damage the IC.
The external VDD resistor limits the current during this
over-stress situation and has been found to prevent
latch-up or destructive damage for many overvoltage
transient events.
Under normal operation, the low microamp IDD current
of the IC produces an insignificant voltage drop across
the series resistor resulting in no impact to switch
operation or performance.
10
HSD1+
D+
The maximum normal operating signal range for the HSx
switches is from 0V to 3.6V. For normal operation, the
signal voltage should not be allowed to exceed these
voltage levels or go below ground by more than -0.3V.
-5V
D-
FAULT
VOLTAGE
HSD2+
HSD1HSD2-
OVP
SEL LOGIC
OE
GND
FIGURE 7. VDD SERIES RESISTOR TO LIMIT IDD
CURRENT DURING NEGATIVE OVP AND
FOR ENHANCED ESD AND LATCH-UP
IMMUNITY
25
VCOM+ = VCOM- = -5V
20
IDD (mA)
The OVP and power-off protection circuitry allows the
COM pins (D-, D+) to be driven up to 5.25V while the
VDD supply voltage is in the range of 0V to 5.25V. In this
condition, the part draws < 100µA of ICOMx and IDD
current and causes no stress to the IC. In addition, the
SPDT switches are OFF and the fault voltage is isolated
from the other side of the switch.
IDD
VDD
OVERVOLTAGE PROTECTION (OVP)
However, in the event that a positive voltage > 3.8V
(typ) to 5.25V, such as the USB 5V VBUS voltage, gets
shorted to one or both of the COM+ and COM- pins or a
negative voltage < -0.5V (typ) to -5V gets shorted to one
or both of the COM pins, the ISL54225 has OVP circuitry
to detect the overvoltage condition and open the SPDT
switches to prevent damage to the USB down-stream
transceivers connected at the signal pins (HS1D-,
HS1D+, HS2D-, HS2D+).
C
5.25V
15
10
5
0
100
3.6V
2.7V
200
300
400 500 600 700
RESISTOR (Ω)
800
900 1k
FIGURE 8. NEGATIVE OVP IDD CURRENT vs
RESISTOR VALUE vs VSUPPLY
ISL54225 Operation
The following will discuss using the ISL54225 shown in
the “Application Block Diagram” on page 9.
POWER
The power supply connected at the VDD pin provides the
DC bias voltage required by the ISL54225 part for proper
operation. The ISL54225 can be operated with a VDD
voltage in the range of 2.7V to 5.25V.
For lowest power consumption you should use the lowest
VDD supply.
A 0.01µF or 0.1µF decoupling capacitor should be
connected from the VDD pin to ground to filter out any
power supply noise from entering the part. The
capacitor should be located as close to the VDD pin as
possible.
In a typical application, VDD will be in the range of
2.8V to 4.3V and will be connected to the battery or
LDO of the portable media device.
FN7627.0
July 2, 2010
ISL54225
LOGIC CONTROL
The state of the ISL54225 device is determined by the
voltage at the SEL pin and the OE pin. SEL is only active
when the OE pin is logic “0” (Low). Refer to “Truth Table”
on page 2.
The ISL54225 logic pins are designed to minimize
current consumption when the logic control voltage is
lower than the VDD supply voltage. With VDD = 3.6V and
logic pins at 1.4V, the part typically draws only 25µA.
With VDD = 4.3V and logic pins at 2.6V, the part typically
draws only 35µA. Driving the logic pins to the VDD supply
rail minimizes power consumption.
The SEL pin and OE pin have special circuitry that allows
them to be driven with a voltage higher than the VDD
supply voltage. These pins can be driven up to 5.25V
with a VDD supply in the range of 2.7V to 5.25V.
The SEL pin is internally pulled low through 4MΩ resistor
to ground. The OE pin is internally pulled high through a
4MΩ resistor to VDD. These pins can be tri-stated by a
µProcessor or left floating.
Logic Control Voltage Levels
TABLE 2. LOGIC CONTROL VOLTAGE LEVELS
VDD SUPPLY
RANGE
2.7V to 3.6V
LOGIC = “0” (LOW)
LOGIC = “1”
(HIGH)
When a USB cable from a computer or USB hub is
connected at the common USB connector and the part
has Channel 2 active, a link will be established between
the USB 2 driver section of the media player and the
computer. The device will be able to transmit and receive
data from the computer.
All Switches OFF Mode
If the SEL pin = Logic “0” and the OE pin = Logic “1”, all of
the switches will turn OFF (high impedance) and the part
will be put in a low power mode. In this mode, the part
draws only 10µA (max) of current across the operating
temperature range. In the low power mode, the persistence
checking of the OVP circuitry is de-activated.
If the SEL pin = Logic “1” and the OE pin = Logic “1”, all
of the switches will turn OFF (high impedance). In this
state the complete OTV circuitry is activated.
The all OFF state can be used to switch between the two
USB sections of the media player. When disconnecting
from one USB device to the other USB device, you can
momentarily put the ISL54225 switch in the “all off”
state in order to get the computer to disconnect from
the one device so it can properly connect to the other
USB device when that channel is turned ON.
Whenever the ISL54225 senses a fault condition on the
COM pins, all switches will be turned OFF regardless of
the voltage levels at the SEL and OE pins.
OE
SEL
OE
SEL
≤ 0.5V
≤ 0.5V
or
floating
≥1.4V
or
floating
≥1.4V
USB 2.0 VBUS Short Requirements
The USB specification in section 7.1.1 states a USB
device must be able to withstand a VBUS short (4.4V to
5.25V) or a -1V short to the D+ or D- signal lines when
the device is either powered off or powered on for at
least 24 hours.
3.7V to 4.2V
≤ 0.7V
≤ 0.7V
or
floating
≥1.7V
or
floating
≥1.7V
4.3V to 5.25V
≤ 0.8V
≤ 0.8V
or
floating
≥2.0V
or
floating
≥2.0V
HSD1 USB Channel
If the SEL pin = Logic “0” and the OE pin = Logic “0”,
high-speed Channel 1 will be ON. The HSD1- and HSD1+
switches are ON and the HSD2- and HSD2+ switches are
OFF (high impedance).
When a computer or USB hub is plugged into the
common USB connector and Channel 1 is active, a link
will be established between the USB 1 transceiver section
of the media player and the computer. The device will be
able to transmit and receive data from the computer.
HSD2 USB Channel
The ISL54225 part has special power-off protection and
OVP detection circuitry to meet these short circuit
requirements. This circuitry allows the ISL54225 to
provide protection to the USB down-stream transceivers
connected at its signal pins (HS1D-, HS1D+, HS2D-,
HS2D+) to meet the USB specification short circuit
requirements.
The power-off protection and OVP circuitry allows the COM
pins (D-, D+) to be driven up to 5.25V or down to -5V while
the VDD supply voltage is in the range of 0V to 5.25V. In
these overvoltage conditions with a 500Ω external VDD
resistor, the part draws < 55µA of current into the COM pins
and causes no stress/damage to the IC. In addition, all
switches are OFF and the shorted VBUS voltage will be
isolated from getting through to the other side of the switch
channels, thereby protecting the USB transceivers.
If the SEL pin = Logic “1” and the OE pin = Logic “0”,
high-speed Channel 2 will be ON. The HSD2- and HSD2+
switches are ON and the HSD1- and HSD1+ switches are
OFF (high impedance).
11
FN7627.0
July 2, 2010
ISL54225
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified
30
6.5
6.4
ICOM = 17mA
ICOM = 17mA
25
2.7V
6.3
20
rON (Ω)
rON (Ω)
6.2
3.0V
6.1
6.0
3.3V
5.9
3.6V
5.8
4.3V
5.7
5.25V
15
2.7V
10
3.3V
5
5.6
0
0.1
0.2
VCOM (V)
0.3
0
0
0.4
0.6
1.2
1.8
2.4
3.0
3.6
VCOM (V)
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
8
12
ICOM = 17mA
+85°C
7
10
3.6V
+25°C
rON (Ω)
rON (Ω)
3.0V
8
5.25V
6
4.3V
-40°C
6
5
VDD = 2.7V
4
0
0.6
1.2
1.8
VCOM (V)
2.4
3.0
3.6
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
8
4
0
0.2
VCOM (V)
0.3
0.4
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
VDD = 4.3V
ICOM = 17mA
+85°C
+85°C
7
rON (Ω)
7
rON (Ω)
0.1
8
VDD = 3.3V
ICOM = 17mA
+25°C
6
5
4
0
ICOM = 17mA
0.2
VCOM (V)
0.3
0.4
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
12
+25°C
5
-40°C
0.1
6
4
-40°C
0
0.1
0.2
VCOM (V)
0.3
0.4
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
FN7627.0
July 2, 2010
ISL54225
Typical Performance Curves
18
VDD = 2.7V
ICOM = 17mA
25
15
20
12
rON (W)
rON (W)
30
TA = +25°C, Unless Otherwise Specified (Continued)
15
+85°C
9
+25°C
+85°C
6
10
0
-40°C
+25°C
5
3
-40°C
0
0.6
1.2
1.8
VCOM (V)
2.4
3.0
0
0
3.6
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
350
-40°C TO +85°C
IDD CURRENT (µA)
VINH AND VINL (V)
1.2
1.8
2.4
VCOM (V)
3.0
3.6
SEL = “0” OR “1”
300
1.4
VINH
1.2
1.0
VINL
0.8
0.6
250
3.2
3.7
4.2
VDD (V)
4.7
150
100
50
-50
0
5.25
VDD = 5.25V
200
0
0.4
2.7
VDD = 3.3V
1
2
3
4
OE LOGIC VOLTAGE (V)
5
FIGURE 18. IDD vs OE LOGIC VOLTAGE vs VDD
FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY
VOLTAGE
700
45
VDD = 3.3V
40
600
30
OE = “0” (NORMAL OPERATION)
25
20
15
10
OE = “1” (LOW POWER)
5
0
IDD CURRENT (µA)
35
VDD = 5.25V
500
400
300
200
OE = “0” (NORMAL OPERATION)
100
0
-5
-10
0.6
FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE
1.6
IDD CURRENT (µA)
VDD = 3.3V
ICOM = 17mA
0
1
2
3
4
OE LOGIC VOLTAGE (V)
5
FIGURE 19. IDD vs SEL LOGIC VOLTAGE vs OE STATE
13
-100
0
OE = “1” (LOW POWER)
1
2
3
4
OE LOGIC VOLTAGE (V)
5
FIGURE 20. IDD vs SEL LOGIC VOLTAGE vs OE STATE
FN7627.0
July 2, 2010
ISL54225
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified (Continued)
VOLTAGE SCALE (0.1V/DIV)
VDD = 3.3V
TIME SCALE (0.2ns/DIV)
FIGURE 21. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH
VOLTAGE SCALE (0.5V/DIV)
VDD = 3.3V
TIME SCALE (10ns/DIV)
FIGURE 22. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH
14
FN7627.0
July 2, 2010
ISL54225
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified (Continued)
-10
1
RL = 50Ω
-20 VIN = 0dBm, 0.2VDC BIAS
0
-30
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
-1
-2
-3
-4
RL = 50Ω
VIN = 0dBm, 0.86VDC BIAS
1M
-40
-50
-60
-70
-80
-90
-100
10M
100M
FREQUENCY (Hz)
1G
-110
0.001
0.01
0.1
1
10
100
500
FREQUENCY (MHz)
FIGURE 24. OFF-ISOLATION
FIGURE 23. FREQUENCY RESPONSE
Die Characteristics
SUBSTRATE AND TDFN THERMAL PAD
POTENTIAL (POWERED UP):
-10
NORMALIZED GAIN (dB)
RL = 50Ω
-20 VIN = 0dBm, 0.2VDC BIAS
GND
-30
TRANSISTOR COUNT:
-40
-50
1297
-60
PROCESS:
Submicron CMOS
-70
-80
-90
-100
-110
0.001
0.01
0.1
1
10
100
500
FREQUENCY (MHz)
FIGURE 25. CROSSTALK
15
FN7627.0
July 2, 2010
ISL54225
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
7/2/10
FN7627.0
CHANGE
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL54225
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
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patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN7627.0
July 2, 2010
ISL54225
Package Outline Drawing
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
1.80
B
6
PIN #1 ID
A
1
1
1.40
3
10
0.50
6 PIN 1
INDEX AREA
9 X 0.40
2
10X 0.20 4
0.10 M C A B
0.05 M C
0.70
8
5
0.10
7
2X
4X 0.30
6
6X 0.40
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
MAX. 0.55
C
SEATING PLANE
0.08 C
(9 X 0.60)
1
(10X 0.20)
(4X 0.30)
3
10
8
(0.70)
SIDE VIEW
(0.70)
C
5
6
0 .1 27 REF
7
(6X 0.40)
PACKAGE OUTLINE
0-0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
JEDEC reference MO-255.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
17
FN7627.0
July 2, 2010
ISL54225
Package Outline Drawing
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
3.00
A
2.0 REF
6
PIN 1
INDEX AREA
B
8X 0.50 BSC
5
1
6
PIN 1
INDEX AREA
10X 0 . 30
3.00
1.50
0.15
(4X)
10
0.10 M C A B
0.05 M C
5
4 10 X 0.25
TOP VIEW
2.30
( 2.30 )
BOTTOM VIEW
0 .80 MAX
SEE DETAIL "X"
0.10 C
C
(2.90)
SEATING PLANE
0.08 C
(1.50)
SIDE VIEW
(10 X 0.50)
0 . 2 REF
5
C
( 8X 0 .50 )
( 10X 0.25 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
Angular ±2.50°
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7.
18
Compliant to JEDEC MO-229-WEED-3 except exposed pad length (2.30mm).
FN7627.0
July 2, 2010
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