DATASHEET

ISL54221
®
Data Sheet
December 16, 2008
High-Speed USB 2.0 (480Mbps)
Multiplexer
FN6820.0
Features
• High-Speed (480Mbps) and Full-Speed (12Mbps)
Signaling Capability per USB 2.0
The Intersil ISL54221 is a single supply dual 2:1 multiplexer
that can operate from a single 2.7V to 5.5V supply. It contains
two SPDT (Single Pole/Double Throw) switches configured as
a DPDT. The part was designed for switching or routing of
USB High-Speed signals and/or USB Full-speed signals in
portable battery powered products.
• 1.8V Logic Compatible (2.7V to +3.6V supply)
• Enable Pin to Open all Switches
• Power OFF Protection
• D-/D+ Pins Overvoltage Tolerant to 5.5V
The 6.7Ω switches can swing rail to rail and were specifically
designed to pass USB full-speed data signals that range from
0V to 3.3V and USB high-speed data signals that range from
0V to 400mV. They have high bandwidth and low capacitance
to pass USB high-speed data signals with minimal distortion.
• -3dB Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 742MHz
• Low ON Capacitance. . . . . . . . . . . . . . . . . . . . . . . . 7.4pF
• Low ON-Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6.7Ω
• Single Supply Operation (VDD) . . . . . . . . . . . . 2.7V to 5.5V
The part can be used in Personal Media Players and other
portable battery powered devices that need to route USB
high-speed signals or full-speed signals to different
transceiver sections of the device while connected to a single
USB host (computer).
• Available in µTQFN Package
• Pb-Free (RoHS Compliant)
• Compliant with USB 2.0 Short Circuit and Overvoltage
Requirements Without Additional External Components
The digital logic inputs are 1.8V logic compatible when
operated with a 2.7V to 3.6V supply. The ISL54221 has an
output enable pin to open all the switches. It can be used to
facilitate proper bus disconnect and connection when
switching between the USB sources.
Applications
• MP3 and other Personal Media Players
• Cellular/Mobile Phones
• PDA’s
The ISL54221 is available in a tiny 10 Ld 2.1mmx1.6mm
µTQFN package. It operates over a temperature range of
-40 to +85°C.
• Digital Cameras and Camcorders
• USB Switching
Application Block Diagram
µCONTROLLER
VDD
ISL54221
SEL
USB CONNECTOR
OE
LOGIC CIRCUITRY
VBUS
HSD1-
D-
D-
HSD1+
D+
D+
HSD2HSD2+
GND
USB
HIGH-SPEED
OR
FULL-SPEED
TRANSCEIVER
USB
HIGH_SPEED
OR
FULL-SPEED
TRANSCEIVER
GND
PORTABLE MEDIA DEVICE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54221
Pinout
VDD
ISL54221
10 LD 2.1 X 1.6 µTQFN
TOP VIEW
10
LOGIC
CONTROL
9
OE
2
8
HSD1-
HSD2+
3
7
HSD2-
D+
4
6
D-
SEL
1
HSD1+
GND
5
NOTE:
1. Switches Shown for SEL = Logic “1” and OE = Logic “0”.
Truth Table
Pin Descriptions
OE
SEL
HSD1-, HSD1+
HSD2-, HSD2+
PIN NAME
0
0
ON
OFF
VDD
Power Supply
0
1
OFF
ON
GND
Ground Connection
1
X
OFF
OFF
SEL
Select Logic Control Input
OE
Bus Switch Enable
Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a 2.7V to 3.6V
Supply.
DESCRIPTION
D+, D-, HSDx+, HSDx- USB Data Port
Ordering Information
PART NUMBER
(Note)
ISL54221IRUZ-T*
PART
MARKING
GL
TEMP. RANGE
(°C)
-40 to +85
PACKAGE
(Pb-Free)
10 Ld 2.1x1.6mm µTQFN (Tape and Reel)
PKG.
DWG. #
L10.2.1x1.6A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6820.0
December 16, 2008
ISL54221
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5V
Input Voltages
HSD2x, HSD1x (Note 2). . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
SEL, OE (Note 2) . . . . . . . . . . . . . . . . . . . . -0.3 to ((VDD) + 0.3V)
Output Voltages
D+, D- (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Continuous Current (HSD2x, HSD1x) . . . . . . . . . . . . . . . . . . ±40mA
Peak Current (HSD2x, HSD1x)
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±100mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
10 Ld µTQFN Package . . . . . . . . . . . . . . . . . . . . . .
155
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Logic Control Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on HSD1x, HSD2x, D+,D- exceeding GND by specified amount are clamped. Signals on OE and SEL exceeding VDD or GND by
specified amount are clamped. Limit current to maximum current ratings.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 2.7V to 5.5V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V,
VOEH = 1.4V, VOEL = 0.5V, (Note 4), Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 6)
TYP
MAX
(Notes 5, 6) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
VDD = VDD, SEL = 0V or VDD, OE = 0V
Full
0
-
VDD
V
ON-Resistance, rON (High-Speed)
VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA,
VHSD1x or VHSD2 x = 0V to 400mV (see Figure 3, Note 9)
25
-
6.7
8
Ω
Full
-
-
10
Ω
25
-
0.117
0.45
Ω
Full
-
-
0.55
Ω
25
-
0.94
1.2
Ω
Full
-
-
1.3
Ω
25
-15
0.31
15
nA
Full
-20
-
20
nA
25
-20
2.2
20
nA
Full
-25
-
25
nA
25
-15
0.26
15
nA
Full
-20
-
20
nA
25
-20
2.1
20
nA
Full
-25
-
25
nA
25
-
0.0047
0.025
µA
Full
-
-
0.40
µA
rON Matching Between Channels,
ΔrON (High-Speed)
VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA,
V VHSD1x or VHSD2 x = Voltage at max rON, (Notes 8, 9)
rON Flatness, RFLAT(ON)
(High-Speed)
VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA,
VHSD1x or VHSD2 x = 0V to 400mV, (Notes 7, 9)
OFF Leakage Current, IHSD1x(OFF) VDD = 5.5V, SEL = VDD and OE = 0V or OE = VDD,
VDx = 0.3V, 3.3V, VHSD1X = 3.3V, 0.3V, VHSD2x = 0.3V,
3.3V
ON Leakage Current, IHSD1x(ON)
VDD = 5.5V, SEL = OE = 0V, VDx = 0.3V, 3.3V,
VHSD1X = 0.3V, 3.3V, VHSD2x = 3.3V, 0.3V
OFF Leakage Current, IHSD2x(OFF) VDD = 5.5V, SEL = OE = 0V or OE = VDD, VDx = 3.3V,
0.3V, VHSD2x = 0.3V, 3.3V, VHSD1X = 3.3V, 0.3V
ON Leakage Current, IHSD2x(ON)
VDD = 5.5V, SEL = VDD, OE = 0V, VDx= 0.3V, 3.3V,
VHSD2x = 0.3V, 3.3V, VHSD1X = 3.3V, 0.3V
Power OFF Leakage Current, ID+, ID- VDD = 0V, VD+ = 0V to 5.25V, VD-= 0V to 5.25V,
SEL = OE = VDD
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VDD = 3.3V, RL = 50Ω, CL = 10pF (see Figure 1)
25
-
35
-
ns
Turn-OFF Time, tOFF
VDD = 3.3V, RL = 50Ω, CL = 10pF (see Figure 1)
25
-
27
-
ns
Break-Before-Make Time Delay, tD
VDD = 3.3V, RL = 50Ω, CL = 10pF (see Figure 2)
25
-
10
-
ns
3
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ISL54221
Electrical Specifications - 2.7V to 5.5V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V,
VOEH = 1.4V, VOEL = 0.5V, (Note 4), Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 6)
TYP
MAX
(Notes 5, 6) UNITS
Skew, (tSKEWOUT - tSKEWIN)
VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45Ω,
CL = 10pF, tR = tF = 720ps at 480Mbps,
(Duty Cycle = 50%) (see Figure 6)
25
-
50
-
ps
Rise/Fall Degradation (Propagation
Delay), tPD
VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45Ω,
CL = 10pF (see Figure 6)
25
-
250
-
ps
Crosstalk
VDD = 3.3V, RL = 50Ω, f = 240MHz (see Figure 5)
25
-
-36
-
dB
OFF-Isolation
VDD = 3.3V, OE = 3.3V, RL = 50Ω, f = 240MHz
25
-
-32
-
dB
-3dB Bandwidth
Signal = 0dBm, 0.2Vdc offset, RL = 50Ω
25
-
742
-
MHz
OFF Capacitance, CHSxOFF
f = 1MHz, VDD = 3.3V, SEL = 0V, OE = 3.3V, VHSD1x or
VHSD2x = VDx = 0V (see Figure 4)
25
-
2.8
-
pF
COM ON Capacitance, CDX(ON)
f = 1MHz, VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V,
VHSD1x or VHSD2x = VDx = 0V (see Figure 4)
25
-
7.4
-
pF
Full
2.7
5.5
V
25
-
0.009
0.03
µA
Full
-
-
1
µA
25
-
0.159
0.6
µA
Full
-
-
1.6
µA
25
-
6.6
10
µA
Full
-
-
12
µA
POWER SUPPLY CHARACTERISTICS
Power Supply Range, VDD
Positive Supply Current, IDD
VDD = 5.5V, SEL = 0V or VDD, OE = 0V or VDD
Positive Supply Current, IDD
VDD = 4.3V, SEL = 2.6V, OE = 0V or 2.6V
Positive Supply Current, IDD
VDD = 3.6V, SEL = 1.4V, OE = 0V or 1.4V
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VSELL, VOEL
VDD = 2.7V to 3.6V
Full
-
-
0.5
V
Input Voltage High, VSELH, VOEH
VDD = 2.7V to 3.6V
Full
1.4
-
-
V
Input Voltage Low, VSELL, VOEL
VDD = 4.3V to 5.5V
Full
-
-
0.8
V
Input Voltage High, VSELH, VOEH
VDD = 4.3V to 5.5V
Full
2.0
-
-
V
Input Current, ISELL, IOEL
VDD = 5.5V, SEL = 0V, OE = 0V
Full
-
3.3
-
nA
Input Current, ISELH
VDD = 5.5V, SEL = 5.5V
Full
-
-3.6
-
nA
Input Current, IOEH
VDD = 5.5V, OE = 5.5V
Full
-
-8.2
-
nA
NOTES:
4. VLOGIC = Input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range
8. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between HSD2+ and HSD2- or between HSD1+ and HSD1-.
9. Limits established by characterization and are not production tested.
4
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December 16, 2008
ISL54221
Test Circuits and Waveforms
VDD
LOGIC
INPUT
VDD
tr < 20ns
tf < 20ns
50%
0V
VINPUT
tOFF
SWITCH
INPUT VINPUT
SWITCH
INPUT
VOUT
HSDxx
Dx
SEL
VOUT
90%
90%
SWITCH
OUTPUT
C
VIN
RL
50Ω
OE
GND
0V
CL
10pF
tON
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (INPUT) -----------------------R L + r ON
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
VDD
C
VDD
LOGIC
INPUT
HSD2x
VINPUT
0V
RL
50Ω
SEL
SWITCH
OUTPUT
VOUT
90%
GND
VIN
0V
VOUT
Dx
HSD1x
CL
10pF
OE
tD
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. BREAK-BEFORE-MAKE TIME
VDD
C
rON = V1/40mA
HSDx
VHSDX
SEL
V1
40mA
OV OR VDD
Dx
GND
OE
Repeat test for all switches.
FIGURE 3. rON TEST CIRCUIT
5
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December 16, 2008
ISL54221
Test Circuits and Waveforms (Continued)
VDD
VDD
C
C
SIGNAL
GENERATOR
HSDxx
HSD1x
SEL
SEL
IMPEDANCE
ANALYZER
0V OR
VDD
Dx
GND
OE
VIN
Dx
ANALYZER
HSD2x
GND
RL
Repeat test for all switches.
50Ω
Dx
NC
OE
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 4. CAPACITANCE TEST CIRCUIT
FIGURE 5. CROSSTALK TEST CIRCUIT
VDD
C
tri
90%
DIN+
10%
50%
VIN
tskew_i
DIN-
90%
SEL
15.8Ω
DIN+
50%
143Ω
10%
DIN-
tfi
tro
15.8Ω
OUT+
D2
COMD2
CL
COMD1
143Ω
OUT-
D1
OE
45Ω
CL
45Ω
90%
OUT+
OUT-
10%
50%
GND
tskew_o
50%
90%
10%
tf0
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals.
|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
FIGURE 6A. MEASUREMENT POINTS
FIGURE 6B. TEST CIRCUIT
FIGURE 6. SKEW TEST
6
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December 16, 2008
ISL54221
Application Block Diagram
µCONTROLLER
VDD
ISL54221
SEL
USB CONNECTOR
OE
LOGIC CIRCUITRY
VBUS
HSD1-
D-
D-
HSD1+
D+
D+
HSD2HSD2+
GND
USB
HIGH-SPEED
OR
FULL-SPEED
TRANSCEIVER
USB
HIGH_SPEED
OR
FULL-SPEED
TRANSCEIVER
GND
PORTABLE MEDIA DEVICE
Detailed Description
The ISL54221 device is a dual single pole/double throw
(SPDT) analog switch configured as a DPDT that operates
from a single DC power supply in the range of 2.7V to 5.5V.
It was designed to function as a dual 2-to-1 multiplexer to
select between two USB high-speed differential data signals
in portable battery powered products. It is offered in a small
µTQFN package for use in MP3 players, cameras, PDAs,
cellphones, and other personal media players. The device
has an enable pin to open all switches.
The part consists of four 6Ω high-speed (HSx) switches.
These switches have high bandwidth and low capacitance to
pass USB high-speed (480Mbps) differential data signals
with minimal edge and phase distortion. They can also swing
from 0V to VDD to pass USB full-speed (12Mbps) differential
data signals with minimal distortion.
The ISL54221 was designed for MP3 players, cameras,
cellphones, and other personal media player applications
that have multiple high-speed or full-speed transceivers
sections and need to multiplex between these USB sources
to a single USB host (computer). A typical application block
diagram of this functionality is shown on page 7.
A detailed description of the HS switches is provided in the
following section.
High-Speed (HSx) Switches
The HSx switches (HSD1-, HSD1+, HSD2-, HSD2+) are
bi-directional switches that can pass rail-to-rail signals.
When powered with a 3.3V supply, these switches have a
nominal rON of 6Ω over the signal range of 0V to 400mV with
a rON flatness of 0.94Ω. The rON matching between the
7
HSD1 and HSD2 switches over this signal range is only
0.12Ω, ensuring minimal impact by the switches to USB
high-speed signal transitions. As the signal level increases,
the rON switch resistance increases. At signal level of 3.3V,
the switch resistance is nominally 129Ω. See Figures 7, 8, 9
and 10 in the “Typical Performance Curves” on page 9.
The HSx switches were specifically designed to pass USB
2.0 high-speed (480Mbps) differential signals in the range of
0V to 400mV. They have low capacitance and high
bandwidth to pass the USB high-speed signals with
minimum edge and phase distortion to meet USB 2.0
high-speed signal quality specifications. See Figure 11 in the
“Typical Performance Curves” on page 10 for USB
High-speed Eye Pattern taken with switch in the signal path.
The HSx switches can also pass USB full-speed signals
(12Mbps) with minimal distortion and meet all the USB
requirements for USB 2.0 full-speed signaling. See Figure 12
in the “Typical Performance Curves” on page 11 for the USB
Full-speed Eye Pattern taken with switch in the signal path.
The maximum normal operating signal range for the HSx
switches is from 0V to VDD. The signal voltage should not be
allow to exceed the VDD voltage rail or go below ground by
more than 0.3V for normal operation.
However in the event that the USB 5.25V VBUS voltage gets
shorted to one or both of the D-/D+ pins, the ISL54221 has
special fault protection circuitry to prevent damage to the
ISL54221 part. The fault circuitry allows the signal pins (D-,
D+, HS1D-, HS1D+, HS2D-, HS2D+) to be driven up to 5.5V
while the VDD supply voltage is in the range of 0V to 5.5V. In
this condition the part draws < 500µA of current and causes
no stress to the IC. In addition when VDD is at 0V (ground)
FN6820.0
December 16, 2008
ISL54221
all switches are OFF and the fault voltage is isolated from
the other side of the switch. When VDD is in the range of
2.7V to 5.5V the fault voltage will pass through to the output
of an active switch channel.
The HS1 channel switches are active (turned ON) whenever
the SEL voltage is logic”0”(Low) and the OE voltage is
logic”0”(Low).
The HS2 channel switches are active (turned ON) whenever
the SEL voltage is logic “1” (High) and the OE voltage is
logic “0” (Low).
ISL54221 Operation
The following will discuss using the ISL54221 the “Application
Block Diagram” on page 7.
POWER
The power supply connected at the VDD pin provides the
DC bias voltage required by the ISL54221 part for proper
operation. The ISL54221 can be operated with a VDD
voltage in the range of 2.7V to 5.5V. When used in a USB
application, the VDD voltage should be kept in the range of
3.0V to 5.5V to ensure you get the proper signal levels for
good signal quality.
A 0.01µF or 0.1µF decoupling capacitor should be
connected from the VDD pin to ground to filter out any power
supply noise from entering the part. The capacitor should be
located as close to the VDD pin as possible.
In a typical application, VDD will be in the range of 2.8V to
4.3V and will be connected to the battery or LDO of the
portable media device.
With VDD supply voltage in the range of 4.3V to 5.5V the
logic levels are:
OE = Logic “0” (Low) when VOE ≤ 0.8V
OE = Logic “1” (High) when VOE ≥ 2.0V
SEL = Logic “0” (Low) when VSEL ≤ 0.8V
SEL = Logic “1” (High) when VSEL ≥ 2.0V
HSD1 USB Channel
If the SEL pin = Logic “0” and the OE pin = Logic “0”,
high-speed Channel 1 will be ON. The HSD1- and HSD1+
switches are ON and the HSD2- and HSD2+ switches are
OFF (high impedance).
When a computer or USB hub is plugged into the common
USB connector and channel one is active, a link will be
established between the USB 1 driver section of the media
player and the computer. The device will be able to transmit
and receive data from the computer at a data rate of
480Mbps.
HSD2 USB Channel
If the SEL pin = Logic “1” and the OE pin = Logic “0”,
high-speed Channel 2 will be ON. The HSD2- and HSD2+
switches are ON and the HSD1- and HSD1+ switches are
OFF (high impedance).
When a USB cable from a computer or USB hub is
connected at the common USB connector and the part has
Channel 2 active, a link will be established between the USB
2 driver section of the media player and the computer. The
device will be able to transmit and receive data from the
computer at a data rate of 480Mbps.
All Switches OFF Mode
LOGIC CONTROL
The state of the ISL54221 device is determined by the
voltage at the SEL pin and the OE pin. SEL is only active
when the OE pin is logic “0” (Low). Refer to “Truth Table” on
page 2.
The ISL54221 logic pins are designed to minimize current
consumption when the logic control voltage is lower than the
VDD supply voltage. With VDD = 3.6V and logic pins at 1.4V
the part typically draws only 6.6µA. With VDD = 4.3V and
logic pins at 2.6V the part typically draws only 0.2µA. Driving
the logic pins to the VDD supply rail minimizes power
consumption.
The logic pins must be held High or Low and must not float.
Logic Control Voltage Levels
With VDD supply voltage in the range of 2.7V to 3.6V the
logic levels are:
OE = Logic “0” (Low) when VOE ≤ 0.5V
OE = Logic “1” (High) when VOE ≥ 1.4V
SEL = Logic “0” (Low) when VSEL ≤ 0.5V
SEL = Logic “1” (High) when VSEL ≥ 1.4V
8
If the SEL pin = Logic “0” or Logic “1” and the OE pin =
Logic “1”, all of the switches will turn OFF (high impedance).
The all OFF state can be used to switch between the two
USB sections of the media player. When disconnecting from
one USB device to the other USB device, you can
momentarily put the ISL54221 switch in the “all off” state in
order to get the computer to disconnect from the one device
so it can properly connect to the other USB device when that
channel is turned ON.
USB 2.0 VBUS Short Requirements
The USB specification in section 7.1.1 states a USB device
must be able to withstand a VBUS short to the D+ or Dsignal lines when the device is either powered off or
powered on for at least 24 hours. The ISL54220 part has
special fault protection circuitry to meet these short circuit
requirements.
The fault protection circuitry allows the signal pins (D-, D+,
HS1D-, HS1D+, HS2D-, HS2D+) to be driven up to 5.5V
while the VDD supply voltage is in the range of 0V to 5.5V. In
this overvoltage condition the part draws < 500µA of current
and causes no stress/damage to the IC.
FN6820.0
December 16, 2008
ISL54221
In addition when VDD is at 0V (ground) all switches are OFF
and the shorted VBUS voltage is isolated from the other side
of the switch. When VDD is in the range of 2.7V to 5.5V the
shorted VBUS voltage will pass through to the output of an
active (turned ON) switch channel but not through a turned
OFF channel. Any components connected on the active
channel must be able to withstand the overvoltage condition.
Note: During the fault condition normal operation of the USB
channel is not guaranteed until the fault condition is
removed.
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
200
8
ICOM = 1mA
ICOM = 40mA
VDD = 3.0V
150
7
VDD = 2.7V
rON (Ω)
rON (Ω)
VDD = 2.7V
VDD = 3.6V
5
50
VDD = 5.5V
4
0
0.05
0.10
0.15
0.20
0.25
VCOM (V)
VDD = 3.3V
100
VDD = 3.3V
6
0.30
0.35
0
0.40
FIGURE 7. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0
0.5
1.0
2.5
3.0
3.3
FIGURE 8. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
9
8
V+ = 2.7V
ICOM = 40mA
+85°C
8
V+ = 3.3V
ICOM = 40mA
7
+85°C
6
7
+25°C
rON (Ω)
+25°C
rON (Ω)
1.5
2.0
VCOM (V)
6
5
-40°C
-40°C
5
4
4
3
3
0
0.1
0.2
VCOM (V)
0.3
FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE
9
0.4
2
0
0.1
0.2
VCOM (V)
0.3
0.4
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
FN6820.0
December 16, 2008
ISL54221
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
VDD = 3.3V
VOLTAGE SCALE (0.1V/DIV)
VDD = 3.3V
TIME SCALE (0.2ns/DIV)
FIGURE 11. EYE PATTERN: 480Mbps WITH SWITCHES IN THE SIGNAL PATH
10
FN6820.0
December 16, 2008
ISL54221
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
VOLTAGE SCALE (0.5V/DIV)
VDD = 3.3V
TIME SCALE (10ns/DIV)
1
-10
0
-20
-1
-30
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
FIGURE 12. EYE PATTERN: 12Mbps WITH SWITCHES IN THE SIGNAL PATH
-2
-3
-4
RL = 50Ω
VIN = 0dBm, 0.2VDC BIAS
RL = 50Ω
VIN = 0dBm, 0.2VDC BIAS
-40
-50
-60
-70
-80
-90
-100
1M
10M
100M
FREQUENCY (Hz)
FIGURE 13. FREQUENCY RESPONSE
11
1G
-110
0.001
0.01
0.1
1M
10M
FREQUENCY (Hz)
100M
500M
FIGURE 14. OFF-ISOLATION
FN6820.0
December 16, 2008
ISL54221
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
Die Characteristics
-10
-20
RL = 50Ω
VIN = 0dBm, 0.2VDC BIAS
SUBSTRATE POTENTIAL (POWERED UP):
GND
NORMALIZED GAIN (dB)
-30
TRANSISTOR COUNT:
-40
325
-50
PROCESS:
-60
Submicron CMOS
-70
-80
-90
-100
-110
0.001
0.01
0.1
1M
10M
FREQUENCY (Hz)
100M
500M
FIGURE 15. CROSSTALK
12
FN6820.0
December 16, 2008
ISL54221
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
6
INDEX AREA
A
L10.2.1x1.6A
B
N
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
E
SYMBOL
2X
MIN
NOMINAL
MAX
1
2X
2
0.10 C
TOP VIEW
C
A
0.05 C
SEATING PLANE
1
0.45
0.50
0.55
-
A1
-
-
0.05
-
0.127 REF
-
b
0.15
0.20
0.25
5
D
2.05
2.10
2.15
-
E
1.55
1.60
1.65
-
A1
e
SIDE VIEW
k
0.20
-
-
L
0.35
0.40
0.45
(DATUM A)
PIN #1 ID
A
A3
0.10 C
4xk
2
NX L
0.50 BSC
-
NX b
e
2
Nd
4
3
Ne
1
3
0
12
-
NOTES:
5
BOTTOM VIEW
CL
(A1)
L
5
e
SECTION "C-C"
TERMINAL TIP
C C
4
Rev. 3 6/06
0.10 M C A B
0.05 M C
3
(ND-1) X e
-
10
(DATUM B)
N-1
-
N
θ
N
NX (b)
NOTES
0.10 C
FOR ODD TERMINAL/SIDE
b
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. Same as JEDEC MO-255UABD except:
No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm
"L" MAX dimension = 0.45 not 0.42mm.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
2.50
1.75
0.05 MIN
L
2.00
0.80
0.275
0.10 MIN
DETAIL “A” PIN 1 ID
0.50
0.25
LAND PATTERN 10
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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13
FN6820.0
December 16, 2008
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