User Guide 009 ISL8011xEVAL1Z Evaluation Board User Guide Key Features Description The ISL8011xEVAL1Z provides a simple platform to evaluate performance of the ISL8011x family of split supply LDOs. Jumpers are provided to easily set popular output voltages. The ISL80111, ISL80112 and ISL80113 are single-output LDOs specified for 1A, 2A, 3A of output current and are optimized for less than 2.5V and less output voltage conversions. The ISL8011x supports VIN voltages down to 1V, provided a standard legacy 2.9V or 5.5V is applied on the VBIAS pin. The output voltage is adjustable from 0.8V to 3.3V. • Ultra low dropout: 75mV at 3A, (typ) • Excellent VIN PSRR: 70dB at 1kHz (typ) • ±1.6% guaranteed VOUT accuracy for -40ºC < TJ < +125ºC • Very fast load transient response References ISL80111, ISL80112, ISL80113 Datasheet Ordering Information Specifications PART NUMBER DESCRIPTION This board has been configured and optimized for the following operating conditions: ISL80111EVAL1Z 1A, Split Supply LDO Evaluation Board • VIN range of 1V to 3.6V ISL80112EVAL1Z 2A, Split Supply LDO Evaluation Board • VOUT adjustable from 0.8V to 3.3V ISL80113EVAL1Z 3A, Split Supply LDO Evaluation Board • Convenient power connection • Popular output voltages can easily set by jumpers FIGURE 1. ISL80111EVAL1Z TOP SIDE October 30, 2014 UG009.0 1 FIGURE 2. ISL80111EVAL1Z BOTTOM SIDE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. User Guide 009 What’s Inside PCB Layout Guidelines The evaluation kit contains the following: The following is an example of how to use vias to remove heat from the IC. • The ISL80113EVAL1Z with the appropriate parts installed • ISL80111, ISL80112, ISL80113 Datasheet Test Steps 1. Select the desired output voltage by shorting one of the jumpers from JP2 through JP5. Filling the thermal pad area with vias is recommended. A typical via array is to fill the thermal pad footprint with vias spaced such that they are center on center 3x the radius apart from each other. Keep the vias small but not so small that their inside diameter prevents solder from wicking through the holes during reflow. 2. Connect both the BIAS and VIN supplies and the load. Enable the IC using jumper JP6 (bottom position) or via a signal on the center post, observe the output. 3. The shipped configuration is enabled and VOUT = 3.3V. 4. Scope shots taken from ISL8011xEVAL1Z boards. Functional Description The ISL8011xEVAL1Z provides a simple platform to evaluate performance of the ISL8011x family of split supply LDOs. Jumpers are provided to easily set popular output voltages. The ISL80111, ISL80112 and ISL80113 are single-output LDOs specified for 1A, 2A, 3A of output current and are optimized for less than 2.5V and less output voltage conversions. The ISL8011X supports VIN voltages down to 1V, provided a standard legacy 2.9V or 5.5V is applied on the VBIAS pin. The output voltage is adjustable from 0.8V to 3.3V. FIGURE 3. PCB VIA PATTERN Connect all vias to the round plane. For efficient heat transfer, it is important that the vias have low thermal resistance. Do not use “thermal relief” patterns to connect the vias. It is important to have a complete connection of the plated through-hole to each plane. An enable input, having a threshold <1V, allows the part to be placed into a low quiescent current shutdown mode. A submicron CMOS process is utilized for this product family to deliver best-in-class analog performance and overall value for applications in need of input voltage conversions to typically below 2.5V. It also has the superior load transient regulation unique to a NMOS power stage. These LDOs consume significantly lower quiescent current as a function of load compared to bipolar LDOs. This lower consumption translates into higher efficiency and the ability to consider packages with smaller footprints. The quiescent current has been modestly compromised in design to enable leading class fast load transient response and load regulation. Submit Document Feedback 2 UG009.0 October 30, 2014 User Guide 009 Schematic U1 VADJ GND C2 1UF JP6 R7 100K TP2 VIN VOUT VIN 10 2 VOUT VIN 9 3 ADJ NC 8 4 VBIAS EN 7 5 GND PG 6 TP4 C3 C1 VBIAS 10UF TP1 1 11 10UF VOUT TP5 PG EP TP6 ISL80113IRAJZ TP3 GND EN 5.62K JP5 R5 JP4 R4 4.02K 2.61K JP3 R3 2.05K JP2 R2 1K R1 JP1 TP7 EVALUATION BOARD FOR: ISL80111 3.3V 2.5V 1.8V ISL80113 ISL80114 1K R6 1.5V 1.0V ISL80112 Bill of Materials REFERENCE DESIGNATOR VALUE U1 DESCRIPTION MANUFACTURER ISL80111, ISL80112 or ISL80113 as noted on Intersil the evaluation board C1, C3 10µF CAP, SMD, 0805, 50V, 10% Generic C2 1µF CAP, SMD, 0603 Generic R1 1kΩ RES, SMD, 0603, 1% Generic R2 2.05kΩ RES, SMD, 0603, 1% Generic R3 2.61kΩ RES, SMD, 0603, 1% Generic R4 4.02kΩ RES, SMD, 0603, 1% Generic R5 5.62kΩ RES, SMD, 0603, 1% Generic R6 1kΩ RES, SMD, 0603, 1% Generic R7 100kΩ RES, SMD, 0603, 1% Generic JP1, JP2, JP3, JP4, JP5, JP6 Jumper Generic TP1, TP2, TP3 TP4, TP5, TP6 Terminal Connector Generic Submit Document Feedback 3 PART NUMBER ISL80111IRAJZ, ISL80112IRAJZ, ISL80113IRAJZ UG009.0 October 30, 2014 User Guide 009 Board Layout FIGURE 4. SILKSCREEN TOP FIGURE 5. TOP LAYER COMPONENT SIDE FIGURE 6. BOTTOM LAYER SOLDER SIDE FIGURE 7. SILKSCREEN BOTTOM Submit Document Feedback 4 UG009.0 October 30, 2014 User Guide 009 Typical Performance Curves 100 3A V = 3.3V BIAS 90 80 2A V = 3.3V BIAS 3A V = 5V BIAS 70 80 IOUT = 1A 60 PSRR (dB) VIN DROPOUT VOLTAGE (mV) 100 50 2A V = 5V BIAS 40 BIAS = 5V VIN = 3.3V VOUT = 2.5V COUT = 10µF 60 IOUT = 0A IOUT = 2A 40 IOUT = 3A 30 20 20 10 1A V = 3.3V BIAS 1A V = 5V BIAS 0 -40 25 TEMPERATURE (°C) 0 125 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 8. DROPOUT vs VBIAS FIGURE 9. VIN PSRR vs LOAD CURRENT 100 IOUT = 0A PSRR (dB) 80 BIAS = 3.3V VIN = 1.5V VOUT = 1.0V COUT = 10µF IOUT = 1.1A IOUT = 0.1A IOUT = 1A 60 IOUT = 2A IOUT = 3A 40 VOUT (20mV/DIV) 20 0 100 1k 10k 100k 1M FREQUENCY (Hz) TIME (20µs/DIV) FIGURE 10. VVIN PSRR vs LOAD CURRENT FIGURE 11. 1A LOAD TRANSIENT RESPONSE IOUT = 3.1A IOUT = 2.1A IOUT = 0.1A IOUT = 0.1A VOUT (50mV/DIV) VOUT (20mV/DIV) TIME (20µs/DIV) TIME (20µs/DIV) FIGURE 12. 2A LOAD TRANSIENT RESPONSE FIGURE 13. 3A LOAD TRANSIENT RESPONSE Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 5 UG009.0 October 30, 2014