DATASHEET

ISL9103, ISL9103A
Data Sheet
December 9, 2015
500mA 2.4MHz Low IQ High Efficiency
Synchronous Buck Converter
FN6828.3
Features
The ISL9103, ISL9103A is a 500mA, 2.4MHz step-down
regulator, which is ideal for powering low-voltage
microprocessors in compact devices such as PDAs and
cellular phones. It is optimized for generating low output
voltages down to 0.8V. The supply voltage range is from
2.7V to 6V allowing the use of a single Li+ cell, three NiMH
cells or a regulated 5V input. It has guaranteed minimum
output current of 500mA. A high switching frequency of
2.4MHz pulse-width modulation (PWM) allows using small
external components. Under light load condition, the device
operates at low IQ skip mode with typical 20µA quiescent
current for highest light load efficiency to maximize battery
life, and it automatically switches to fixed frequency PWM
mode under heavy load condition.
• High Efficiency Integrated Synchronous Buck Regulator
with up to 95% Efficiency
• 2.7V to 6.0V Supply Voltage
• 2.4MHz PWM Switching Frequency
• 500mA Guaranteed Output Current
• 3% Output Accuracy Over-Temperature and Line for Fixed
Output Options
• 20µA Quiescent Supply Current in Skip Mode
• Less than 1µA Logic Controlled Shutdown Current
• 100% Maximum Duty Cycle for Lowest Dropout
• Ultrasonic Switching Frequency at Skip Mode to Prevent
Audible Frequency Noise (For ISL9103A Only)
The ISL9103, ISL9103A includes a pair of low
ON-resistance P-Channel and N-Channel internal MOSFETs
to maximize system efficiency and minimize the external
component count. 100% duty-cycle operation allows less
than 300mV dropout voltage at 500mA.
• Discharge Output Capacitor when Disabled
The ISL9103, ISL9103A offers internal digital soft-start,
enable for power sequence, overcurrent protection and
thermal shutdown functions. In addition, the ISL9103,
ISL9103A offers a quick bleeding function that discharges
the output capacitor when the IC is disabled.
• Chip Enable
The ISL9103, ISL9103A is offered in a 1.6x1.6mm UTDFN
package. The complete converter occupies less than
0.5cm2.
• Internal Digital Soft-Start
• Peak Current Limiting, Short Circuit Protection
• Over-Temperature Protection
• Small 6 Pin 1.6mmx1.6mm UTDFN Package
• Pb-Free (RoHS Compliant)
Applications
• Single Li-ion Battery-Powered Equipment
• Mobile Phones and MP3 Players
• PDAs and Palmtops
Pinout
ISL9103, ISL9103A
(6 LD 1.6x1.6 UTDFN)
TOP VIEW
VIN 1
6 SW
EN 2
5 GND
NC 3
4 FB
1
• WCDMA Handsets
• Portable Instruments
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL9103, ISL9103A
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
VIN
Input supply voltage. Typically connect a 10µF ceramic capacitor to ground.
2
EN
Regulator enable pin. Enable the device when driven to high. Shut down the chip and
discharge output capacitor when driven to low. Do not leave this pin floating.
3
NC
No connect; leave floating.
4
FB
Buck converter output feedback pin. For adjustable output version, its typical value is
0.8V and connect it to the output through a resistor divider for desired output voltage;
for fixed output version, directly connect this pin to the converter output.
5
GND
6
SW
Ground connection.
Switching node connection. Connect to one terminal of inductor.
Ordering Information
PART NUMBER
(Notes 1, 3, 4)
OUTPUT
VOLTAGE (V)
PART
(Note 2)
MARKING
TEMP
RANGE
(°C)
PACKAGE
Tape and Reel
(RoHS Compliant)
PKG
DWG. #
ULTRASONIC
FUNCTION
ISL9103IRUJZ-T
(No longer available, recommended
replacement:ISL9103AIRUJZ-T)
J1
2.8
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
NO
ISL9103IRUFZ-T
(No longer available, recommended replacement:
ISL9103AIRUFZ-T)
J2
2.5
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
NO
ISL9103IRUDZ-T
(No longer available, recommended replacement:
ISL9103AIRUDZ-T)
J3
2.0
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
NO
ISL9103IRUCZ-T
(No longer available, recommended replacement:
ISL9103AIRUCZ-T)
J4
1.8
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
NO
ISL9103IRUBZ-T
(No longer available, recommended replacement:
ISL9103AIRUBZ-T)
J5
1.5
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
NO
ISL9103IRUWZ-T
(No longer available, recommended replacement:
ISL9103AIRUWZ-T)
J6
1.2
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
NO
ISL9103IRUAZ-T
(No longer available, recommended replacement:
ISL9103AIRUAZ-T)
J7
ADJ
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
NO
ISL9103AIRUJZ-T
J9
2.8
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
YES
ISL9103AIRUFZ-T
K0
2.5
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
YES
ISL9103AIRUDZ-T
K1
2.0
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
YES
ISL9103AIRUCZ-T
K2
1.8
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
YES
ISL9103AIRUBZ-T
K3
1.5
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
YES
ISL9103AIRUWZ-T
K4
1.2
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
YES
ISL9103AIRUAZ-T
K5
ADJ
-40 to +85 6 Ld UTDFN
L6.1.6x1.6
YES
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. Other output voltage options may be available upon request, please contact Intersil for more details.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL9103, ISL9103A. For more information on MSL please see
techbrief TB363.
2
FN6828.3
December 9, 2015
ISL9103, ISL9103A
Absolute Maximum Ratings
Thermal Information
VIN, EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FB to GND (for adjustable version) . . . . . . . . . . . . . . .
FB to GND (for fixed output version) . . . . . . . . . . . . . .
JA (°C/W)
Thermal Resistance (Typical, Note 5)
-0.3V to 6.5V
-1.5V to 6.5V
-0.3V to 2.7V
-0.3V to 3.6V
6 Ld 1.6x1.6 UTDFN Package . . . . . . . . . . . . . . . . .
160
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 2.7V to 6.0V
Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .up to 500mA
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: TA = +25°C, VIN = VEN = 3.6V, L = 2.2µH,
C1 = 10µF, C2 = 10µF, IOUT = 0A (see “Typical Applications” on page 8). Boldface limits apply over the
operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note6)
TYP
MAX
(Note 6)
UNITS
-
2.5
2.7
V
50
150
-
mV
SUPPLY
Undervoltage Lockout Threshold (UVLO)
VUVLO
TA = +25°C, Rising
UVLO Hysteresis
Quiescent Supply Current (for ISL9103
Adjustable Output Voltage Only)
IVIN1
In skip mode, no load at the output, no switch,
VIN = 6.0V
-
20
34
µA
Quiescent Supply Current (for ISL9103A
Adjustable Output Only)
IVIN2
In skip mode, no load at the output, no switch,
VIN = 6.0V
-
32
45
µA
VIN = 6.0V, EN = LOW
-
0.05
1
A
TA = 0°C to +85°C
-2
-
+2
%
-2.5
-
+2.5
%
Shut Down Supply Current
ISD
OUTPUT REGULATION
FB Voltage Accuracy (for Adjustable Output
Only)
FB Voltage
VFB
FB Bias Current (for Adjustable Output Only)
IFB
0.8
VFB = 0.75V
V
-
5
100
nA
-3
-
3
%
Output Voltage Accuracy (for Fixed Output
Voltage Only)
PWM Mode
Line Regulation
VIN = VO + 0.5V to 6V (minimal 2.7V)
-
0.2
-
%/V
Load Regulation
VIN = 3.6V, IO = 150mA to 500mA
-
0.0009
-
%/mA
VIN = 3.6V, IO = 200mA
-
0.45
0.6

VIN = 2.7V, IO = 200mA
-
0.55
0.72

VIN = 3.6V, IO = 200mA
-
0.4
0.52

VIN = 2.7V, IO = 200mA
-
0.5
0.65

-
100
-

0.7
0.95
1.30
A
-
100
-
%
-
0.01
2
µA
1.9
2.4
2.75
MHz
SW
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
N-Channel Bleeding MOSFET
ON-Resistance
P-Channel MOSFET Peak Current Limit
IPK
VIN = 4.2V
Maximum Duty Cycle
SW Leakage Current
SW at Hi-Z state
PWM Switching Frequency
fS
3
VIN = 3.6V
FN6828.3
December 9, 2015
ISL9103, ISL9103A
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: TA = +25°C, VIN = VEN = 3.6V, L = 2.2µH,
C1 = 10µF, C2 = 10µF, IOUT = 0A (see “Typical Applications” on page 8). Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
MIN
(Note6)
TYP
MAX
(Note 6)
UNITS
SW Minimum On-Time
-
65
-
ns
Soft-Start-Up Time
-
1.2
-
ms
Logic Input Low
-
-
0.4
V
Logic Input High
1.4
-
-
V
Logic Input Leakage Current
-
0.1
1
µA
Thermal Shutdown
-
130
-
°C
Thermal Shutdown Hysteresis
-
30
-
°C
PARAMETER
SYMBOL
TEST CONDITIONS
EN
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested
Typical Operating Performance
100
100
VIN = 2.7V
90
90
80
70
VIN = 4.9V
VIN = 3.8V
60
EFFICIENCY (%)
EFFICIENCY (%)
80
50
40
30
70
30
20
10
0.1
0.2
0.3
0.4
0
0.5
VIN = 5.5V
40
10
0
VIN = 4.5V
50
20
0
VIN = 3.5V
60
0
0.1
0.2
0.3
0.4
0.5
IO (A)
IO (A)
FIGURE 1. EFFICIENCY vs LOAD CURRENT (VO = 1.5V)
FIGURE 2. EFFICIENCY vs LOAD CURRENT (VO = 2.5V)
1.800
30
T = +85°C
VIN = 3.6V, RISING
1.795
25
VO (V)
Iq (µA)
T = +25°C
20
1.790
1.785
VIN = 3.6V, FALLING
15
1.780
T = -45°C
10
2.70
3.25
3.80
4.35
VIN (V)
4.90
5.45
6.00
FIGURE 3. INPUT QUIESCENT CURRENT vs VIN (VO = 2.5V)
4
1.775
0
100
200
300
400
500
IOUT (mA)
FIGURE 4. OUTPUT VOLTAGE vs LOAD CURRENT
(ISL9103, VO_NORMINAL = 1.8V)
FN6828.3
December 9, 2015
ISL9103, ISL9103A
Typical Operating Performance (Continued)
2.520
5V/DIV
2.515
VSW
VIN = 4.0V, RISING
VO (V)
2.510
VOUT
1V/DIV
2.505
VIN = 4.0V, FALLING
2.500
200mA/DIV
IL
2.495
0
100
200
300
400
500
5V/DIV
EN
IOUT(mA)
FIGURE 6. SOFT-START TO PFM MODE (VIN = 3.6V,
VOUT = 1.5V, IOUT = 0.001mA)
FIGURE 5. OUTPUT VOLTAGE vs LOAD CURRENT
(ISL9103, VO_NORMINAL = 2.5V)
5V/DIV
VSW
5V/DIV
VSW
VOUT
VOUT
2V/DIV
1V/DIV
IL
500mA/DIV
200mA/DIV
IL
EN
5V/DIV
FIGURE 7. SOFT-START TO PWM MODE (VIN = 3.6V,
VOUT = 1.5V, IOUT = 500mA)
5V/DIV
5V/DIV
EN
FIGURE 8. SOFT-START TO PFM MODE (VIN = 3.6V,
VOUT = 2.5V, IOUT = 0.001mA)
5V/DIV
VSW
VSW
50mV/DIV
50mV/DIV
VOUT
VOUT
Io
20mA/DIV
20mA/DIV
Io
FIGURE 9. LOAD TRANSIENT IN PFM MODE (VIN = 3.6V,
VOUT = 1.5V, 5mA TO 30mA)
5
FIGURE 10. LOAD TRANSIENT IN PFM MODE (VIN = 3.6V,
VOUT = 1.5V, 30mA TO 5mA)
FN6828.3
December 9, 2015
ISL9103, ISL9103A
Typical Operating Performance (Continued)
5V/DIV
5V/DIV
VSW
50mV/DIV
VSW
50mV/DIV
VOUT
20mA/DIV
VOUT
IL
20mA/DIV
IL
FIGURE 11. LOAD TRANSIENT IN PFM MODE (VIN = 3.6V,
VOUT = 2.5V, 5mA TO 30mA)
5V/DIV
FIGURE 12. LOAD TRANSIENT IN PFM MODE (VIN = 3.6V,
VOUT = 2.5V, 30mA TO 5mA)
5V/DIV
VSW
50mV/DIV
50mV/DIV
VOUT
Io
200mA/DIV
VSW
VOUT
Io
200mA/DIV
FIGURE 13. LOAD TRANSIENT FROM PFM TO PWM MODE
(VIN = 3.6V, VOUT = 1.5V, 5mA TO 300mA)
5V/DIV
FIGURE 14. LOAD TRANSIENT FROM PWM TO PFM MODE
(VIN = 3.6V, VOUT = 1.5V, 300mA TO 5mA)
5V/DIV
VSW
VSW
50mV/DIV
50mV/DIV
VOUT (AC COUPLED)
VOUT (AC COUPLED)
200mA/DIV
200mA/DIV
IL
FIGURE 15. LOAD TRANSIENT FROM PFM TO PWM MODE
(VIN = 3.6V, VOUT = 2.5V, 5mA TO 300mA)
6
IL
FIGURE 16. LOAD TRANSIENT FROM PWM TO PFM MODE
(VIN = 3.6V, VOUT = 2.5V, 300mA TO 5mA)
FN6828.3
December 9, 2015
ISL9103, ISL9103A
Typical Operating Performance (Continued)
5V/DIV
5V/DIV
VSW
VSW
50mV/DIV
50mV/DIV
VOUT
VOUT (AC COUPLED)
500mA/DIV
Io
500mA/DIV
Io
FIGURE 17. LOAD TRANSIENT IN PWM MODE (VIN = 3.6V,
VO = 1.5V, 200mA TO 500mA)
FIGURE 18. LOAD TRANSIENT IN PWM MODE (VIN = 3.6V,
VO = 1.5V, 500mA TO 200mA)
5V/DIV
5V/DIV
VSW
VSW
50mV/DIV
VOUT
500mA/DIV
Io
FIGURE 19. LOAD TRANSIENT IN PWM MODE (VIN = 3.6V,
VO = 2.5V, 200mA TO 500mA)
7
50mV/DIV
VOUT
500mA/DIV
Io
FIGURE 20. LOAD TRANSIENT IN PWM MODE (VIN = 3.6V,
VO = 2.5V, 500mA TO 200mA)
FN6828.3
December 9, 2015
ISL9103, ISL9103A
Typical Applications
ISL9103, ISL9103A ADJUSTABLE OUTPUT
L
2.2µH
INPUT: 2.7V TO 6V
OUTPUT
UP TO 500mA
SW
VIN
C2
10µF
C1
10µF
R1
100k
C3
47pF
R2
100k
ENABLE
EN
FB
DISABLE
GND
ISL9103, ISL9103A FIXED OUTPUT
L
2.2µH
INPUT: 2.7V TO 6V
VIN
OUTPUT
UP TO 500mA
SW
C2
10µF
C1
10 µ F
ENABLE
FB
EN
DISABLE
GND
FIGURE 21. TYPICAL APPLICATIONS DIAGRAM
Note: For adjustable output version, the internal feedback resistor divider is disabled and the FB pin is directly connected to the
error amplifier.
TABLE 1. BILL OF MATERIALS
PARTS
DESCRIPTION
MANUFACTURERS
PART NUMBER
SPECIFICATIONS
SIZE
L
Inductor
Sumida
CDRH2D14NP-2R2NC
2.2µH
3.2mmx3.2mm
C1, C2
Input and output
capacitor
Panasonic
ECJ-1VB1A106M
10µF/10V, X5R
0603
C3
Capacitor
KEMET
C0402C470J5GACTU
47pF/50V
0402
R1, R2
Resistor
Various
-
100kSMD, 1%
0402
8
FN6828.3
December 9, 2015
ISL9103, ISL9103A
Block Diagram
SHUTDOW N
SHUTDOW N
SO
SO FTF TA
S TSATR
T
RT
O S C IL L A T O R
BANDGAP
VREF
+
EN
+
COMP
EAMP
SLO PE
COMP
V IN
P W M /P F M
L O G IC
CONTROLLER
P R O T E C T IO N
D R IV E R
SW
X
GND
*N O T E
FB
B L E E D IN G
FET
100
+
+
OCP
CSA
VREF1
SCP
VREF3
+
+
S K IP
VREF2
Z E R O -C R O S S
S E N S IN G
*N O T E : F O R F IX E D O U T P U T O P T IO N S O N L Y
NOTE: For Adjustable output version, the internal feedback resistor divider is disabled and the FB pin
is directly connected to the error amplifier.
FIGURE 22. FUNCTIONAL BLOCK DIAGRAM
Theory of Operation
The ISL9103, ISL9103A is a step-down switching regulator
optimized for battery-powered handheld applications. The
regulator operates at typical 2.4MHz fixed switching
frequency under heavy load condition to allow small external
inductor and capacitors to be used for minimal printed-circuit
board (PCB) area. At light load, the regulator can
automatically enter the skip mode (PFM mode) to reduce the
switching frequency to minimize the switching loss and to
maximize the battery life. The quiescent current under skip
mode, and under no load and no switch condition is typically
only 20µA. The supply current is typically only 0.05µA when
the regulator is disabled.
PWM Control Scheme
control reference for the current loops comes from the Error
Amplifier (EAMP) of the voltage loop.
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the P-Channel
MOSFET starts ramping up. When the sum of the CSA
output and the compensation slope reaches the control
reference of the current loop, the PWM comparator COMP
sends a signal to the PWM logic to turn off the P-Channel
MOSFET and to turn on the N-Channel MOSFET. The
N-MOSFET remains on till the end of the PWM cycle. Figure 23
shows the typical operating waveforms during the normal PWM
operation. The dotted lines illustrate the sum of the slope
compensation ramp and the CSA output.
The ISL9103, ISL9103A uses the peak-current-mode
pulse-width modulation (PWM) control scheme for fast
transient response and pulse-by-pulse current limiting.
Figure 22 shows the circuit functional block diagram. The
current loop consists of the oscillator, the PWM comparator
COMP, current sensing circuit, and the slope compensation
for the current loop stability. The current sensing circuit
consists of the resistance of the P-Channel MOSFET when it
is turned on and the Current Sense Amplifier (CSA). The
9
FN6828.3
December 9, 2015
ISL9103, ISL9103A
vEAMP
vCSA
d
iL
vOUT
FIGURE 23. PWM OPERATION WAVEFORMS
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a
0.8V reference voltage to the voltage control loop. The
feedback signal comes from the FB pin. The soft-start block
only affects the operation during the start-up and will be
discussed separately in “Soft-Start” on page 11. The EAMP
is a transconductance amplifier, which converts the voltage
error signal to a current output. The voltage loop is internally
compensated by a RC network. The maximum EAMP
voltage output is precisely clamped to the bandgap voltage.
Skip Mode (PFM Mode)
Under light load condition, ISL9103, ISL9103A automatically
enters a pulse-skipping mode to minimize the switching loss
by reducing the switching frequency. Figure 24 illustrates the
skip mode operation. A zero-cross sensing circuit (as shown
in Figure 22) monitors the current flowing through SW node
for zero crossing. When it is detected to cross zero for
16-consecutive cycles, the regulator enters the skip mode.
During the 16-consecutive cycles, the inductor current could
be negative. The counter is reset to zero when the sensed
current flowing through SW node does not cross zero during
any cycle within the 16-consecutive cycles. Once ISL9103,
ISL9103A enters the skip mode, the pulse modulation starts
being controlled by the SKIP comparator shown in Figure 22.
Each pulse cycle is still synchronized by the PWM clock. The
P-Channel MOSFET is turned on at the rising edge of clock
and turned off when its current reaches ~20% of the peak
current limit. As the average inductor current in each cycle is
higher than the average current of the load, the output
voltage rises cycle over cycle. When the output voltage is
sensed to reach 1.5% above its nominal voltage, the
P-Channel MOSFET is turned off immediately and the
inductor current is fully discharged to zero and stays at zero.
The output voltage reduces gradually due to the load current
discharging the output capacitor. When the output voltage
drops to the nominal voltage, the P-Channel MOSFET will
be turned on again, repeating the previous operations.
The regulator resumes normal PWM mode operation when
the output voltage is sensed to drop below 1.5% of its
nominal voltage value.
Enable
The enable (EN) pin allows user to enable or disable the
converter for purposes such as power-up sequencing. With
EN pin pulled to high, the converter is enabled and the
internal reference circuit wakes up first and then the soft
start-up begins. When EN pin is pulled to logic low, the
converter is disabled, both P-Channel MOSFET and
N-Channel MOSFETS are turned off, and the output
capacitor is discharged through internal discharge path.
16 CYCLES
CLOCK
20% PEAK CURRENT LIMIT
IL
0
1.015*VOUT_NOMINAL
VOUT
VOUT_NOMINAL
FIGURE 24. SKIP MODE OPERATION WAVEFORMS
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FN6828.3
December 9, 2015
ISL9103, ISL9103A
Overcurrent Protection
The overcurrent protection is provided on ISL9103, ISL9103A
when overload condition happens. It is realized by monitoring
the CSA output with the OCP comparator, as shown in
Figure 22. When the current at P-Channel MOSFET is sensed
to reach the current limit, the OCP comparator is triggered to
turn off the P-Channel MOSFET immediately.
Short-Circuit Protection
ISL9103, ISL9103A has a Short-Circuit Protection (SCP)
comparator, which monitors the FB pin voltage for output
short-circuit protection. When the output voltage is sensed to
be lower than a certain threshold, the SCP comparator
reduces the PWM oscillator frequency to a much lower
frequency to protect the IC from being damaged.
Undervoltage Lockout (UVLO)
When the input voltage is below the Undervoltage Lock Out
(UVLO) threshold, ISL9103, ISL9103A is disabled.
Soft-Start
The soft-start feature eliminates the inrush current during the
circuit start-up. The soft-start block outputs a ramp reference
to both the voltage loop and the current loop. The two ramps
limit the inductor current rising speed as well as the output
voltage speed so that the output voltage rises in a controlled
fashion.
Low Dropout Operation
The ISL9103, ISL9103A features low dropout operation to
maximize the battery life. When the input voltage drops to a
level that ISL9103, ISL9103A can no longer operate under
switching regulation to maintain the output voltage, the
P-Channel MOSFET is completely turned on (100% duty
cycle). The dropout voltage under such condition is the
product of the load current and the ON-resistance of the
P-Channel MOSFET. Minimum required input voltage VIN
under this condition is the sum of output voltage plus the
voltage drop cross the inductor and the P-Channel MOSFET
switch.
Thermal Shut Down
The ISL9103, ISL9103A provides built-in thermal protection
function. The thermal shutdown threshold temperature is
+130°C (typ) with a 30°C (typ) hysteresis. When the internal
temperature is sensed to reach +130°C, the regulator is
completely shut down and as the temperature drops to
+100°C (typ), the ISL9103, ISL9103A resumes operation
starting from the soft-start.
Applications Information
Inductor and Output Capacitor Selection
To achieve better steady state and transient response,
ISL9103, ISL9103A typically uses a 2.2µH inductor. The
peak-to-peak inductor current ripple can be expressed in
Equation 1:
11
VO 

V O   1 – ---------
V

IN
I = --------------------------------------L  fS
(EQ. 1)
In Equation 1, usually the typical values can be used but to
have a more conservative estimation, the inductance should
consider the value with worst case tolerance; and for
switching frequency fS, the minimum fS from the “Electrical
Specifications” table on page 3 can be used.
To select the inductor, its saturation current rating should be
at least higher than the sum of the maximum output current
and half of the delta calculated from Equation 1. Another
more conservative approach is to select the inductor with the
current rating higher than the P-Channel MOSFET peak
current limit.
Another consideration is the inductor DC resistance since it
directly affects the efficiency of the converter. Ideally, the
inductor with the lower DC resistance should be considered
to achieve higher efficiency.
Inductor specifications could be different from different
manufacturers so please check with each manufacturer if
additional information is needed.
For the output capacitor, a ceramic capacitor can be used
because of the low ESR values, which helps to minimize the
output voltage ripple. A typical value of 10µF ceramic
capacitor should be enough for most of the applications and
the capacitor should be X5R or X7R.
Input Capacitor Selection
The main function for the input capacitor is to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current from flowing back to
the battery rail. A 10µF ceramic capacitor (X5R or X7R) is a
good starting point for the input capacitor selection.
Output Voltage Setting Resistor Selection
For ISL9103, ISL9103A adjustable output option, the voltage
resistors, R1 and R2, as shown in Figure 21, set the desired
output voltage values. The output voltage can be calculated
using Equation 2:
R 1

V O = V FB   1 + -------
R 2

(EQ. 2)
where VFB is the feedback voltage (typically it is 0.8V). The
current flowing through the voltage divider resistors can be
calculated as VO/(R1 + R2), so larger resistance is desirable
to minimize this current. On the other hand, the FB pin has
leakage current that will cause error in the output voltage
setting. The leakage current has a typical value of 0.1µA. To
minimize the accuracy impact on the output voltage, select
the R2 no larger than 200k.
FN6828.3
December 9, 2015
ISL9103, ISL9103A
For adjustable output versions, C3 (shown in Figure 21) is
highly recommended for improving stability and achieving
better transient response.
Table 2 provides the recommended component values for
some output voltage options.
TABLE 2. RECOMMENDED ISL9103, ISL9103A ADJUSTABLE
OUTPUT VERSION CIRCUIT CONFIGURATION vs
VOUT
VOUT
(V)
L
(µH)
C2
µF)
R1
(k
C3
(pF)
R2
(k
0.8
2.2
10
0
N/A
N/A
1.0
2.2
10
44.2
100
178
1.2
2.2
10
80.6
47
162
1.5
2.2
10
84.5
47
97.6
1.8
2.2
10
100
47
80.6
2.5
2.2
10
100
47
47.5
2.8
2.2
10
100
47
40.2
3.3
2.2
10
102
47
32.4
Layout Recommendation
The PCB layout is a very important converter design step to
make sure the designed converter works well, especially
under the high current high switching frequency condition.
For ISL9103, ISL9103A, the power loop is composed of the
output inductor L, the output capacitor COUT, the SW pin and
the PGND pin. It is necessary to make the power loop as
small as possible and the connecting traces among them
should be direct, short and wide; the same type of traces
should be used to connect the VIN pin, the input capacitor
CIN and its ground.
The switching node of the converter, the SW pin, and the
traces connected to this node are very noisy, so keep the
voltage feedback trace and other noise sensitive traces
away from these noisy traces.
The input capacitor should be placed as close as possible to
the VIN pin. The ground of the input and output capacitors
should be connected as close as possible as well. In
addition, a solid ground plane is helpful for EMI performance.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN6828.3
December 9, 2015
ISL9103, ISL9103A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
December 9, 2015
FN6828.3
CHANGE
Updated the Ordering Information table on page 2.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing L6.1.6X1.6 to the latest revision. Changes are as follows:
-Side View- changed thickness from 0.55 to 0.5 ±0.05.
-Tiebar Note updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or
ends).
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
13
FN6828.3
December 9, 2015
ISL9103, ISL9103A
Package Outline Drawing
L6.1.6x1.6
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD COL PLASTIC PACKAGE (UTDFN COL)
Rev 3, 05/15
2X 1.00
1.60
A
6
PIN 1
INDEX AREA
PIN #1 INDEX AREA
6
B
4X 0.50
1
3
5X 0 . 40 ± 0 . 1
1X 0.5 ±0.1
1.60
(4X)
0.15
4
6
0.10 M C A B
TOP VIEW
4 0.25 +0.05 / -0.07
BOTTOM VIEW
( 6X 0 . 25 )
SEE DETAIL "X"
( 1X 0 .70 )
0.5 ±0.05
0.10 C
C
BASE PLANE
(1.4 )
SEATING PLANE
0.08 C
SIDE VIEW
( 5X 0 . 60 )
C
5
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
( 4X 0 . 5 )
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature and may
be located on any of the 4 sides (or ends).
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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FN6828.3
December 9, 2015
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