DATASHEET

sPMIC for Micro Converter Bias and Drivers
ISL1801
Features
The ISL1801 is a power management IC (PMIC) optimized for
solar array micro converters and other systems operating from
a high voltage DC supply. The ISL1801 can be used in buck,
boost or buck-boost microconverter topologies in order to
maximize the energy harvest from a solar array. In addition to
the power stage and main controller, the ISL1801 includes the
bias regulators, gate drivers, current sense amplifier and
comparators needed for micro converters.
• 90V input buck switching regulator
- 120mA (minimum) output with OCP, OVP, OTP
- Integrated upper and lower MOSFETs
• 90V on-chip start-up 6.7V LDO
• Low voltage buck switching regulator
- 200mA (minimum) output with OCP, OVP
- Integrated upper and lower MOSFETs
- PGOOD output
The ISL1801 integrates two switching regulators that can be
used to generate the driver and the micro-controller (MCU)
power supplies. In addition, it has a low offset, low drift
amplifier for current sensing, two comparators for overvoltage
and overcurrent protection plus a watchdog timer to reset the
MCU if necessary. This single IC solution offers high integration
and dramatically reduces the total number of components in
the microconverter system improving the system reliability and
reducing cost.
• Low voltage bias LDO
- Input voltage range from 6V to 14V
- Regulated 5V output up to 10mA
• Dual high-speed gate driver
- 14V voltage rating
- 2A peak sourcing and 5A peak sinking current
- Peak current limit for DRIVE3
The first regulator takes input voltages ranging from 9V to 90V
from the solar panel and outputs a regulated supply for drivers
and the secondary regulator. The secondary regulator converts
the output of the first regulator to a programmable
micro-controller supply, typically 3.3V. A high voltage start-up
LDO provides the necessary bias voltage until the switching
regulator is operating.
• Dedicated amplifier for accurate current sense
• Two comparators for general purpose protection
• Integrated watchdog timer
Applications
• Solar power optimizer
The ISL1801 integrates two high-speed MOSFET drivers for
buck, flyback or boost converters configured as shown in the
application schematics. The Drive3 also has the integrated
peak current limiting capabilities.
• Solar power micro-inverter
• Solar charge controller
• Telecom power supply
The ISL1801 includes comprehensive start-up, shutdown and
fault logic to ensure reliable operation of micro converters in
solar applications.
PV MODULE
VIN +
VOUT +
SENSE
VOUT -
ISL1801
3.3V
CONTROL
PROCESSOR AND/OR
COMMUNICATIONS
FIGURE 1. TYPICAL APPLICATION
July 24, 2014
FN8259.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL1801
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
High Voltage 10V Bias Regulator VR1 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Low Voltage 3.3V Bias Regulator VR2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Driver Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WatchDog Timer Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current Sense Op amp Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Dual High-Speed Comparator Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Preload Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Test Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Summary of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Detailed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual Synchronous Buck Switching Regulators With Constant On Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual LDO Bias Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual Low-Side MOSFET Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual High-Speed Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Precision Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WatchDog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Temperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
18
18
19
19
20
20
22
23
23
23
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PC Board Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Layout Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Submit Document Feedback
2
FN8259.1
July 24, 2014
ISL1801
Block Diagram
BRESET
VCC1
BCMD
FF3
PVCC3
Q
SET
VIN1
LDO1
UVLO
PVCC3
S
AGND
BDRIVE
Q
CLR
R
ENABLE
PGND4
BOOT1
PVCC3
DRIVE3
LEVEL
SHIFT
ENABLE
PGND3
PHASE1
VCC1
PWM3
OC, OV,
OT, SS
FF2
ISEN
OCSET3
S
R
SET
CLR
PWM
Logic
Q
PWM1
CL
Q
120µA
PGND1
EN1
PHASE3
+
Q
ONE
SHOT
Q
SET
CLR
S
FB1
R
GND
CMP2+
CMP2-
VREF1
-
LATCHRPT
ON-TIME
CONTROL
CMP2
S
SET
TON1
Q
FF1
R
CMP1+
CMP1-
CLR
Q
PVCC3
CMP1
7V
LDO2
VCC5V
-
CMP1O
PVCC3
GND
+
RPWM3
PGOOD2
POR
+
DELAY
VREF2*0.88
TON2
ON-TIME
CONTROL
+
FB2
-
0.5*VDDREF
BOOT2
VCC5V
VIN2
GND
S
VREF2
SET
Q
+
R
CLR
Q
PWM
Logic
PHASE2
VCC5V
VDDREF
PGND2
SS, OC, OV, OT
WDI
WDO
WATCHDOG
AMPO
GND
VDDREF
AMP-
PRE-LOAD
CONTROL
-
AMP+
TIMER
+
SGND
GND
PRELOAD
FIGURE 2. ISL1801 BLOCK DIAGRAM
Submit Document Feedback
3
FN8259.1
July 24, 2014
ISL1801
Pin Configuration
ISL1801
(48 LD TSSOP)
TOP VIEW
NC1
NC2
VCC1
AGND
OCSET3
NC3
PHASE3
PGND3
DRIVE3
PVCC3
BDRIVE
PGND4
PWM3
RPWM3
BCMD
BRESET
WDI
VDDREF
LATCHRPT
PGOOD2
AMPO
AMPAMP+
SGND
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
NC6
PGND1
NC5
VIN1
NC4
PHASE1
BOOT1
TIMER
TON1
FB1
PRELOAD
GND
VCC5V
VIN2
BOOT2
PHASE2
PGND2
TON2
FB2
CMP2+
CMP2CMP1O
CMP1CMP1+
Pin Descriptions
PIN#
PIN NAME
DESCRIPTION
1, 2, 6,
44, 46,
48
NC1, NC2,
NC3, NC4,
NC5, NC6
3
VCC1
High voltage start-up LDO1 output and also the pin providing bias to the HV circuitry on the ISL1801. Place a 1µF ceramic
capacitor from this pin to ground as decoupling cap. Connect this pin to the output of the high voltage regulator. When the
output of the switching regulator is stable, the start-up LDO is disabled and the chip bias is supplied by the more efficient
switching regulator.
Note: As VCC1 is the power supply of the high voltage die, DO NOT connect it to any low impedance potential by any means.
This may damage the device.
4
AGND
Analog ground pin for VCC1.
5
OCSET3
A resistor between this pin and ground set the peak current limit threshold for the power stage MOSFET at Phase3. The 0.01µF
capacitor can be used at this pin to filter any switching noise.
7
PHASE3
The phase node pin of the power stage controlled by DRIVE3. This pin should be connected to the drain of the power MOSFET
through one resistor and diode which prevent the voltage at Phase3 pin from dropping below -0.6V. Refer to the typical
application schematics starting on page 24, for correct connections.
8
PGND3
The ground pin for the high-speed driver DRIVE3.
9
DRIVE3
The output of the high-speed driver.
10
PVCC3
The bias input pin for both the high-speed driver and the low speed driver. It is normally connected to VOUT1. The PVCC3 also
powers LDO2 which provides the bias supply for all internal control circuits.
11
BDRIVE
The output of the high-speed driver controlled by the BCMD signal.
12
PGND4
The ground pin for BDRIVE.
13
PWM3
The PWM input signal for DRIVE3.
NC pin.
Submit Document Feedback
4
FN8259.1
July 24, 2014
ISL1801
Pin Descriptions (Continued)
PIN#
PIN NAME
DESCRIPTION
14
RPWM3
The reset signal for both flip-flops in the LATCHRPT circuit and overcurrent-protection circuit of DRIVE3/PHASE3. The
RPWM3=0 will reset both flip-flops. Avoid running PWM3=1 with RPWM3=0 for a long time or at very high frequency, since
it may result in very high switching frequency at DRIVE3 in the overcurrent protection condition.
15
BCMD
16
BRESET
17
WDI
18
VDDREF
19
LATCHRPT
20
PGOOD2
21
AMPO
Integrated amplifier output.
22
AMP-
Integrated amplifier inverting input.
23
AMP+
Integrated amplifier non-inverting input.
24
SGND
The ground pin of the sensitive control circuits biased by VCC5V. Connect this pin to a ground plane with minimum noise.
25
CMP1+
Comparator 1 non-inverting input.
26
CMP1-
Comparator 1 inverting input.
27
CMP1O
Comparator 1 output. This signal also triggers the flip-flop for the LATCHRPT signal.
28
CMP2-
Comparator 2 inverting input.
29
CMP2+
Comparator 2 non-inverting input.
30
FB2
31
TON2
On time adjustment for the secondary (low voltage) switching regulator. Connect a resistor from this pin to the input voltage
of the low voltage regulator to adjust the on time and switching frequency.
32
PGND2
The ground pin of the low voltage switching regulator’s power stage. There are switching power current pulses coming out of
this pin. Place the ground pad of the input power stage decoupling cap as close to this pin as possible.
33
PHASE2
The phase node of the low voltage switching regulator. This pin should be connected to the output inductor.
34
BOOT2
The boot pin of the low voltage switching regulator. An external bootstrap capacitor is required. This pin provides bias voltage
to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive the internal N-channel MOSFET.
The boot diode is included within the IC.
35
VIN2
36
VCC5V
37
GND
38
PRELOAD
39
FB1
40
TON1
On time adjustment for the high voltage switching regulator. Connect a resistor from this pin to the input voltage of the high
voltage regulator to adjust the on time and switching frequency.
41
TIMER
Tie a resistor from VCC5V to this pin and a cap from this pin to ground. The RC time constant sets the time needed for both
start-up and watchdog timing. A minimum of 0.01µF should be connected to this pin to filter the switching noise from BOOT1.
The pull-up resistor should not be more than 200kΩ to assure correct operation.
Logic input to control BDRIVE.
Logic input to reset the LATCHRPT flip-flop in the BDRIVE control circuit.
Watchdog circuit clock input signal.
Reference signal for output signals to the MCU. Connect this pin to VOUT2, which provides a clamp voltage for all the output
pins (CMP1O, AMPO) interfacing with the MCU.
Open drain output signal. When either comparator or Phase3 overcurrent protection is triggered, this pin is pulled LOW to
inform the MCU. The two internal flip-flops used to latch these faults can be reset by setting RWPM3=0.
Open drain output pin indicating power-good for the low voltage regulator. A logic low signal at the watchdog output will also
pull this pin LOW allowing it to reset the MCU in either fault condition.
The feedback sense pin for the low voltage switching regulator. The output voltage is programmable by a resistor divider
feeding back the output voltage.
Input of the low voltage switching regulator. This pin is connected to the drain of the internal high-side MOSFET.
The output of the internal 5V LDO providing the bias supply for the IC. A 1µF ceramic decoupling capacitor should be placed
from this pin to ground.
The analog ground pin.
Place a resistor from this pin to VOUT1 to provide the loading for the high voltage switching regulator. When this load can be
successfully driven, the low voltage switching regulator will be enabled. If the PV module output power is insufficient, the low
voltage switching regulator will not start.
The feedback sense pin for the high voltage switching regulator. The output voltage is programmable by a resistor divider
feeding back the output voltage.
Submit Document Feedback
5
FN8259.1
July 24, 2014
ISL1801
Pin Descriptions (Continued)
PIN#
PIN NAME
DESCRIPTION
42
BOOT1
The boot pin of the high voltage switching regulator. An external bootstrap capacitor is required. This pin provides bias voltage
to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive the internal N-channel MOSFET.
The boot diode is included within the IC.
43
PHASE1
The phase node of the high voltage switching regulator, VR1. This pin should be connected to the output inductor.
45
VIN1
47
PGND1
Input to both the high voltage switching regulator and the high voltage start-up LDO1. This pin connects the high voltage
supply to the drain of the internal high-side MOSFET.
The ground pin of the high voltage switching regulator’s power stage. There are switching power current pulses coming out of
this pin. Place the VIN1 decoupling capacitor as close as possible to this pin.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL1801IVZ
ISL1801 IVZ
ISL1801EVAL1ZA
Evaluation Board
VIN1 RANGE
(V)
TEMP RANGE
(°C)
9 to 90
-40 to +85
PACKAGE
(Pb-free)
48 Ld TSSOP
PKG.
DWG. #
M48.240
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL1801. For more information on MSL please see tech brief TB363.
Submit Document Feedback
6
FN8259.1
July 24, 2014
ISL1801
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC1, VBOOT1-VPHASE1 . . . . . . . . . . . . . . . . . -0.3V to 16V
Voltage on VIN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 100V
Voltage on BOOT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 116V
Voltage on PHASE1, PHASE3 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 100V
Voltage on VIN2, PRELOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Voltage on PHASE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Voltage on BOOT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 22.5V
BDRIVE, DRIVE3 Voltages . . . . . . . . . . . . . . . . . . . . . . -0.3V to PVCC3 +0.3V
Supply Voltage, VCC5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Voltage on All Other Pins . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC5V +0.3V
LDO(VCC5V) Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
LDO(VCC1) Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
48 Ld TSSOP Package (Notes 4, 5) . . . . . .
58
16
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage, VCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V to 14V
Voltage on VIN1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 90V
Voltage on BOOT1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V to 104V
Voltage on VIN2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V to 14V
Voltage on BOOT2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10.5V to 19.5V
Supply Voltage, VCC5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For JC, the “case temp” location is taken at the package top center.
High Voltage 10V Bias Regulator VR1 Electrical Specifications
limits apply across the operating temperature range, -40°C to +85°C. (Notes 6, 7)
SYMBOL
PARAMETER
TEST CONDITIONS
TA = +25°C, VR1 = 10V, VR2 = 3.3V. Boldface
MIN
(Note 7)
TYP
(Note 6)
MAX
(Note 7)
UNITS
90
V
VIN1 SUPPLY
VIN1
Input Voltage Range
9
Shut-Down Current
VIN1 = 9V to 90V
700
1000
µA
Operating Current
VIN1 = 9V to 90V, PVCC3 = 0V, all inner
circuits of the low voltage section are
disabled, and only LDO1 and some inner
circuits of the high voltage section are
running.
1.3
2
mA
VCC1 SUPPLY
VCC1 LDO Regulator Output
6.8
Rising UV Threshold
5.2
UV Threshold Hysteresis
5.9
V
6.6
1
V
V
REFERENCE AND SOFT-START
VFB1
Internal Reference Voltage
1.960
2.000
2.040
V
POWER MOSFETS
rDS(ON)
Upper Switch ON-Resistance
IOUT = 50mA, BOOT1-PHASE1 = 6V,
test at wafer sort
2.3
3.2
Ω
rDS(ON)
Lower Switch ON-Resistance
IOUT = 50mA, VCC1 = 10V, test at wafer
sort
1.2
2
Ω
3
3.25
µs
ON TIME GENERATOR
tON
VIN1 = 10V, rON = 1M
tON
VIN1 = 90V, rON = 1M
2.75
0.3
µs
0.3
µs
MINIMUM OFF TIME
tMINOFF
Submit Document Feedback
7
FN8259.1
July 24, 2014
ISL1801
High Voltage 10V Bias Regulator VR1 Electrical Specifications
limits apply across the operating temperature range, -40°C to +85°C. (Notes 6, 7) (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TA = +25°C, VR1 = 10V, VR2 = 3.3V. Boldface
MIN
(Note 7)
TYP
(Note 6)
MAX
(Note 7)
UNITS
MINIMUM ON TIME
tMINON
0.3
µs
100
mV
REGULATION AND RIPPLE
Output Voltage Ripple
VIN1 = 40V, VOUT = 10V, FSW = 100kHz,
LOUT = 470µH, COUT = 22µF
OVERCURRENT PROTECTION
Overcurrent Protection Threshold
Test on Wafer Sort and characterized on
bench
120
185
250
mA
OVERVOLTAGE PROTECTION
FB1 OVP Threshold
2.4
V
150
°C
30
°C
THERMAL SHUTDOWN
Thermal Shut-down Temperature
Rising Threshold
Thermal Shut-down Hysteresis
Low Voltage 3.3V Bias Regulator VR2 Electrical Specifications
limits apply over the operating temperature range, -40°C to +85°C. (Notes 6, 7)
SYMBOL
PARAMETER
TEST CONDITIONS
TA = +25°C, VR1 = 10V, VR2 = 3.3V. Boldface
MIN
(Note 7)
TYP
(Note 6)
MAX
(Note 7)
UNITS
14
V
VIN2 SUPPLY
Input Voltage Range
VCC5 SUPPLY
VCC5 LDO Output
5
Rising UV Threshold
4.760
Hysteresis
5.000
V
5.190
165
V
mV
REFERENCE AND SOFT-START
VFB2
Internal Reference Voltage
Soft-Start Interval
0.686
Current Limiting Threshold of VR2
Ramps from 25% to 100%
0.700
0.714
1.5
V
ms
POWER MOSFETs
rDS(ON)
Upper Switch ON-Resistance
IOUT = 200mA
1
2
Ω
rDS(ON)
Lower Switch ON-Resistance
IOUT = 200mA
1
2
Ω
1100
1250
ns
ON TIME GENERATOR (4 trim options)
tON
VIN2 = 10V, rON = 1M
tON
VIN2 = 12V, rON = 1M
950
800
ns
150
ns
150
ns
30
mV
MINIMUM ON TIME
tMINON
MINIMUM OFF TIME
tMINOFF
REGULATION AND RIPPLE
Output Voltage Ripple
Submit Document Feedback
8
VIN2 = 10V, VOUT2 = 3.3V,
FSW = 300kHz,
LOUT = 47µH, COUT = 22µF
FN8259.1
July 24, 2014
ISL1801
Low Voltage 3.3V Bias Regulator VR2 Electrical Specifications
limits apply over the operating temperature range, -40°C to +85°C. (Notes 6, 7)
SYMBOL
PARAMETER
TEST CONDITIONS
TA = +25°C, VR1 = 10V, VR2 = 3.3V. Boldface
MIN
(Note 7)
TYP
(Note 6)
MAX
(Note 7)
UNITS
200
245
300
mA
OVERCURRENT PROTECTION
Overcurrent Protection Threshold
OVERVOLTAGE PROTECTION
FB2 OVP Threshold
0.775
V
PGOOD2 (OPEN DRAIN OUTPUT)
Power-Good Lower Threshold
Fraction of VOUT2 set point; 3µs noise
filter
PGOOD2 Leakage Current
PGOOD2 Voltage Low
Driver Electrical Specifications
-40°C to +85°C. (Notes 6, 7)
SYMBOL
83
90
95
%
VPULLUP = 3.3V
1
µA
IPGOOD2 = 4mA
0.5
V
TA = +25°C, VR1 = 10V, VR2 = 3.3V. Boldface limits apply over the operating temperature range,
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
(Note 6)
MAX
(Note 7)
UNITS
PVCC3 SUPPLY
Shutdown Current
PVCC3 = 3V
0.85
1.1
mA
Operating Current
PVCC3 = 10V, Drive3 = Bdrive = 1, or 0
1.75
3.2
mA
Operating Current
PVCC3 = 10V, FS = 50kHz, 10nF load on
Drive3
8
11
mA
0.7
V
LOGIC INPUT PINS
Low Level Voltage Threshold
PWM3, RPWM3, BCMD, BRESET,
VDDRFE = 3.3V
High Level Voltage Threshold
PWM3, RPWM3, BCMD, BRESET,
VDDRFE = 3.3V
2.4
V
Hysteresis
187
mV
Input Pull-Down Current
500
nA
DRIVE3 AND BDRIVE GATE DRIVER
Low Level Output Voltage
IDRIVE = 100mA
50
9.25
250
mV
High Level Output Voltage
IDRIVE = -100mA
9.8
V
Peak Pull-Down Current
VDRIVE = 0V
5
A
Peak Pull-Up Current
VDRIVE = 10V
2
A
Active Pull-Down Resistance Before POR
VCC1 = 10V
270
600
Ω
120
130
µA
OVERCURRENT PROTECTION OCSET3
OC Threshold Current
Current from OCSET3 Pin
110
OC Comparator Input Offset
3
mV
DRIVE3 AND BDRIVE SWITCHING CHARACTERISTICS
tPHL
Turn-Off Propagation Delay
PWM Falling to DRIVE Falling
200
320
ns
tPLH
Turn-On Propagation Delay
PWM Rising to DRIVE Rising
150
300
ns
tRC
Output Rise Time (10% to 90%)
CL = 10nF
90
ns
tFC
Output Fall Time (90% to 10%)
CL = 10nF
50
ns
tPW
Input Pulse Width that Changes the
Output
Submit Document Feedback
9
300
ns
FN8259.1
July 24, 2014
ISL1801
WatchDog Timer Electrical Specifications
TA = +25°C, VR1 = 10V, VR2 = 3.3V. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Notes 6, 7)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
(Note 6)
MAX
(Note 7)
UNITS
INPUT PIN
WDI Rising Threshold
WDI, VDDRFE = 3.3V, VCC5 = 5V
1.50
1.64
1.80
V
WDI Falling Threshold
WDI, VDDRFE = 3.3V, VCC5 = 5V
1.40
1.56
1.70
V
61
kΩ
WDI Hysteresis
80
Disable Mode Input Voltage Threshold
WDI, VDDRFE = 3.3V, VCC5 = 5V
Inner Pull-up Resistor
Pull up to VCC5
4.5
Minimum Pulse Width
WDI, VDDRFE = 3.3V, VCC5 = 5V
300
ns
VCC5 = 5V
4.5
V
1.5
ms
37
50
V
TIME-OUT CHARACTERISTICS
Timer Rising Threshold
SWITCHING CHARACTERISTICS
Timer Reset Pulse Width
Timer Leakage Current
Timer = 5V
Timer Voltage Low
ITimer = 4mA
1.2
0.5
PGOOD2 Reset Pulse Width
1
Current Sense Op amp Electrical Specifications
operating temperature range, -40°C to +85°C. (Notes 6, 7)
SYMBOL
PARAMETER
µA
V
ms
TA = +25°C, VR1 = 10V, VR2 = 3.3V. Boldface limits apply over the
TEST CONDITIONS
Input Offset Voltage
MIN
(Note 7
TYP
(Note 6)
MAX
(Note 7)
UNITS
-1000
µV
Input Bias Current
3
nA
Input Offset Current
±1
nA
VCM_min
Minimum Common-Mode Voltage
-0.1
V
VCM_max
Maximum Common-Mode Voltage
2
V
CMRR
Common-Mode Rejection Ratio
VCM = -0.1V to 2V
100
dB
PSRR
Power Supply Rejection Ratio
VCC = 3.3V to 5.5V, VOUT2 = 3.3V
100
dB
Large Signal Voltage Gain
220
V/mV
Output low, RL = 100kΩ to VCM
5.3
mV
Output high, RL = 100kΩ to VCM;
VDDREF tied to 3.3V VOUT2
3.0
V
RL = 10Ω to VCM
30
mA
Gain Bandwidth Product
RL = 10kΩ to VCM
130
kHz
Maximum Output Voltage Swing
Short-Circuit Output Source Current
AC SPECIFICATIONS
Input Noise Voltage Peak-to-Peak
F = 0.1Hz to 10Hz
1.4
µVP-P
Input Noise Voltage Density
fO = 1kHz
64
nV/√Hz
Input Noise Current Density
fO = 10kHz
0.19
pA/√Hz
100
V/ms
Slew Rate
Submit Document Feedback
10
FN8259.1
July 24, 2014
ISL1801
Dual High-Speed Comparator Electrical Specifications
over the operating temperature range, -40°C to +85°C. (Notes 6, 7)
SYMBOL
PARAMETER
TA = +25°C, VR1 = 10V, VR2 = 3.3V. Boldface limits apply
TEST CONDITIONS
Input Offset Voltage
VCM_min
VCM_max
CMRR
MIN
(Note 7)
-5.5
TYP
(Note 6)
MAX
(Note 7)
UNITS
0
5.5
mV
Input Bias Current
±1
pA
Input Offset Current
±1
pA
Minimum Common-Mode Voltage
-0.2
V
Maximum Common-Mode Voltage
3.3
V
62
dB
Input Common-Mode Capacitance
2
pF
Input Differential Capacitance
4
pF
3
V
Common-Mode Rejection Ratio
VCM = -0.2V to VOUT2
Output High Voltage
IOUT = -0.3mA; VDDREF Tied to 3.3V
VOUT2
Output Low Voltage
IOUT = 0.3mA
2.7
175
Short Circuit Current
300
1
mV
mA
SWITCHING SPECIFICATIONS
Low-to-High Propagation Delay Time
Input overdrive = 100mV
0.55
µs
High-to-low Propagation Delay Time
Input overdrive = 100mV
0.2
µs
CMP1 Rise Time
CL = 10pF, CMP1+ toggled from 0V to
1V
5
100
550
ns
CMP1 Fall Time
CL = 10pF, CMP1+ toggled from 1V to
0V
5
100
550
ns
1.1
2.5
µs
1
µA
0.5
V
LATCHRPT (OPEN DRAIN OUTPUT)
LATCHRPT One-Shot Pulse Width
Under pulse by pulse OC condition,
LATCHRPT pulled low for one-shot
period of each OC cycle
LATCHRPT Leakage Current
VPULLUP = 3.3V
LATCHRPT Voltage Low
ILATCHRPT = 4mA
Preload Electrical Specifications
-40°C to +85°C. (Notes 6, 7)
SYMBOL
PARAMETER
TA = +25°C, VR1 = 10V, VR2 = 3.3V. Boldface limits apply over the operating temperature range,
TEST CONDITIONS
MIN
(Note 7
TYP
(Note 6)
MAX
(Note 7)
UNITS
POWER MOSFET
rDS(ON)
Switch 1 ON ON-Resistance
Pull-up to VCC1 = 10V through 100Ω
resistor (Note 8)
242
350
472
Ω
rDS(ON)
Switch 2 ON ON-Resistance
Pull-up to VCC1 = 10V through 100Ω
resistor (Note 8)
90
120
165
Ω
rDS(ON)
Switch 3 ON ON-Resistance
Pull-up to VCC1 = 10V through 100Ω
resistor (Note 8)
40
56
76
Ω
rDS(ON)
Switch 4 ON ON-Resistance
Pull-up to VCC1 = 10V through 100Ω
resistor (Note 8)
8.7
11.4
14.8
Ω
NOTES:
6. Compliance to datasheet values is assured by one or more methods: production test, characterization and/or design.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. Not production tested.
Submit Document Feedback
11
FN8259.1
July 24, 2014
ISL1801
Typical Performance Curves
95
94
90
92
6VIN
80
30VIN
EFFICIENCY (%)
EFFICIENCY (%)
45VIN
85
15VIN
75
90VIN
75VIN
70
90
88
14VIN
10VIN
86
84
60VIN
65
82
60
0
0.05
0.10
OUTPUT CURRENT (A)
80
0.025
0.15
0.125
0.175
OUTPUT CURRENT (A)
0.225
FIGURE 4. VR2 EFFICIENCY vs LOAD CURRENT WITH
VOUT2 = 2.5V at FSW2 = 210kHz
FIGURE 3. VR1 EFFICIENCY vs LOAD CURRENT WITH
VOUT1 = 10V at FSW1 = 170kHz
89
10.14
87
10.12
85
10.10
83
VOUT1 (V)
EFFICIENCY (%)
0.075
81
10.08
15VIN
10.06
45VIN
60VIN 75VIN
30VIN
90VIN
10.04
79
VOUT1 = 10V
IOUT1 = 100mA
FSW1 = 170kHz
77
75
10
20
30
10.02
VOUT2 = 2.5V
IOUT2 = 200mA
FSW2 = 210kHz
40
50
60
10.00
70
80
90
9.98
100
0
0.05
0.10
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
FIGURE 5. VR1 + VR2 EFFICIENCY vs INPUT VOLTAGE
0.15
FIGURE 6. VR1 REGULATION vs LOAD CURRENT WITH
VOUT1 = 10V at FSW1 = 170kHz
2.56
190
2.55
180
50VIN
10VIN
2.54
FSW1 (kHz)
VOUT2 (V)
2.53
2.52
2.51
6VIN
160
90VIN
150
140
2.50
130
2.49
2.48
0.025
15VIN
170
14VIN
0.075
0.125
0.175
OUTPUT CURRENT (A)
FIGURE 7. VR2 REGULATION vs LOAD CURRENT WITH
VOUT2 = 2.5V at FSW2 = 210kHz
Submit Document Feedback
12
0.225
120
0
0.05
0.10
0.15
OUTPUT CURRENT (A)
FIGURE 8. VR1 SWITCHING FREQUENCY vs LOAD CURRENT WITH
VOUT1 = 10V
FN8259.1
July 24, 2014
ISL1801
Typical Performance Curves (Continued)
250
230
210
190
FSW2 (kHz)
14VIN
170
6VIN
150
10VIN
130
110
90
70
50
0
0.05
0.10
OUTPUT CURRENT (A)
0.15
0.2
FIGURE 9. VR2 SWITCHING FREQUENCY vs LOAD CURRENT WITH VOUT2 = 2.5V
Submit Document Feedback
13
FN8259.1
July 24, 2014
ISL1801
Test Waveforms
200mA load holds VOUT2 at 0V until the inductor current is greater than 200mA
FIGURE 10. VR1 SOFT-START (FROM TOP TO BOTTOM: PHASE1, I_L1,
VOUT1)
FIGURE 11. VR2 SOFT-START WITH 200mA LOAD (FROM TOP TO
BOTTOM: PHASE2, I_L2, VOUT2)
THE CAPACITOR ON THE TIMER PIN
IS 1nF TO GENERATE A VERY SHORT
PRELOAD DURATION FOR THIS PLOT
FIGURE 12. WATCHDOG OPERATION
FIGURE 13. NORMAL POWER-UP SEQUENCE
FIGURE 14. SOFT-START WHEN PRELOAD TEST FAILS
FIGURE 15. NORMAL POWER-DOWN SEQUENCE
Submit Document Feedback
14
FN8259.1
July 24, 2014
ISL1801
Test Waveforms (Continued)
FIGURE 16. OCSET3 THRESHOLD CROSSING TRIGGERS OCP
Submit Document Feedback
15
FN8259.1
July 24, 2014
ISL1801
Summary of Operation
The ISL1801 is a versatile Solar Power Management IC (sPMIC).
It has two switching regulators, two LDOs, two general purpose
comparators, two power MOSFET drivers, a current sense OPAMP
and other logic functions. Figure 17 shows the main blocks in the
ISL1801.
The high voltage LDO1 can be directly connected to a high
voltage input power source up to 90V. The output can be used to
start-up the high voltage switching regulator VR1. Once the VR1’s
output is greater than 6.7V, LDO1 is disabled to save power. The
second low voltage regulator, LDO2, can be connected to the
output of VR1 to generate the 5V supply required for the internal
control circuits including those that operate VR1 and VR2.
The first switching regulator, VR1, can be directly connected to an
input voltage up to 90V. The VR1 provides a regulated voltage for
the second switching regulator, VR2, and the two integrated
MOSFET drivers. The low voltage switching regulator, the VR2,
can be used to generate the regulated voltage for an MCU or
other external circuitry. The PGOOD2 signal is used to indicate
that VR2 output voltage is within the regulation window. The
output voltage of both VR1 and VR2 can be set through resistor
dividers at the FB1 and FB2 pins respectively. The switching
frequencies of VR1 and VR2 are determined by the resistors at
the TON1 and TON2 pins respectively.
There are two low-side drivers for the external power MOSFETs.
Both drivers are powered by the PVCC3 pin, which is normally
connected to the output of VR1.
The integrated amplifier has low offset and drift so, the MCU can
accurately sense the amplified module current.
Overcurrent and overvoltage conditions can be monitored by the
two general purpose high-speed comparators. Any detected fault
condition can be used to trigger an MCU interrupt.
The preload function is specially designed for solar applications.
It applies a resistive load to the input power source to verify that
it is sufficient for device operation. VR2, the MCU supply, will not
be enabled until the input power source has enough power. This
function can significantly reduce the power cycling of the MCU at
system start-up and shutdown.
The ISL1801 also includes a watchdog circuit to prevent the
software in the MCU from hanging in an unknown state. The MCU
can use the watchdog input (WDI) pin to periodically restart the
timer. The watchdog timeout is set by a resistor to VCC5V and a
capacitor to ground, both connected to the TIMER pin. If the RC
timer expires before an MCU reset on the WDI pin the PGOOD2
pin will be pulled low to reset the MCU.
PVCC3
ISL1801
MCU
MCU
BCMD
PWM3
WDI
MCU
BDRIVER POWER
MOSFET
DRIVER3 POWER
MOSFET
HIGH
SPEED
DRIVER
PGOOD2
VIN1
VCC5V
VR1
+
-
TIMER
PV
PANEL
PWM1
Vth2
WATCHDOG
PRE-LOAD
CONTROL
+
VCC
1
Vth3
ENABLE
VR2
VOUT1
VCC
1
L1
VOUT1
(10V)
VCC1
LDO1
FB1
ENABLE
VR1
PRELOAD
PVCC3
POR
VCC5
V
PWM2
+
-
VIN2
VR2
LDO2
VCC5
V
L2
VOUT2
(3.3V)
OPAMP AND
COMPARATORS
VCC5V
PGOOD2
MCU
+
0.88*Vref2
FB2
-
FIGURE 17. ISL1801 SIMPLIFIED BLOCK DIAGRAM
Submit Document Feedback
16
FN8259.1
July 24, 2014
ISL1801
Detailed Operation
When VIN1 is much larger than 1V, the switching frequency of
VR1 is almost independent of its input voltage:
Dual Synchronous Buck Switching
Regulators With Constant On Time Control
V OUT1
F SW1  ----------------------------------------– 11
2.7e
 R ON1
There are two synchronous Buck switching regulators in the
ISL1801. The high voltage switching regulator, VR1, can be
connected to a power source up to 90V. The low voltage
switching regulator, VR2, supports input voltages up to 14V.
Typically, VR2 is connected to the output of VR1. Both switching
regulators include integrated MOSFETs.
Both VR1 and VR2 employ a constant on time PWM control
architecture with input voltage feed-forward. The constant on
time PWM control architecture relies on the output ripple voltage
to provide the PWM ramp signal; thus the output filter capacitor's
ESR acts as a current feedback resistor. For some applications
with ceramic capacitors, the output voltage ripple is small due to
very low ESR. In order to achieve the stable operation for very low
voltage ripple applications, one internal ramp is generated and
added to the FB signal to emulate the output voltage ripple. The
high-side switch ON time is determined by a one-shot, which
period is inversely proportional to input voltage and directly
proportional to output voltage. Another one-shot sets a minimum
OFF time (300ns typical for VR1 and 150ns typical for VR2). The
ON time one-shot triggers when the following conditions are met;
the error comparator's output is high, the synchronous rectifier
current is below the current limit threshold, and the minimum
OFF time one-shot has timed out. The controller utilizes the valley
point of the output ripple to regulate and determine the OFF
time.
SWITCHING FREQUENCY OF VR1 AND VR2
Each PWM core includes a one-shot that sets the ON time for the
high-side switch of each voltage regulator. Each fast, low jitter,
adjustable one-shot includes circuitry that varies the ON time in
response to the input voltage and output voltage. This algorithm
results in a nearly constant switching frequency despite the lack
of a fixed-frequency clock generator.
The high-side switch ON time is inversely proportional to the
input voltage as measured by the TON1 and TON2 pins for VR1
and VR2 respectively. Both TON1 and TON2 pins are tied to an
internal voltage reference and the current flowing into these pins
is monitored to generate the ON time one-shot.
For high voltage VR1, the TON1 pin is tied to an internal 1V
reference and the width of the ON time one-shot is:
– 11
2.7e
 R ON1
T ON1 = ----------------------------------------V IN1 – 1
(EQ. 1)
VIN1 is the input voltage for high voltage VR1, while RON1 is the
resistor from VIN1 to the TON1 pin.
(EQ. 3)
For a 10V output, the switching frequency of VR1 is about
370kHz with RON1 = 1MΩ.
For low voltage VR2, the TON2 pin is tied to an internal 0.5V
reference and the width of the ON time one-shot is:
– 11
1.05e
 R ON2
T ON1 = --------------------------------------------V IN2 – 0.5
(EQ. 4)
VIN2 is the input voltage for VR2, while RON2 is the resistor from
VIN2 to the TON2 pin.
The switching frequency of VR2 is:
V OUT2   V IN2 – 0.5 
F SW2 = -------------------------------------------------------------– 11
 R ON2  V IN2
1.05e
(EQ. 5)
When VIN2 is much larger than 0.5V, the switching frequency of
VR2 is almost independent of its input voltage:
V OUT2
F SW2  --------------------------------------------– 11
1.05e
 R ON2
(EQ. 6)
For a 3.3V output, the switching frequency of VR2 is about
314kHz with RON2 = 1MΩ.
CURRENT LIMITING OF VR1 AND VR2
To prevent the output current from becoming too high, a new ON
time pulse can start only when the current through the
synchronous MOSFET is below the current limiting threshold. This
limits the valley of the output inductor current to a fixed value,
typically 140mA for VR1 and 200mA for VR2.
The maximum peak current through the output inductor is the
sum of the current limiting threshold and the current ripple
determined by the ON time, inductor value and the input/output
voltage.
DIODE EMULATION OPERATION
To improve the efficiency for light loads, the synchronous
MOSFET is turned off when its current drops to 0. This prevents
negative current through the output inductor emulating diode
operation.
With diode emulation operation under light load conditions, the
output voltage may drop slowly after the synchronous MOSFET
turns OFF. It may take a long time for the output voltage to drop
below the reference voltage to start a new switching cycle. This
will have the effect of reducing the switching frequency under
light load conditions.
The switching frequency of VR1 is:
V OUT1   V IN1 – 1 
F SW1 = ----------------------------------------------------------– 11
 R ON1  V IN1
2.7e
Submit Document Feedback
(EQ. 2)
17
FN8259.1
July 24, 2014
ISL1801
OVERVOLTAGE PROTECTION
Dual Low-Side MOSFET Drivers
The feedback voltage for VR1 and VR2 is continuously monitored
to prevent the output voltage from going too high.
The ISL1801 has two low-side drivers for power MOSFETs
connected to the DRIVE3 and BDRIVE pins. Their high output
current enables them to rapidly charge and discharge the gate
capacitance of power MOSFETs. Both drivers are powered by the
PVCC3 pin, and each driver has its own ground pin. PGND3 is the
ground connection for DRIVE3 and PGND4 is the ground
connection for BDRIVE. The gate drivers (DRIVE3 and BDRIVE)
are always pull-down to ground by internal 14kΩ resistor.
Additional 250Ω pull-down resistor is available only after the 5V
LDO VCC5V has come up higher than 3.2V.
When the VR1 output voltage feedback FB1 is higher than 120%
of VREF1, the Overvoltage Protection (OVP) is triggered. When
this condition occurs, the lower-side MOSFET of VR1 is turned on
immediately. At the same time, the preload current will be
applied to VOUT1 to discharge the output. When the current
through the lower side MOSFET drops to 0, turn off this MOSFET
to prevent the negative inductor current. the OVP is reset when
FB1 voltage drops to VREF1.
For low voltage VR2, OVP is triggered when the FB2 voltage is
above 0.775V. When this condition occurs, the lower
synchronous MOSFET of VR2 is turned on immediately. It is held
on until the FB2 voltage drops below 0.73V.
POWER-GOOD SIGNAL (PGOOD2)
Both VR1 and VR2 have their own power-good signals to indicate
that their output voltage is within the regulation window. Only the
VR2 power-good signal is externally available at the PGOOD2 pin.
VR1’s power-good signal is used internally and is not available on
an external pin.
The PGOOD2 pin is a true open drain output. The power-good
comparator continuously monitors the feedback voltage FB2 for
an undervoltage condition. PGOOD2 is active low during
shutdown or when FB2 is below the threshold voltage. When the
FB2 voltage goes above 88% of its reference voltage
(0.88 * 0.73V = 0.64V), PGOOD2 is released and the pin will be a
high impedance.
The PGOOD2 signal can be used to reset the MCU powered by the
output of VR2.
The watchdog timer will also pull PGOOD2 low when a timeout
occurs. Please refer to “WatchDog Timer” on page 20 for more
information.
Dual LDO Bias Supplies
There are two LDOs in the ISL1801 to manage start-up and
power internal control circuitry.
The high voltage LDO1 can be directly connected to an input power
source up to 90V. Its output is connected to the VCC1 pin and is
typically about 6.7V. VCC1 provides the bias voltage for the power
stage of high voltage regulator. Typically, the VCC1 pin should be
connected to VOUT1, the output of high voltage regulator VR1.
Before VR1 starts to operate, LDO1 can charge up the capacitor at
VCC1 when it is tied to VOUT1. When the VOUT1/VCC1 voltage
reaches 6.5V, VR1 starts to operate and will ramp VOUT1/VCC1 to
a higher voltage. Once the VCC1 voltage is above 6.7V, LDO1 is
disabled. LDO1 limits its output current to 10mA.
DRIVE3 CONTROL LOGIC
DRIVE3 is controlled by the PWM3 signal. When PWM3 = 1, the
DRIVE3 output is connected to PVCC3 by its upper switch. When
PWM3 = 0, DRIVE3 is connected to PGND3 through its lower
switch. However there are other logic signals which influence the
state of DRIVE3.
Before Power On Reset (POR) DRIVE3 is forced low. When the
output of comparator 1 (CMP1O) or comparator 2 (CMP2O) is
high it triggers a flip-flop (FF1) setting the open drain latch report
(LATCHRPT) signal low. It also connects DRIVE3 to PGND3
immediately. The RPWM3 pin has to be forced low to reset this
condition. Since the set input of flip-flop FF1 overrides the reset
input, DRIVE3 is always held low when CMP1O or CMP2O is high
even when RPWM3 = 0.
DRIVE3 OVERCURRENT LIMITING
A comparator monitors the PHASE3 voltage when DRIVE3 is high
to detect a possible overcurrent condition. When this comparator
output is high, DRIVE3 is immediately connected to PGND3. This
action provides overcurrent protection (OCP) for the power stage
driven by DRIVE3. Figure 18 shows the block diagram of the
PHASE3 OCP function.
The PHASE3 overcurrent limiting level is defined by the OCSET3 pin.
A 120µA current is supplied by the OCSET3 pin. Placing a resistor
from the OCSET3 pin to PGND3 sets the overcurrent threshold
voltage. A capacitor may be placed in parallel with the OCSET3
resistor to filter noise and provide a more consistent OCP threshold.
When DRIVE3 = 1, the internal switch S3 is turned on feeding the
PHASE3 signal to the OCP comparator. The PHASE3 voltage is
equal to the product of the current I1 and the conduction
resistance rDS(ON) of the power MOSFET Q1. When the PHASE3
pin voltage is higher than the OCSET3 pin voltage, the DRIVE3
OCP is triggered. The overcurrent limiting level is:
120A  R1
I OC3 = ------------------------------r DS  ON 
(EQ. 7)
There is a second low voltage LDO2 which can be connected to
inputs up to 14V. LDO2’s 5V output is connected to the VCC5V pin.
Typically, LDO2 is connected to the input voltage of low voltage
VR2 (typically VOUT1). LDO2 supplies power for internal circuitry
such as the current sense Op amp, logic circuits, comparators and
the VR2 control circuits. One 2.2µF capacitor is recommended at
the VCC5V pin. LDO2 limits its output current to 10mA.
Submit Document Feedback
18
FN8259.1
July 24, 2014
ISL1801
ISL1801
120µA
LATCHRPT
ON
SHOT
OCSET
Q
RPWM3
S
R
SET
CLR
S
FF2
Q
CMP1O
CMP2O
SET
CLR
R1
R
Q
Q
C1
PGND3
FF1
S3
PHASE3
I1
DRIVE3
Q1
PVCC3
PWM3
PGND3
POR
FIGURE 18. LOW-SIDE DRIVER LOGIC
Once the overcurrent protection is triggered flip-flop FF2 is set
forcing DRIVE3 low. RPWM3 or PWM3 must be pulled low to
reset an OCP event. Since the set input of flip-flop FF2 overrides
the reset input, DRIVE3 is always held low in an overcurrent
condition even if RWPM3 = 0.
The OCP flip-flop output also triggers a one-shot block to
generate a narrow pulse setting LATCHRPT low for 1µs.
For normal operation an OCP event terminates the DRIVE3 on state
early by forcing DRIVE3 to PGND3. The OCP event is reset by setting
PWM3 = 0. This allows DRIVE3 to be turned on by the following
PWM3 = 1 pulse. However, special attention is needed for long-term
or continuous OCP operation. If the OCP is continuously triggered
with RPWM3 = 0 and PWM3 = 1, then a very high switching
frequency may occur on the DRIVE3 pin. Referring to Figure 18 the
following sequence of events will lead to this oscillation. When I1 is
larger than the preset OCP level, it may trigger OCP immediately
when DRIVE3 = 1. Once OCP is triggered, DRIVE3 is pulled low, and
S3 is turned off setting the OCP comparator output low. Since
RPWM3 = 0, the flip-flop FF2 is reset immediately. However, the 1µs
one-shot will keep LATCHRPT low for at least 1µs forcing the DRIVE3
pin low for at least 1µs. After 1µs DRIVE3 is forced high resulting in
another OCP. This operation repeats until PWM3 = 0, RPWM3 = 1 or
I1 drops below the OCP threshold. This condition may result in a
100kHz switching frequency at DRIVE3.
BDRIVE CONTROL LOGIC
The BDRIVE pin is controlled by the BCMD signal. When
BCMD = 1, the BDRIVE output is connected to PVCC3 by its upper
switch. When BCMD = 0 the BDRIVE pin is connected to PGND4
through its lower switch.
When any fault condition occurs, the LATCHRPT signal is set low.
It will also set flip-flop FF3 and connect the BDRIVE pin to PGND4
until flip-flop FF3 is reset by setting BRESET = 1. BDRIVE is held
at PGND4 prior to POR. The BDRIVE logic is shown in Figure 19.
FIGURE 19. BDRIVE CONTROL LOGIC
When VDDREF is not applied during the start, the output of the
level shift block is undefined. In order to prevent BDRIVE turning
on by mistake, it’s recommended adding some offset (~50mV)
on VDDREF pin to make the POR AND gate output low.
Dual High-Speed Comparator
The ISL1801 has two high-speed comparators for fault detection.
The output of either comparator can set the flip-flop FF1 to
indicate a fault at the open-drain LATCHRPT pin. The fault can be
cleared by setting RPWM3 = 0 to reset flip-flop FF1.
The two comparators are identical but only the output of
comparator 1 (CMP1) is available at the CMP1O pin. CMP1O is a
push-pull output and its output high level is clamped to VDDREF.
The fault detection logic is shown in Figure 20.
LATCHRPT
ONE
SHOT
OCP3
CMP2+
CMP2CMP1+
CMP1-
CMP2
S
VDDREF
SET
Q
FF1
R
CLR
Q
CMP1
CMP1O
ISL1801
RPWM3
FIGURE 20. FAULT DETECTION LOGIC
Submit Document Feedback
19
FN8259.1
July 24, 2014
ISL1801
Precision Amplifier
The ISL1801 includes a precision amplifier for current sensing.
This low offset and low temperature drift Op amp can be used to
accurately amplify the voltage drop across a known shunt
resistor to provide a current measurement for the MCU. Due to
the very low amplitude input signal, it is necessary to include
some capacitance as a noise filter. The typical application circuit
is shown in Figure 21. The current sense gain is set by the ratio of
R1/R2. Capacitor C1 implements a low-pass filter to reduce high
frequency noise effectively averaging the desired signal. C2 is
optional and can provide additional noise filtering if required.
.
C1
R1
AMP-
Next, Q3 turns on with Q1 and Q2; Finally all the MOSFETs are on
resulting in the minimum resistance from the PRELOAD pin to
GND:
V VR1
I VR1 = ----------------------------------------------------------------------------------------------------------------------------------------------
R PL +  r DS  ON 1 r DS  ON 2  r DS  ON 3  r DS  ON 4 
After all the MOSFET switches are on the TIMER pin is pulled to GND
for 1ms and then released to ramp-up. If the VR1 output voltage
stays above the preset threshold until the TIMER pin ramps to 90%
of VCC5V, the preload is removed step-by-step, as shown in Figure
23. If the VR1 output drops below the preset threshold all the
switches are turned off immediately. The “Power-Up Sequence” on
page 22 provides additional details.
R2
-
VDDREF
VR1
OUTPUT
ISL1801
C2
Rs
-
AMPO
AMP+
+
C1
(EQ. 10)
R2
+
PRELOAD
ISENSE
rDS(ON)1
350
rDS(ON)2
120
rDS(ON)3
50
R_PL
rDS(ON)4
12
R1
PGND
Q1
Q2
Q4
Q3
FIGURE 21. PRECISION CURRENT SENSE AMPLIFIER
Preload Operation
During morning start-up, shading events or evening shutdown, PV
modules may not provide enough output power to run the micro
converter. When this happens it may result in a repetitive voltage
dropout at the VR2 output. When the VR2 output powers the
MCU, this may cause a system reset after each dropout. The
repetitive restart operation of MCU may impact on the system
reliability.
To avoid this issue, the ISL1801 includes the preload feature to
test the power source before enabling VR2. This test is performed
by gradually applying a preload current to the output of
VR1/VOUT1. If the preloaded VR1 output voltage drops below the
preset threshold, the preload is removed immediately. After the
VR1 output voltage recovers, the preload test is repeated. If VR1
can support the preload current and maintain its output voltage
above the preset threshold for some time the input power source
has enough power for the system operation. The preload is then
removed, and VR2 is enabled and will perform a soft-start.
Figure 22 shows the ISL1801s preload circuit. The four MOSFETs
each have a different ON resistance that can be connected to the
preload pin. This allows the ISL1801 to increase the preload
current step-by-step, as shown in Figure 23. When the preload is
enabled, Q1 turns on for about 500µs. During this time the
current applied to the VR1 output as shown by Equations::
V VR1
I VR1 = ------------------------------------------R PL + r DS  ON 1
(EQ. 8)
Next, Q2 turns on with Q1 and the preload current becomes:
V VR1
I VR1 = -------------------------------------------------------------------------------R PL +  r DS  ON 1  r DS  ON 2 
Submit Document Feedback
20
(EQ. 9)
FIGURE 22. PRELOAD SWITCHES
ENABLE
Q1
OFF
ON
OFF
Q2
OFF
ON
OFF
Q3
OFF
ON
OFF
Q4
OFF
ON
OFF
t0
t1
t2
t3
t4
t5
t6 t7
FIGURE 23. PRELOAD TIMING DIAGRAM
WatchDog Timer
The Watchdog Timer circuit in Figure 24 verifies correct MCU
operation by monitoring the WDI input pin. The MCU must
periodically toggle the WDI pin to prevent a timeout. If a timeout
occurs, the PGOOD2 pin will be pulsed low for 0.5ms providing a
signal that can reset the MCU. PGOOD2 will then remain high
until the next timeout or invalid voltage event.
The timeout interval is determined by the capacitor and resistor
connected to the TIMER pin. Any low-to-high or high-to-low
transition on the WDI pin forces the TIMER pin low for 1.5ms to
discharge the capacitor from the TIMER pin to ground. After the
1.5ms period the TIMER pin is released so the resistor can start
charging the capacitor. When the TIMER pin voltage reaches 90%
of the VCC5V supply voltage a time-out event is triggered.
FN8259.1
July 24, 2014
ISL1801
The WDI pin is pulled to VDDREF by an internal 40kΩ resistor.
When the WDI pin is floating, the WDI voltage will be VDDREF.
The WDI signal is compared to two threshold voltages resulting in
the periodic discharge of the capacitor on the TIMER pin or
disabling the watchdog function.
The WDI pin voltage is compared to VDDREF/2 to determine if
there is any activity on the pin. Any rising or falling transition on
the WDI pin that crosses the VDDREF/2 threshold will generate a
one-shot pulse to pull the TIMER pin low for 1.5ms.
The WDI pin voltage is also compared to 90% of VCC5V. If the
WDI pin is above 90% of VDD5V the watchdog feature will be
disabled and the TIMER capacitor will not be discharged.
If the WDI pin voltage stays at any constant voltage below the
disable threshold the resistor from TIMER to VCC5V will charge
the capacitor. When the TIMER pin voltage reaches 90% of
VCC5V a time-out event is triggered and PGOOD2 will be set low
for 0.5ms.
Whenever WDI enters or exits its disable mode the TIMER pin is
pulled low for 1.5ms.
ISL1801
0.9*VCC5V
TIME-OUT
VCC5V
VDDREF
TIMER
R
40k
ONE
SHOT
WDI
because soft-start is initiated by crossing the 90% of VDD5V
threshold and the watchdog timeout also depends on crossing
this threshold.
Figure 25 shows the typical operational waveforms of the
watch-dog timer circuit.
t0: The VR1/VOUT1 voltage ramps up to its threshold voltage;
WDI is pulled to VDDREF, which is 0V; TIMER starts to
ramp-up.
t1: TIMER reaches the 90% threshold (0.9 * 5V = 4.5V) and
starts to initialize the ISL1801.
t2: All preloads are sequentially applied, reset TIMER and hold
it low for 1.5ms.
t3: 1.5ms timeout, TIMER starts to ramp up.
t4: TIMER voltage reaches 90% threshold, release all preloads
and enable VR2 soft-start.
t5: VR2 finishes soft-start and PGOOD2 goes high; reset TIMER
and hold for 1.5ms, then enable the watchdog function; MCU
starts to run, WDI is floating at VDDREF, TIMER ramps up.
t6: MCU sends out the first pulse and the WDI falling edge
(from high to low) resets TIMER for 1.5ms; then TIMER
ramps up.
t7: TIMER is reset for 1.5ms by the WDI rising edge; then
TIMER ramps up.
t8: TIMER is reset for 1.5ms by the WDI falling edge; then
TIMER ramps up.
t9: TIMER is not reset in time and reaches 90% threshold level;
PGOOD2 is pulled low for 1ms to reset MCU; and TIMER is
reset for 1.5ms.
EN
R
t10: PGOOD2 goes back high to exit MCU reset.
t11: 1.5ms timeout, TIMER ramps up.
0.9*VCC5V
t12: TIMER is reset for 1.5ms by the WDI rising edge; then
TIMER ramps up.
FIGURE 24. WATCHDOG TIMER LOGIC
It is important to note that the maximum leakage current into
the TIMER pin is 1µA. This leakage current across the pull-up
resistor will set the maximum voltage on the TIMER pin. In order
to assure correct operation, the pull-up resistor from the TIMER
pin to VCC5V should never be more than 200kΩ. The voltage drop
for 1µA across 200kΩ is 200mV, well below the 90% threshold
value of 5V - (5V * 90%) or 5V - 4.5V = 500mV. This is important
t13: TIMER is not reset in time and reaches the 90% threshold
level; PGOOD2 is pulled low for 1ms to reset MCU; and
TIMER is reset for 1.5ms.
t14: PGOOD2 goes back high to exit MCU reset; then TIMER
ramps up.
VOUT1
4.5V
0.6*VDDREF
WDI
4.5V
TIMER
PGOOD2
t0
t1
t2 t3 t4 t5
t6
t7
t8
t9 t10 t11 t12
t13 t14
t15 t16 t17
t18
t19
t20
FIGURE 25. WATCHDOG TIMER WAVEFORMS
Submit Document Feedback
21
FN8259.1
July 24, 2014
ISL1801
t15: WDI voltage changes from VDDREF to 0.6*VDDREF; Since
it does not cross the VDDREF/2 threshold no falling edge
signal is generated; TIMER continues ramping up.
t16: TIMER is not reset in time, and reaches the 90% threshold
level; PGOOD2 is pulled low for 1ms to reset MCU; and
TIMER is reset for 1.5ms.
t17: PGOOD2 goes back high to exit MCU reset; then TIMER
ramps up.
t18: TIMER is reset for 1.5ms by the WDI falling edge; then
TIMER ramps up.
t19: TIMER is reset by the WDI rising edge; WDI is above
90%*VCC5V threshold level, watchdog function is disabled.
TIMER ramps up and stays at its high state however it does
not trigger a time-out.
t20: WDI drops below the 90%*VCC5V threshold level,
watch-dog function is enabled; TIMER is reset for 1.5ms by
the WDI falling edge; then TIMER ramps up.
VIN1
PWM1
Vth2Vth3
FB1
PVCC3
VR1 current
limiting level
ON
PRELOAD
Current
ON
OFF
4.5V
TIMER
4.5V
VCC5V
POR
PWM2
Vout2
PGOOD2
OPAMP,
COMPARATORS,
DRIVER3,
BDRIVE
Disabled
Enabled
PWM3
t0
t1
t2
t3 t4 t5
t6
t7
t8 t9
t10
FIGURE 26. POWER-UP SEQUENCE
Power-Up Sequence
Before t0, the PV module does not output any voltage
t0: Panel output voltage VIN1 starts to ramp up; LDO1 is ON to
pull VOUT1 (=PVCC3) up; LDO2 runs in saturated condition
to pull VCC5V up.
t1: When VCC5V reaches its power on reset (POR) level (4.5V),
the ISL1801 starts to operate and monitor the voltage at the
TIMER pin; after TIMER reaches its threshold (90% * VCC5),
the ISL1801 starts to initialize all internal circuits; then VR1
starts to run at the maximum duty cycle, and the VR1 current
Submit Document Feedback
22
limiting level starts to ramp up step-by-step; LDO1 continues
to output some current until PVCC3 reaches about 6.2V.
t2: VR1 current limiting level ramps up to its final value.
t3: FB1 reaches Vth3 (90% of its final value), the preload
switches are turned on in sequence to apply the preload
current to the VR1 output.
t4: If the PV module does not have sufficient output power,
PVCC3 will drop to Vth2 (fixed at 7V) when the preload is
applied; this triggers the immediate removal of all preload
current followed by a 500µs delay.
FN8259.1
July 24, 2014
ISL1801
t5: When PVCC3 goes above Vth2 again, slowly apply the
preload current to VR1 output.
t8: Preload is removed; VR2 starts to ramp up.
t6: If PVCC3 stays above Vth2 after the maximum preload
current is applied the TIMER voltage is pulled to 0V for
1.5ms and released; the external R-C causes the TIMER pin
voltage to ramp up.
t7: TIMER voltage reaches its 90% threshold; starts to remove
preload step-by-step; from now on, PVCC3 and FB1 are not
monitored for shut-down. Only VCC5V is monitored for
undervoltage lock out (UVLO).
t9: FB2 reaches 90% of its final value; PGOOD2 open-drain
switch is open to allow PGOOD2 to rise.
t10: PGOOD2 is high; all internal circuits, including driver,
OPAMP and comparators are enabled.
NOTE: VR1 current limiting level will ramp up step-by-step with a 25%
increase for each step. The preload will be applied only after the VR1
current limiting level reaches its final value and FB1 is above Vth3.
VIN1
OFF
Pre_load
PWM1
Vth2
PVCC3
Timer
LDO2
OFF
ON
4.5V
VCC5V
POR
PWM2
Vout2
PGOOD2
OPAMP,
COMPARATOR
DRIVER3/
BDRIVE
Disabled
Enabled
Disabled
GND
GND
Enabled
PWM3
t0
t1
t2
t3
FIGURE 27. POWER-DOWN SEQUENCE
Power-Down Sequence
Before t0, the system runs in normal mode:
t0: PVCC3 drops below Vth2, both drivers’ outputs are pulled to
GND; MCU should stop sending PWM signal; both VR1 and
VR2 continue operating.
t3: PVCC3 drops to a very low level and VCC5V drops below the
POR level (4.5V); the IC shuts down and all internal circuits
are disabled.
When VCC1 drops below 6V, the VR1 power stage stops
operating. The VR1 control circuit will still run until VCC5V drops
below the 90% * VCC5 (4.5V) POR threshold.
t1: PVCC3 returns above Vth2, both drivers are ready to run.
t2: PVCC3 drops below Vth2, both drivers’ outputs are pulled to
GND; both VR1 and VR2 continue operating.
Submit Document Feedback
23
FN8259.1
July 24, 2014
ISL1801
Over-Temperature Protection
Over-temperature protection (OTP) is placed on the HV die.
Temperature higher than +150°C (typical) will trip the OTP disabling
VR1, VR2 and the MOSFET drivers. When the temperature
decreases to +135°C (typical), the ISL1801 will restart.
When the VR1 output voltage feedback is higher than 120% of
VREF1, the PWM output will be tri-stated and at the same time
the PRELOAD current will be applied to VOUT1 to discharge the
output. When VOUT1 is discharged and FB1 reaches VREF1 the
OCP will turn off and normal PWM operation will resume.
When the VR2 output voltage feedback is higher than 120% of
VREF2, the PWM output will be tri-stated. After VOUT2 falls so that
FB2 is equal to VREF2 the OCP will turn off and normal PWM
operation will resume.
Overvoltage Protection
VR1 and VR2 include overvoltage protection (OVP):
Applications Information
Application Circuits
Lo
VIN+
VOUT+
PV
PANEL
Q1
Inverter /
Load
Rs
VIN-
VOUT-
GND
ISEN+
ISEN-
1
2
3
4
5
6
7
8
9
VOUT1
10
11
12
13
14
15
16
17
VOUT2
MCU
18
VOUT2
19
VOUT2
20
21
22
ISEN+
ISEN-
23
24
NC1
NC6
NC2
PGND1
VCC1
NC5
AGND
VIN1
OCSET3
NC4
NC3
PHASE1
PHASE3
BOOT1
PGND3
TIMER
DRIVE3
TON1
PVCC3
FB1
BDRIVE
PRELOAD
PGND4
GND
PWM3
RPWM3
BCMD
BRESET
WDI
VDDREF
LATCHRPT
PGOOD2
AMPO
AMPAMP+
SGND
VCC5V
ISL1801
48
47
46
45
VIN+
44
43
42
VOUT1
10V
VCC5V
41
40
39
38
37
36
35
VIN2
BOOT2 34
33
PHASE2
32
PGND2
31
TON2
30
FB2
29
CMP2+
28
CMP2CMP1O 27
CMP1- 26
VOUT2
3.3V
CMP1+ 25
FIGURE 28. BOOST REGULATOR
Submit Document Feedback
24
FN8259.1
July 24, 2014
ISL1801
Application Circuits (Continued)
VIN+
PV
PANEL
Load
Q1
Rs
VINISEN+
ISEN-
1
2
3
4
5
6
7
8
9
VOUT1
10
11
12
13
14
15
16
17
VOUT2
MCU
18
VOUT2
19
VOUT2
20
21
22
ISEN+
ISEN-
23
24
NC1
NC6
NC2
PGND1
VCC1
NC5
AGND
VIN1
OCSET3
NC4
NC3
PHASE1
PHASE3
BOOT1
PGND3
TIMER
DRIVE3
TON1
PVCC3
FB1
BDRIVE
PRELOAD
PGND4
GND
PWM3
RPWM3
BCMD
BRESET
WDI
VDDREF
LATCHRPT
PGOOD2
AMPO
AMPAMP+
SGND
VCC5V
ISL1801
48
47
46
45
VIN+
44
43
42
VOUT1
10V
VCC5V
41
40
39
38
37
36
35
VIN2
BOOT2 34
33
PHASE2
32
PGND2
31
TON2
30
FB2
29
CMP2+
28
CMP2CMP1O 27
CMP1- 26
VOUT2
3.3V
CMP1+ 25
FIGURE 29. FLY BACK REGULATOR
Submit Document Feedback
25
FN8259.1
July 24, 2014
ISL1801
Application Circuits (Continued)
VIN+
PV
PANEL
ISL2110
HI
HO
Q1
Half
Bridge
driver
LI
LO
Lo
VOUT+
Load
Q2
Rs
VINISEN+
ISEN-
1
2
3
4
5
6
7
8
9
VOUT1
10
11
12
13
14
15
16
17
VOUT2
MCU
18
VOUT2
19
VOUT2
20
21
22
ISEN+
ISEN-
23
24
NC1
NC6
NC2
PGND1
VCC1
NC5
AGND
VIN1
OCSET3
NC4
NC3
PHASE1
PHASE3
BOOT1
PGND3
TIMER
DRIVE3
TON1
PVCC3
FB1
BDRIVE
PRELOAD
PGND4
GND
PWM3
RPWM3
BCMD
BRESET
WDI
VDDREF
LATCHRPT
PGOOD2
AMPO
AMPAMP+
SGND
VCC5V
ISL1801
48
47
46
45
VIN+
44
43
42
VOUT1
10V
VCC5V
41
40
39
38
37
36
35
VIN2
BOOT2 34
33
PHASE2
32
PGND2
31
TON2
30
FB2
29
CMP2+
28
CMP2CMP1O 27
CMP1- 26
VOUT2
3.3V
CMP1+ 25
FIGURE 30. SYNCHRONOUS BUCK REGULATOR WITH EXTERNAL HALF BRIDGE DRIVER
Submit Document Feedback
26
FN8259.1
July 24, 2014
ISL1801
Application Circuits (Continued)
VIN+
VOUT+
PV
PANEL
ISL2110
ISL2110
HI
HO
LI
LO
ISEN-
Q3
Q1
Half
Bridge
driver
HO
Q2
HI
Half
Bridge
driver
Lo
Q4
LO
Load
LI
Rs
VINISEN+
ISEN-
1
2
3
4
5
6
7
8
9
VOUT1
10
11
12
13
14
15
16
17
VOUT2
MCU
18
VOUT2
19
VOUT2
20
21
22
ISEN+
ISEN-
23
24
NC1
NC6
NC2
PGND1
VCC1
NC5
AGND
VIN1
OCSET3
NC4
NC3
PHASE1
PHASE3
BOOT1
PGND3
TIMER
DRIVE3
TON1
PVCC3
FB1
BDRIVE
PRELOAD
PGND4
GND
PWM3
RPWM3
BCMD
BRESET
WDI
VDDREF
LATCHRPT
PGOOD2
AMPO
AMPAMP+
SGND
VCC5V
ISL1801
48
47
46
45
VIN+
44
43
42
VOUT1
10V
VCC5V
41
40
39
38
37
36
35
VIN2
BOOT2 34
33
PHASE2
32
PGND2
31
TON2
30
FB2
29
CMP2+
28
CMP2CMP1O 27
CMP1- 26
VOUT2
3.3V
CMP1+ 25
FIGURE 31. BUCK-BOOST REGULATOR WITH EXTERNAL HALF BRIDGE DRIVERS
PC Board Layout Guidelines
Careful PC board layout is critical to achieve minimal switching
losses and clean, stable operation. This is especially true when
multiple converters are on the same PC board where one circuit
can affect the other. For specific layout example of the
ISL1801EVAL1ZA evaluation board please contact Intersil sales
support with your needs.
Mount all of the power components on the top side of the board
with their ground terminals flush against one another, if possible.
Follow these guidelines for good PC board layout:
• Isolate the power components on the top side from the
sensitive analog components on the bottom side with a ground
shield. Use a separate PGND plane under the VOUT1 and VOUT2
sections (called PGND1 and PGND2). Avoid the introduction of
AC currents into the PGND1 and PGND2 ground planes. Run
the power plane ground currents on the top side only, if
possible.
Submit Document Feedback
27
• Use a star ground connection on the power plane to minimize
the crosstalk between VOUT1 and VOUT2.
• Keep the high-current paths short, especially at the ground
terminals. This practice is essential for stable, jitter-free
operation.
• Keep the power traces and load connections short. This practice
is essential for high efficiency. Using thick copper PC boards
(2oz vs 1oz) can enhance full-load efficiency by 1% or more.
Correctly routing PC board traces must be approached in terms
of fractions of centimeters, where a single mW of excess trace
resistance causes a measurable efficiency penalty.
• PHASE3 and GND connections to the synchronous rectifiers for
current limiting must be made using Kelvin-sense connections
to guarantee the current-limit accuracy. This is best done by
routing power to the MOSFETs from outside using the top
copper layer, while connecting PHASE traces inside
(underneath) the MOSFETs.
• When trade-offs in trace lengths must be made, it is preferable
to allow the inductor charging path to be made longer than the
FN8259.1
July 24, 2014
ISL1801
discharge path. For example, it is better to allow some extra
distance between the input capacitors and the high-side
MOSFET than to allow distance between the inductor and the
synchronous rectifier or between the inductor and the output
filter capacitor.
• Ensure that the OUT connection to COUT is short and direct.
However, in some cases it may be desirable to deliberately
introduce some trace length between the OUT connector node
and the output filter capacitor.
• Route high-speed switching nodes (BOOT, PHASE, DRIVE3 and
BDRIVE) away from sensitive analog areas (VDDREF, FB and
AMP±). Use PGND1 and PGND2 as an EMI shield to keep
radiated switching noise away from the IC's feedback divider
and analog bypass capacitors.
• Make all pin-strap control input connections to GND or VCC of
the device.
Layout Procedure
Place the power components first with ground terminals
adjacent. If possible, make all these connections on the top layer
with wide, copper-filled areas.
Mount the controller IC adjacent to the synchronous rectifier
MOSFETs close to the hottest spot, preferably on the back side in
order to keep DRIVE3, GND, and the BDRIVE gate drive lines
short and wide. The DRIVE3 gate trace must be short and wide,
measuring 50 mils to 100 mils wide if the MOSFET is 1” from the
controller device.
Submit Document Feedback
28
Group the gate-drive components (BOOT capacitor, VIN bypass
capacitor) together near the controller device.
Make the DC/DC controller ground connections as follows:
1. Near the device, create a small analog ground plane.
2. Connect the small analog ground plane to GND and use the
plane for the ground connection for the VDDREF and VCC
bypass capacitors, FB dividers and ILIM resistors (if any).
3. Create another small ground island for PGND and use the
plane for the VIN bypass capacitor, placed very close to the
device.
4. Connect the GND and PGND planes together under device.
On the board's top-side (power planes), make a star ground to
minimize crosstalk between the two sides. The top-side star
ground is a star connection of the input capacitors and
synchronous rectifiers. Keep the resistance low between the star
ground and the source of the synchronous rectifiers for accurate
current limit. Connect the top-side star ground (used for MOSFET,
input, and output capacitors) to the small island with a single
short, wide connection (preferably just a via). Create PGND
islands on the layer just below the top-side layer to act as an EMI
shield if multiple layers are available (highly recommended).
Connect each of these individually to the star ground via, which
connects the top-side to the PGND plane. Add one more solid
ground plane under the device to act as an additional shield, and
also connect the solid ground plane to the star ground via.
Connect the output power planes directly to the output filter
capacitor positive and negative terminals with multiple vias.
FN8259.1
July 24, 2014
ISL1801
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
July 24, 2014
FN8259.1
“Absolute Maximum Ratings” on page 7: changed BDRIVE, DRIVE3 Voltages from: -0.3V to VCC1+0.3V
BDRIVE, to:-0.3V to PVCC3+0.3V.
Updated description of pin VCC1 on page 4.
Updated Electrical Spec Tables.
June 29, 2012
FN8259.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
29
FN8259.1
July 24, 2014
ISL1801
Package Outline Drawing
M48.240
48 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 11/10
0.50
B
0.09-0.20
48
8.1
C
L
6.1±0.10
4
0.20 C A B
2X N/2 TIPS
123
PIN 1 ID
0.17-0.27
SEE
DETAIL "A"
0.08 M C A B 5
BOTTOM VIEW
TOP VIEW
A
1.10 MAX
0.90±0.05
0.05
(1.45)
C
12.50±0.10
0.05/0.15
4
0.10 C
SEATING
PLANE
(7.35)
SIDE VIEW
(12°) TYP
(1.00)
(46X 0.50)
(48X 0.28)
0.25
PARTING
LINE
TYPICAL RECOMMENDED LAND PATTERN
H 3
(0-8°)
0.6±0.15
DETAIL "A"
SCALE: (NONE)
(VIEW ROTATED 90° C.W.)
NOTES:
1. All dimensions are in millimeters (angles in degrees).
2. Dimensioning & tolerances per ASME. Y14.5m-1994.
3. Datum plane H located at mold parting line and coincident
with lead where lead exits plastic body at bottom of parting line.
4. At reference datum and does not include mold flash or protrusions,
and is measured at the bottom parting line. Mold flash or protrusions
shall not exceed 0.15mm on the package ends and 0.25mm between
the leads.
5. The lead width dimension does not include dambar protrusion.
Allowable dambar protrusion shall be 0.08mm total in excess of
the lead width dimension at maximum material condition. Dambar
cannot be located on the lower radius or the foot. Minimum space
between protrusions and an adjacent lead should be 0.07mm.
6. This part is compliant with JEDEC specification MO-153 variation
ED except it is 0.1mm thinner.
7. Dimensions in ( ) are for reference only.
Submit Document Feedback
30
FN8259.1
July 24, 2014
Similar pages