LTC2937 Programmable Six Channel Sequencer and Voltage Supervisor with EEPROM FEATURES DESCRIPTION Time and Event Based Sequencing n12 Programmable Undervoltage (UV) and Overvoltage (OV) Comparators: ±0.75% Accuracy n I2C/SMBus Interface n Stalled Power Supply Detection n Single Wire Synchronization Allows Controller Expansion to 50 Devices (300 Power Supplies) n Configuration and Fault Logging in EEPROM n EEPROM Specified over Entire Temperature Range, Rated to 85°C, 10k Writes, 20yr Retention n Supported by LTpowerPlay™ GUI n Fault and System Status Registers n Reset Output with Programmable Delay n Wide Input Supply Voltage Range: 2.9V to 16.5V n28-Lead QFN (5mm × 6mm) Package The LTC®2937 is a six-channel power supply sequencer and voltage supervisor. Supplies are enabled or disabled with precise user controlled order and time spacing. To detect power supply output faults during sequencing and monitoring, the LTC2937 accurately monitors supply turn-on/-off delays and output voltage levels. In the event of a fault, response actions include complete power supply shutdown and optional restarts. Root cause of power faults are logged to EEPROM. For systems with high supply count, a simple single wire connection between multiple LTC2937 devices allows sequencing expansion to 300 supplies. After successful sequencing and supply voltage stabilization, the reset output pulls high to initiate microprocessor or other system activity. To accommodate supply margin testing, the reset output can be disabled. Upon supply turn-off, integrated current sources are available as needed to discharge slowly decaying supplies. Configuration EEPROM supports autonomous operation without software. n APPLICATIONS n n n n Network Servers Data Storage Systems Telecom Equipment High Availability Computer Systems L, LT, LTC, LTM, Linear Technology, the Linear logo and PolyPhase are registered trademarks and LTpowerPlay is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 8627132. TYPICAL APPLICATION Six Power Supply Sequencer and Supervisor Sequenced Power Supply Waveforms DC/DC CONVERTERS SDA SCL ALERTB I2C/SMBus INTERFACE TO/FROM OTHER DEVICES R1 3.3k C1 2.2µF 5V VIN VPWR LTC2937 ON MARGB FAULTB RSTB SPCLK SHARE_CLK ASEL1 ASEL2 ASEL3 WP VDD GND EN1 EN2 EN3 EN4 EN5 EN6 RUN1 RUN2 RUN3 RUN4 RUN5 RUN6 GND OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 5.0V 3.3V 2.5V 1.8V 1.5V 1.2V 3.3V VOLTAGE 12V V1 V2 V3 V4 V5 V1 V2 V3 V4 V5 V6 2.5V 1.8V 1.5V 1.2V V6 ON TIME 2937 TAO1b 2937 TA01a 2937f For more information www.linear.com/LTC2937 1 LTC2937 TABLE OF CONTENTS Features...................................................... 1 Applications................................................. 1 Description.................................................. 1 Typical Application......................................... 1 Absolute Maximum Ratings............................... 3 Pin Configuration........................................... 3 Order Information........................................... 3 Electrical Characteristics.................................. 4 Serial Bus Timing Diagram............................... 7 Sequence-Up Threshold Timing Diagram............... 7 Sequence-Down Event Based Timing Diagram........ 8 Sequence-Down Time Based Timing Diagram......... 8 Typical Performance Characteristics.................... 9 Pin Functions............................................... 11 Block Diagram.............................................. 12 Operation................................................... 13 Slave Addresses...................................................... 14 I2C Interface............................................................ 15 Condensed Command Summary........................ 16 Command Descriptions................................... 17 WRITE_PROTECTION.............................................. 17 SPECIAL_LOT.......................................................... 17 ON_OFF_CONTROL.................................................. 18 V_RANGE................................................................ 19 V_THRESHOLD_n....................................................20 Voltage Threshold Encoding....................................20 TON_TIMERS_n....................................................... 21 TOFF_TIMERS_n......................................................22 SEQ_UP_POSITION_n.............................................23 SEQ_DOWN_POSITION_n....................................... 24 RSTB_CONFIG.........................................................25 FAULT_RESPONSE..................................................26 MONITOR_STATUS_HISTORY................................. 28 CLEAR_ALERTB......................................................29 STORE.....................................................................29 RESTORE.................................................................29 CLEAR.....................................................................29 STATUS_INFORMATION..........................................30 BREAK_POINT......................................................... 31 SEQ_POSITION_COUNT.......................................... 31 MONITOR_BACKUP................................................. 32 MONITOR_STATUS.................................................33 DEVICE_ID...............................................................33 Applications Information................................. 34 Introduction.............................................................34 Powering the LTC2937.............................................34 Write Protection.......................................................34 Updating Volatile or Non-Volatile Memory...............34 Sequence Position Clock (SPCLK)...........................35 System Configuration..............................................36 Sequence-Up and Sequence-Down Control.............36 Sequence-Up Parameters........................................ 37 Voltage Supervision................................................. 37 Voltage Monitor Range............................................ 37 UV and OV Thresholds.............................................38 UV Thresholds and Sequence-Up Hysteresis...........38 Selecting Resistors for Adjustable Range................38 OV Thresholds in Adjustable Applications............... 39 RSTB Response.......................................................40 Sequence-Down Parameters...................................40 Discharge Thresholds.............................................. 41 Active Supply Discharge.......................................... 41 Fault Descriptions.................................................... 42 CONTROL Faults...................................................... 42 SEQUENCE Faults.................................................... 42 SUPERVISOR Faults................................................ 42 EXTERNAL Faults.................................................... 42 SHARE_CLK Faults.................................................. 42 Fault Reporting........................................................43 Fault Management...................................................43 Fault Debugging Tools.............................................45 Share Clock (SHARE_CLK)......................................45 Asynchronous Supply Control.................................45 LTpowerPlay: An Interactive GUI for Power System Management............................................................46 External Connection Design Checklist.....................46 Minimum Connections for Programming................. 47 Interconnect Between Multiple LTC2937s................ 47 System Event Based Sequencing............................. 47 Package Description...................................... 49 Typical Application........................................ 50 Related Parts............................................... 50 2937f 2 For more information www.linear.com/LTC2937 LTC2937 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) V6 V5 V4 V3 V2 V1 TOP VIEW 28 27 26 25 24 23 MARGB 1 22 WP VPWR 2 21 SHARE_CLK VDD 3 20 SPCLK GND 4 19 SCL 29 ON 5 18 SDA ASEL1 6 17 RSTB ASEL2 7 16 FAULTB ASEL3 8 15 ALERTB EN6 EN5 EN4 EN3 EN2 9 10 11 12 13 14 EN1 VPWR......................................................... –0.3V to 18V EN1, EN2, EN3, EN4, EN5, EN6................... –0.3V to 16V VDD, ALERTB, FAULTB, MARGB, RSTB, ON, SCL, SDA, SHARE_CLK, SPCLK, WP, V1, V2, V3, V4, V5, V6................................... –0.3V to 6V ASEL1, ASEL2, ASEL3................................ –0.3V to VDD Input Currents V1, V2, V3, V4, V5, V6........................................–1mA Operating Junction Temperature Range LTC2937C................................................. 0°C to 70°C LTC2937I..............................................–40°C to 85°C Storage Temperature Range................... –65°C to 150°C Maximum Junction Temperature........................... 130°C UHE PACKAGE 28-LEAD (5mm × 6mm) PLASTIC QFN TJMAX = 130°C, θJA = 43°C/W EXPOSED PAD (PIN 29) PCB CONNECTION TO GND OPTIONAL ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2937CUHE#PBF LTC2937CUHE#TRPBF 2937 28-Lead (5mm × 6mm) Plastic QFN 0°C to 70°C LTC2937IUHE#PBF LTC2937IUHE#TRPBF 2937 28-Lead (5mm × 6mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2937f For more information www.linear.com/LTC2937 3 LTC2937 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C and VPWR = 12V. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Device Power VVPWR VPWR Supply Input Operating Range IVPWR VPWR Supply Current Sequencing Complete, No VDD Load Writing to EEPROM l l VDDREG VDD Regulated Output VPWR ≥ 4.5V, IVDD = –1mA l 3.234 VOP VDD Operating Range VDD Connected to VPWR l 2.9 VUVL VDD Undervoltage Lockout VDD Rising l 2.55 VUVL(HYST) VDD Undervoltage Lockout Hysteresis VDD Falling l 4.5 16.5 1 3 3.3 2.7 V mA mA 3.366 V 5.5 V 2.85 75 V mV V1, V2, V3, V4, V5, V6 VMON Vn Monitoring Thresholds (n = 1 through 6) (Note 3) Adjustable Range Low Range High Range VRES Vn Threshold Programming LSB Resolution Adjustable Range Low Range High Range VMON(ACC) Vn Threshold Accuracy by Code (Note 4) Threshold Codes 155 through 255 Threshold Codes 55 through 154 Threshold Codes 5 through 54 l l l Sequence Up Threshold Achieved l 2 LSB Overdrive of Configured Threshold 10 LSB Overdrive of Configured Threshold l VMON(HYST) Temporary Sequence-Up Threshold Hysteresis (Note 5) tPD Vn Comparator Propagation Delay l l l 0.2 0.5 1 1.2 3 6 4 10 20 –4 400 V V V mV mV mV ±0.75 ±0.75 ±1.5 % % % –5 –6 % 35 10 25 µs µs 800 kΩ ±10 nA RIN Vn Input Resistance Low Range and High Range l ILKG Vn Input Leakage Current Adjustable Range, V = 1.2V l 600 RON Vn Discharge On Resistance V = 0.4V l 25 40 50 Ω IAD(MAX) Vn Discharge Current V = 1.8V l 25 35 45 mA VDTH Vn Discharge Threshold High and Low Range Adjustable Range (Positive Polarity) Adjustable Range (Negative Polarity) l l l 300 50 1.12 400 120 1.2 500 190 1.28 mV mV V Retention (Notes 6, 7) l 20 10,000 EEPROM Years Cycles Endurance 1 Cycle = 1 STORE Command (Notes 6, 7) l tPT Programming Time (Note 8) STORE Command l 120 ms tRT Restore Time RESTORE Command l 2 ms Programmable Reset Delay (Register 0x22, RSTB_CONFIG) b[15:13] = 000b b[15:13] = 001b b[15:13] = 010b b[15:13] = 011b b[15:13] = 100b b[15:13] = 101b b[15:13] = 110b b[15:13] = 111b l l l l l l l l 0.1 1.8 7 29 56 220 450 1800 ms ms ms ms ms ms ms ms RSTB tRST 0 1.4 5.8 22 46 180 370 1480 0.05 1.6 6.4 26 51 200 410 1640 2937f 4 For more information www.linear.com/LTC2937 LTC2937 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C and VPWR = 12V. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Sequence Timers tON_MAX ton_max time (Registers 0x0A through 0x0F) b[15:13] = 000b b[15:13] = 001b b[15:13] = 010b b[15:13] = 011b b[15:13] = 100b b[15:13] = 101b b[15:13] = 110b b[15:13] = 111b l l l l l l l l ∞ 136 540 2.2 8.7 35 140 560 ∞ 160 640 2.6 10.2 41 164 655 ∞ 190 740 2.9 11.7 47 188 750 s µs µs ms ms ms ms ms tOND ton_delay Time (Registers 0x0A through 0x0F) Timer Register Value N = b[12:0] l 68 • N 80 • N 92 • N µs tOFF_MAX toff_max Time (Registers 0x10 through 0x15) b[15:13] = 000b b[15:13] = 001b b[15:13] = 010b b[15:13] = 011b b[15:13] = 100b b[15:13] = 101b b[15:13] = 110b b[15:13] = 111b l l l l l l l l ∞ 2.2 8.7 35 140 560 2.3 9 ∞ 2.6 10.2 41 164 655 2.6 10.5 ∞ 2.9 11.7 47 188 750 3 12 s ms ms ms ms ms s s tOFFD toff_delay Time (Registers 0x10 through 0x15) Timer Register Value N = b[12:0] l 68 • N 80 • N 92 • N µs SPCLK tONSQ ON Input to Start of SPCLK (Note 9) l 40 80 120 µs IPU SPCLK Pull-Up Current VSPCLK = GND l –30 –55 –80 µA tLO Minimum SPCLK Low Time l 16 20 24 µs tHI Minimum SPCLK High Time l 48 60 72 µs tFLOAT SPCLK Float High Time l 260 320 380 µs l 90 100 110 kHz l 1 1.2 1.4 V End of Sequencing SHARE_CLK fSHR Share Clock Frequency Analog and Digital I/O VTH Input Threshold: ON, MARGB, WP, RSTB, FAULTB, SHARE_CLK, SPCLK VTH(HYST) Input Threshold Hysteresis: ON, MARGB, WP, RSTB, FAULTB, SHARE_CLK, SPCLK VOL Voltage Output Low: ALERTB, RSTB, FAULTB, SHARE_CLK, SPCLK, EN1, EN2, EN3, EN4, EN5, EN6 ISINK = 3mA l IPU Internal Pull-Up Current: ON, MARGB, WP, ALERTB, RSTB, FAULTB V = GND l Leakage Current: ALERTB, RSTB, FAULTB Leakage Current: EN1, EN2, EN3, EN4, EN5, EN6 V = 5.5V V = 15V l l VOH Voltage Output High: ALERTB, RSTB, FAULTB ISOURCE = –1μA l VDD – 1 tPW Minimum Detectable Pulse Width: ON, FAULTB 50 l –4 25 mV 0.2 0.4 V –10 –16 µA ±1 ±1 µA µA V µs 2937f For more information www.linear.com/LTC2937 5 LTC2937 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C and VPWR = 12V. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Serial Bus Interface and Address Inputs VASEL(H) ASEL Input High Threshold l VDD – 0.4 VASEL(L) ASEL Input Low Threshold l VASEL(OC) ASEL Open Circuit Voltage V 0.4 0.5 • VDD VASEL(OCR) ASEL Allowable Open Circuit Voltage Range l 0.4 • VDD IASEL(HZ) Allowable Leakage in Open State l V V 0.6 • VDD V ±1 µA kΩ ASEL Input Resistance l 125 180 250 VSTH SDA, SCL Input Threshold l 1.5 1.8 2 V ISTH SDA, SCL Input Current SDA or SCL = 5.5V l 0 ±2 µA VSDA(OL) SDA Output Low Voltage ISDA = 3mA l 0.3 0.4 V 10 kHz Serial Bus Timing (Note 10) fSCL(MIN) Minimum Serial Clock Frequency l fSCL(MAX) Maximum Serial Clock Frequency l tLOW(MIN) Serial Clock Low Period l 1.3 µs tHIGH(MIN) Serial Clock High Period l 0.6 µs tBUF(MIN) Bus Free Time Between Stop and Start l 1.3 µs tHD,STA(MIN) Start Condition Hold Time l 600 ns tSU,STA(MIN) Start Condition Setup Time l 600 ns tSU,STO(MIN) Stop Condition Setup Time l 600 ns tHD,DAT(MIN) Data Hold Time tHD,DAT Data Hold Time (LTC2937 Receiving Data) l (LTC2937 Transmitting Data) l tSU,DAT(MIN) Data Setup Time l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive. All currents out of device pins are negative. All voltages are referenced to GND unless otherwise specified. Note 3: Subscript (or placeholder) n denotes a channel number and is applied throughout this document. Note 4: Threshold codes 0 through 4 are not used. Note 5: During sequence-up operation, undervoltage comparators participating in sequencing receive a temporary 5% hysteresis after the respective monitored voltage exceeds its threshold for the first time. The hysteresis remains active until 50% of the programmed reset delay time 400 300 kHz 0 ns 900 ns 100 ns has been completed. See the timing diagram and applications information for more details. Note 6: EEPROM endurance and retention are guaranteed by design, characterization and correlation with statistical process controls. Note 7: EEPROM endurance and retention will be degraded when TJ > 85°C. Note 8: The LTC2937 will not acknowledge any commands while a STORE command is being executed. Note 9: If multiple LTC2937s are in use, tONSQ can stretch indefinitely until all devices are ready to sequence. Note 10: Maximum capacitive load, CB, for SCL and SDA is 400pF. Data and clock rise time (tr) and fall time (tf) are: (20 + 0.1 • CB) (ns) < tr < 300ns and (20 + 0.1 • CB) (ns) < tf < 300ns. CB = capacitance of one bus line in pF. SCL and SDA external pull-up voltage, VIO, is 2.9V < VIO < 5.5V. 2937f 6 For more information www.linear.com/LTC2937 LTC2937 SERIAL BUS TIMING DIAGRAM SDA tLOW tf tf tSU:DAT tr tHD:STA tf tSP tBUF SCL tHD:STA S tHD:DAT tHIGH tSU:STA Sr tSU:STO P S 2937 TD1 SEQUENCE-UP THRESHOLD TIMING DIAGRAM Sequencing 2 Channels (V1, V2), Both Combined into RSTB Logic tRT VDD ON IGNORED tONSQ tHI tLO tFLOAT SPCLK EN1 V1MON(UV) V1MON(HYST) V1 EN2 V2MON(UV) V2MON(HYST) 0.5 • tRST V2 tRST RSTB 2937 TD02 2937f For more information www.linear.com/LTC2937 7 LTC2937 SEQUENCE-DOWN EVENT BASED TIMING DIAGRAM Sequencing 2 Channels (V1, V2), Both Combined into RSTB Logic ON tONSQ tHI tLO tFLOAT SPCLK EN1 V1 V1MON(UV) V1DTH EN2 V2 V2 DTH RSTB 2937 TD03 SEQUENCE-DOWN TIME BASED TIMING DIAGRAM Sequencing 2 Channels (V1, V2), Both Combined into RSTB Logic. toff_max Timers Used for Post Disable Sequencing Delay; ON_OFF_CONTROL b[0] = 1 ON tONSQ tHI tLO tFLOAT SPCLK toff_max_1 EN1 V1 EN2 V1MON(UV) toff_max_2 RSTB 2937 TD04 2937f 8 For more information www.linear.com/LTC2937 LTC2937 TYPICAL PERFORMANCE CHARACTERISTICS VPWR Input Current (Regulated VDD) Input Current (VDD tied to VPWR) 1000 –40°C 25°C 85°C 700 600 800 400 400 6 8 10 12 VVPWR (V) 14 16 3.32 600 500 3.30 3.28 3.26 300 2.5 18 3 2937 G01 3.5 4 4.5 VOP (V) 5 5.5 3.24 6 6 8 10 12 VVPWR (V) 14 16 18 2937 G03 Comparator Threshold Accuracy vs Temperature 3.36 1 –40°C 25°C 85°C 3.34 0.75 VDD 50mV/DIV 0.5 VMON(ACC) (%) 3.32 VDDREG (V) 4 2937 G02 VDD Load Step Transient Response VDD Load Regulation –40°C 25°C 85°C 3.34 700 500 4 –40°C 25°C 85°C VDDREG (V) IVPWR (µA) 800 3.36 900 IVPWR + IVDD (µA) 900 300 VDD Line Regulation 1000 3.30 LOAD STEP 2mA/DIV 3.28 0.25 0 –0.25 –0.5 3.26 0 –1 –2 –3 IVDD (mA) –4 –1 –50 –5 Timer Variation vs Temperature 15 10 30 TIMER VARIATION (%) GLITCH DURATION (µs) 35 GLITCHES ABOVE CURVE ARE DETECTED 20 15 10 0 10 THRESHOLD OVERDRIVE (LSBs) 100 2937 G07 75 100 Timer Line Regulation 15 ton_max, ton_delay, toff_max, toff_delay 10 5 0 –5 –10 GLITCHES BELOW CURVE ARE IGNORED 1 0 25 50 TEMPERATURE (°C) 2937 G06 Comparator Glitch Immunity 5 –25 2937 G04 40 25 –0.75 TIMER VARIATION (%) 3.24 2937 G05 50ms/DIV –15 –50 ton_max, ton_delay, toff_max, toff_delay 5 0 –5 –10 –25 0 25 50 TEMPERATURE (°C) 75 100 2937 G08 –15 2.5 3 3.5 4 4.5 VOP (V) 5 5.5 6 2937 G09 2937f For more information www.linear.com/LTC2937 9 LTC2937 TYPICAL PERFORMANCE CHARACTERISTICS VOL vs Output Sink Current RSTB, FAULTB, ALERTB 1 1 –40°C 25°C 85°C 0.4 0.2 0 10 CURRENT (µA) 0.6 ASELn Current vs Input Voltage 20 –40°C 25°C 85°C 0.8 VOL (V) VOL (V) 0.8 ENn VOL vs Output Sink Current 0.6 0.4 2 4 6 CURRENT (mA) 8 0 10 0 2 4 6 CURRENT (mA) 8 0 –20 10 2937 G10 0 1 2 3 VASEL (V) 2937 G11 SHARE_CLK Frequency vs Temperature SHARE_CLK Frequency Line Regulation 110 VDD = 5V –10 0.2 0 VDD = 3.3V 4 5 2937 G12 Reset Delay Variation vs Temperature 10 15 FREQUENCY VARIATION (%) FREQUENCY (kHz) 106 104 102 100 98 96 94 RESET TIMEOUT VARIATION (%) 108 5 0 –5 10 5 0 –5 –10 92 90 –50 –25 0 25 50 TEMPERATURE (°C) 75 –10 2.5 100 3 2937 G13 Active Discharge Current vs Monitor Input Voltage 5 5.5 –15 –50 6 –25 0 25 50 TEMPERATURE (°C) 75 2937 G14 100 2937 G15 RSTB (Low) vs VDD 15 1 10k PULL-UP FROM VDD TO RSTB 35 10 20 15 10 0.8 5 RSTB (V) 25 VDTH VARIATION (%) –40°C 25°C 85°C 30 IAD (mA) 4 4.5 VOP (V) Discharge Threshold Variation vs Temperature 40 0 0 1 2 3 VMON (V) 4 5 6 2937 G16 0.6 0.4 –5 0.2 –10 5 0 3.5 –15 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 2937 G17 0 0 0.5 1 1.5 VDD (V) 2 2.5 3 2937 G18 2937f 10 For more information www.linear.com/LTC2937 LTC2937 PIN FUNCTIONS ALERTB: Alert Open-Drain Output with 10µA Pull-Up to VDD. Asserts low in response to any designated fault. Conforms to SMBus standard. Apply the Alert Response Protocol to clear the ALERTB output and to identify the alerting device. Performing a read from the CLEAR_ALERTB register will also remove ALERTB pull-down. ASEL1, ASEL2, ASEL3: Three-State Address-Select Inputs. Connect to GND, VDD or open to encode 1 of 27 device addresses. Consult the Operation section for the address look-up table. EN1, EN2, EN3, EN4, EN5, EN6: Power Supply Enable Outputs. Connect these open-drain outputs to a respective power supply enable input or to a gate of an N-channel MOSFET (for pass applications). The enable outputs must be pulled up externally (to a maximum of 15V) if necessary. Some power supply enable inputs have internal pull-up sources, which eliminates the need for an external pull-up. Exposed Pad: Leave open or connect to device GND. FAULTB: Fault I/O with 10µA Pull-Up to VDD. Asserts low in response to any designated fault. Configure fault behavior in the FAULT_RESPONSE register. External devices may also pull down on FAULTB to initiate an optional fault response. GND: Device Ground. MARGB: Margin Input. Pull to ground to disable RSTB and prevent SUPERVISOR faults. Typically applied prior to margining supplies high or low during system test. Leave open or pull to VDD when not margining. ON: Sequencing Up/Down Control Input. ON input response is gated by settings in the ON_OFF_CONTROL register. Internally pulled up to VDD with 10µA current source. RSTB: Reset I/O with 10µA Pull-Up to VDD. Pulls low in response to designated voltage comparator violations. Pulls high when selected voltage sense thresholds are satisfied (ie not UV and/or not OV), and can be used as a system power-on-reset. The reset assertion delay after satisfying thresholds is programmable. May be pulled low by external devices and detected with b[12] of the MONITOR_STATUS command. SCL: Serial Clock Input (400kHz Maximum). Requires external pull-up resistor. SDA: Bi-Directional Serial Data I/O. Requires external pull-up resistor. SHARE_CLK: Clock Sharing Node. Connect multiple SHARE_CLK nodes together to establish a common time base between devices. Pull-up with a 3.3k to 10k resistor to VDD. SPCLK: Sequence Position Clock I/O. Connect multiple LTC2937 SPCLK lines together for automatic sequence position control between devices. Pull-up devices are not recommended. Leave unconnected in a single device application. Minimize capacitance on this line to ensure reliable operation. V1, V2, V3, V4, V5, V6: Undervoltage, Overvoltage and Discharge Comparator Inputs. There are three sense ranges. Adjustable: 0.2V to 1.2V in 4mV increments, Low: 0.5V to 3V in 10mV increments, and High: 1V to 6V in 20mV increments. When monitored supplies are shut off, internal pull-down current sources can be activated to accelerate the discharge of supply capacitance. Connect to device GND if unused. VDD: 3.3V Internal Regulator Output. Bypass with a 2.2µF (or greater) capacitor to GND. Use this output to bias the address inputs or an external resistor network for sensing negative supply voltages. Do not load the regulated output with more than 5mA. Override the regulated output with an external supply (2.9V to 5.5V) connected to VPWR and VDD. VPWR: Supply Voltage Input. Power supply operating range is 4.5V to 16.5V. Tie to VDD if unused. Bypass with 0.1µF (or greater) capacitor to GND. WP: Write Protection Input. Pull to GND to enable write capability into the device. Leave open or tie to VDD to keep write protection active. The software controlled lock bit in the WRITE_PROTECTION register may also need deactivation to enable write capability. 2937f For more information www.linear.com/LTC2937 11 LTC2937 BLOCK DIAGRAM VPWR EN1 LDO UVLO VDD EN2 VDD CHANNEL 1 EN3 + OV EN4 – EN5 ADJPOL V1 – 30mA + EN6 UV ADJPOL REF 10µA RSTB 10µA FAULTB 10µA ALERTB 50µA SPCLK VDD GND + VDD DISCH – V2 V3 V4 V5 V6 LOGIC CHANNEL 2 VDD CHANNEL 3 VDD CHANNEL 4 SHARE_CLK CHANNEL 5 CHANNEL 6 SCL 10µA VDD MARGB SDA 10µA VDD WP VDD 10µA ON EEPROM AND REGISTERS SERIAL PORT INTERFACE ASEL1 ASEL2 OSC VDD ASEL3 2937f 12 For more information www.linear.com/LTC2937 LTC2937 OPERATION The LTC2937 is a six-channel programmable power supply sequencer and supervisor that can perform the following operations: • Control the timing relationships and sequence order for six power supplies per device. Sequence supplies on the basis of time delays and/or qualifying events. • Monitor power supplies for undervoltage (UV) and overvoltage (OV) conditions using two independent comparators on each of six inputs. • Generate a system reset that is a function of user selected inputs with a programmable release delay. • Synchronize sequencing across multiple controllers with a one wire connection (SPCLK). • Synchronize timing across multiple controllers with a one wire connection (SHARE_CLK). • Discharge slowly decaying supplies with built-in pulldown current sources. • Monitor power supplies for discharge condition using the discharge comparators. • Accept I2C/SMBus programming commands. • Initiate supply sequencing from an external source and/ or programming command. • Retrieve real-time system status. • Generate a fault related interrupt on the ALERTB output and respond to an issued SMBus Alert Response. • Respond to fault conditions by continuing operation indefinitely or disabling supplies immediately. Optionally, sequencing may be retried multiple times automatically (0 to 6 or unlimited) after a supply shutdown event. • Report voltage and/or timing limit violations upon request. • Pause sequencing operations to help identify system power problems. • Store system configuration to EEPROM. • Restore EEPROM contents to operating memory through programming or when VDD is applied on power-up. • Recall first fault violations logged to EEPROM. • EEPROM reads and writes over the entire specified supply voltage and temperature range. • Provide two stage write protection to prevent inadvertent writes to memory. • Disable system reset when performing voltage margining of supplies. • Monitor negative power supplies. 2937f For more information www.linear.com/LTC2937 13 LTC2937 OPERATION Slave Addresses The LTC2937 responds to one of 27 addresses. Connect the ASEL1, ASEL2 and ASEL3 inputs to VDD, GND, or leave open, as shown in Table 1. The LTC2937 always responds to the Global and Alert Response addresses regardless of the ASEL input states. The ASEL inputs are always active and operate in real time. Table 1. LTC2937 Address Look-Up Table DESCRIPTION HEX DEVICE ADDRESS BINARY DEVICE ADDRESS ADDRESS INPUTS 7-Bit 8-Bit 6 5 4 3 2 1 0 R/W ASEL3 ASEL2 ASEL1 Alert Response 0C 19 0 0 0 1 1 0 0 1 X X X Global 36 6C 0 1 1 0 1 1 0 0 X X X 37 6E 0 1 1 0 1 1 1 X L L L 38 70 0 1 1 1 0 0 0 X L L NC 39 72 0 1 1 1 0 0 1 X L L H 3A 74 0 1 1 1 0 1 0 X L NC L 3B 76 0 1 1 1 0 1 1 X L NC NC 3C 78 0 1 1 1 1 0 0 X L NC H 3D 7A 0 1 1 1 1 0 1 X L H L 3E 7C 0 1 1 1 1 1 0 X L H NC 3F 7E 0 1 1 1 1 1 1 X L H H 40 80 1 0 0 0 0 0 0 X NC L L 41 82 1 0 0 0 0 0 1 X NC L NC 42 84 1 0 0 0 0 1 0 X NC L H 43 86 1 0 0 0 0 1 1 X NC NC L 44 88 1 0 0 0 1 0 0 X NC NC NC 45 8A 1 0 0 0 1 0 1 X NC NC H 46 8C 1 0 0 0 1 1 0 X NC H L 47 8E 1 0 0 0 1 1 1 X NC H NC 48 90 1 0 0 1 0 0 0 X NC H H 49 92 1 0 0 1 0 0 1 X H L L 4A 94 1 0 0 1 0 1 0 X H L NC 4B 96 1 0 0 1 0 1 1 X H L H 4C 98 1 0 0 1 1 0 0 X H NC L 4D 9A 1 0 0 1 1 0 1 X H NC NC 4E 9C 1 0 0 1 1 1 0 X H NC H 4F 9E 1 0 0 1 1 1 1 X H H L 50 A0 1 0 1 0 0 0 0 X H H NC 51 A2 1 0 1 0 0 0 1 X H H H H = Tie to VDD, L = Tie to GND, NC = No Connect = Open, X = Don’t Care 2937f 14 For more information www.linear.com/LTC2937 LTC2937 OPERATION I2C Interface S START CONDITION Sr REPEATED START CONDITION Rd READ (BIT VALUE OF 1) Wr WRITE (BIT VALUE OF 0) x SHOWN UNDER A FIELD INDICATES THAT THAT FIELD IS REQUIRED TO HAVE THE VALUE OF x A ACKNOWLEDGE A NOT ACKNOWLEDGE P STOP CONDITION MASTER TO SLAVE SLAVE TO MASTER 2937 F01 Figure 1. Serial Bus Protocol Diagram Element Key 1 S 1 1 SLAVE ADDRESS Wr A COMMAND CODE A 7 1 1 8 P 2937 F02 Figure 2. Send Byte Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 1 DATA BYTE LOW A DATA BYTE HIGH A P 2937 F03 Figure 3. Write Word Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 1 7 1 1 Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 1 1 DATA BYTE HIGH A 8 P 2937 F04 Figure 4. Read Word Protocol 1 S 1 1 SLAVE ADDRESS Rd A DEVICE ADDRESS A 7 1 1 8 P 0001100 2937 F05 Figure 5. Alert Response Protocol 2937f For more information www.linear.com/LTC2937 15 LTC2937 CONDENSED COMMAND SUMMARY ON/OFF Commands COMMAND NAME ON_OFF_CONTROL CMD CODE DESCRIPTION 0x02 ON input and/or I2C directed sequence up/down control settings. WORD EEPROM TYPE LENGTH CAPACITY REF (Note 11) (BITS) (BITS) PAGE R/W 16 16 18 Sequencing-Up Configuration Commands SEQ_UP_POSITION_n 0x16 – 0x1B Sequence-up position for EN1 through EN6. Asynchronous enable controls. R/W 16 16 23 TON_TIMERS_n 0x0A – 0x0F Encode ENn delay time and maximum rise time for Vn. R/W 16 16 21 R/W 16 16 19 Voltage Supervisor Commands V_RANGE V_THRESHOLD_n 0x03 Encode Vn comparator ranges and Adjustable Range polarity. R/W 16 16 20 Select comparator outputs for combination into RSTB response. Select RSTB assertion delay. R/W 16 16 25 SEQ_DOWN_POSITION_n 0x1C – 0x21 Sequence-down position for EN1 through EN6. Active discharge select for V1 through V6. R/W 16 16 24 TOFF_TIMERS_n 0x10 – 0x15 Encode ENn delay time and maximum fall time for Vn. R/W 16 16 22 RSTB_CONFIG 0x04 – 0x09 Encode high and low thresholds for Vn. 0x22 Sequencing-Down Configuration Commands Fault, Status and Debugging Commands FAULT_RESPONSE 0x23 Configure fault response actions. R/W 16 16 26 STATUS_INFORMATION 0x29 Summary of current device faults and status. R 16 0 30 MONITOR_STATUS_HISTORY 0x26 History of voltage monitor violations, SUPERVISOR faults and SEQUENCE faults. R 16 0 28 MONITOR_BACKUP 0x2F An EEPROM copy of the MONITOR_STATUS_HISTORY word after the first SUPERVISOR or SEQUENCE fault. R 16 16 32 MONITOR_STATUS 0x30 Live voltage monitor and RSTB status. R 16 0 33 SEQ_POSITION_COUNT 0x2B Sequence position counter. BREAK_POINT 0x2A Enable and configure sequencing break points. R 16 0 31 R/W 16 0 31 CLEAR 0x2E Clear all status, fault and volatile history information. S 0 0 29 CLEAR_ALERTB 0x28 Clear the ALERTB output by performing a read from this command address. The returned word contains no information. R 16 0 29 Contains lock key code and software lock bit to prevent accidental overwrites of volatile and non-volatile memory. Status of WP input. R/W 16 16 17 Security and Device Information Commands WRITE_PROTECTION 0x00 STORE 0x2C Store device configuration to EEPROM. S 0 0 29 RESTORE 0x2D Restore device configuration from EEPROM. S 0 0 29 SPECIAL_LOT 0x01 Contains customer specific codes that identify the factory programmed configuration stored in EEPROM. Use as a scratchpad if customer codes are not applied. R/W 16 16 17 DEVICE_ID 0x31 Read only. Contains 0x2937. R 16 0 33 Note 11: R = read, W = write, S = send byte. 2937f 16 For more information www.linear.com/LTC2937 LTC2937 COMMAND DESCRIPTIONS WRITE_PROTECTION (Command Byte 0x00) Prevent write operations into EEPROM or volatile memory with the software lock bit b[0] = 1 and/or hardware lock bit b[1] = 1. Deactivate the software lock bit by matching the device key string in b[15:2] while b[1:0] = 00b. Retrieve the state of the external hardware lock input (WP) in b[1]. Improve write security by having at least one bit in the device key set to logic 1. Change the device key if desired, when the device is unlocked. The contents of any supported command may be read regardless of the lock bit settings. Commands are acknowledged under write protection. However, the device configuration will not change. WRITE_PROTECTION Data Contents BIT(S) SYMBOL OPERATION b[15:2] device_key Must match against programmed string in order to deactivate software write lock (default = 0x0EAA). b[1] hw_lock_bit WP input status. 0: Unlocked. 1: Locked. b[0] sw_lock_bit Software lock bit. 0: Unlocked. 1: Locked (default). SPECIAL_LOT (Command Byte 0x01) Read the SPECIAL_LOT register to retrieve a customer specific code that identifies the factory programmed configuration stored in EEPROM. Use as a scratchpad if customer codes are not applied. Contact LTC Marketing to request a custom factory programmed configuration and special lot number. The default value is 0x0000. 2937f For more information www.linear.com/LTC2937 17 LTC2937 COMMAND DESCRIPTIONS ON_OFF_CONTROL (Command Byte 0x02) Configure the combination of ON input and/or I2C inputs needed to control sequencing. Activate margin mode operation using b[6] or the external MARGB input. Specify time or event based sequence-down qualification. Prevent sequenceup initiation if supplies selected for sequencing are not discharged. ON_OFF_CONTROL Data Contents BIT(S) SYMBOL OPERATION b[15:8] reserved Ignore. b[7] on_state Internal ON status. Representation of the ON input logically modified by the b[5:1] directives below and/or freeze mode bit b[8] from FAULT_RESPONSE (read only). 0: Internal ON is low. 1: Internal ON is high. b[6] i2c_margin b[5] discharge_start b[4] i2c_on_off b[3] i2c_on_off_mask Serial bus on/off control mask. 0: Ignore b[4]. If b[3] and b[2] are low, device is in sequence down state (default). 1: Listen to b[4]. If b[2] is high, the ON input is also required to initiate sequencing. b[2] on_input_mask ON input mask. 0: Ignore the ON input. Sequencing control directed by b[4] if not masked (default). 1: Listen to ON input. b[1] on_polarity b[0] seq_down_qual RSTB disable used during supply margining. 0: RSTB operates normally (default). 1: RSTB is allowed to pull high. Sequenced supply discharge threshold qualification. 0: Discharged supplies not required to start sequence-up (default). 1: Discharged supplies required to start sequence-up. Serial bus directed sequence on/off control. 0: Sequence down (default). 1: Sequence up. Invert ON input logical state. Changing polarity should be performed with b[2] low because the response is immediate and could initiate a sequencing event. 0: Sequence up with ON input at logic high (default). 1: Sequence up with ON input at logic low. Select time or event based sequence down. 0: Event based. Sequence position clock (SPCLK) advances when supplies drop below their discharge threshold (default). 1: Time based. Sequence position clock (SPCLK) advances when respective toff_max time has elapsed, including any preceding toff_delay time (if timer set to infinity, operation defaults to voltage decay mode). 2937f 18 For more information www.linear.com/LTC2937 LTC2937 COMMAND DESCRIPTIONS V_RANGE (Command Byte 0x03) Select the operating threshold range for each of the six voltage monitor inputs. The range selection applies to the OV and UV comparators connected to each input. The High Range covers thresholds between 1V and 6V in 20mV steps. The Low Range covers thresholds between 0.5V and 3V in 10mV steps. The Adjustable Range covers 0.2V to 1.2V in 4mV steps. Select the negative polarity option in the Adjustable Range when sensing negative voltages. Discharge comparator threshold and polarity adjusts automatically in response to the configured range selection. V_RANGE Data Contents BIT(S) SYMBOL OPERATION b[15:12] reserved Ignore. b[11:10] v6_range Select V6 range. 00b: High Range (default). 01b: Low Range. 10b: Adjustable Range (positive polarity). 11b: Adjustable Range (negative polarity). b[9:8] v5_range Select V5 range. 00b: High Range (default). 01b: Low Range. 10b: Adjustable Range (positive polarity). 11b: Adjustable Range (negative polarity). b[7:6] v4_range Select V4 range. 00b: High Range. 01b: Low Range (default). 10b: Adjustable Range (positive polarity). 11b: Adjustable Range (negative polarity). b[5:4] v3_range Select V3 range. 00b: High Range. 01b: Low Range (default). 10b: Adjustable Range (positive polarity). 11b: Adjustable Range (negative polarity). b[3:2] v2_range Select V2 range. 00b: High Range. 01b: Low Range (default). 10b: Adjustable Range (positive polarity). 11b: Adjustable Range (negative polarity). b[1:0] v1_range Select V1 range. 00b: High Range. 01b: Low Range (default). 10b: Adjustable Range (positive polarity). 11b: Adjustable Range (negative polarity). 2937f For more information www.linear.com/LTC2937 19 LTC2937 COMMAND DESCRIPTIONS (Note 3) V_THRESHOLD_n n 1 2 3 4 5 6 Command Byte 0x04 0x05 0x06 0x07 0x08 0x09 Program the OV and UV thresholds for each of the six voltage monitor inputs. V_THRESHOLD_n Data Contents BIT(S) SYMBOL OPERATION b[15:8] ov_threshold_n Encode one of 250 thresholds (0x05 through 0xFF). See below for voltage threshold encoding (TE) procedure. b[7:0] uv_threshold_n Encode one of 250 thresholds (0x05 through 0xFF). See below for voltage threshold encoding (TE) procedure. Voltage Threshold Encoding Depending on the selected voltage range, threshold encoding (TE) is determined as follows: For the high input range of 1V to 6V, the equation is: TE = ROUND[50 • (VMON – 0.9)] For the low input range of 0.5V to 3V, the equation is: TE = ROUND[100 • (VMON – 0.45)] For the high impedance adjustable input range of 0.2V to 1.2V, the equation is: TE = ROUND[250 • (VMON – 0.18)] As an example, consider the channel 1 Low Range defaults from the table below (ov_threshold_1 = 1.32V, uv_threshold_1 = 1.08V). The threshold encodings (TE) are therefore: TEOV = ROUND[100 • (1.32 – 0.45)] = ROUND[100 • (0.87)] = 87 (0x57) TEUV = ROUND[100 • (1.08 – 0.45)] = ROUND[100 • (0.63)] = 63 (0x3F) The16-bit word contained in the V_THRESHOLD_1 register (0x573F) is formed from the simple concatenation of the OV and UV hexadecimal values. Factory Defaults n RANGE VMON(OV) VMON(UV) TEOV TEUV 1 Low 1.32 V 1.08 V 0x57 0x3F 2 Low 1.65 V 1.35 V 0x78 0x5A 3 Low 1.98 V 1.62 V 0x99 0x75 4 Low 2.75 V 2.25 V 0xE6 0xB4 5 High 3.63 V 2.97 V 0x89 0x68 6 High 5.5 V 4.5V 0xE6 0xB4 2937f 20 For more information www.linear.com/LTC2937 LTC2937 COMMAND DESCRIPTIONS (Note 3) TON_TIMERS_n n 1 2 3 4 5 6 Command Byte 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F The TON_TIMER registers encode the enable delay time and the maximum allowable rise time per channel in one 16-bit word. The lowest thirteen bits (ton_delay) determine the amount time delay between the beginning of the programmed sequence position (determined by the SEQ_UP_POSITION_n command) and the release of the respective ENn output (in 80µs increments). The upper three bits (ton_max) determine the amount of time that is allowed to elapse between the release of ENn and the voltage at the respective Vn input reaching its UV threshold. Failing this test can cause a sequence-up fault depending on the FAULT_RESPONSE settings. A setting of ∞ defeats time checking during the sequence-up phase for the respective channel (sequencing will pause indefinitely until the UV threshold is crossed). TON_TIMERS_n Data Contents BIT(S) SYMBOL b[15:13] ton_max_n b[12:0] ton_delay_n OPERATION Maximum rise time selection. Defined as the maximum time allowed between ENn release and successful crossing of UV threshold at the Vn input. b[15:13] ton_max 000b ∞ (default) 001b 160µs 010b 640µs 011b 2.6ms 100b 10.2ms 101b 41ms 110b 164ms 111b 655ms Time delay from start of selected sequence position to enable (ENn) release. ton_delay = 80 • N µs, where N is a 13-bit unsigned integer in b[12:0]. Delay range is from 0ms to 655ms. The default setting for b[12:0] = 0. 2937f For more information www.linear.com/LTC2937 21 LTC2937 COMMAND DESCRIPTIONS (Note 3) TOFF_TIMERS_n n 1 2 3 4 5 6 Command Byte 0x10 0x11 0x12 0x13 0x14 0x15 The TOFF_TIMER registers encode the disable delay time and the maximum allowable fall time per channel in one 16-bit word. The lowest thirteen bits (toff_delay) determine the amount time delay between the beginning of the programmed sequence position (determined by the SEQ_DOWN_POSITION_n command) and the pull-down of the respective ENn output (in 80µs increments). The upper three bits (toff_max) determine the amount of time that is allowed to elapse between the pull-down of ENn and the voltage at the respective Vn input falling below its discharge threshold. Failing this test can cause a sequencedown fault depending on the FAULT_RESPONSE settings. A setting of ∞ defeats time checking during the sequencedown phase for the respective channel (sequencing will pause indefinitely until the monitored voltage decays below its discharge threshold). Sequence-down progress may also be gated by time instead of voltage decay. Choose the time based mode of operation with b[0] = 1 in the ON_OFF_CONTROL register. Use the toff_max settings below to set the time from ENn pulling low to the start of next sequence position. If multiple channels occupy the same sequence position, the longest combined time (toff_delay_n + toff_max_n) determines the sequence position hold time. In time delay mode, a toff_max setting of ∞ defaults operation to voltage decay mode. TOFF_TIMERS_n Data Contents BIT(S) SYMBOL b[15:13] toff_max_n b[12:0] toff_delay_n OPERATION Maximum fall time selection. Defined as the maximum time allowed between ENn pull-down and successful crossing of the discharge threshold at the Vn input. b[15:13] toff_max 000b ∞ (default) 001b 2.6ms 010b 10.2ms 011b 41ms 100b 164ms 101b 655ms 110b 2.6s 111b 10.5s Time delay from start of selected sequence position to enable (ENn) pull-down. toff_delay = 80 • N µs, where N is the 13-bit unsigned integer in b[12:0]. The default setting for b[12:0] = 0. 2937f 22 For more information www.linear.com/LTC2937 LTC2937 COMMAND DESCRIPTIONS (Note 3) SEQ_UP_POSITION_n n 1 2 3 4 5 6 Command Byte 0x16 0x17 0x18 0x19 0x1A 0x1B Program the sequence position in which the respective enable output is allowed to pull high. Select from 1023 positions (1 through 1023) controlled by the sequence position clock (SPCLK) connected to all LTC2937s. Sequence-up positions may be different from the respective sequence-down positions. Any and all enable outputs may operate in any sequence position. If b[9:0] are set equal to 0, the respective channel is not participating and is ignored during sequencing up and down. A setting of zero enables the asynchronous on/off bit providing immediate enable output response. If the asynchronous on/off bit is in use, the respective channel does not participate in sequencing events but the respective UV/OV monitor conditions may be included in the RSTB response. Unused sequence positions add an 80µs space (tHI + tLO) between configured sequence positions. SPCLK self terminates after the last used sequence position. SEQ_UP_POSITION_n Data Contents BIT(S) SYMBOL OPERATION b[15:11] reserved Ignore. b[10] async_on_off_n b[9:0] seq_up_position_n Asynchronous enable control. Release or pull-down the respective enable output immediately provided that b[9:0] = 0. 0: Pull down ENn immediately (default). 1: Release ENn immediately. Specify a sequence-up position from 1 to 1023. If b[9:0] = 0, the channel does not participate in sequencing operations. Default b[9:0] = 0x001 (position 1). 2937f For more information www.linear.com/LTC2937 23 LTC2937 COMMAND DESCRIPTIONS (Note 3) SEQ_DOWN_POSITION_n n 1 2 3 4 5 6 Command Byte 0x1C 0x1D 0x1E 0x1F 0x20 0x21 Program the sequence position in which the respective enable output is pulled down. Select from 1023 positions (1 through 1023) controlled by the sequence position clock (SPCLK) connected to all LTC2937s. Sequence-down positions may be different from the respective sequence-up positions. Any and all enable outputs may operate in any sequence position. If b[9:0] are set equal to 0, the respective channel is not participating and is ignored during sequencing down and up. Selectively configure Vn inputs to receive current source pull-down when respective enable outputs are low. The active pull-down can be used to reduce power supply discharge time. Unused sequence positions add an 80µs space (tHI + tLO) between configured sequence positions. SPCLK self terminates after the last used sequence position. SEQ_DOWN_POSITION_n Data Contents BIT(S) SYMBOL OPERATION b[15:11] reserved Ignore. b[10] active_pull_down_n Apply pull-down current source to respective Vn inputs to reduce power supply discharge time. If enabled, the source is active when the respective ENn output is low. 0: Active pull-down disabled (default). 1: Active pull-down enabled. b[9:0] seq_down_position_n Specify a sequence-down position from 1 to 1023. If b[9:0] = 0, the channel does not participate in sequencing operations. Default b[9:0] = 0x001 (position 1). 2937f 24 For more information www.linear.com/LTC2937 LTC2937 COMMAND DESCRIPTIONS RSTB_CONFIG (Command Byte 0x22) Select the RSTB assertion delay. Select UV and OV comparator outputs for combination into the RSTB output. If no comparators are included, the RSTB output assertion delay is gated only by the device’s internal undervoltage lockout condition. After sequencing up has commenced, SUPERVISOR faults may optionally cause device faults (set with b[12]). Consult the Applications Information for a complete discussion regarding the distinctions between SUPERVISOR faults and the state of the RSTB output. RSTB_CONFIG Data Contents BIT(S) SYMBOL OPERATION b[15:13] rstb_delay Encode RSTB output assertion delay. b[15:13] rstb_delay 000b 0.05ms 001b 1.6ms 010b 6.4ms 011b 26ms 100b 51ms 101b 200ms (default) 110b 410ms 111b 1640ms b[12] sv_fault_enable Allow a SUPERVISOR fault to pull FAULTB. 0: SUPERVISOR fault does not pull FAULTB.1: SUPERVISOR fault pulls FAULTB (default). b[11] v6_ov_enable Add V6 OV status into RSTB output. 0: Not enabled (default).1: Enabled. b[10] v5_ov_enable Add V5 OV status into RSTB output. 0: Not enabled (default).1: Enabled. b[9] v4_ov_enable Add V4 OV status into RSTB output. 0: Not enabled (default).1: Enabled. b[8] v3_ov_enable Add V3 OV status into RSTB output. 0: Not enabled (default).1: Enabled. b[7] v2_ov_enable Add V2 OV status into RSTB output. 0: Not enabled (default).1: Enabled. b[6] v1_ov_enable Add V1 OV status into RSTB output. 0: Not enabled (default).1: Enabled. b[5] v6_uv_enable Add V6 UV status into RSTB output. 0: Not enabled.1: Enabled (default). b[4] v5_uv_enable Add V5 UV status into RSTB output. 0: Not enabled.1: Enabled (default). b[3] v4_uv_enable Add V4 UV status into RSTB output. 0: Not enabled.1: Enabled (default). b[2] v3_uv_enable Add V3 UV status into RSTB output. 0: Not enabled.1: Enabled (default). b[1] v2_uv_enable Add V2 UV status into RSTB output. 0: Not enabled.1: Enabled (default). b[0] v1_uv_enable Add V1 UV status into RSTB output. 0: Not enabled.1: Enabled (default). 2937f For more information www.linear.com/LTC2937 25 LTC2937 COMMAND DESCRIPTIONS FAULT_RESPONSE (Command Byte 0x23) The FAULT_RESPONSE command defines the LTC2937 response to system faults (SEQUENCE, SUPERVISOR, CONTROL or OTHER). An OTHER fault may occur from external pull-down on the FAULTB output, or a loss of SHARE_CLK operation (mask EXTERNAL faults with b[9]). FAULTB pulls low after any of these faults occur. A freeze mode is available, stopping the sequencing process (if any) and leaving any enabled supplies turned on. This mode should be used with care and is discussed in the applications information. Automatic re-sequencing is permitted on a time basis or voltage basis, depending on the fault_response_action bits b[4:3]. Using voltage basis, automatic re-sequencing is allowed when monitored supplies have decayed below their respective discharge thresholds. Using time basis allows re-sequencing after 1 of 8 selectable time delays with b[7:5] (without regard to the level of the monitored input voltages). Retries using the combined basis of discharge condition and time delay is also available. Another option is to continue without shutdown, as if nothing is wrong (FAULTB still pulls low). Set the number of retries allowed with b[2:0]. Retrieve the number of retries attempted (with b[13:11]) after the initial sequencing operation. Consult the Applications Information for a complete discussion regarding the definition of SEQUENCE, SUPERVISOR, CONTROL and OTHER faults, including more information concerning fault response operations. 2937f 26 For more information www.linear.com/LTC2937 LTC2937 COMMAND DESCRIPTIONS The FAULT_RESPONSE data content is shown below. FAULT_RESPONSE Data Contents BIT(S) SYMBOL OPERATION b[15:14] reserved Ignore. b[13:11] retry_count Read the number of retries attempted. The counter is cleared with any new sequencing-up operation initiated by the ON input or I2C command. The counter may also be cleared using the CLEAR command (read only). b[10] faultb_state Read the state of FAULTB (read only). b[9] faultb_mask Select device response to external pull-down on FAULTB. 0:Ignore external FAULTB pull-down (default). 1:Respond to external FAULTB pull-down. Sequenced ENn outputs pull down immediately if not frozen with b[8] below. b[8] freeze b[7:5] retry_delay b[4:3] b[2:0] fault_response_ action retry_number Select system freeze response due to a fault. 0:Do not freeze on fault (default). 1:Freeze device state on fault. Specify the delay between automatic re-sequencing retries. b[7:5] retry_delay 000b 0.05 ms (default) 001b 200ms 010b 410ms 011b 820ms 100b 1.64s 101b 3.28s 110b 6.55s 111b 13.1s Select shutdown and restart action after a fault. Consult applications information for more details. b[4:3] fault_response_action 00b Continue operation 01b Discharged retry (default) 10b Delayed retry 11b Discharge and Delay retry Specify the automatic retry count. Consult applications information for more details. b[2:0] retry_number 000b 0 (default) 001b 1 010b 2 011b 3 100b 4 101b 5 110b 6 111b Unlimited retries 2937f For more information www.linear.com/LTC2937 27 LTC2937 COMMAND DESCRIPTIONS MONITOR_STATUS_HISTORY (Command Byte 0x26) The MONITOR_STATUS_HISTORY command returns two bytes of information with a summary of present and past SUPERVISOR and SEQUENCE faults. Consult the Applications Information section for a complete definition of SUPERVISOR and SEQUENCE faults. Detected SEQUENCE faults are reported with the lowest numbered channel having report priority. SUPERVISOR faults can only occur through comparators mapped to the reset logic. A valid sequence-up initiation automatically clears the MONITOR_STATUS_HISTORY. Use the CLEAR command (0x2E) to reset the history contents to 0x0000. MONITOR_STATUS_HISTORY Data Contents (read only) BIT(S) SYMBOL b[15:13] sf_chan_hist OPERATION SEQUENCE fault channel. Lowest numbered channel has report priority. b[15:13] sf_channel 000b No fault 001b V1 010b V2 011b V3 100b V4 101b V5 110b V6 111b reserved b[12] sv_fault_status SUPERVISOR fault status.0: SUPERVISOR fault has not occurred.1: SUPERVISOR fault has occurred. b[11] v6_ov_sv_fault V6 OV SUPERVISOR fault history.0: No fault.1: Fault occurred. b[10] v6_uv_sv_fault V6 UV SUPERVISOR fault history.0: No fault.1: Fault occurred. b[9] v5_ov_sv_fault V5 OV SUPERVISOR fault history.0: No fault.1: Fault occurred. b[8] v5_uv_sv_fault V5 UV SUPERVISOR fault history.0: No fault.1: Fault occurred. b[7] v4_ov_sv_fault V4 OV SUPERVISOR fault history.0: No fault.1: Fault occurred. b[6] v4_uv_sv_fault V4 UV SUPERVISOR fault history.0: No fault.1: Fault occurred. b[5] v3_ov_sv_fault V3 OV SUPERVISOR fault history.0: No fault.1: Fault occurred. b[4] v3_uv_sv_fault V3 UV SUPERVISOR fault history.0: No fault.1: Fault occurred. b[3] v2_ov_sv_fault V2 OV SUPERVISOR fault history.0: No fault.1: Fault occurred. b[2] v2_uv_sv_fault V2 UV SUPERVISOR fault history.0: No fault.1: Fault occurred. b[1] v1_ov_sv_fault V1 OV SUPERVISOR fault history.0: No fault.1: Fault occurred. b[0] v1_uv_sv_fault V1 UV SUPERVISOR fault history.0: No fault.1: Fault occurred. 2937f 28 For more information www.linear.com/LTC2937 LTC2937 COMMAND DESCRIPTIONS CLEAR_ALERTB (Command Byte 0x28) Release the ALERTB output pull-down by performing a read from the CLEAR_ALERTB register. All other status information remains unaffected. The returned data word contains no useful information and the contents should be ignored. STORE (Command Byte 0x2C) Send the STORE command whenever the current operating configuration requires saving to non-volatile memory. Future power-on events automatically load the stored operating configuration. The STORE command is ignored when the WP input is high and/or b[0] of the WRITE_PROTECTION register is equal to 1. Write permission is guarded by a 14-bit security key providing additional security to stored content. The STORE command is best used while controlled supplies are off or sequenced-down, to prevent unintended results. RESTORE (Command Byte 0x2D) Send the RESTORE command whenever the current operating configuration requires an update from non-volatile memory. A restore from EEPROM occurs automatically when emerging from power-on reset after device power is applied. The RESTORE command is best used while controlled supplies are off or sequenced-down, to prevent unintended results. CLEAR (Command Byte 0x2E) Send the CLEAR command to clear active status, fault and volatile history information. The CLEAR command also resets the sequencing state machine so it is best used while controlled supplies are off or sequenced-down to prevent inadvertent system operation. Affected registers are: STATUS_INFORMATION, MONITOR_STATUS_HISTORY, MONITOR_STATUS and SEQ_POSITION_COUNT, ON_OFF_CONTROL b[7] and FAULT_RESPONSE b[13:11]. If CLEAR is immediately followed by a STORE command, the MONITOR_BACKUP register is also cleared. 2937f For more information www.linear.com/LTC2937 29 LTC2937 COMMAND DESCRIPTIONS STATUS_INFORMATION (Command Byte 0x29) The STATUS_INFORMATION command returns a summary of faults and sequencing status flags which have occurred. The register is self-clearing at the beginning of a new sequence-up operation or after a power-on reset. One exception is mb_state (b[12]) which indicates whether or not the MONITOR_BACKUP register has been written. After a poweron reset, b[12] is updated automatically. Perform a CLEAR command followed by a STORE command to reset b[12] to logic low. STATUS_INFORMATION Data Contents (read only) BIT(S) SYMBOL b[15:13] sf_channel b[12] mb_state b[11:10] local_seq_status b[9:8] OPERATION SEQUENCE fault channel. Lowest numbered channel has report priority. b[15:13] sf_channel 000b No fault 001b V1 010b V2 011b V3 100b V4 101b V5 110b V6 111b reserved MONITOR_BACKUP register status.0: MONITOR_BACKUP empty.1: MONITOR_BACKUP written. Addressed device sequencing status. 00b: Sequence-down complete (power-on default state). 01b: Sequence-up in progress. 11b: Sequence-up complete. 10b: Sequence-down in progress. group_seq_status Device group sequencing status (for multiple devices connected to SPCLK). 00b: Sequence-down complete (power-on default state). 01b: Sequence-up in progress. 11b: Sequence-up complete. 10b: Sequence-down in progress. b[7] seq_up_fault Maximum rise time fault.0: No fault.1: Fault occurred. b[6] seq_down_fault Maximum fall time fault.0: No fault.1: Fault occurred. b[5] ov_fault SUPERVISOR fault caused by mapped OV condition.0: No fault.1: Fault occurred. b[4] uv_fault SUPERVISOR fault caused by mapped UV condition.0: No fault.1: Fault occurred. b[3] sv_fault b[2] discharge b[1] seq_control_fault b[0] other_fault SUPERVISOR fault status.0: No fault.1: Fault occurred. Discharge status. 0: One or more sequenced voltages are above discharge thresholds. 1: All sequenced voltages are below discharge thresholds. Sequence CONTROL fault status.0: No fault.1: Fault. EXTERNAL fault or SHARE_CLK fault status.0: No fault.1: Fault occurred. 2937f 30 For more information www.linear.com/LTC2937 LTC2937 COMMAND DESCRIPTIONS BREAK_POINT (Command Byte 0x2A) Pause sequencing at any valid sequence position (occurs during SPCLK low period). Set sequence position break points in the sequence-up or sequence-down phase of operation. Enable break point usage with bp_enable b[10]. With break point usage enabled, a valid control input (ON transition or I2C command) will sequence the device until sp_count in the SEQ_POSITION_COUNT register is equal to bp_value in the BREAK_POINT register. Perform register inspections and system measurements at each paused sequence position. Increment the BREAK_POINT register repeatedly for controlled single stepping through all sequence positions. SPCLK holds low until bp_value is changed to be not equal to sp_count or bp_enable is set low. The sequencing enable delay timers and maximum rise/fall timers function normally at each sequence position. BREAK_POINT Data Contents BIT(S) SYMBOL OPERATION b[15:11] reserved Ignore. b[10] bp_enable Break point mode. 0: Break point mode not enabled (default). 1: Break point mode enabled. b[9:0] bp_value Break point sequence position value. Specify a sequence position break point from 0 to 1023. (Default = 0x000). SEQ_POSITION_COUNT (Command Byte 0x2B) Read the current sequence position count contained in the sp_count bit field. The sp_count bit field is zero after initial application of device power or after a CLEAR command. At the conclusion of all sequence-up or sequencedown operations, sp_count increments by one. For example, if the last configured sequence position is 10, sp_count increments to 11 when the sequencing operation completes. If the last sequence position is 1023, sp_count rolls over to zero at the end of sequencing. After a fault (whether in break point mode or normal operation), the current sequence position value is reported until the fault exit conditions are satisfied. SEQ_POSITON_COUNT Data Contents (read only) BIT(S) SYMBOL OPERATION b[15:11] reserved Ignore. b[10] sp_bp_test b[9:0] sp_count Compare sp_count with bp_value. 0: sp_count is not equal to bp_value. 1: sp_count is equal to bp_value. Sequence position count. 2937f For more information www.linear.com/LTC2937 31 LTC2937 COMMAND DESCRIPTIONS MONITOR_BACKUP (Command Byte 0x2F) The MONITOR_BACKUP register mirrors the contents of the MONITOR_STATUS_HISTORY upon the first detected SEQUENCE or SUPERVISOR fault. Subsequent faults are not stored so that the first fault can always be retrieved even after complete device power cycling. Retrieve the backup word by issuing a RESTORE command followed by a MONITOR_BACKUP read. Clear the backup word by performing a CLEAR command followed by a STORE command. After a device power cycle, MONITOR_BACKUP updates automatically, so a RESTORE command is not required prior to a MONITOR_BACKUP read. Backup register contents can be modified by the first SUPERVISOR or SEQUENCE fault if a power cycle or CLEAR command has been performed. Please note that when resetting the backup register using CLEAR and STORE, any modifications to the volatile memory in other registers will be written to EEPROM during the STORE procedure. MONITOR_BACKUP Data Contents (read only) BIT(S) SYMBOL b[15:13] bu_sf_chan b[12] bu_svf_state OPERATION SEQUENCE fault channel backup. Lowest numbered channel has report priority. b[15:13] sf_channel 000b No fault 001b V1 010b V2 011b V3 100b V4 101b V5 110b V6 111b reserved SUPERVISOR fault status backup.0: SUPERVISOR fault has not occurred.1: SUPERVISOR fault has occurred. b[11] bu_v6_ov_sv_fault V6 OV SUPERVISOR fault backup.0: No fault.1: Fault occurred. b[10] bu_v6_uv_sv_fault V6 UV SUPERVISOR fault backup.0: No fault.1: Fault occurred. b[9] bu_v5_ov_sv_fault V5 OV SUPERVISOR fault backup.0: No fault.1: Fault occurred. b[8] bu_v5_uv_sv_fault V5 UV SUPERVISOR fault backup.0: No fault.1: Fault occurred. b[7] bu_v4_ov_sv_fault V4 OV SUPERVISOR fault backup.0: No fault.1: Fault occurred. b[6] bu_v4_uv_sv_fault V4 UV SUPERVISOR fault backup.0: No fault.1: Fault occurred. b[5] bu_v3_ov_sv_fault V3 OV SUPERVISOR fault backup.0: No fault.1: Fault occurred. b[4] bu_v3_uv_sv_fault V3 UV SUPERVISOR fault backup.0: No fault.1: Fault occurred. b[3] bu_v2_ov_sv_fault V2 OV SUPERVISOR fault backup.0: No fault.1: Fault occurred. b[2] bu_v2_uv_sv_fault V2 UV SUPERVISOR fault backup.0: No fault.1: Fault occurred. b[1] bu_v1_ov_sv_fault V1 OV SUPERVISOR fault backup.0: No fault.1: Fault occurred. b[0] bu_v1_uv_sv_fault V1 UV SUPERVISOR fault backup.0: No fault.1: Fault occurred. 2937f 32 For more information www.linear.com/LTC2937 LTC2937 COMMAND DESCRIPTIONS MONITOR_STATUS (Command Byte 0x30) The MONITOR_STATUS command returns a summary of the present (live) voltage monitor conditions. UV and OV status are always active. The external status of the RSTB I/O is reported on b[12] and will indicate low if an external device is pulling down on RSTB. Comparator live status is not affected by settings in the RSTB_CONFIG register. MONITOR_STATUS Data Contents (read only) BIT(S) SYMBOL OPERATION b[15:14] reserved Ignore. b[13] margin_status b[12] rstb_status b[11] v6_ov_status V6 OV comparator live status.0: No violation.1: High limit violation. b[10] v6_uv_status V6 UV comparator live status.0: No violation.1: Low limit violation. b[9] v5_ov_status V5 OV comparator live status.0: No violation.1: High limit violation. b[8] v5_uv_status V5 UV comparator live status.0: No violation. b[7] v4_ov_status V4 OV comparator live status.0: No violation.1: High limit violation. b[6] v4_uv_status V4 UV comparator live status.0: No violation.1: Low limit violation. b[5] v3_ov_status V3 OV comparator live status.0: No violation.1: High limit violation. b[4] v3_uv_status V3 UV comparator live status.0: No violation.1: Low limit violation. b[3] v2_ov_status V2 OV comparator live status.0: No violation.1: High limit violation. b[2] v2_uv_status V2 UV comparator live status.0: No violation.1: Low limit violation. b[1] v1_ov_status V1 OV comparator live status.0: No violation.1: High limit violation. b[0] v1_uv_status V1 UV comparator live status.0: No violation.1: Low limit violation. Logical representation of the external margin input and/or I2C margin control bit. 0: Margin function inactive.1: Margin function active. Status of the RSTB I/O.0: RSTB is high.1: RSTB is low. 1: Low limit violation. DEVICE_ID (Command Byte 0x31) The DEVICE_ID command returns two bytes containing the part number 0x2937. This register is read only. 2937f For more information www.linear.com/LTC2937 33 LTC2937 APPLICATIONS INFORMATION Introduction Write Protection The LTC2937 power management IC provides time and event based sequencing, undervoltage and overvoltage supervision and fault management. To prevent accidental writes to memory (volatile and non-volatile), apply the software and/or hardware lock functions. Software protection is active when the WRITE_ PROTECTION register lock bit b[0] = 1. Deactivate the software lock by writing bit[0] = 0 while matching the 14 bit key string contained in b[15:2]. The hardware lock is active when the WP input is pulled to VDD. Deactivate the hardware lock by pulling the WP input to ground. Powering the LTC2937 Two options exist for applying LTC2937 device power. If an intermediate bus voltage between 4.5V and 16.5V is available, connect it to the VPWR input. An internal linear regulator converts VPWR down to 3.3V which drives all internal circuitry. The regulated 3.3V also drives VDD and requires a 2.2µF (or greater) compensation capacitor. Alternatively, apply an external supply voltage between 2.9V and 5.5V directly to VDD and VPWR. When driving VDD directly, a compensation capacitor is not required, but a decoupling capacitor (0.1µF) is recommended. 4.5V ≤ VPWR ≤ 16.5V C2 0.1µF C1 2.2µF VPWR LTC2937 VDD GND 2937 F06 Figure 6. Powering LTC2937 Directly from an Intermediate Bus Voltage 2.9V ≤ VDD ≤ 5.5V VPWR LTC2937 C1 0.1µF VDD GND 2937 F07 Figure 7. Powering LTC2937 Directly from Low Supply Voltage During initial application of LTC2937 device power, device configuration transfers from EEPROM into the volatile operating memory after VDD exceeds undervoltage lockout. The restore time is 2ms maximum. Perform changes to device configuration, sequencing and/or supervisory operations after completion of the restore procedure. Write protection must be de-activated when it is desired to write changes to the volatile or non-volatile memory. The usual cause of seemingly ignored write operations is due to active write protection. The LTC2937 will acknowledge I2C commands while under write protection. However, the part configuration will not change. Updating Volatile or Non-Volatile Memory Changes to the EEPROM require a two-step procedure. First, write desired values to the command registers. Then, perform the STORE command. Command register configuration will be copied to the EEPROM. Maximum write time is 120ms. Perform a RESTORE command to move EEPROM data into the volatile command registers. The LTC2937 does not acknowledge commands while the EEPROM is writing. Volatile command register contents are often changed during system testing or development. If desired, restore the command register contents to the stored configuration in EEPROM by performing the RESTORE command. To prevent unintended operation, send the RESTORE command after sequence-down and after sending a CLEAR command. A RESTORE is performed automatically at initial device power-on. Changes to the volatile memory can be performed at any time. However, some changes should only be made when the system is in the sequenced-down or off state because writes to volatile memory have immediate influence. If the system is actively sequencing or monitoring, and certain changes occur, unintended consequences may 2937f 34 For more information www.linear.com/LTC2937 LTC2937 APPLICATIONS INFORMATION result because of contradictions within the sequencing state machine. To prevent unintended operation, send a CLEAR command after sequence-down, prior to making changes to volatile memory. Use caution when writing the following commands during the sequencing and monitoring phases of operation: • ON_OFF_CONTROL b[5, 1, 0] • V_RANGE When a system requires more than six controlled power supplies, use SPCLK to maintain seamless multi-channel sequencing control across all devices. SPCLK is a single wire event control signal and other than the simple interconnection of SPCLK between devices, additional external device connections to SPCLK are not required or recommended. Using SPCLK, up to 300 power supplies can be controlled by connecting up to 50 LTC2937s together. Arrange power supply sequence order in any one of 1023 available sequence positions. When applying device power directly to VDD, connect VDD together across all devices. When applying device power to VPWR, the regulated VDD outputs do not require parallel connection. • V_THRESHOLD_n • TON_TIMERS_n • TOFF_TIMERS_n • SEQ_UP_POSITION_n • SEQ_DOWN_POSITION_n • RSTB_CONFIG • FAULT_RESPONSE • CLEAR, STORE, RESTORE Certain registers have reserved bits in some bit locations. To avoid confusion, mask out or ignore those bits when reading back the contents of those registers. Each command description details the location of the reserved bits. When writing to commands with reserved bits, data content in those bit locations are disregarded. ON SPCLK Sequence Position Clock (SPCLK) After initial device power is applied, SPCLK holds low in the non-sequencing phase of operation. Once sequencing is initiated, SPCLK pulls high for 60µs (tHI) and then pulls low. The system is now in sequence position 1. If there are no supplies scheduled for sequencing in position 1, SPCLK pulls high again after 20µs (tLO). SPCLK remains high for 60µs (tHI) and then pulls low again. This cycle repeats (Figure 8) until a power supply scheduled for sequencing is encountered. SEQUENCE POSITION NUMBER tONSQ 1 2 (tHI) 3 (tLO) 2937 F08 Figure 8. SPCLK Nominal Timing ON (UNASSIGNED) SPCLK SPCLK STRETCHING 1 2 SUPPLY A SUPPLY B (tHI) Vn (UV THRESHOLD) 2937 F09 Figure 9. SPCLK Stretching 2937f For more information www.linear.com/LTC2937 35 LTC2937 APPLICATIONS INFORMATION During the sequence-up phase, enable outputs on any LTC2937 scheduled for a particular sequence position pull high after their respective turn-on delay. Turn-on delay is measured from the falling edge of SPCLK. The delay times are individually programmed for each enable output. SPCLK is stretched and remains low (Figure 9) until all supplies scheduled for the current sequence position have crossed their UV threshold. SPCLK then pulls high for 60µs (tHI) and again pulls low, placing all devices into the next sequence position. The process repeats until all power supplies scheduled for sequencing have completed powering up. After the last power supply powers up, SPCLK pulls high for 320µs (tFLOAT) and then pulls low. The sequence-up phase of operation is complete. SPCLK operates in the same manner during sequence-down operation. Enable any number of supplies in any sequence position using any number of LTC2937s (Figure 9). When using multiple LTC2937s, freely interleave power supply sequencing between devices. For example, enable any number of supplies on a first device, then enable any number of supplies on another device, then again from the first device and so forth. Reserve certain sequence positions for possible insertion of additional power supplies. Note that in Figure 9, sequence position 1 is unassigned or reserved for future use. Leaving sequence positions unassigned can be good practice during system development as it allows for future expansion or insertion of supplies without having to reprogram all LTC2937's in the system. Simply position a new supply in an unassigned sequence position and all succeeding positions slide appropriately. System Configuration The procedure described herein is intended as a reference and for the purpose of understanding the registers in a software development environment. Configure LTC2937 standalone operation using the LTC USB to I2C/SMBus/ PMBus controller (DC1613) and LTpowerPlay software GUI using intuitive menu driven objects. Simplify the procedure of system configuration by configuring command register contents in a task oriented manner. For example, a typical system can be divided into four regions of operation: 1.Sequence-Up and Sequence-Down Control (select sequence initiation method) 2.Sequence-Up Parameters (sequence-up order, time spacing and maximum rise time) 3.Voltage Supervision (monitored voltage range, voltage threshold and reset response) 4.Sequence-Down Parameters (sequence-down order, time spacing and maximum fall time) Beyond the sequence and supervisory commands are a set of commands for fault management, status information, system debug and general information. These commands are discussed further below. Note that the command summary table is also organized in a task oriented fashion. Sequence-Up and Sequence-Down Control Various sequence-up and sequence-down control options are specified through the ON_OFF_CONTROL command. To initiate sequencing, use the polarity selectable ON input and/or I2C on/off bit. If specifications require sequencing-up to begin with discharged supplies, set b[5]=1 to enforce qualification. If b[5] = 1, the LTC2937 prohibits initial sequencing until supplies configured for sequencing are discharged. If a fault has occurred and automatic retries are enabled, re-sequencing conditions obey the discharge and/or time delay rules specified in the FAULT_RESPONSE register. To start sequence-down operations, switch the ON input or I2C on/off bit to the off state. Sequence positions are advanced on the basis of sequenced supply voltage level or configured time-delay. Select this distinction with ON_OFF_CONTROL b[0]. The i2c_on_off_mask and on_input_mask bits (b[3:2]) are set low by default. This prevents any sequencing from occurring at initial application of device power. Since the ON input has an internal pull-up current source, automatic sequencing is possible (with default ON polarity) if the on_input_mask = 1 and the ON input is not held low. 2937f 36 For more information www.linear.com/LTC2937 LTC2937 APPLICATIONS INFORMATION ON ton_delay_1 SPCLK 1 ton_max_1 2 EN1 uv_threshold_1 V1 FAULTB 2937 F10 Figure 10. Sequence-Up Timing Parameters (V1 Set to Sequence Up in Sequence Position 2) Showing SEQUENCE Fault Sequence-Up Parameters Sequence-up configuration consists of defining the sequence position for each sequenced supply, the time delay to enable (measured from the falling edge of SPCLK) and the maximum allowed elapsed time (from enable) for each sequenced supply to reach its UV threshold. Configure these parameters with the SEQ_UP_POSITION_n and TON_TIMERS_n commands (where n denotes the channel number). Figure 10 graphically depicts parameters for a hypothetical supply operating in channel 1. Sequencing is initiated with the ON input. In this example, the supply is enabled in sequence position 2, with an enable delay (ton_delay_1) of 800µs and a maximum rise time (ton_max_1) of 10.24ms. Because V1 does not meet its rise time requirements (V1 is below uv_threshold_1 when ton_max is reached), a sequence-up fault occurs and all enables are turned off. The corresponding command register values are: SEQ_UP_POSITION_1 = 0x0002 TON_TIMERS_1 = 0x8064 Voltage Supervision There are three steps to programming voltage supervision. First, configure the voltage range for each monitored input. Second, configure the UV, OV and discharge thresholds for each monitored input. Lastly, decide on which monitored inputs contribute to the RSTB response. The LTC2937 provides 12 independently programmable high accuracy voltage monitor comparators. There are two comparators per Vn input, typically used for undervoltage and overvoltage detection. Each comparator provides 750 thresholds (250 thresholds in each of 3 voltage input ranges), from 0.2V to 6V. Additionally, each Vn input contains a discharge comparator which determines when monitored voltages have decayed to a substantially low level. Voltage Monitor Range The V_RANGE command contains encoding to program the voltage threshold range for each of the six monitor inputs (V1 through V6). The range selection applies to the OV and UV comparators connected to each input. The High Range covers thresholds between 1V and 6V in 20mV steps. The Low Range covers thresholds between 0.5V and 3V in 10mV steps. The Adjustable Range covers 0.2V to 1.2V in 4mV steps. Select the negative polarity option in the Adjustable Range when sensing negative voltages. The Adjustable Range is high impedance. If the Adjustable Range is used in conjunction with external resistive dividers, keep the Thevenin divider resistance below 100k to maintain threshold accuracy. Because there are 750 fixed thresholds per comparator, external resistive dividers are rarely necessary. This keeps part counts low and board layout simple. When monitored 2937f For more information www.linear.com/LTC2937 37 LTC2937 APPLICATIONS INFORMATION supplies are below 6V, consider using one of the fixed thresholds in any of the three monitoring ranges. UV and OV Thresholds Each V_THRESHOLD_n command (n = 1..6) configures the UV and OV thresholds for the corresponding input channel. Each command word contains encoding for the OV threshold in the upper byte, and for the UV threshold in the lower byte. Voltage threshold encoding examples are given below the command description. In the High Range and Low Range modes, the Vn inputs have finite input impedance, and should not be loaded with an external resistive divider. In the Adjustable Range, the Vn inputs are high impedance. Use the adjustable range with or without external resistors to customize thresholds. At each Vn input, the adjustable range senses voltages between 0.2V and 1.2V. External resistors can divide-down larger voltages, and provide level-shifting for negative voltage applications. UV Thresholds and Sequence-Up Hysteresis During sequencing-up, systems are subject to large electrical disturbances as loads become energized. Each of the LTC2937 comparators has built-in glitch filtering, and accommodation for short-term sagging in supervised voltages during sequence-up. The UV thresholds on channels selected for sequencing receive temporary hysteresis during sequencing-up. Each UV threshold moves down by 5% (for positive sensing applications) after the voltage first crosses its configured UV threshold. The temporary hysteresis remains effective for ½ of the configured RSTB assertion delay. The RSTB assertion delay commences when the last configured supply rises above its UV threshold for the first time (supplies configured for sequencing and for RSTB logic). For negative sensing applications, hysteresis moves the UV threshold up by 5%, instead of down. The UV threshold during temporary hysteresis is equal to the programmed threshold. When temporary hysteresis is not active, the UV threshold is 5% below the value configured by the V_THRESHOLD_n word. This is important because the UV threshold used in all negative calculations is 5% below that programmed in the V_THRESHOLD_n word. If a channel is not participating in sequencing, its UV comparator threshold does not move. For positive sensing applications it remains at the value encoded in the V_THRESHOLD_n word, and for negative sensing applications it remains at a value 5% below the value encoded in the V_THRESHOLD_n word. Selecting Resistors for Adjustable Range For positive voltage sensing applications, use Figure 11 as a configuration reference. For example, assume a positive input voltage of +15V applied to the top of R2, with a desired UV threshold at 14.3V (VTH(UV)). Use the V_RANGE command to select the Positive Adjustable Range. When the input voltage is 14.3V we choose the Vn input to be VMON(UV) = 1.0V (somewhat arbitrarily, for numerical simplicity). VMON(UV) = 1.0V is a code of uv_threshold_n = 0xCD (205). The resistor ratio, R2/R1 is easily determined by the equation: ( ) R2 VTH(UV) – VMON(UV) (14.3V – 1V) = = = 13.3 VMON(UV) 1V R1 Suitable values are R1 = 10k and R2 = 133k. With a Thevenin divider resistance of less than 10k, leakage current in the Vn pin causes less than 0.01% threshold error. Errors in the resistor ratio will produce proportional voltage threshold errors. LTC2937 + POSITIVE MONITORED SUPPLY VMON(OV) R2 – – Vn R1 VMON(UV) + – VDTH 0.12V + 2937 F11 Figure 11. Configuring Custom Positive Thresholds (Operating in the Positive Adjustable Range) 2937f 38 For more information www.linear.com/LTC2937 LTC2937 APPLICATIONS INFORMATION Calculations for negative input voltage applications are more complex due to level shifting and temporary input hysteresis. Use Figure 12 as a configuration reference. Because the voltage at the Vn input must be between 0.2V and 1.2V in the adjustable range (at threshold), a positive level-shifting voltage (VLS) is required. VLS must be stable before the negative voltage pulls down to prevent the Vn input voltage from going below ground. Level-shifting voltage accuracy affects threshold sensing accuracy. Use VDD as a convenient level-shifting voltage when ±2% threshold variation is tolerable. Use a more accurate level-shifting voltage for better than 2% threshold accuracy. the Negative Adjustable Range. When the input voltage is −0.864V, we choose the Vn input to be VMON(UV) = 1.2V. VMON(UV) = 1.2V is a code of uv_threshold_n = 0xFF (255). The resistor ratio, R2/R1 is easily determined by the equation: For any negative sensing application, the actual UV comparator threshold is 5% below the value programmed in the V_THRESHOLD_n word. For example, if the UV comparator is programmed for the top of the adjustable range (1.2V), the comparator will trip at a voltage of 0.95 • 1.2V = 1.14V. This is true whether the supply is participating in sequencing or not. If the supply is participating in sequencing, the temporary hysteresis threshold moves to the value programmed in the V_THRESHOLD_n word. As a final example, consider the case of the negative supply participating in sequencing. Keep the UV threshold VTH(UV) = −0.864V, and select 5% temporary hysteresis (H = 0.05). Select the monitor threshold VMON(UV) = 0.748V (uv_threshold_n = 0x8E (142)). R2/R1 is given by: Consider an example of a negative supply that is not participating in sequencing (no temporary hysteresis). Assume a negative input voltage of −0.9V applied to the bottom of R1, and a desired UV threshold voltage of VTH(UV) = −0.864V. Use the V_RANGE command to select LTC2937 VDD 3.3V – 1.14V ≈ 1.078 1.14V + 0.864V Suitable choices for R2 = 22.1k and R1 = 20.5k. R2 3.3V − 0.748V = ≈ 1.626 R1 0.748V + 0.864V • 0.95 Suitable resistor values are R2 = 17.4k and R1 = 10.7k. OV Thresholds in Adjustable Applications + VMON(OV) = R2 Vn + R1 NEGATIVE MONITORED SUPPLY 0.95 • VMON(UV) – VTH(OV) R2 1+ R1 Choosing a 10% overvoltage threshold, VTH(OV) = (15V∙1.1) = 16.5V. The monitor threshold becomes: + VDTH 1.2V VLS – VMON(UV) R2 = R1 VMON(UV) – VTH(UV) •(1–H) After selecting external resistors, configure the OV thresholds. Following the positive adjustable example of Figure 11, the monitor comparator OV threshold is determined from: – VMON(OV) VLS – 0.95 • V MON(UV) R2 = = R1 0.95 • VMON(UV) – VTH(UV) VMON(OV) = – 2937 F12 Figure 12. Configuring Custom Negative Thresholds (Operating in the Negative Adjustable Range) 16.5V ≈ 1.154V 133k 1+ 10k The closest comparator code (ov_threshold_n) is 0xE3 (243). 2937f For more information www.linear.com/LTC2937 39 LTC2937 APPLICATIONS INFORMATION Following the negative adjustable example of Figure 12, the monitor comparator OV threshold is determined from: VMON(OV) = VLS + R2 •V R1 TH(OV) R2 1+ R1 Choosing a 10% overvoltage threshold: VTH(OV) = (−0.9V • 1.1) = −0.99V The monitor threshold becomes: VMON(OV) = 3.3V + 17.4k •(−0.99V) 10.7k ≈ 0.644V 17.4k 1+ 10.7k The closest comparator code (ov_threshold_n) is 0x74 (116). RSTB Response Tie RSTB to any device requiring a reset signal. RSTB is low when any selected voltage monitor violates its respective threshold. RSTB is allowed to pull high when all selected voltages are in compliance (UV and/or OV) and the assertion delay has expired. An external pull-up resistor (10k to 100k) is recommended. Use the RSTB_CONFIG command to configure RSTB response. Combine any voltage monitor input into the RSTB response whether or not the channel is participating in sequencing. If there are no channels selected, RSTB is affected only by the device’s internal undervoltage lockout and initialization circuits. The assertion delay remains active. After initial application of device power, RSTB assertion delay cannot start until device configuration is complete. The configuration (or restore) time (tRT) is a maximum of 2ms after crossing VDD undervoltage lockout (VUVL). Force RSTB high anytime by pulling the MARGB input low. MARGB overrides the RSTB function and is typically used while system voltages are margined high or low and a device reset is not desired. The RSTB override may also be controlled with I2C writes to b[6] of the ON_OFF_CONTROL register. Sequence-Down Parameters Sequence-down configuration consists of defining the sequence position for each sequenced supply, the time delay to enable pulling low (measured from the falling edge of SPCLK) and the maximum allowed elapsed time (from enable) for each sequenced supply to reach its discharge threshold. Configure these parameters with the SEQ_DOWN_POSITION_n and TOFF_TIMERS_n commands (where n denotes the channel number). Figure 13 graphically depicts parameters for a hypothetical supply operating in channel 1. Sequencing is initiated with the ON input. In this example, the supply is disabled in sequence position 2, with an enable delay (toff_delay_1) of ON toff_delay_1 SPCLK 1 toff_max_1 2 EN1 V1 discharge_threshold = V1DTH FAULTB 2937 F13 Figure 13. Sequence-Down Timing Parameters (V1 Set to Sequence Down in Sequence Position 2) 2937f 40 For more information www.linear.com/LTC2937 LTC2937 APPLICATIONS INFORMATION 800µs and a maximum fall time (toff_max_1) of 10.24ms. Because V1 does not meet its fall time requirements (V1 is above the discharge threshold when toff_max is reached), a sequence-down fault occurs and all enables are turned off. The corresponding command register values are: SEQ_DOWN_POSITION_1 = 0x0002 to 120mV. In the negative adjustable range, the discharge threshold VDTH is 1.2V. The adjustable ranges are often used in conjunction with external resistive dividers to configure custom thresholds as described earlier. For positive adjustable applications, the discharge threshold (DT) referred to the input voltage is TOFF_TIMERS_1 = 0x4064 Two options exist for triggering sequence position advancement during the sequence-down phase of operation. ON_OFF_CONTROL register bit b[0] determines the trigger method. The first option (b[0] = 0) allows sequence position advancement on the basis of voltage decay, and applies to all sequenced supplies. A supply (or supplies) that has been commanded off in a particular sequence position is required to fall below its discharge threshold before system advancement to the next sequence position (Figure 13). The decay must occur before the toff_max time has transpired. The second option (b[0] = 1) allows sequence position advancement on the basis of time delay. The time delay is equal to the configured toff_max time. If toff_max is set to ∞, operation reverts back to voltage decay mode. The selected voltage range for each monitor input determines the respective discharge threshold value at the monitor input. Operating in the high or low range sets the discharge threshold VDTH to 400mV. Operating in the positive adjustable range sets the discharge threshold VDTH VDTH VMON(UV) Applying values from the example using Figure 11, the discharge threshold is: DT = 14.3V • 0.12V = 1.716V 1V For negative adjustable applications, the discharge threshold (DT) referred to the negative input voltage is DT = VDTH − ( VLS − VDTH ) R2 R1 Applying values from the example using Figure 12, the discharge threshold is: Discharge Thresholds The LTC2937 monitor inputs have discharge monitor comparators with thresholds used to determine if a monitored supply is substantially discharged when in the off state. This feature is used in two ways. First, prevent the start of sequencing-up if any supply scheduled for sequencing is above its discharge threshold. Enable this qualification with b[5] in the ON_OFF_CONTROL register. Second, as discussed above, use b[0] to allow sequence-down advancement when the disabled supplies have decayed below their discharge threshold. Read the combined discharge status for sequenced channels from b[2] in the STATUS_INFORMATION register. DT = VTH(UV) • DT = 1.2V − (3.3V −1.2V ) = −0.091V 17.4k 10.7k Active Supply Discharge When power supplies are commanded off, system load characteristics and bulk capacitance can make it difficult to discharge supply voltages to a low level quickly. Use the active supply discharge feature to reduce discharge time. Apply b[10] of the respective SEQ_DOWN_POSITION_n register to enable the 30mA pull-down current. The pulldown current is always active while the respective supply is off (enable low). The discharge feature is best used in monitor applications that do not have an external resistive divider at the monitor input. CAUTION: Applying active discharge through a divider network in positive or negative voltage applications can cause a false sense of discharge at the monitor input. 2937f For more information www.linear.com/LTC2937 41 LTC2937 APPLICATIONS INFORMATION Fault Descriptions SUPERVISOR Faults Various faults can be detected during system operation. First fault information is logged to EEPROM. Program fault response actions using the FAULT_RESPONSE command. Actions include total shutdown with optional restart, system freeze and ignore. Faults can occur due to sequence control violations (CONTROL fault), sequence-up and sequencedown violations, voltage threshold violations, external inputs and loss of SHARE_CLK. It is important to understand the difference between a SUPERVISOR fault and the RSTB output response. Using the RSTB_CONFIG command (0x22), UV and OV comparator outputs combine to form the RSTB response. The RSTB output is always active (unless masked during margining). SUPERVISOR faults are generated from the same set of selected UV and OV comparators. However, a SUPERVISOR fault is active only under a restricted set of operating conditions. CONTROL Faults A sequence-up or sequence–down phase is initiated by an ON input change of state and/or i2c_on_off bit state change. After the sequence-up phase has commenced, the ON input and/or i2c_on_off bit must remain in the same state until all sequenced supplies have reached their undervoltage threshold. Similarly, after the sequence-down phase has commenced, the ON input and/or i2c_on_off bit must remain in the same state until all sequenced supplies have reached their discharge threshold. A change of sequence control state during sequencing operations is considered a CONTROL fault. A CONTROL fault causes all enable outputs to pull low immediately. The FAULTB output pulls low in response to any CONTROL fault. The reporting of CONTROL fault status is described below in the Fault Reporting section. To force a shutdown at any time, create an intentional CONTROL fault by toggling the ON input. The width of the ON pulse must be greater than 25µs in order to be detected. SEQUENCE Faults Each of the six channels has a dedicated timer defining maximum turn-on and turn-off time for each sequenced voltage, used to protect against stalled power supplies. Any enabled supply that fails to exceed its sequence threshold before its timer expires will cause a SEQUENCE fault. A SEQUENCE fault causes all enable outputs to pull low immediately. The FAULTB output pulls low in response to any SEQUENCE fault. The reporting of SEQUENCE fault status is described below in the Fault Reporting section. SUPERVISOR faults are allowed to occur when the system is in the sequence-up phase or supervisory phase of operation. These phases reside within the time region bracketed by ON input changes of state (rising ON to falling ON under default polarity). Furthermore, UV comparator contributions to a SUPERVISOR fault are only active after the sensed voltages have crossed their UV threshold for the first time. OV comparator contributions are active throughout the sequence-up and supervisory phases of operation. In the event of a SUPERVISOR fault, it may be desirable to turn off all sequenced supplies. Set b[12] = 1 in the RSTB_CONFIG register (0x22), to allow the FAULTB output to pull low in response to a SUPERVISOR fault. All sequenced enable outputs pull low when the fault is generated. The reporting of SUPERVISOR fault status is described below in the Fault Reporting section. EXTERNAL Faults It may be desirable to turn off enabled supplies on the basis of an external event. Apply an external signal to pull down on FAULTB and force a shutdown event if b[9] of the FAULT_RESPONSE register is set to a logic 1. To ignore external pull downs on FAULTB, set b[9] to logic 0. The reporting of EXTERNAL fault status is described below in the Fault Reporting section. SHARE_CLK Faults If SHARE_CLK becomes inactive for more than 32µs after it has initially started to operate, a fault is automatically generated. The fault causes FAULTB to pull low. All enable outputs pull low when the SHARE_CLK fault is generated. The reporting of SHARE_CLK fault status is described below in the Fault Reporting section. 2937f 42 For more information www.linear.com/LTC2937 LTC2937 APPLICATIONS INFORMATION Fault Reporting Retrieve important fault information from the following useful registers: • STATUS_INFORMATION (0x29) • MONITOR_STATUS (0x30) • MONITOR_STATUS_HISTORY (0x26) • MONITOR_BACKUP (0x2F) Obtain device status with an I2C read word operation from STATUS_INFORMATION (command address 0x29). Embed the read operation in a software loop for continuous polling. Otherwise, read the register on an as needed basis, for example after ALERTB or FAULTB has pulled low. Fault related data in STATUS_INFORMATION includes: • SEQUENCE fault channel number • Monitor backup status • Sequence-up fault status • Sequence-down fault status • OV fault status • UV fault status • SUPERVISOR fault status • CONTROL fault status • EXTERNAL or SHARE_CLK fault status Device status at the time of a fault is latched into STATUS_ INFORMATION (except for the discharge status in b[2]). This implies that although the system may be commanded off and in the sequence-down state (due to a fault), the STATUS_INFORMATION register will not necessarily indicate sequence-down status. The STATUS_INFORMATION register retains the state of the device at the time of the fault until the beginning of the next sequence-up operation, or until cleared. conditions and external status of RSTB is available from the MONITOR_STATUS register. Retrieve a summary of collected SUPERVISOR and SEQUENCE faults with a read from MONITOR_STATUS_ HISTORY. If two or more supplies have simultaneous SEQUENCE faults, the sequence fault is reported with the lowest numbered channel having report priority. SUPERVISOR faults can only occur through comparators mapped to the reset logic. A valid sequence-up initiation automatically clears the MONITOR_STATUS_HISTORY. Use the CLEAR command (0x2E) to reset the history contents to the defaults. The MONITOR_BACKUP register mirrors the contents of the MONITOR_STATUS_HISTORY upon the first detected SEQUENCE or SUPERVISOR fault. Subsequent faults are not stored so that the first fault can always be retrieved even after complete device power cycling. If device power has not been cycled, retrieve the backup word by issuing a RESTORE command followed by a MONITOR_BACKUP read operation. Clear the backup word by performing a CLEAR command followed by a STORE command. After a device power cycle, MONITOR_BACKUP updates automatically, so a RESTORE command is not required prior to a MONITOR_BACKUP read. After any device power cycle or CLEAR command, backup register contents are directly modified by the next SUPERVISOR or SEQUENCE fault. Monitoring b[12] of the STATUS_INFORMATION register alerts the existence of a logged fault. Fault Management In the event of a fault, a variety of responses can be configured in the FAULT_RESPONSE register (0x23). Response actions include: • Shut-down and stay off. • Shut-down and restart after discharging supplies. • Shut-down and restart after a time delay. Other non-fault related data contained in STATUS_ INFORMATION includes sequence region status and discharge level status. A valid sequence-up initiation automatically clears STATUS_INFORMATION. • Continue operation. A summary of the present (live) voltage monitor • Freeze system in current state. • Shut-down and restart after discharging supplies and time delay. 2937f For more information www.linear.com/LTC2937 43 LTC2937 APPLICATIONS INFORMATION Some applications require the ability to retry operation after a shut-down event. Specify the automatic retry count in the FAULT_RESPONSE register (0x23) with b[2:0]. Retry counts can be set to zero, range from one to six, or be unlimited. When configured for retry operation, leave the sequencing control (ON input or I2C directive) in the sequence-up state, unless a sequence-down operation is required. Retries do not occur in response to faults during the sequence-down phase of operation. The zero retry option is useful when a new system requires some debug or adjustments after initial application of sequenced power. If power supply turn-on does not meet requirements, the fault response action of simply shutting down supplies and remaining off allows for status register inspections without the risk of re-energizing loads improperly. The status information helps determine the source of failure. Re-sequencing is permitted after the ON input has been taken to the sequence-down level and retry conditions specified in b[4:3] have been satisfied. Some systems can tolerate retry attempts after failed operation. In the one to six retry mode, the retry counter can be read to retrieve the number of attempted retries. With the ON input at the sequence-up level, the retry counter is never cleared automatically. The retry counter is cleared to zero after the ON input has been taken to the sequence-down level and retry conditions have been satisfied. With unlimited retries selected, retries are attempted continuously, until commanded off (by the ON input, I2C bus or both), device power is removed, or another fault condition causes the device to turn off the power supply enable signals. The retry counter does not count in infinite retry mode. Certain criteria must be satisfied before a retry occurs. For example, all sequenced supplies may be required to be below their discharge threshold before a retry occurs. This ensures that sequencing begins only after all sequenced supplies have returned to a low voltage level. After a fault, all sequenced enable outputs turn off immediately. FAULTB pulls low if required. Automatic retries are allowed after sequenced voltages have decayed below their discharge thresholds. Alternatively, allow retries after a specified time delay. Select 1 of 8 time delays between 50µs and 13 seconds. The use of time delay can allow overheated components to drop in temperature before a retry is attempted. After a fault, all sequenced enable outputs turn off immediately. FAULTB pulls low if required. Automatic retries are allowed after the time period specified in b[7:5]. Automatic retries do not occur in the case of CONTROL faults, however CONTROL faults can occur during retry operations. If desired, retries may require both discharge and time delay. The combined discharge and time delay feature is only available when using automatic retries. The FAULT_RESPONSE register reports the number of retries attempted in b[13:11]. The count is updated when the retry criteria discussed above are met. In a system with multiple LTC2937s, retry counts can differ among devices if some devices have met retry criteria and others have not. If the number of retries allowed is unlimited, the retry counter reports a value of zero. Avoid changing the allowed number of retries while sequencing control is in the sequence-up state to prevent unintended operation. To safely change configuration, place sequencing control into the sequence-down state, perform a CLEAR operation and then make changes to the retry number. Systems that experience complete shutdown after a fault can be difficult to debug because the power is gone. The continue and freeze fault response actions can be useful when debugging system problems, because power supplies remain on, allowing for meaningful measurements. However, use caution when applying the continue and freeze modes because some loads are highly sensitive to the applied supply voltages and, if one or more voltages are incorrectly applied, damage to a load may result. In the continue mode, there is no shutdown except in the case of a CONTROL fault. Information is logged to status registers and a FAULTB output is generated, but shutdown procedures do not take place. EXTERNAL faults are ignored. SPCLK attempts to operate, so a complete sequence-up process can occur even if one or more supplies have a problem. To prepare for restart after a fault in continue mode, bring the ON input to the sequence-down state and perform a CLEAR operation. 2937f 44 For more information www.linear.com/LTC2937 LTC2937 APPLICATIONS INFORMATION In the freeze mode, fault information is logged to status registers and a FAULTB output is generated, but shutdown procedures do not take place. If the fault occurs during sequencing, SPCLK stops and does not advance further. SHARE_CLK continues to operate normally. ON input state changes are ignored after the original fault. If both freeze mode and continue mode are selected, freeze mode takes precedence. Exit from a freeze condition by setting b[8] = 0 in the FAULT_RESPONSE register (provided that continue mode is not selected) or perform a CLEAR operation. These actions cause enable outputs to pull low, returning the system to a shut-down state. Fault Debugging Tools While STATUS_INFORMATION, FAULT_RESPONSE, MONITOR_STATUS_HISTORY, MONITOR_STATUS and MONITOR_BACKUP provide insight into system behavior, additional commands and functions are available to assist with system debug. These include: • BREAK_POINT (0x2A) • SEQ_POSITION_COUNT (0x2B) • SMBus Alert Response Address The break point feature holds the system at user specified sequence positions during SPCLK low periods. Set sequence position break points in the sequence-up or sequence-down phase of operation. Enable break point usage with bp_enable b[10]. With break point usage enabled, a valid control input (ON transition or I2C command) will sequence the device until sp_count in the SEQ_POSITION_COUNT register is equal to bp_value in the BREAK_POINT register. Perform register inspections and system measurements at each paused sequence position. Increment the BREAK_POINT register repeatedly for controlled single stepping through all sequence positions. SPCLK holds low until bp_value is changed to be not equal to sp_count or bp_enable is set low. The sequencing enable delay timers and maximum rise/fall timers function normally at each sequence position. Knowing the sequence position after a fault can help identify problems. Read the current sequence position count contained in the sp_count bit field of the SEQ_ POSITION_COUNT register. The sp_count bit field is zero after initial application of device power or after a CLEAR command. At the conclusion of all sequence-up or sequence-down operations, sp_count increments by one. For example, if the last configured sequence position is 10, sp_count increments to 11 when the sequencing operation completes. If the last sequence position is 1023, sp_count rolls over to zero at the end of sequencing. After a fault (whether in break point mode or normal operation), the current sequence position value is reported until the fault exit conditions are satisfied. The ALERTB output pulls low in response to any fault. Connect ALERTB as an interrupt to a host processor. The host can access all devices through the Alert Response Address. Only the devices which asserted their ALERTB will acknowledge the Alert Response Address. If more than one device is alerting, the device with the lowest address will return its address as data. After acknowledging the slave address, the slave device releases pull-down on ALERTB. If the host recognizes that ALERTB remains low due to another device, it can read the alert response address again. The ALERTB output pull-down may also be removed by performing a read from the CLEAR_ALERTB register. All other status information remains unaffected. The returned data word contains no useful information and the contents should be ignored. Faults may persist even though ALERTB is cleared. Share Clock (SHARE_CLK) Synchronize multiple LTC2937s (and any other LTC device with a SHARE_CLK function) in an application by connecting together the open-drain SHARE_CLK input/ outputs to a pull-up resistor as a wired OR. A single 3.3k resistor is recommended. The fastest clock will take over and synchronize timing on all devices. Asynchronous Supply Control Any supply controlled by an LTC2937 enable output may be asynchronously commanded on or off. Activate this capability by setting the respective b[9:0] = 0 in SEQ_UP_POSITION_n or SEQ_DOWN_POSITION_n. To release the enable pull-down and turn on the controlled 2937f For more information www.linear.com/LTC2937 45 LTC2937 APPLICATIONS INFORMATION supply, write b[10] = 1 in SEQ_UP_POSITION_n. To shut off the supply, write b[10] = 0. A supply may be asynchronously turned on before or after sequence-up operations. It is not recommended to turn on supplies asynchronously during sequence-up operations. If a supply has been turned on before sequencing, its respective monitor input will be checked for UV compliance in sequence position 1. If the monitor input is not above its configured UV threshold before its respective ton_max time has elapsed (measured from the start of sequence position 1), a SEQUENCE fault is generated. The UV and OV comparator outputs from asynchronously enabled channels may be combined into the RSTB response. Furthermore, if the asynchronous channel is enabled prior to sequencing-up and combined into the RSTB response, it will also contribute to SUPERVISOR faults if the monitored voltage falls back below its UV threshold after sequence-up operations have started. If an asynchronous channel is enabled after sequencingup is complete, its UV and OV comparator outputs can still be combined into the RSTB response. However, the comparators will not contribute to SUPERVISOR faults. After sequence-down operations have completed, a CLEAR command must be issued prior to assigning any asynchronously operated channel a position in the sequencing order. To use the LTC2937 as a simple multi-channel voltage supervisor without sequencing, configure all contributing channels to be asynchronously enabled and configure unused channels for sequence position zero. Select channels to be combined into the RSTB and optional SUPERVISOR fault responses. LTpowerPlay: An Interactive GUI for Power System Management LTpowerPlay is a powerful Windows based development environment that supports Linear Technology power system manager ICs with EEPROM, including the LTC2937 6-channel sequencer and voltage supervisor. The software supports a variety of different tasks. You can use LTpowerPlay to evaluate Linear Technology ICs by connecting to a demo board system. LTpowerPlay can also be used in an offline mode (with no hardware present) in order to build a multichip configuration file that can be saved and reloaded at a later time. LTpowerPlay provides unprecedented diagnostic and debug features. It becomes a valuable diagnostic tool during board bring-up to program or tweak the power management scheme in a system or to diagnose power issues when bringing up rails. LTpowerPlay utilizes Linear Technology’s DC1613 USB-to-I2C/SMBus/PMBus Controller to communicate with one of many potential targets, including the DC2313 demo board set, the DC2347socketed programming board, or a customer target system. The software also provides an automatic update feature to keep the software current with the latest set of device drivers and documentation. A great deal of context sensitive help is available within LTpowerPlay along with several tutorial demos. Complete information is available at: www.linear.com/ltpowerplay. External Connection Design Checklist • Apply device power through VPWR or VDD and ground. If powered through VPWR, place 2.2µF (or greater) compensation capacitor between VDD and GND. • Tie unused Vn inputs to GND. • Have control of WP if needed for device programming. • Have control of ON if needed for sequencing. • Have control of MARGB if needed for voltage margining operations. • Use pull-up resistors to ENn as needed (10k to 100k). • Apply pull-up resistor to SHARE_CLK (3.3k to 10k) and connect to other SHARE_CLK nodes as needed. • Connect SPCLK to other SPCLK nodes as needed. Do not apply pull-up resistors. • Use pull-up resistors to RSTB, FAULTB and ALERTB as needed (10k to 100k). • If using I2C for programming and/or readback: • Configure device address with ASELn inputs. • Check addresses for collision with other devices on the I2C bus. • Verify logic level compatibility for all I/O between LTC2937 and other devices. 2937f 46 For more information www.linear.com/LTC2937 LTC2937 APPLICATIONS INFORMATION Minimum Connections for Programming Interconnect Between Multiple LTC2937s For users interested in performing their own programming, Figure 14 shows the minimum recommended connections for a programming socket. Make sure that the SCL and SDA levels match the VDD level. Set the software lock bit to 0 in the WRITE_PROTECTION register before writing new register values. Changing the software lock bit from a 1 to 0 requires matching the key string in b[15:2]. A socketed programming board is available for use with the LTpowerPlay system. Figure 15 shows how to interconnect the pins in a typical multi-LTC2937 array. In this example, device power is derived from an intermediate bus voltage. It is recommended that SPCLK, SHARE_CLK and ON are tied together. Optional interconnections include RSTB, FAULTB, MARGB, ALERTB, SDA and SCL. Connect FAULTB lines together with external fault listening enabled to allow any one fault to shut off all power supplies. The host controller asserts ON for sequencing control and listens to ALERTB to gain information about system faults. 2.9V ≤ VDD ≤ 5.5V 8-BIT DEVICE ADDRESS = 0x88 OR USE GLOBAL ADDRESS = 0x6C VPWR VDD SCL SDA System Event Based Sequencing LTC2937 SHARE_CLK ON WP GND 2937 F14 The schematic shown on the back page demonstrates how power sequences can be coordinated in a system of systems. A logic output from System 1 (READY) is used as a gating input to the sequence order. System 2 does not sequence-up until System 1 is qualified by the LTC2937. Figure 14. Programming Socket Connections 2937f For more information www.linear.com/LTC2937 47 LTC2937 APPLICATIONS INFORMATION TO HOST CONTROLLER SEQUENCE UP/DOWN CONTROL STATUS AND I2C CONTROL I/0 INTERFACE DC/DC CONVERTERS 12V VIN C3 0.1µF SDA SCL ALERTB R1 3.3k C1 2.2µF VPWR LTC2937 ON MARGB FAULTB RSTB SPCLK SHARE_CLK ASEL1 ASEL2 ASEL3 WP VDD GND EN1 EN2 EN3 EN4 EN5 EN6 RUN1 RUN2 RUN3 RUN4 RUN5 RUN6 GND OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 V1 V2 V3 V4 V5 V6 V1 V2 V3 V4 V5 V6 DC/DC CONVERTERS VIN C4 0.1µF SDA SCL ALERTB C2 2.2µF VPWR LTC2937 ON MARGB FAULTB RSTB SPCLK SHARE_CLK ASEL1 ASEL2 ASEL3 WP VDD GND EN1 EN2 EN3 EN4 EN5 EN6 RUN1 RUN2 RUN3 RUN4 RUN5 RUN6 GND OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 V7 V8 V9 V10 V11 V12 V1 V2 V3 V4 V5 V6 2937 F15 DEVICE HANDSHAKING TO OTHER DEVICES Figure 15. Typical Connections Between Multiple LTC2937s 2937f 48 For more information www.linear.com/LTC2937 LTC2937 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UHE Package 28-Lead Plastic QFN (5mm × 6mm) (Reference LTC DWG # 05-08-1932 Rev Ø) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 2.50 REF PACKAGE OUTLINE 3.65 ±0.05 4.65 ±0.05 0.25 ±0.05 0.50 BSC 3.50 REF 5.10 ±0.05 6.50 ±0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ±0.10 0.00 – 0.05 0.200 REF R = 0.10 TYP 2.50 REF 23 28 0.40 ±0.10 PIN 1 TOP MARK (SEE NOTE 6) 22 6.00 ±0.10 1 3.50 REF 4.65 ±0.10 3.65 ±0.10 15 8 (UHE28) QFN 1012 REV Ø 14 0.75 ±0.05 0.25 ±0.05 9 R = 0.125 TYP 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2937f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC2937 49 LTC2937 TYPICAL APPLICATION Coordinating Power Sequence in a System of Systems. System 2 Does Not Sequence Until System 1 Is Ready SYSTEM 1 VIN 12V 0.1µF VPWR V1 V2 V3 ON/OFF /MARGIN EN1 VCORE EN2 VIO EN3 (OPTIONAL) VCORE1 VIO1 GPI READY µP/FPGA ON MARGB GND LTC2937 V4 V5 V6 SYSTEM 2 VIN SHARE_CLK 3.3k VDD GND EN4 VCORE EN5 VIO EN6 FAULTB RSTB SPCLK 2.2µF VCORE2 VIO2 VAUX VAUX µP/FPGA GND CONNECT FOR EXPANSION VCORE1 VIO1 READY VCORE2 VIO2 VAUX SOME CONNECTIONS AND COMPONENTS OMITTED FOR CLARITY 2937 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2928 4-Channel Power Supply Sequencer and Supervisor Hardware Configurable Power Management LTC2933 Programmable Hex Voltage Supervisor with EEPROM Software Configurable Supply Monitoring LTC2936 Programmable Hex Voltage Supervisor with EEPROM and Comparator Outputs Software Configurable Supply Monitoring LTC2945 Wide Range I2C Power Monitor 2.7V to 80V, ±0.75% Total Unadjusted Error LTC2946 Wide Range I2C Power/Charge/Energy Monitor 2.7V to 100V, ±0.4% Total Unadjusted Error LTC2970 Dual I2C Power Supply Monitor and Margining Controller 4.5V to 15V, 0.5% TUE 14-bit ADC, 8-bit DAC, Temperature Sensor LTC2974 4-Channel PMBus Power System Manager 0.25% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and Supervision LTC2977 8-Channel PMBus Power System Manager 0.25% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and Supervision LTC3880 Dual Output PolyPhase® Step-Down DC/DC Controller 0.5% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and Supervision LTC3883 Single Output PolyPhase Step-Down DC/DC Controller 0.5% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and Supervision LTC4151 High Voltage I2C Current and Voltage Monitor 7V to 80V, 12-bit Resolution 2937f 50 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2937 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2937 LT 0915 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2015