DATASHEET

5962-0623601, 5962-0623602
DESIGNS
DED FOR NEW
N
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CEMENT
NDED REPLA
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Data
Sheet
3, 2011
at
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N
t CenterNovember
chnical Suppor com/tsc
Te
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ou
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ac
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co
rsil.
IL or www.inte
1-888-INTERS
670MHz Low Noise Amplifiers
Features
The 5962-0623601QPC and 5962-0623602QPC are fully
DLA SMD compliant parts and the SMD data sheets are
available on the DLA website
(http://www.landandmaritime.dla.mil/Programs/MilSpec/Doc
Search.aspx). The 5962-0623601QPC is electrically
equivalent to the EL5132 and the 5962-0623602QPC is
electrically equivalent to the EL5133, reference these data
sheets for additional information. These amplifiers are
ultra-low voltage noise, high speed, low power
consumption voltage feedback amplifiers.
• 670MHz -3dB bandwidth
Both amplifiers are stable at gains as low as 10. Not only do
these devices find perfect application in high gain
applications, they maintain their performance down to lower
gain settings.
Applications
These amplifiers are available in SBDIP packages. All parts
are specified for operation over the -55°C to +125°C
temperature range.
• Filter
Ordering Information
• DAC buffers
PART
NUMBER
PART
MARKING TEMP (°C) PACKAGE
PKG.
DWG.
#
5962-0623601QPC 5962-0623
601QPC
-55 to +125 8 Ld SBDIP D8.3
5962-0623602QPC 5962-0623
602QPC
-55 to +125 8 Ld SBDIP D8.3
FN6473.1
• Ultra low noise 0.9nV/Hz
• 1000V/µs slew rate
• Low supply current = 16mA
• Single supplies from 5V to 12V
• Dual supplies from ±2.5V to ±6V
• Fast disable on the 5962-0623601QPC
• Pre-amplifier
• Receiver
• IF and baseband amplifier
• ADC drivers
• Instrumentation
• Communications devices.
Pinouts
5962-0623601QPC
(8 LD SBDIP)
TOP VIEW
NC 1
IN- 2
IN+ 3
8 CE
+
VS- 4
7 VS+
6 OUT
5 NC
5962-0623602QPC
(8 LD SBDIP)
TOP VIEW
NC 1
IN- 2
IN+ 3
VS- 4
1
8 NC
+
7 VS+
6 OUT
5 NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007, 2011. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
5962-0623601, 5962-0623602
Absolute Maximum Ratings (TA = +25°C)
Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . .
Slewrate between VS+ and VS- . . . . . . . . . . . . . . . . . . . . . . . .
IIN-, IIN+, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . .-55°C to +125°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192mW
13.2V
1V/µs
±5mA
20mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 500, RF = 10k, RG = 100, TA = +25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
RIN
Input Resistance
CIN
Input Capacitance
BW
-3dB Bandwidth
BW
±0.1dB Bandwidth
GBWP
Gain Bandwidth Product
PM
Phase Margin
RL = 1k, CL = 6pF
SR
Slew Rate
RL = 100, VOUT = ±2.5V
tR, tF
Rise Time, Fall Time
OS
Overshoot
tS
0.01% Settling Time
dG
Differential Gain
dP
MIN
Common mode
TYP
MAX
UNIT
5
M
2
pF
RF = 225AV = +10, RL = 1k
670
MHz
RF = 225AV = +10, RL = 1k
90
MHz
3000
MHz
55
°
1000
V/µs
±0.1VSTEP
2.0
ns
±0.1VSTEP
10
%
6.6
ns
RF = 1kRLOAD = 150
0.01
%
Differential Phase
RF = 1kRLOAD = 150
0.01
°
eN
Input Noise Voltage
f = 10kHz
0.9
nV/Hz
iN
Input Noise Current
f = 10kHz
3.5
pA/Hz
ENABLE (5962-0623601QPC Only)
tEN
Enable Time
220
nS
tDIS
Disable Time
175
nS
Pin Descriptions
PART
5962-0623601QPC
5962-0623602QPC
PIN NAME
1, 5
1, 5, 8
NC
Not connected
2
2
IN-
Inverting input
3
3
IN+
Non-inverting input
4
4
VS-
Negative power supply
6
6
OUT
Amplifier output
7
7
VS+
Positive power supply
CE
Enable and disable input
8
2
FUNCTION
FN6473.1
November 3, 2011
5962-0623601, 5962-0623602
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1
-A-
D8.3 MIL-STD-1835 CDIP2-T8 (D-4, CONFIGURATION C)
LEAD FINISH
8 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
-DBASE
METAL
E
b1
M
(b)
M
-Bbbb S C A - B S
(c)
SECTION A-A
D S
D
BASE
PLANE
Q
S2
-C-
SEATING
PLANE
A
L
S1
eA
A A
b2
b
e
eA/2
c
aaa M C A - B S D S
ccc M C A - B S D S
NOTES:
INCHES
SYMBOL
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.405
-
10.29
-
E
0.220
0.310
5.59
7.87
-
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
5
S1
0.005
-
0.13
-
6
S2
0.005
-
0.13
-
7

90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
N
8
8
5. Dimension Q shall be measured from the seating plane to the
base plane.
8
Rev. 0 4/94
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
3
FN6473.1
November 3, 2011
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