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1-888-
HA-5170
®
November 2004
FN2912.5
8MHz, Precision, JFET Input
Operational Amplifier
Features
The Intersil HA-5170 is a precision, JFET input, operational
amplifier which features low noise, low offset voltage and
low offset voltage drift. Constructed using FET/Bipolar
technology, the Intersil Dielectric Isolation (DI) process, and
laser trimming this amplifier offers low input bias and offset
currents. This operational amplifier design also completely
eliminates the troublesome errors due to warm-up drift.
• Low Offset Voltage Drift . . . . . . . . . . . . . . . . . . . . . 2µV/oC
• Low Offset Voltage. . . . . . . . . . . . . . . . . . . . . . . . . .100µV
• Low Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10nV/ Hz
• High Open Loop Gain . . . . . . . . . . . . . . . . . . . . . 600kV/V
• Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8MHz
• Unity Gain Stable
Complementing these excellent input characteristics are
dynamic performance characteristics never before available
from precision operational amplifiers. An 8V/µs slew rate and
8MHz bandwidth allow the designer to extend precision
instrumentation applications in both speed and bandwidth.
These characteristics make the HA-5170 well suited for
precision integrator amplifier designs.
Applications
The superior input characteristics also make the HA-5170
ideally suited for transducer signal amplifiers, precision
voltage followers and precision data acquisition systems.
For application assistance, please refer to Application Note
AN540 addressing specifically this device.
• For Further Design Ideas, Refer to Application Note 540
• High Gain Instrumentation Amplifiers
• Precision Data Acquisition
• Precision Integrators
• Precision Threshold Detectors
Part Number Information
PART NUMBER
HA7-5170-5
Pinout
TEMP.
RANGE (oC)
0 to 75
PACKAGE
8 Ld CERDIP
PKG.
NO.
F8.3A
HA-5170
(CERDIP)
TOP VIEW
BAL
1
-IN-
2
+IN
3
V-
4
8 NC
7 V+
+
6 OUT
5 BAL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HA-5170
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 44V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Output Short Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . .
115
28
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range
HA-5170-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
VSUPPLY = ±15V, Unless Otherwise Specified
Electrical Specifications
HA-5170-5
TEST
CONDITIONS
TEMP.
(oC)
MIN
TYP
MAX
UNITS
25
-
0.1
0.3
mV
Full
-
-
0.5
mV
Average Offset Voltage Drift (Note 3)
Full
-
2
5
µV/oC
Bias Current
25
-
20
100
pA
Full
-
0.1
2
nA
Bias Current Average Drift
Full
-
3
-
pA/oC
Offset Current
25
-
3
60
pA
Full
-
-
0.1
nA
Offset Current Average Drift (Note 3)
Full
-
0.3
1
pA/oC
Common Mode Range
Full
±10
+15.1
-
V
Full
-
-12
-
V
Differential Input Capacitance
25
-
80
100
pF
Differential Input Resistance (Note 3)
25
1 x 1010
6 x 1010
-
Ω
Input Capacitance (Single Ended)
25
-
12
-
pF
PARAMETER
INPUT CHARACTERISTICS
Offset Voltage
Input Noise Voltage (Note 3)
0.1Hz to10Hz
25
-
0.5
5
µVP-P
Input Noise Voltage Density (Note 3)
f = 10Hz
25
-
20
150
nV/ Hz
f = 100Hz
25
-
12
50
nV/ Hz
f = 1000Hz
25
-
10
25
nV/ Hz
f = 10Hz
25
-
0.05
-
pA/ Hz
f = 100Hz
25
-
0.01
-
pA/ Hz
f = 1000Hz
25
-
0.01
0.1
pA/ Hz
Input Noise Current Density (Note 3)
2
HA-5170
VSUPPLY = ±15V, Unless Otherwise Specified (Continued)
Electrical Specifications
HA-5170-5
TEST
CONDITIONS
TEMP.
(oC)
MIN
TYP
MAX
UNITS
25
300
600
-
kV/V
Full
250
-
-
kV/V
Full
90
100
-
dB
25
1
-
-
V/V
AVCL = +1
25
4
8
-
MHz
Output Voltage Swing
RL = 2kΩ
25
±10
±12
-
V
Full Power Bandwidth (Note 4)
RL = 2kΩ
25
80
120
-
kHz
Output Current (Note 5)
VOUT = ±10V
25
±10
±15
-
mA
Output Resistance (Note 3)
Open Loop, 100Hz
25
-
45
100
Ω
Rise Time
Note 2
25
-
45
100
ns
Slew Rate
Note 2
25
5
8
-
V/µs
25
-
1
5
µs
Supply Current
Full
-
1.9
2.5
mA
Power Supply Rejection Ratio (Note 7)
Full
90
105
-
dB
PARAMETER
TRANSFER CHARACTERISTICS
VOUT = ±10V,
RL = 2kΩ
Large Signal Voltage Gain
∆VCM = ±10V
Common Mode Rejection Ratio
Minimum Stable Gain
Closed Loop Bandwidth
OUTPUT CHARACTERISTICS
TRANSIENT RESPONSE
Settling Time (Notes 3, 6)
POWER SUPPLY CHARACTERISTICS
NOTES:
2. See “Test Circuits and Waveforms” section.
3. Parameter is not 100% tested. 90% of all units meet or exceed these specifications.
Slew Rate
4. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = ----------------------------- .
2πV PEAK
5. I
turns on at ≅ 23mA.
SC
6. Settling time is measured to 0.1% of final value for a 10V output step and AV = -1.
7. V+ = +15V, V- = -10V to -20V and V- = -15V, V+ = +10V to +20V.
Test Circuits and Waveforms
V+
7
3
+
IN
6
OUT
2
-
5
+
OUT
2kΩ
50pF
1
4
100kΩ
V-
Tested Offset Adjustment Range is |VOS + 1mV| minimum referred to
output. Typical range is ±5mV with RT = 1kΩ and ±15mV with
RT = 100kΩ.
FIGURE 1. VOS ADJUSTMENT
3
FIGURE 2. LARGE AND SMALL SIGNAL RESPONSE CIRCUIT
HA-5170
Test Circuits and Waveforms
(Continued)
Vertical Scale: 5V/Div.
Horizontal Scale: 1µs/Div.
Vertical Scale: 10mV/Div.
Horizontal Scale: 100ns/Div.
LARGE SIGNAL RESPONSE
SMALL SIGNAL RESPONSE
+15V
100Ω
3
7
+
100Ω
6
3.5kΩ
OUT
2
4
-15V
2.5MΩ
4.7µF
≅ 10Hz FILTER
AV = 25,000
FIGURE 3.
LOW FREQUENCY NOISE TEST CIRCUIT
4
Vertical Scale: 200nV/Div. (Noise Referred to Input)
5mV/Div. at Output, AVCL = 25,000
Horizontal Scale: 1s/Div.
HA-5170 LOW FREQUENCY NOISE (0.1HZ TO 10HZ)
Schematic Diagram
V+
R13
Q48
Q44
R12
Q23
Q46
R9
R10
R6
R5
R11
R20
Q36
Q19
Q14
Q43
Q21
Q42
5
R14
Q3
J4
Q47
Q33
Q16
Q15
Q4
Q45
D1
Q31
NC
Q32
Q24
-INPUT
D5
J5
J1
+INPUT
J2
C1
Q8
Q7
R18
R8
J3
Q37
D3
D4
Q35
D2
Q11
Q22
Q30
Q13
R7
HA-5170
R16
OUT
Q25
Q28
R17
R19
Q10
Q26
Q29
Q27
Q12
C3
Q9
Q21
Q51
Q34
R23
Q6
R24
Q40
Q18
Q38
Q39
Q1
Q41
Q5
C2
R3
Q49
BAL
R15
R4
R21
Q50
BAL
Q20
Q17
R22
R1
Q52
R2
V-
HA-5170
Typical Performace Curves
1000
0.6
0.1
INPUT NOISE CURRENT
10
0.01
INPUT NOISE VOLTAGE
0.4
OFFSET VOLTAGE (mV)
100
INPUT NOISE CURRENT (pA/√Hz)
INPUT NOISE VOLTAGE (nV/√Hz)
0.5
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
1
1
10
100
1K
FREQUENCY (Hz)
10K
0.001
100K
FIGURE 4. INPUT NOISE vs FREQUENCY
-0.6
-55
-25
0
25
50
75
TEMPERATURE (oC)
100
125
FIGURE 5. OFFSET VOLTAGE DRIFT vs TEMPERATURE OF
REPRESENTATIVE UNITS
10
10mV
1
1mV
5
IBIAS (nA)
OUTPUT VOLTAGE STEP (V)
10
0
1mV
0.1
-5
0.01
10mV
-10
0
0.5
1
0.001
-50
1.5
-25
SETTLING TIME (µs)
FIGURE 6. SETTLING TIME FOR VARIOUS OUTPUT STEP
VOLTAGES
25
50
75
TEMPERATURE (oC)
100
125
FIGURE 7. BIAS CURRENT vs TEMPERATURE
1.2
2
NORMALIZED PARAMETERS REFERRED
TO PARAMETERS AT 25oC
3
SUPPLY CURRENT (mA)
0
125oC
25oC
-55oC
1
±5
±10
±15
SUPPLY VOLTAGE (V)
±20
FIGURE 8. POWER SUPPLY CURRENT vs SUPPLY VOLTAGE
6
1.1
BANDWIDTH
1.0
SLEW RATE
0.9
0.8
-55
-25
0
25
50
75
100
125
TEMPERATURE (oC)
FIGURE 9. NORMALIZED AC PARAMETERS vs TEMPERATURE
HA-5170
Typical Performace Curves
(Continued)
120
120
PSRR+
100
CMRR (dB)
PSRR (dB)
100
80
PSRR-
60
80
60
40
40
20
20
10
100
1K
10K
FREQUENCY (Hz)
100K
1M
10
FIGURE 10. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
5
40
4
BANDWIDTH
3
2
20
PHASE MARGIN
1
10
0
10
0
100
1000
10000
LOAD CAPACITANCE (pF)
FIGURE 12. SMALL SIGNAL BANDWIDTH AND PHASE MARGIN
vs LOAD CAPACITANCE
7
OUTPUT VOLTAGE SWING (VP-P)
50
UNITY GAIN BANDWIDTH (MHz)
PHASE MARGIN (DEGREES)
6
30
1K
10K
FREQUENCY (Hz)
100K
1M
FIGURE 11. COMMON MODE REJECTION RATIO vs
FREQUENCY
RL = 2kΩ
60
100
RL = 2kΩ
CL = 50pF
28
±15V SUPPLIES
24
20
±10V SUPPLIES
16
8
±5V SUPPLIES
4
0
1K
10K
100K
FREQUENCY (Hz)
1M
FIGURE 13. OUTPUT VOLTAGE SWING vs FREQUENCY AND
SUPPLY VOLTAGE
HA-5170
Typical Performace Curves
(Continued)
35
OUTPUT VOLTAGE SWING (VP-P)
TA = 25oC
NORMALIZED AC PARAMETERS
REFERRED TO VALUE AT ±15V
1.0
BANDWIDTH
0.8
0.6
0.4
SLEW RATE
0.2
0
±2
±4
±6
±8
±10
±12
±14
±16
30
VS = ±15V
25
20
VS = ±10V
15
10
VS = ±5V
5
0
100
±18 ±20
1K
SUPPLY VOLTAGE (V)
10K
100K
LOAD RESISTANCE (Ω)
FIGURE 14. NORMALIZED AC PARAMETERS vs SUPPLY
VOLTAGE
FIGURE 15. MAXIMUM OUTPUT VOLTAGE SWING vs LOAD
RESISTANCE
110
RL = 2kΩ
CL = 50pF
100
80
0
GAIN
70
60
45
50
40
90
PHASE
30
20
135
CLOSED LOOP GAIN (dB)
90
PHASE (DEGREES)
OPEN LOOP VOLTAGE GAIN (dB)
100
80
60
40
20
10
180
0
-10
10
100
1K
10K
100K
1M
FREQUENCY (Hz)
10M
100M
FIGURE 16. OPEN LOOP FREQUENCY RESPONSE
8
0
10
100
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 17. CLOSED LOOP FREQUENCY RESPONSE FOR
VARIOUS CLOSED LOOP GAINS
HA-5170
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
LEAD FINISH
c1
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.405
-
10.29
5
E
0.220
0.310
5.59
7.87
5
eA
e
ccc M
C A-B S
eA/2
c
aaa M C A - B S D S
D S
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
8
8
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
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