DATASHEET

EL7154
Data Sheet
November 23, 2015
High Speed, Monolithic Pin Driver
Features
The EL7154 three-state pin driver is particularly well suited
for ATE and level shifting applications. The 4A peak drive
capability, makes the EL7154 an excellent choice when
driving high speed capacitive lines.
• Comparatively low cost
The P-Channel MOSFET is completely isolated from the
power supply, providing a high degree of flexibility. Pin (7)
can be grounded, and the output can be taken from pin (8)
when a “source follower” output is desired. The N-Channel
MOSFET has an isolated drain, but shares a common bus
with pre-drivers and level shifter circuits. This is necessary to
ensure that the N-Channel device can turn off effectively
when VL goes below GND. In some power-FET and IGBT
applications, negative drive is desirable to insure effective
turn-off. The EL7154 can be used in these applications by
returning VL to a moderate negative potential.
• Clocking speeds up to 10MHz
FN7278.4
• Three-State output
• 3V and 5V Input compatible
• 20ns Switching/delay time
• 4A Peak drive
• Isolated drains
• Low output impedance: 2.5
• Low quiescent current: 5mA
• Wide operating voltage: 4.5V to16V
• Isolated P-Channel device
• Separate ground and VL pins
Pinout
• Pb-free available (RoHS compliant)
EL7154
(8 LD PDIP, 8 LD SOIC)
TOP VIEW
Applications
• Loaded circuit board testers
VDD
1
VH
• Digital testers
8
• Level shifting below GND
• IGBT drivers
THREE-STATE
2
3
• CCD drivers
POUT
LEVEL
SHIFT
AND
LOGIC
VL
7
6
INPUT
NOUT
4
5
GND
VL
VL
Truth Table
THREE-STATE
INPUT
POUT
NOUT
0
0
Open
Open
0
1
Open
Open
1
0
HIGH
Open
1
1
Open
LOW
Manufactured under U.S. Patent Nos. 5,334,883, #5,341,047,
#5,352,578, #5,352,389, #5,351,012, #5,374,898
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC
Copyright Intersil Americas LLC 1996, 2005, 2007, 2010, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL7154
Ordering Information
PART
NUMBER
PART
MARKING
PKG.
DWG. #
PACKAGE
EL7154CNZ (No longer available,
recommended replacement:
EL7154CSZ)
EL7154CN Z
8 Ld PDIP* (Pb-free)
MDP0031
EL7154CSZ (See Note)
7154CSZ
8 Ld SOIC (Pb-free)
M8.15E
EL7154CSZ-T7** (See Note)
7154CSZ
8 Ld SOIC (Pb-free)
M8.15E
EL7154CSZ-T13** See Note)
7154CSZ
8 Ld SOIC (Pb-free)
M8.15E
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
**Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
Nominal Operating Voltage Range
PIN
MIN
MAX
VL
-3
0
VDD to VL
5
15
VH to VL
2
15
-0.5
15
5
15
VDD to VH
VDD
2
FN7278.4
November 23, 2015
EL7154
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply (VDD to VL; VH to VL, VH to GND),
V+ to VH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V
VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V
Input Pins . . . . . . . . . . . . . . . . . -0.3V below VL to +0.3V above VDD
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Power Dissipation
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW
PDIP* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. Limits established by characterization and are not production tested.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER
TA = +25°C, VDD = +12V, VH = +12V, VL = -3V, unless otherwise specified.
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX
UNITS
INPUT
VIH
Logic “1” Input Voltage
IIH
Logic “1” Input Current
VIL
Logic “0” Input Voltage
IIL
Logic “0” Input Current
VHVS
Input Hysteresis
2.4
VIH = VDD
V
0.1
VIL = 0V
0.1
10
µA
0.6
V
10
µA
0.3
V
OUTPUT
ROH
Pull-Up Resistance
IOUT = -100mA
1.5
4

ROL
Pull-Down Resistance
IOUT = +100mA
2
4

IOUT
Output Leakage Current
VDD/GND
0.2
10
µA
IPK
Peak Output Current
Source/Sink
4.0
IDC (Note 1)
Continuous Output Current
Source/Sink
IS
Power Supply Current
Inputs = VDD
VS
Operating Voltage
IG
Current to GND (Pin 4)
IH
Off Leakage at VH
A
200
mA
POWER SUPPLY
AC Electrical Specifications
PARAMETER
1
2.5
mA
16
V
1
10
µA
1
10
µA
TYP
MAX
UNITS
CL = 100pF
4
25
ns
CL = 2000pF
20
CL = 100pF
4
CL = 2000pF
20
CL = 2000pF
20
4.5
Pin 8 = 0V
TA = +25°C unless otherwise specified.
DESCRIPTION
TEST CONDITIONS
MIN
SWITCHING CHARACTERISTICS (VDD = VH = 12V; VL = -3V)
tR (Note 1)
Rise Time
tF (Note 1)
Fall Time
tD-1 (Note 1)
Turn-Off Delay Time
3
ns
25
ns
25
ns
ns
FN7278.4
November 23, 2015
EL7154
AC Electrical Specifications
PARAMETER
TA = +25°C unless otherwise specified. (Continued)
DESCRIPTION
TEST CONDITIONS
CL = 2000pF
MIN
TYP
MAX
UNITS
10
tD-2 (Note 1)
Turn-On Delay Time
25
ns
tD-1 (Note 1)
Three-State Delay
25
ns
tD-2 (Note 1)
Three-State Delay
25
ns
Timing Table
Standard Test Configuration
4
FN7278.4
November 23, 2015
EL7154
Typical Performance Curves
FIGURE 1. MAX POWER DERATING CURVES
FIGURE 2. SWITCH THRESHOLD vs SUPPLY VOLTAGE
FIGURE 3. INPUT CURRENT vs VOLTAGE
FIGURE 4. PEAK DRIVE vs SUPPLY VOLTAGE
FIGURE 5. QUIESCENT SUPPLY CURRENT
FIGURE 6. “ON” RESISTANCE vs SUPPLY VOLTAGE
FIGURE 7. AVERAGE SUPPLY CURRENT vs VOLTAGE AND
FREQUENCY
5
FIGURE 8. RISE/FALL TIME vs LOAD
FN7278.4
November 23, 2015
EL7154
Typical Applications
FIGURE 9. PIN DRIVER
FIGURE 10. ADJUSTABLE AMPLITUDE PULSE GENERATOR
FIGURE 11. IGBT DRIVER WITH NEGATIVE SWING
FIGURE 12. PMDS FOLLOWER
FIGURE 13. RESONANT GATE DRIVER
6
FN7278.4
November 23, 2015
EL7154
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
November 23, 2015
FN7278.4
CHANGE
- Updated Ordering Information Table on page 2.
- Added Revision History.
- Added About Intersil Verbiage.
-Changed POD MDP0027 to POD M8.15E.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
7
FN7278.4
November 23, 2015
EL7154
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
8
FN7278.4
November 23, 2015
EL7154
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
9
FN7278.4
November 23, 2015
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