DATASHEET

EL7158
®
Data Sheet
May 14, 2007
FN7349.2
Ultra-High Current Pin Driver
Features
The EL7158 high performance pin
driver with three-state is suited to
many ATE and level-shifting
applications. The 12A peak drive capability makes this part
an excellent choice when driving high capacitance loads.
• Clocking speeds up to 40MHz
The output pin OUT is connected to input pins VH or VL
respectively, depending on the status of the IN pin. When the
OE pin is active low, the output is placed in the three-state
mode. The isolation of the output FETs from the power
supplies enables VH and VL to be set independently,
enabling level-shifting to be implemented. Related to the
EL7155, the EL7158 adds a lower supply pin VS- and makes
VL an isolated and independent input. This feature adds
applications flexibility and improves switching response due
to the increased enhancement of the output FETs.
• 3.5pF typical input capacitance
• 12ns tR/tF at 2000pF CLOAD
• 0.2ns rise and fall times mismatch
• 0.5ns tON-tOFF prop delay mismatch
• 12A peak drive
• Low ON-resistance of 0.5Ω
• High capacitive drive capability
• Operates from 4.5V to 12V
• Pb-free plus anneal available (RoHS compliant)
Applications
This pin driver has improved performance over existing pin
drivers. It is specifically designed to operate at voltages
down to 0V across the switch elements while maintaining
good speed and ON-resistance characteristics.
• ATE/burn-in testers
Available in the 8 Ld SOIC package, the EL7158 is specified
for operation over the full -40°C to +85°C temperature range.
• CCD drivers
Pinout
OE 2
IN 3
8 VH
L
O
G
I
C
7 OUT
6 VL
5 VS-
GND 4
• IGBT drivers
Ordering Information
PART
NUMBER
EL7158
(8 LD SOIC)
TOP VIEW
VS+ 1
• Level shifting
PART
MARKING
PACKAGE
TAPE &
REEL
PKG.
DWG. #
EL7158IS
7158IS
8 Ld SOIC
-
MDP0027
EL7158IS-T7
7158IS
8 Ld SOIC
7”
MDP0027
EL7158IS-T13
7158IS
8 Ld SOIC
13”
MDP0027
EL7158ISZ
(Note)
7158ISZ
8 Ld SOIC
(Pb-free)
-
MDP0027
EL7158ISZ-T7
(Note)
7158ISZ
8 Ld SOIC
(Pb-free)
7”
MDP0027
EL7158ISZ-T13 7158ISZ
(Note)
8 Ld SOIC
(Pb-free)
13”
MDP0027
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2004, 2007. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL7158
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.3V, VS +0.3V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +12V, VH = +12V, VL = 0V, VS- = 0V, TA = +25°C, unless otherwise specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
INPUT
VIH
Logic ‘1’ Input Voltage
IIH
Logic ‘1’ Input Current
VIL
Logic ‘0’ Input Voltage
IIL
Logic ‘0’ Input Current
CIN
Input Capacitance
3.5
pF
RIN
Input Resistance
50
MΩ
2.4
VIH = VS+
V
0.1
VIL = 0V
0.1
10
µA
0.8
V
10
µA
OUTPUT
ROVH
ON-Resistance VH to OUT
IOUT = -500mA
0.5
1
Ω
ROVL
ON-Resistance VL to OUT
IOUT = +500mA
0.5
1
Ω
IOUT
Output Leakage Current
OE = 0V, OUT = VH/VL
0.1
10
µA
IPK
Peak Output Current
(linear resistive operation)
Source
12
A
Sink
12
A
Continuous Output Current
Source/Sink
IS
Power Supply Current
Inputs = VS+
1.3
3
mA
IVH
Off Leakage at VH and VL
VH, VL = 0V
4
10
µA
IDC
500
mA
POWER SUPPLY
SWITCHING CHARACTERISTICS
tR
Rise Time
CL = 2000pF
12.0
ns
tF
Fall Time
CL = 2000pF
12.2
ns
tRFΔ
tR, tF Mismatch
CL = 2000pF
0.2
ns
td-1
Turn-Off Delay Time
CL = 2000pF
22.5
ns
td-2
Turn-On Delay Time
CL = 2000pF
22.0
ns
tdΔ
td-1-td-2 Mismatch
CL = 2000pF
0.5
ns
td-3
Three-State Delay Enable
22
ns
td-4
Three-State Delay Disable
22
ns
SR+
VOUT+ Slew Rate
RLOAD = 6Ω
800
V/µs
SR-
VOUT- Slew Rate
RLOAD = 6Ω
800
V/µs
2
FN7349.2
May 14, 2007
EL7158
Electrical Specifications
PARAMETER
VS+ = +12V, VH = +1.2V, VL = 0V, VS- = 0V, TA = +25°C, unless otherwise specified. (Continued)
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
INPUT
VIH
Logic ‘1’ Input Voltage
IIH
Logic ‘1’ Input Current
VIL
Logic ‘0’ Input Voltage
IIL
Logic ‘0’ Input Current
CIN
Input Capacitance
3.5
pF
RIN
Input Resistance
50
MΩ
2.0
VIH = VS+
V
0.1
VIL = 0V
0.1
10
µA
0.8
V
10
µA
OUTPUT
ROVH
ON-Resistance VH to OUT
IOUT = -500mA
0.5
1
Ω
ROVL
ON-Resistance VL to OUT
IOUT = +500mA
0.5
1
Ω
IOUT
Output Leakage Current
OE = 0V, OUT = VH/VL
0.1
10
µA
IPK
Peak Output Current
(linear resistive operation)
Source
1.2
A
Sink
1.2
A
Continuous Output Current
Source/Sink
IS
Power Supply Current
Inputs = VS+
1
2.5
mA
VH
Off Leakage at VH and VL
VH, VL = 0V
4
10
µA
IDC
500
mA
POWER SUPPLY
SWITCHING CHARACTERISTICS
tR
Rise Time
CL = 2000pF
11
ns
tF
Fall Time
CL = 2000pF
11
ns
tRFΔ
tR, tF Mismatch
CL = 2000pF
0
ns
td-1
Turn-Off Delay Time
CL = 2000pF
20.5
ns
td-2
Turn-On Delay Time
CL = 2000pF
20.0
ns
tdΔ
td-1-td-2 Mismatch
CL = 2000pF
0.5
ns
td-3
Three-State Delay Enable
20
ns
td-4
Three-State Delay Disable
20
ns
SR+
VOUT+ Slew Rate
RLOAD = 6Ω
80
V/µs
SR-
VOUT- Slew Rate
RLOAD = 6Ω
80
V/µs
3
FN7349.2
May 14, 2007
EL7158
Typical Performance Curves
T = +25°C
T = +25°C
2.0
INPUT VOLTAGE (V)
HIGH THRESHOLD
1.6
HYSTERESIS
1.4
1.2
LOW THRESHOLD
SUPPLY CURRENT (mA)
1.8
1.6
1.2
ALL INPUTS = GND
0.8
0.4
ALL INPUTS = VS+
1.0
0
5
10
5
12
12
10
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 1. INPUT THRESHOLD vs SUPPLY VOLTAGE
FIGURE 2. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
IOUT = 500mA, T = +25°C, VS+ = VH, VS- = VL = 0V
15
CL = 2000pF, T = +25°C, VS+ = VH, VS- = VL = 0V
RISE/FALL TIME (ns)
“ON” RESISTANCE (Ω)
0.8
VH TO VOUT
0.7
0.6
0.5
0.4
VOUT TO VL
5
7.5
10
14
tR
13
12
tF
11
12.5
5
6
SUPPLY VOLTAGE (V)
FIGURE 3. “ON”-RESISTANCE vs SUPPLY VOLTAGE (VS+)
CL = 2000pF, VS+ = VH = 12V, VS- = VL = 0V
30
9
10
11
12
CL = 2000pF, T = +25°C, VS+ = VH = 12V,
VS- = VL = 0V
28
16
ttR
r
14
12
tR
26
td1
24
td2
22
10
8
-50
8
FIGURE 4. RISE/FALL TIME vs SUPPLY VOLTAGE
DELAY TIME (ns)
RISE/FALL TIME (ns)
18
7
SUPPLY VOLTAGE (V)
20
0
50
100
150
TEMPERATURE (°C)
FIGURE 5. RISE/FALL TIME vs TEMPERATURE
4
5
6
7
8
9
10
11
12
SUPPLY VOLTAGE (V)
FIGURE 6. PROPAGATION DELAY vs SUPPLY VOLTAGE
FN7349.2
May 14, 2007
EL7158
Typical Performance Curves
26
(Continued)
CL = 2000pF, VS+ = VH = 12V, VS- = VL = 0V
70
VS+ = +12V, T = +25°C
RISE/FALL TIME (ns)
60
DELAY TIME (ns)
24
tD1
22
tD2
20
50
40
tF
30
20
tR
10
18
-50
-25
0
25
50
75
100
0
100
125
LOAD CAPACITANCE (pF)
TEMPERATURE (°C)
FIGURE 7. PROPAGATION DELAY vs TEMPERATURE
FIGURE 8. RISE/FALL TIME vs LOAD CAPACITANCE
VS+ = VH = 12V, VS- = VL = 0V, T = +25°C, f = 20kHz
100
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
5
10k
1k
4
3
2
1
CL = 1000pF, T = +25°C
VS+=12V
10
VS+=10V
1.0
VS+=5V
0
100
1k
0.1
10k
10k
100k
LOAD CAPACITANCE (pF)
FIGURE 9. SUPPLY CURRENT vs LOAD CAPACITANCE
10M
FIGURE 10. SUPPLY CURRENT vs FREQUENCY
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.0
1.4
POWER DISSIPATION (W)
0.9
POWER DISSIPATION (W)
1M
FREQUENCY (Hz)
0.8
0.7 625mW
0.6
θ
0.5
JA
=
0.4
SO
16
0.3
IC
8
0°
C/
W
0.2
0.1
0
1.2
1.0
909mW
0.8
θ
JA
0.6
0.4
=
SO
IC
11 8
0°
C/
W
0.2
0
0
25
75 85 100
50
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
5
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7349.2
May 14, 2007
EL7158
TABLE 1. TRUTH TABLE
TABLE 2. OPERATING VOLTAGE RANGE
OE
IN
OUT
PIN
MIN
MAX
0
0
Three-State
VS- to GND
-5
0
0
1
Three-State
VS+ to VS-
5
18
1
0
VH
VH to VL
0
12
1
1
VL
VS+ to VH
0
12
VS+ to GND
5
12
VL to VS-
0
12
Three-State Output
VL
VH
5V
INPUT 2.5V
0
INVERTED
OUTPUT
90%
10%
td2
td1
tF
tR
FIGURE 13. TIMING DIAGRAM
VH
VS+
4.7µF
0.1µF
VS+
4.7µF
10kΩ
1
0.1µF
2
OE
IN
3
GND
4
8
L
O
G
I
C
OUT
7
2000pF
6
5
0.1µF
VL
4.7µF
EL7158
0.1µF
VS-
4.7µF
FIGURE 14. STANDARD TEST CONFIGURATION
6
FN7349.2
May 14, 2007
EL7158
Pin Descriptions
PIN
NAME
FUNCTION
1
VS+
Positive Supply Voltage
2
OE
Output Enable
EQUIVALENT CIRCUIT
VS+
INPUT
VSCircuit 1
3
IN
Input
Reference Circuit 1
4
GND
Ground
5
VS-
Negative Supply Voltage
6
VL
Lower Output Voltage
7
OUT
Output
VH
VSVS+
VOUT
VSVSVL
Circuit 2
8
VH
High Output Voltage
VH
OE
VS+
IN
LEVEL
SHIFTER
GND
THREESTATE
CONTROL
OUT
VSVL
FIGURE 15. BLOCK DIAGRAM
7
FN7349.2
May 14, 2007
EL7158
Applications Information
Product Description
The EL7158 is a high performance 40MHz pin driver. It
contains two analog switches connecting VH and VL to OUT.
Depending on the value of the IN pin, one of the two
switches will be closed and the other switch open. An output
enable (OE) is also supplied which opens both switches
simultaneously.
Due to the topology of the EL7158, both the VH and VL pins
can be connected to any voltage between the VS+ and VSpins, but VH must be greater than VL in order to prevent
turning on the body diode at the output stage.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the
EL7158 drive capability is limited by the rise in die
temperature brought about by internal power dissipation. For
reliable operation die temperature must be kept below
TJMAX (+125°C). It is necessary to calculate the power
dissipation for a given application prior to selecting the
package type.
Power dissipation may be calculated:
2
2
PD = ( V S × I S ) + ( C INT × V S × f ) + ( C L × V OUT × f )
(EQ. 1)
where:
Three-State Operation
When the OE pin is low, the output is three-state (floating).
The output voltage is the parasitic capacitance’s voltage. It
can be any voltage between VH and VL, depending on the
previous state. At three-state, the output voltage can be
pushed to any voltage between VH and VL. The output
voltage can’t be pushed higher than VH or lower than VL
since the body diode at the output stage will turn on.
Supply Voltage Range and Input Compatibility
The EL7158 is designed for operation on supplies from 5V to
18V (4.5V to 18V maximum). Table 2 shows the
specifications for the relationship between the VS+, VS-, VH,
VL, and GND pins.
All input pins are compatible with both 3V and 5V CMOS
signals. With a positive supply (VS+) of 5V, the EL7158 is
also compatible with TTL inputs.
VS is the total power supply to the EL7158 (from VS+ to
GND)
VOUT is the swing on the output (VH - VL)
CL is the load capacitance
CINT is the internal load capacitance (100pF max)
IS is the quiescent supply current (3mA max)
f is frequency
Having obtained the application’s power dissipation, a
maximum package thermal coefficient may be determined,
to maintain the internal die temperature below TJMAX:
T JMAX – T MAX
θ JA = ----------------------------------------PD
(EQ. 2)
where:
TJMAX is the maximum junction temperature (+125°C)
Power Supply Bypassing
TMAX is the maximum operating temperature
When using the EL7158, it is very important to use adequate
power supply bypassing. The high switching currents
developed by the EL7158 necessitate the use of a bypass
capacitor between the supplies (VS+ and VS-) and GND
pins. It is recommended that a 2.2µF tantalum capacitor be
used in parallel with a 0.1µF low-inductance ceramic MLC
capacitor. These should be placed as close to the supply
pins as possible. It is also recommended that the VH and VL
pins have some level of bypassing, especially if the EL7158
is driving highly capacitive loads.
PD is the power dissipation calculated above
θJA thermal resistance on junction to ambient
θJA is 160°C/W for the SOIC8 package when using a
standard JEDEC JESD51-3 single-layer test board. If TJMAX
is greater than +125°C when calculated using Equation 2 ,
then one of the following actions must be taken:
Reduce θJA the system by designing more heat-sinking
into the PCB (as compared to the standard JEDEC
JESD51-3)
De-rate the application either by reducing the switching
frequency, the capacitive load, or the maximum operating
(ambient) temperature (TMAX)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
FN7349.2
May 14, 2007
EL7158
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
9
FN7349.2
May 14, 2007
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