DATASHEET

Radiation Hardened, SEE Hardened, Non-Inverting,
Quad CMOS Driver
ISL7457SRH
Features
The ISL7457SRH is a radiation hardened, SEE hardened, high
speed, non-inverting, quad CMOS driver. It is capable of running
at clock rates up to 40MHz and features 2A typical peak drive
capability and a nominal On-resistance of just 3.5. The
ISL7457SRH is ideal for driving highly capacitive loads, such as
storage and vertical clocks in CCD applications. It is also well
suited to level-shifting and clock-driving applications.
• Electrically screened to SMD 5962-08230
Each output of the ISL7457SRH can be switched to either the
high (VH) or low (VL) supply pins, depending on the related input
pin. The inputs are compatible with both 3.3V and 5V CMOS
logic. The output enable (OE) pin can be used to put the outputs
into a high-impedance state. This is especially useful in CCD
applications, where the driver should be disabled during
power-down.
The ISL7457SRH also features very fast rise and fall times, which
are typically matched to within 1ns. The propagation delay is also
matched between rising and falling edges to typically within
1.5ns.
The ISL7457SRH is available in a 16 Ld ceramic flatpack
package and specified for operation over the full -55°C to
+125°C ambient temperature range.
Related Literature
• QML qualified per MIL-PRF-38535 requirements
• Full mil-temp range operation . . . . . . . . . . TA = -55°C to +125°C
• Radiation hardness
- TID [50-300 rad(Si)/s] . . . . . . . . . . . . . . . . . . 10krad(Si) min
• SEE hardness
- LET (SEL and SEB Immunity) . . . . . . 40MeV/mg/cm2 min
- LET [SET = VOUT < 15V, t < 500ns] . . . 40MeV/mg/cm2
• 4 Channels
• Clocking speeds up to 40MHz
• 11ns/12ns typical tR/tF with 1nF Load (15V bias)
• 1ns typical rise and fall time match (15V bias)
• 1.5ns typical prop delay match (15V bias)
• Low quiescent current - < 1mA Typical
• Fast output enable function - 12ns typical (15V bias)
• Wide output voltage range
- 0V VL 8V
- 2.5V VH 16.5V
• 2A typical peak drive current (15V Bias)
• AN1458, Extending the TID Capability of the ISL7457SRH
• 3.5typical on-resistance (15V bias)
Applications
• Input level shifters
• 3.3V/5V CMOS compatible inputs
• CCD Drivers, Clock/line Drivers, Level-Shifters
VH
OE
VS+
INx
GND
LEVEL
SHIFTER
3-STATE
CONTROL
OUTx
VSVL
FIGURE 1. BLOCK DIAGRAM
June 9, 2014
FN6874.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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ISL7457SRH
Ordering Information
ORDERING SMD
NUMBER (Note 1)
PART NUMBER
(Note 2)
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
5962D0823001QXC
ISL7457SRHQF
-55 to +125
16 Ld Flatpack
k16.A
5962D0823001VXC
ISL7457SRHVF
-55 to +125
16 Ld Flatpack
k16.A
5962D0823001V9A
ISL7457SRHVX
-55 to +125
Die
ISL7457SRHF/PROTO
ISL7457SRHF/PROTO
-55 to +125
16 Ld Flatpack
ISL7457SRHX/SAMPLE
ISL7457SRHX/SAMPLE
-55 to +125
Die
k16.A
NOTES:
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
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FN6874.2
June 9, 2014
ISL7457SRH
Pin Configuration
ISL7457SRH
(16 LD FLATPACK)
TOP VIEW
INA
1
16
VS+
OE
2
15
OUTA
INB
3
14
OUTB
VL
4
13
NC
GND
5
12
VH
NC
6
11
OUTC
INC
7
10
OUTD
IND
8
9
VS-
Pin Descriptions
PIN NUMBER
PIN NAME
1
INA
FUNCTION
EQUIVALENT CIRCUIT
Input Channel A
VS+
VS+
INx
VS-
VS-
CIRCUIT 1
2
OE
Output enable
(Reference Circuit 1)
3
4
INB
Input Channel B
(Reference Circuit 1)
VL
Low voltage input pin
5
GND
6, 13
NC
No connection
7
INC
Input Channel C
(Reference Circuit 1)
8
IND
Input Channel D
(Reference Circuit 1)
9
VS-
10
OUTD
Input logic ground
Negative supply voltage
Output Channel D
VH
VS+
OUTx
VSVSVL
CIRCUIT 2
11
OUTC
12
VH
14
OUTB
15
OUTA
16
VS+
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Output Channel C
(Reference Circuit 2)
High voltage input pin
Output Channel B
(Reference Circuit 2)
Output Channel A
(Reference Circuit 2)
Positive supply voltage
FN6874.2
June 9, 2014
ISL7457SRH
Electrical Specifications
PARAMETER
Typical values reflect VS+ = VH = 5V, VS- = VL = 0V, OE = VS+, TA = +25°C unless otherwise specified.
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX
UNITS
INPUT
VIH
Logic “1” Input Voltage
IIH
Logic “1” Input Current
VIL
Logic “0” Input Voltage
IIL
Logic “0” Input Current
CIN
Input Capacitance
5.7
pF
RIN
Input Resistance
500
M
INx = VS+
INx = 0V
1.3
V
10
nA
1.23
V
-5
nA
OUTPUT
ROH
ON-Resistance VH to OUTx
INx = VS+, IOUTx = -100mA
8

ROL
ON-Resistance VL to OUTx
INx = 0V, IOUTx = +100mA
6

ILEAK+
Positive Output Leakage Current
INx = VS+, OE = 0V, OUTx = VS+
5
nA
ILEAK-
Negative Output Leakage Current
INx = VS+, OE = 0V, OUTx = VS-
-5
nA
IS+
VS+ Supply Current
INx = 0V and VS+
0.2
mA
IS-
VS- Supply Current
INx = 0V and VS+
-0.2
mA
IH
VH Supply Current
INx = 0V and VS+
0.1
µA
IL
VL Supply Current
INx = 0V and VS+
0.1
µA
POWER SUPPLY
SWITCHING CHARACTERISTICS
tR
Rise Time
INx = 0V to 4.5V step, CL = 1nF
23
ns
tF
Fall Time
INx = 4.5V to 0V step, CL = 1nF
20
ns
tRF
tR, tF Mismatch
CL = 1nF
3
ns
tD+
Turn-On Delay Time
INx = 0V to 4.5V step, CL = 1nF
20
ns
tD-
Turn-Off Delay Time
INx = 4.5V to 0V step, CL = 1nF
22
ns
tDD
tD+, tD- Mismatch
CL = 1nF
2
ns
tENABLE
Enable Delay Time
INx = VS+, OE = 0V to 4.5V step, RL = 1k
21
ns
tDISABLE
Disable Delay Time
INx = VS+, OE = 4.5V to 0V step, RL = 1k
46
ns
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June 9, 2014
ISL7457SRH
Electrical Specifications
PARAMETER
Typical values reflect VS+ = VH = 15V, VS- = VL = 0V, OE = VS+, TA = +25°C unless otherwise specified.
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX
UNITS
INPUT
VIH
Logic “1” Input Voltage
IIH
Logic “1” Input Current
VIL
Logic “0” Input Voltage
IIL
Logic “0” Input Current
CIN
RIN
1.63
V
10
nA
1.4
V
-5
nA
Input Capacitance
5.7
pF
Input Resistance
1.5
G
INx = VS+
INx = 0V
Output
ROH
ON Resistance VH to OUTx
INx = VS+, IOUTx = -100mA
3.5

ROL
ON Resistance VL to OUTx
INx = 0V, IOUTx = +100mA
3

ILEAK+
Positive Output Leakage Current
INx = VS+, OE = 0V, OUTx = VS+
15
nA
ILEAK-
Negative Output Leakage Current
INx = VS+, OE = 0V, OUTx = VS-
-15
nA
IS+
VS+ Supply Current
INx = 0V and VS+
0.8
mA
IS-
VS- Supply Current
INx = 0V and VS+
-0.8
mA
IH
VH Supply Current
INx = 0V and VS+
0.1
µA
IL
VL Supply Current
INx = 0V and VS+
0.1
µA
POWER SUPPLY
SWITCHING CHARACTERISTICS
tR
Rise Time
INx = 0V to 5V step, CL = 1nF
11
ns
tF
Fall Time
INx = 5V to 0V step, CL = 1nF
12
ns
tRF
tR, tF Mismatch
CL = 1nF
1
ns
tD+
Turn-On Delay Time
INx = 0V to 5V step, CL = 1nF
11.5
ns
tD-
Turn-Off Delay Time
INx = 5V to 0V step, CL = 1nF
13
ns
tDD
tD+, tD- Mismatch
CL = 1nF
1.5
ns
tENABLE
Enable Delay Time
INx = VS+, OE = 0V to 5V step, RL = 1k
12
ns
tDISABLE
Disable Delay Time
INx = VS+, OE = 5V to 0V step, RL = 1k
27
ns
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June 9, 2014
ISL7457SRH
Typical Performance Curves (Pre-rad)
2.0
1.8
HIGH LIMIT = 2.4V
1.6
HYSTERESIS
1.4
TA = ±25°C
SUPPLY CURRENT (mA)
INPUT VOLTAGE (V)
TA = ±15°C
1.2
ALL INPUTS = 0V
1.6
1.2
0.8
0.4
ALL INPUTS = VS+
LOW LIMIT = 0.8V
1.0
5
0
7
10
12
SUPPLY VOLTAGE (V)
15
25
IOUT = 100mA
8
TA = +25°C
VH TO OUT
6
20
RISE/FALL TIME (ns)
7
5
VL TO OUT
4
tR
tF
15
10
CL = 1nF
3
5
5
15
12
10
7
TA = +25°C
5
7
SUPPLY VOLTAGE (V)
FIGURE 4. ON-RESISTANCE vs SUPPLY VOLTAGE
25
CL = 1nF
VS+ = 15V
RISE/FALL TIME (ns)
14
12
tF
tR
10
8
6
-50
-25
15
12
10
SUPPLY VOLTAGE (V)
FIGURE 5. RISE/FALL TIME vs SUPPLY VOLTAGE
PROPAGATION DELAY TIME (ns)
16
15
12
SUPPLY VOLTAGE (V)
9
2
10
7
FIGURE 3. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 2. SWITCH THRESHOLD vs SUPPLY VOLTAGE
ON RESISTANCE (Ω)
5
0
25
50
75
100
TEMPERATURE (°C)
FIGURE 6. RISE/FALL TIME vs TEMPERATURE
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6
125
CL = 1nF
TA = +25°C
20
tD15
tD+
10
5
5
7
10
12
15
SUPPLY VOLTAGE (V)
FIGURE 7. PROPAGATION DELAY TIME vs SUPPLY VOLTAGE
FN6874.2
June 9, 2014
ISL7457SRH
Typical Performance Curves (Pre-rad) (Continued)
140
16
CL = 1nF
VS+ = 15V
tD-
14
tD+
12
10
TA = +25°C
100
80
60
tF
40
8
6
VS+ = 15V
120
RISE/FALL TIME (ns)
PROPAGATION DELAY TIME (ns)
18
tR
20
-50
-25
0
25
50
75
100
0
125
100
470
1k
OPERATING FREQUENCY(MHz)
VS+ = VH = 10V
SUPPLY CURRENT (mA)
10k
50
12
8
4.7k
FIGURE 9. RISE/FALL TIME vs LOAD CAPACITANCE
FIGURE 8. PROPAGATION DELAY TIME vs TEMPERATURE
10
2.2k
LOAD CAPACITANCE (pF)
TEMPERATURE (°C)
VS- = VL = 0V
f = 100kHz
TA = +25°C
6
4
2
VS+ = 15V
40
.
30
TJ = +125°C
.
.
20
.
.
10
TJ = +150°C
.
..
.
0
0
100k
1k
LOAD CAPACITANCE (pF)
FIGURE 10. SUPPLY CURRENT PER CHANNEL vs LOAD
CAPACITANCE
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10k
0
200
400
600
800
1k
LOAD CAPACITANCE (pF)
FIGURE 11. OPERATING FREQUENCY vs LOAD CAPACITANCE
DERATING CURVES
FN6874.2
June 9, 2014
ISL7457SRH
Timing Diagram
TABLE 1. OPERATING VOLTAGE RANGE
PIN
MIN
MAX
VS+ to VS-
4.5V
16.5V
VS- to GND
0V
0V
VH
VS- + 2.5V
VS+
VL
VS-
VS+
VH to VL
0V
16.5V
VL to VS-
0V
8V
5V
INPUT
2.5V
0
OUTPUT
90%
10%
t D-
tD+
tF
tR
Standard Test Configuration
0.1µF
VS+
10kΩ
1
INA
4.7µF
VS+
OUTA
16
1nF
OE
INB
2
15
3
14
OUTB
1nF
VL
4.7µF
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4
13
0.1µF
0.1µF
5
12
6
11
INC
7
10
IND
8
9
8
VH
4.7µF
OUTC
1nF
OUTD
1nF
FN6874.2
June 9, 2014
ISL7457SRH
Application Information
reliable operation, die temperature must be kept below TJMAX
(+150°C).
Product Description
Power dissipation may be calculated as shown in Equation 1:
The ISL7457SRH is a high performance, high speed quad CMOS
driver. Each channel of the ISL7457SRH consists of a single
P-channel high-side driver and a single N-Channel low-side driver.
These 3.5 devices will pull the output (OUTx) to either the high
or low voltage, on VH and VL respectively, depending on the input
logic signal (INx). It should be noted that there is only one set of
high and low voltage pins.
A common output enable (OE) pin is available on the
ISL7457SRH. When this pin is pulled low, it will put all outputs in
a high impedance state.
4
PD =  VS  IS  +
2
(EQ. 1)
1
where:
PD is the power dissipated in the device.
VS is the total power supply to the ISL7457SRH (from VS+ to VS-).
IS is the quiescent supply current.
CINT is the internal load capacitance (80pF max).
Supply Voltage Range and Input
Compatibility
f is the operating frequency.
The ISL7457SRH is designed to operate on nominal 5V to 15V
supplies with ±10% tolerance. Table 1 on page 8 shows the
specifications for the relationship between the VS+, VS-, VH, VL,
and GND pins. The ISL7457SRH does not contain a true analog
switch and therefore VL should always be less than VH.
VOUT is the swing on the output (VH - VL).
All input pins are compatible with both 3.3V and 5V CMOS
signals.
2
   CINT  VS  f  +  CL  VOUT  f  
CL is the load capacitance.
Junction Temperature Calculation
Once the power dissipation for the application is determined, the
maximum junction temperature can be calculated as shown in
Equation 2:
T JMAX = T SMAX +   JC +  CS   P D
(EQ. 2)
PCB Layout Guidelines
1. A ground plane must be used, preferably located on layer #2
of the PCB.
2. Connect the GND and VS- pins directly to the ground plane.
3. The VS+, VH and VL pins should be bypassed directly to the
ground plane using a low-ESR, 4.7µF solid tantalum capacitor
in parallel with a 0.1µF ceramic capacitor. Locate all bypass
capacitors as close as possible to the respective pins of the IC.
4. Keep all input and output connections to the IC as short as
possible.
5. For high frequency operation above 1MHz, consider use of
controlled impedance traces terminated into 50 on all
inputs and outputs.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the
ISL7457SRH drive capability is limited by the rise in die
temperature brought about by internal power dissipation. For
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where:
TJMAX is the maximum operating junction temperature
(+150°C).
TSMAX is the maximum operating sink temperature of the PCB.
JC is the thermal resistance, junction-to-case, of the package.
CSis the thermal resistance, case-to-sink, of the PCB
PD is the power dissipation calculated in Equation 1.
PCB Thermal Management
To minimize the case-to-sink thermal resistance, it is
recommended that multiple vias be placed on the top layer of
the PCB directly underneath the IC. The vias should be connected
to the ground plane, which functions as a heatsink. A gap filler
material (i.e. a Sil-Pad or thermally conductive epoxy) may be
used to insure good thermal contact between the bottom of the
IC and the vias.
FN6874.2
June 9, 2014
ISL7457SRH
Die Characteristics
Substrate:
Type: Silicon
DIE DIMENSIONS:
Isolation: Junction
2390µm x 2445µm (94.1 mils x 96.3 mils)
Backside Finish:
Thickness:13.0 mils 0.5 mil
Silicon
INTERFACE MATERIALS
ASSEMBLY RELATED INFORMATION
Glassivation
Substrate Potential:
Type: PSG and Silicon Nitride
Vs-
Thickness: 0.5µm ± 0.05µm to 0.7µm ±0.05µm
ADDITIONAL INFORMATION
Top Metallization
Worst Case Current Density:
Type: AlCuSi (1%/0.5%)
< 2 x 105 A/cm2
Thickness: 1.0µm ±0.1µm
Transistor Count:
1142
Metallization Mask Layout
ISL7457SRH
INA
VS+
OE
OUTA
INB
OUTB
VL
VH
GND
OUTC
DELAY
OUTD
INC
IND
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June 9, 2014
ISL7457SRH
Layout Characteristics
Step and Repeat: 2390µm x 2445µm
The DELAY pad is not bonded.
TABLE 1. LAYOUT X-Y COORDINATES
PAD NAME
X
(µm)
Y
(µm)
DX
(µm)
DY
(µm)
PROBES
PER PAD
IND
675
190
140
140
1
VS-
995
190
140
140
1
OUTD
2118
490
122
133
1
OUTC
2118
795
122
133
1
VH
2118
1039
122
345
2
2118
1211
OUTB
2118
1554
122
133
1
OUTA
2118
1861
122
133
1
VS+
1015
2140
140
140
1
INA
608
2140
140
140
1
OE
213
1993
140
140
1
INB
213
1673
140
140
1
VL
213
1331
140
345
2
213
1159
GND
213
864
140
140
1
DELAY
213
585
140
140
0
INC
213
213
140
140
1
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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ISL7457SRH
Package Outline Drawing
K16.A
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 2, 1/10
0.015 (0.38)
0.008 (0.20)
PIN NO. 1
ID OPTIONAL
1
2
0.050 (1.27 BSC)
PIN NO. 1
ID AREA
TOP VIEW
0.022 (0.56)
0.015 (0.38)
0.115 (2.92)
0.045 (1.14)
0.440 (11.18)
MAX
0.005 (0.13)
MIN
4
0.045 (1.14)
0.026 (0.66)
-C-
SEATING AND
BASE PLANE
6
0.285 (7.24)
0.245 (6.22)
0.13 (3.30)
MIN
0.009 (0.23)
0.004 (0.10)
-D-
0.370 (9.40)
0.250 (6.35)
-H-
0.03 (0.76) MIN
LEAD FINISH
SIDE VIEW
NOTES:
0.006 (0.15)
0.004 (0.10)
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
LEAD FINISH
0.009 (0.23)
BASE
METAL
0.004 (0.10)
0.019 (0.48)
0.015 (0.38)
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
4. Measure dimension at all four corners.
0.0015 (0.04)
MAX
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
0.022 (0.56)
0.015 (0.38)
3
SECTION A-A
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Controlling dimension: INCH.
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June 9, 2014
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