DATASHEET

X80070, X80071, X80072, X80073
®
Data Sheet
March 15, 2005
Hot Swap Controller with
Advanced Fault Protection and
Voltage Regulator Output
FN8150.0
APPLICATIONS
• -48V Hot Swap Power Backplane/Distribution Central
Office, Ethernet for VOIP
• Positive Voltage Hotswap 12V to 60V Applications
(low side switching)
• Card Insertion Detection
• IP Phone Applications
• Databus Power Interfacing
• Custom Industrial Power Backplanes
• Distributed Power Systems
FEATURES
• Hot swap controller
— Overvoltage and undervoltage protection
— Undervoltage lockout for battery/redundant supplies
— Electronic circuit breaker
— Slew Rate for External FET Gate Control
— Overcurrent Detection and Gate Shut-off
— 3X overcurrent limit on insertion
— 5µs overcurrent filter
— Hardshort Retry and Indicator
— Typically operates from -30V to -80V. Tolerates transients to -200V (limited by external components)
— Positive Voltages (low side switching) from 12V to 60V
— Soft Re-insertion
— Soft extraction
• Battery backup mode
• Hardshort retry
• Overcurrent Filter
• Insertion Limits.
• Selectable Gate Current
• Voltage Regulator Output for Supervisory Functions
• Debounced manual reset input
• Available packages
— 20-lead Quad No-Lead Frame (QFN)
DESCRIPTION
The X80070 is a hot swap controller that allows a board to be
safely inserted and removed from a live backplane without
turning off the main power supply.
During insertion, the gate of an external power MOSFET is
clamped low to suppress contact bounce. The
undervoltage/overvoltage circuits and the power-on reset
circuitry suppress the gate turn on until the mechanical bounce
has ended. The X80070 turns on the gate with a slew rate to
limit the inrush current and incorporates an electronic circuit
breaker set by a sense resistor. After the load is successfully
charged, the PWRGD signal is asserted; indicating that the
device is ready to power sequence the DC-DC power bricks.
At all times, the X80070 monitors for undervoltage, overvoltage,
and overcurrent conditions. If any fault occurs, the gate will be
immediately shut off and the PWRGD will be returned to the
inactive state. The X80070 contains overvoltage, undervoltage
and overcurrent detection, hardshort retry, gate control slew
rate and power good control.
TYPICAL APPLICATION
-48V
Return
*
X80070
ON/OFF
VRGO
R5
30k
1%
R4
182k
1%
IGQ1
OV=75V
IGQ0
Gate
Current
Select
VDD
R6
10k
1%
*
PWRGD
UV=43V
VUV/OV
VEE
DC-DC
Module
1
*
SENSE GATE
100n
100
22K
3.3n
Rs
-48V
0.02Ω
5%
1
Q1
IRFR120
components
* Optional
Depends on choice of DC-DC Module
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X80070, X80071, X80072, X80073
ORDERING INFORMATION
BATT-ON
PWRGD
IGQ1
MR
IGQ0
QFN package
(Top view)
20 19 18 17 16
15
1
14
2
FAR
DNC
DNC
3 5mm x 5mm 13
12
4
NA
VDD
5
ORDER
NUMBER
X80070Q20I
X80071Q20I
X80072Q20I
X80073Q20I
OV
(V)
74.9
68.0
74.9
68.0
UV1
(V)
42.4
42.4
42.4
42.4
UV2
(V)
33.2
33.2
33.2
33.2
NA
DNC
DNC
8
GATE
11
9 10
6 7
VUV/OV
DNC
SENSE
DNC
VEE
VRGO
tNF
(us)
5
5
5
5
VOC
(mV)
50
50
50
50
Over- Retry
VOCI current Delay IGATE TDELAY
(mV)
Retry
(ms) (uA)
(ms)
150 Always 100
50
100
150 Always 100
50
100
150 5 retries 100
50
100
150 5 retries 100
50
100
tPOR
(ms)
100
100
100
100
Temp
-40oC to 85oC
-40oC to 85oC
-40oC to 85oC
-40oC to 85oC
PART
MARK
80070I
80071I
80072I
80073I
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ..............................-65°C to +135°C
Storage temperature ...................................-65°C to +150°C
Voltage on given pin (Hot Side Functions):
Vov / uv pin ............................................................ 5.5V + VEE
SENSE pin ...................................................... 400mV + VEE
VEE pin .......................................................................... -80V
PWRGD pin........................................................... 7 V + VEE
GATE pin.............................................................. VDD + VEE
FAR pin .................................................................. 7V + VEE
MR pin ................................................................. 5.5V + VEE
BATT-ON pin....................................................... 5.5V + VEE
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device (at these or
any other conditions above those listed in the operational
sections of this specification) is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
Voltage on given pin (Cold Side Functions):
IGQ1 and IGQ0 pins............................................ 5.5V + VEE
VDD pin ................................................................. 14V + VEE
D.C. output current ........................................................ 5mA
Lead temperature (soldering, 10 seconds) ..................300°C
2
RECOMMENDED OPERATING CONDITIONS
Temperature
Industrial
Min.
-40°C
Max.
+85°C
Supply Voltage
VDD = 12V
FN8150.0
March 15, 2005
X80070, X80071, X80072, X80073
ELECTRICAL CHARACTERISTICS (Standard Settings)
(Over the recommended operating conditions unless otherwise specified).
Symbol
Parameter
DC Characteristics
Supply Operating Range
VDD
Supply Current
IDD
Regulated 5V output
VRGO
IRGO
VRGO current output
Gate Pin Current
IGATE
Min.
Typ.
Max.
Unit
10
12
2.5
14
5
5.5
50
58.8
V
mA
4.5
46.2
52.5
9
VGATE
VPGA
VIHB
VILB
ILI
ILO
VIL
VIH
VOL
COUT(1)
CIN(1)
VOC
VOCI
VOVR
External Gate Drive (Slew Rate ConVDD-1
trol)
0.9
Power Good Threshold
(PWRGD High to Low)
Voltage Input High (BATT-ON)
VEE + 4
Voltage Input Low (BATT-ON)
Input Leakage Current (MR, IGQ0,
IGQ1)
Output Leakage Current (PWRGD)
Input LOW Voltage (MR, IGQ0, IGQ1)
-0.5 + VEE
Input HIGH Voltage (MR, IGQ0, IGQ1) (VEE + 5) x 0.7
Output LOW Voltage
(FAR, PWRGD)
Output Capacitance (FAR)
Input Capacitance (MR)
Overcurrent threshold
Overcurrent threshold (Insertion)
Gate Drive On,
VGATE = VEE,
VSENSE = VEE (sourcing)
mA VGATE - VEE = 3V
VSENSE-VEE = 0.1V (sinking)
V IGATE = 50uA
1.1
V
Referenced to VEE
VUV1 < VUV/OV < VOV
VEE + 5
VEE + 2
10
V
V
µA
10
(VEE + 5) x 0.3
(VEE + 5) + 0.5
VEE + 0.4
µA
V
V
V
Gate is Off
VIL = GND to VCC
IOL = 4.0 mA
(VEE + 2.7 to VEE + 5.5V)
IOL = 2.0 mA
(VEE + 2.7 to VEE + 3.6V)
pF VOUT = 0V
pF VIN = 0V
mV VOC = VSENSE - VEE
mV VOC = VSENSE - VEE
PWRGD = HIGH
Initial Power-up condition
45
135
50
150
8
6
55
165
3.85
3.49
3.90
3.54
3.95
3.59
V
Referenced to VEE
3.82
3.46
3.87
3.51
3.92
3.56
V
Referenced to VEE
2.19
2.16
1.71
1.68
2.24
2.21
1.76
1.73
2.29
2.26
1.81
1.78
V
V
V
V
Referenced to VEE
BATT-ON = VEE
1.5
2.5
3.5
µs
Overvoltage threshold (falling)
X80070, X80072
X80071, X80073
VUV1R
VUV1F
VUV2R
VUV2F
1
IRGO = 10uA
µA
µA
Overvoltage threshold (rising)
X80070, X80072
X80071, X80073
VOVF
VDD
Test Conditions
Undervoltage 1 threshold (rising)
Undervoltage 1 threshold (falling)
Undervoltage 2 threshold (rising)
Undervoltage 2 threshold (falling)
AC Characteristics
Sense High to Gate Low
tFOC
3
Referenced to VEE
BATT-ON = VRGO
FN8150.0
March 15, 2005
X80070, X80071, X80072, X80073
ELECTRICAL CHARACTERISTICS (Standard Settings) (Continued)
(Over the recommended operating conditions unless otherwise specified).
Symbol
tFUV
tFOV
tVFR
Parameter
Undervoltage conditions to Gate Low
Overvoltage Conditions to Gate Low
Overvoltage/undervoltage failure recovery time to Gate =1V.
tBATT-ON Delay BATT-ON Valid
Minimum time high for reset valid on
tMR
the MR pin
Delay from MR enable to Gate Pin
tMRE
LOW
Delay from MR disable to GATE
tMRD
reaching 1V
Delay from IGQ1 and IGQ0 to valid
tQC
Gate pin current
tSC_RETRY Delay between Retries
Noise Filter for Overcurrent
tNF
tDPOR
Device Delay before Gate assertion
Min.
0.5
1.0
1.2
Typ.
1.0
1.5
1.6
Max.
1.5
2
2
100
5
1.0
1.6
1.8
90
4.5
45
100
5
50
Unit
Test Conditions
µs
µs
µs VDD does not drop below 3V,
No other failure conditions.
ns
µs
2.4
µs
IGATE = 60µA, No Load
2.6
µs
IGATE = 60µA, No Load
1
µs
110
5.5
55
ms
µs
ms
Notes: (1) This parameter is based on characterization data.
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT
5V
4.6kΩ
PWRGD
FAR
30pF
A.C. TEST CONDITIONS
VCC x 0.1 to VCC x 0.9
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
10ns
VCC x 0.5
Standard output load
4
FN8150.0
March 15, 2005
X80070, X80071, X80072, X80073
Figure 1. Overvoltage/Undervoltage GATE Timing
VTH
tDPOR
VDD
VOV
VUV
tFOV
VUV/OV
MR
tFUV
tVFR
tVFR
VOCI
VOC
SENSE
1V
GATE
1V
Figure 2. Overcurrent GATE Timing
VTH
Always Retry
VUV < VUV/OV < VOV
MR = HIGH
tDPOR
VDD
VOCI
VOC
SENSE
tFOC
GATE
tSC_RETRY
tSC_RETRY
tFOC
Figure 3. Manual Reset
MR
tMR
GATE
1V
tMRE
5
tMRD
FN8150.0
March 15, 2005
X80070, X80071, X80072, X80073
TYPICAL PERFORMANCE CHARACTERISTICS
Overcurrent Threshold vs. Temperature
Undervoltage 2 Threshold vs. Temperature
1.780
Undervoltage 2 Threshold (V)
Inrush Current Limit (mV)
52.000
51.000
50.000
49.000
48.000
47.000
46.000
-55 -40 -25 -10
5
20
35
50
65
80
95
1.770
1.760
Rising
1.750
1.740
1.730
1.720
Falling
1.710
1.700
1.690
-55 -40 -25 -10
110 125
5
Temperature
80
95
110 125
IGATE (source) vs. Temperature
Overvoltage Threshold vs. Temperature
200
3.92
150µA
3.91
160
3.90
3.89
3.88
Rising
3.87
Gate Current (µA)
OV Threshold (V)
20 35 50 65
Temperature
120
70µA
80
50µA
40
3.86
10µA
Falling
0
-55 -40 -25 -10
3.85
-55 -40 -25 -10
5
20
35
50
65
80
95 110 125
5
20
35
50
65
80
95 110 125
Temperature
Temperature
Undervoltage 1 Threshold vs. Temperature
IGATE (sink) vs. Temperature
2.250
10.5
2.230
Rising
2.220
2.210
2.200
Falling
Gate Current - Sink (mA)
Undervoltage 1 Threshold (V)
11.0
2.240
10.0
9.5
9.0
8.5
8.0
7.5
2.190
-55 -40 -25 -10
5
20 35 50 65
Temperature
80
95 110 125
7.0
-55 -40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature
6
FN8150.0
March 15, 2005
X80070, X80071, X80072, X80073
tFOC vs. Temperature
tFUV vs. Temperature
2.5
0.800
2.4
0.750
0.650
tUV1
0.600
tOC (µs)
tUV (µs)
2.3
tUV2
0.700
2.2
2.1
2.0
1.9
0.550
1.8
0.500
-55 -40 -25 -10
5
20
35
50
65
80
95 110 125
1.7
-55 -40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature
Temperature
tFOV vs. Temperature
1.4
1.4
tOV (µs)
1.3
1.3
1.2
1.2
1.1
1.1
1.0
-55 -40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature
7
FN8150.0
March 15, 2005
X80070, X80071, X80072, X80073
Figure 4. Block Diagram
VUV/OV
PWRGD
Power Good
Logic
VOV Ref
VEE
2:1
MUX
VUV1 Ref
VUV2 Ref
BATT-ON
FAR
Overcurrent logic,
Hard short relay,
Retry logic status
and delay
VEE
VEE
50uA
GATE
Slew Rate
Selection
IGQ1
IGQ0
Gate
Control
VOC REF
VEE
SENSE
VDD
VDD
5V reg
POR
VRGO
Reset Logic
and Delay
38R
3R
Timing/
Control logic
VEE
MR
8
FN8150.0
March 15, 2005
X80070, X80071, X80072, X80073
PIN CONFIGURATION
6 7
BATT-ON
IGQ1
8
11
9 10
DNC
5
VEE
VDD
GATE
NA2
3 5mm x 5mm 13
12
4
SENSE
NA2
PWRGD
MR
DNC
20 19 18 17 16
15
1
14
2
VUV/OV
VRGO
IGQ0
X80070
20L QFN Package
FAR
NA2
NA1
NA1
DNC
TOP VIEW
NA1 pins connect to VRGO
NA2 pins connect to VEE
PIN DESCRIPTIONS
Pin
Name
Description
Regulated 5V output. Used to pull-up
1
VRGO
user programmable inputs IGQ0, IGQ1,
BATT-ON and MRH (if needed).
2
DNC
Pin not used. Do not connect to this pin.
3
NA2
Not Available. Connect to VEE.
4
NA2
Not Available. Connect to VEE.
Positive Supply Voltage Input.
5
VDD
6
VEE
Negative Supply Voltage Input.
7
VUV/OV Analog Undervoltage and Overvoltage
Input. Turns off the external N-channel
MOSFET when there is an undervoltage
or overvoltage condition.
8
SENSE Circuit Breaker Sense Input. This input
pin detects the overcurrent condition.
9
GATE
FET Gate Drive. This pin supplies the current to turn on the FET.
10
DNC
Pin not used. Do not connect to this pin.
11
DNC
Pin not used. Do not connect to this pin.
12
NA1
Not Available. Connect to VRGO.
13
NA1
Not Available. Connect to VRGO.
14
NA2
Not Available. Connect to VEE.
Failure After Re-try (FAR) output signal.
15
FAR
16
17
BATT-ON Battery On Input. This input signals that
the battery backup (or secondary supply)
is supplying power to the backplane. It has
an internal pulldown resistor. (>10MΩ
typical)
PWRGD Power Good Output. This output pin enables a power module.
9
PIN DESCRIPTIONS (Continued)
Pin
Name
Description
18
IGQ1
Gate Current Quick Select Bit 1 Input.
This pin is used to change the gate current
drive and is intended to allow for current
ramp rate control of the gate pin of an
external FET. It has an internal pulldown
resistor. (>10MΩ typical)
19
IGQ0
Gate Current Quick Select Bit 0 Input.
This pin is used to change the gate current
drive and is intended to allow for current
ramp rate control of the gate pin of an
external FET. It has an internal pulldown
resistor. (>10MΩ typical)
Manual Reset. Pulling the MR pin LOW
20
MR
initiates a GATE pin reset (GATE pin
pulled LOW). The MR signal must be held
LOW for 5µsecs (minimum).
FUNCTIONAL DESCRIPTION
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
bypass capacitors at the input of the board’s power module or
DC/DC converter can draw huge transient currents as they
charge up. This transient current can cause permanent
damage to the board’s components and cause transients on
the system power supply.
The X80070 is designed to turn on a board’s supply voltage in a
controlled manner (see Figure 5), allowing the board to be
safely inserted or removed from a live backplane. The device
also provides undervoltage, overvoltage and overcurrent
protection while keeping the power module (dc-dc converter)
off until the backplane input voltage is stable and within
tolerance.
Figure 5. Typical Inrush with Gate Slew Rate Control
IINRUSH
VGATE
VFET_DRAIN
PWRGD
FN8150.0
March 15, 2005
X80070, X80071, X80072, X80073
Figure 6. Typical -48V Hotswap Application circuit
the equations of Figure 7 the desired operating voltage can be
determined. Figure 8 shows the resistance values for various
operating voltages (X80070 and X80072).
-48V
Return
DC/DC
100uF Converter
VS
3.3n
IRFR120
-48V
The X80070 provides overvoltage and undervoltage protection
circuits.
When an overvoltage (VOV) or undervoltage (VUV1 and VUV2)
condition is detected, the GATE pin immediately pulls low
turning off the supply to the system. The undervoltage
threshold VUV1 applies to the normal operation with a main
supply. The undervoltage threshold VUV2 assumes the system
is powered by a battery. When using a battery backup, the
BATT-ON pin is pulled to VRGO. The default thresholds have
been set so the external resistance values in Figure 6 provide
an overvoltage threshold of 74.9V (X80070 and X80072) or
68V (X80071 and X80073), a main undervoltage threshold of
43V and a battery undervoltage threshold of 33.8V.
As shown in Figure 9, this circuit block contains comparators
and voltage references to monitor for a single overvoltage and
dual undervoltage trip points. The overvoltage and undervoltage
trip points as shown in Table 1 below.
Overvoltage/Undervoltage default thresholds
Threshold
Symbol
VOV
VOV
VUV1
VUV2
Notes:
Max/Min
Voltage Lockout
1
Voltage2
falling rising
3.87V 3.9V
74.3
74.9
Description
Overvoltage
(X80070/72)
Overvoltage 3.51V 3.54V
(X80071/73)
Undervoltage 1 2.21V 2.24V
Undervoltage 2 1.73V 1.76V
67.4
VN
Figure 8. Operating voltage vs. resistor ratio
Overvoltage and Undervoltage Shutdown
Table 1.
68
100
90
80
70
60
50
40
30
20
10
0
42.4
33.2
1: Max/Min Voltage is the maximum and mimimum
operating voltage assuming the recommended VUV/OV
resistor divider.
2: Lockout voltage is the voltage where the X8007x turns
off the FET.
VOV
Operating
Voltage
BATT-ON = VEE
VUV1
BATT-ON = VRGO
VUV2
R1 in kΩ (for R2=10K)
Battery back up operations
An external signal, BATT-ON is provided to switch the
undervoltage trip point. The BATT-ON signal is a LOGIC HIGH
if VIHB > VEE + 4V and is a LOGIC LOW if VILB < VEE + 2V. The
time from a BATT-ON input change to a valid new undervoltage
threshold is 100ns. See Electrical Specifications for more
details.
Note: The VUV/OV pin must be limited to less than VEE + 5.5V.
in worst case conditions. Values for R1 and R2 must be chosen
such that this condition is met. Intersil recommends
R1 = 182kΩ and R2 = 10kΩ to conform to factory settings.
These should be 1% resistors.
Table 2.
43.0
33.8
R1 + R2
V S = V UV ⁄ OV  ----------------------
 R2 
R2
Q1
222
100
or:
214
Iinrush
100n
VUV/OV
206
-48V
GATE
22K
Rs
0.02Ω
5%
R2
V UV ⁄ OV = V S  ----------------------
 R1 + R2
R1
198
SENSE
10K
190
VEE
PWRGD
158
R6
10K
1%
182
VDD
Voltage divider:
VP
ON/OFF
175
X80070
OV=75V/72V
Figure 7. Overvoltage Undervoltage Divider
166
VRGO
150
UV=43V
VUV/OV
Operating Voltage (Volts)
R4
182K
1%
R5
30K
1%
Selecting between Undervoltage Trip Points
Pin
Description
BATT-ON Undervoltage
Trip Point
Selection Pin
Trip Point Selection
If BATT-ON = 0,
VUV1 trip point is selected;
If BATT-ON = 1,
VUV2 trip point is selected.
VUV1 and VUV2 are undervoltage thresholds.
A resistor divider connected between the plus and minus input
voltages and the VUV/OV pin (see Figure 7) determines the
overvoltage and undervoltage shutdown voltages and the
operating voltage range. Using the thresholds in Table 1 and
10
FN8150.0
March 15, 2005
X80070, X80071, X80072, X80073
Figure 9. Overvoltage/Undervoltage for Primary and
Battery Backup
R1
450K
VUV/OV
+
R2
25K
VOV
-48V
To Gate
Control
Voltage
Reference
+
VUV1
Voltage
Reference
2:1
Mux
To Gate
Control
+
VUV2
Voltage
Reference
BATT-ON
Overcurrent Protection (Circuit Breaker Function)
The X80070 overcurrent circuit provides the following functions:
– Overcurrent shut-down of the power FET and external
power good indicators.
– Noise filtering of the current monitor input.
– Relaxed overcurrent limits for initial board insertion.
– Overcurrent recovery retry operation.
During insertion, the board can experience high levels of
current for short periods of time as power supply capacitors
charge up on the power bus. To prevent the overcurrent sensor
from turning off the FET inadvertently, the X80070 has the
ability to allow more current to flow through the power FET and
the sense resistor for a short period of time until the FET turns
on and the PWRGD signal goes active.
In the X80070, 150mV is allowed across sense resistor during
insertion (7.5A assuming a 20mW resistor). This provides a
mechanism to reduce insertion issues associated with huge
current surges. Insertion currents of 1X, 2X, or 4X are also
available. Please contact Intersil for these factory options.
After the PWRGD signal is asserted, the X80070 switches back
to the normal overcurrent setting.
Hardshort Protection - (Retry)
In the event on an overcurrent or hard short condition, the
X80070 includes a retry circuit. This circuit waits for 100ms,
then attempts to again turn on the FET. If the fault condition still
exists, the FET turns off and the sequence repeats. For
versions X80070 and X80072, this process continues indefinely
until the overcurrent condition does not exist. For the X80071
and X80073, this process repeats five times only, then will keep
the FET off and set the FAR pin active. After FAR is asserted, it
can be cleared using the master reset pin, MR, or cycling the
power-on VDD. When using the MR pin, the FAR output is
cleared upon MR assertion.
If an overcurrent condition does not occur on any retry, the gate
pin will proceed to open at the user defined slew rate.
Overcurrent shut-down
A sense resistor, placed in the supply path between VEE and
SENSE (see Figure 6) generates a voltage internal to the
X80070. When this voltage exceeds 50mV, an overcurrent
condition exists and an internal “circuit breaker” trips, turning
off the gate drive to the external FET. The actual overcurrent
level is dependent on the value of the current sense resistor.
For example a 20mΩ sense resistor sets the overcurrent level
to 2.5A.
Figure 10. Overcurrent Detection/Short Circuit
Protection.
Voltage
Reference
Gate
Control
Block
38R
As shown in Figure 10, this overcurrent circuit block contains a
resistor ladder, a comparator, a noise filter and a voltage
reference to monitor for overcurrent conditions.
–
3R
+
5us
noise
filtering
The overcurrent voltage threshold (VOC) is 50mV. This can be
factory set, by special order, to any setting between 30mV and
100mV.
If an overcurrent condition is detected, the GATE output is shut
down and the power good indicator goes inactive.
Overcurrent/
Short-Circuit
Retry Logic
RETRY
Delay
-48V
RSense
Overcurrent Event
Overcurrent during insertion
Overcurrent noise filter
Insertion is defined as the first plug-in of the board to the
backplane. In this case, the X80070 is initially fully powered off
prior to the hot plug connection to the main supply. This
condition is different from a situation where the main supply has
temporarily failed resulting in a partial recycle of the power. This
second condition will be referred to as a power cycle.
The X80070 has a noise (low pass) filter built into the
overcurrent comparator. The comparator will thus require
the current spikes to exceed the overcurrent limit for more
than 5µs.
11
FN8150.0
March 15, 2005
X80070, X80071, X80072, X80073
Gate Drive Output Slew Rate (Inrush Current) Control
The value of C2 can be selected with the following formula.
The gate output drives an external N-Channel FET. The GATE
pin goes high when no overcurrent, undervoltage or
overvoltage conditions exist.
The X80070 provides an IGATE current of 50uA to provide onchip slew rate control to minimize inrush current and provide
the best turn on time for a given load, while avoiding
overcurrent conditions.
Slew Rate (Gate) Control
To give the designer flexibility in the design of the hot swap
circuit, the X80070 provides two external pins, IGQ1 and IGQ0.
These pins allow the user to switch to different GATE currents
on-the-fly by selecting one of four pre-selected IGATE currents.
When IGQ0 and IGQ1 are left unconnected, the gate current is
50uA. The other three settings are 10uA, 70uA and 150uA, as
shown in Table 3.
IGQ Gate Current Selection
IGQ1 IGQ0
pin
pin
Operation
0
0
Defaults to gate current 50µA
0
1
Gate Current is 10µA
1
0
Gate Current is 70µA
1
1
Gate Current is 150µA
IGATE = FET Gate current
IINRUSH = Maximum desired inrush current
IGQ1
IGQ0
In a system where VDD rises very fast, a smaller value of C1
may suffice as the X80070 will control voltage at the gate
before the voltage can rise to the FET turn on threshold. The
circuit of Figure 11 assumes that the input voltage can rise to
80V before the X80070 sees operational voltage on VDD. If C1
is used then the series resistor R1 will be required to revent
high frequency oscillations.
SENSE GATE
R1
100
R2
22K
-48V
C1 = Gate capacitor,
C2 = Feedback capacitor.
Slew Rate
Logic
C1
100n
Where:
V2 = FET threshold Voltage,
Gate
Current
Select
Logic
i.e. 12V
50µA
When power is applied to the system, the FET tries to turn on
due to its internal gate to drain capacitance (Cgd) and the
feedback capacitor C2 (see Figure 11.) The X80070 device,
when powered, pulls the gate output low to prevent the gate
voltage from rising and keep the FET from turning on. However,
unless VDD powers up very quickly, there will be a brief period
of time during initial application of power when the X80070
circuits cannot hold the gate low. The use of an external
capacitor (C1) prevents this. Capacitors C1 and C2 form a
voltage divider to prevent the gate voltage from rising above the
FET turn on threshold before the X80070 can hold the gate low.
Use the following formula for choosing C1.
V1 = Maximum input voltage,
Figure 11. Slew Rate (Inrush Current) Control
VDD
With the X80070, there is some control of the gate current
with the IGQ pins, so one selection of C2 can cover a wide
range of possible loading conditions. Typical values for C2
range from 2.2 to 4.7nF.
V1 – V2
C1 = --------------------- C2
V2
Typically, the delay from IGQ1 and IGQ0 selection to a change
in the GATE pin current is less than 1 µsecond.
VEE
Where:
CLOAD = DC/DC bulk capacitance
As shown in Figure 11, this circuit block contains a current
source (IGATE) that drives the 50uA current into the GATE pin.
This current provides a controlled slew rate for the FET.
Table 3.
I GATE × C
LOAD
C2 = ------------------------------------------I INRUSH
C2
3.3nF
LOAD
RSENSE
RDSON
IINRUSH
Gate Capacitor, Filtering and Feedback
The FET control circuit includes an FET feedback capacitor
C2, which provides compensation for the FET during turn on.
The capacitor value depends on the load, the choice of FET
(because of the FET internal capacitances) and the FET
gate current.
12
Power Good Indication
The PWRGD signal asserts (Logic LOW) only when all of the
below conditions are true:
– there is no overvoltage or no undervoltage condition, (i.e.
undervoltage < VEE < overvoltage.)
– There is no overcurrent condition (i.e. VEE - VSENSE <
VOC.)
– The FET is turned on (i.e. VGATE > VDD - 1V)
FN8150.0
March 15, 2005
X80070, X80071, X80072, X80073
As shown in Figure 12, this circuit block contains a
comparator, and an internal voltage reference. These
provide a circuit to determine the whether the gate drive to
the FET has fully turned on as requested. If so, the power
good indicator (PWRGD) goes active.
Figure 12. Power Good Indicator
Overvoltage Good Signal
Undervoltage Good Signal
Overcurrent Good Signal
Manual Reset
The X80070 has a manual reset pin. MR (manual reset). The
MR signal is used as a manual reset for the GATE pin. This pin
is used to initiate Soft Reinsert. When MR is pulled LOW the
GATE pin will be pulled LOW. It also clears the FAR signal.
When the MR pin goes HIGH, it removes the override signal
and the gate will turn on based on the selected gate control
mechanism. (See Figure 3.)
Table 4.
MR
1
Power
Good
Logic
PWRGD
0
Output
Drive
Manual Reset (Gate Signal)
Gate Pin
Requirements
Operational When MR is HIGH the reset
function is disabled
OFF
MR must be held LOW minimum of
5µsecs
VDD - 1V
ref
VEE
GATE
-48V
LOAD
RSENSE
13
FN8150.0
March 15, 2005
X80070, X80071, X80072, X80073
PACKAGING INFORMATION
C
20-Lead Quad Flat No Lead Package (Package Code: Q20)
5mm x 5mm Body with 0.65mm Lead Pitch
A3
A1
Pin 1 Indent
b
E
E2
e
D2
Note:
1. The package outline drawing is compatilbe with JEDEC MO-220; variations:
WHHC-2, except dimensions D2 and E2.
2. The terminal #1 identifier is a laser
marked feature
L
A
y C
D
Dimensions in Millimeters
Symbols
Min
Nom
Max
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
b
0.25
0.30
0.35
A3
0.19
0.20
0.25
5.10
D
4.90
5.00
D2
3.70
3.80
3.90
E
4.90
5.00
5.10
E2
3.70
3.80
3.90
e
—
0.65
—
L
0.35
0.40
0.45
—
0.08
y
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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14
FN8150.0
March 15, 2005
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