DATASHEET

EL7640A, EL7641A, EL7642A
ESIGNS
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1-888-IN
TFT-LCD DC/DC with Integrated
Amplifiers
Features
The EL7640A, EL7641A, and EL7642A integrate a high
performance boost regulator with 2 LDO controllers for VON
and VOFF, a VON-slice circuit with adjustable delay and
either one (EL7640A), three (EL7641A), or five amplifiers
(EL7642A) for VCOM and VGAMMA applications.
The boost converter in the EL7640A, EL7641A, and
EL7642A is a current mode PWM type integrating an 18V
NHchannel MOSFET. Operating at 1.2MHz, this boost can
operate in either P-mode for superior transient response, or
in PI-mode for tighter output regulation.
Using external low-cost transistors, the LDO controllers
provide tight regulation for VON, VOFF, as well as providing
start-up sequence control and fault protection.
The amplifiers are ideal for VCOM and VGAMMA
applications, with 150mA peak output current drive, 12MHz
bandwidth, and 12V/s slew rate. All inputs and outputs are
rail-to-rail.
Available in the 32 Ld thin QFN (5mm x 5mm) Pb-free
packages, the EL7640A, EL7641A, and EL7642A are specified
for operation over the -40°C to +85°C temperature range.
• Current mode boost regulator
- Fast transient response
- 1% accurate output voltage
- 18V/3A integrated FET
- >90% efficiency
• 2.6V to 5.5V VIN supply
• 2 LDO controllers for VON and VOFF
- 2% output regulation
- VON-slice circuit
• High speed amplifiers
- 150mA short-circuit output current
- 12V/s slew rate
- 12MHz -3dB bandwidth
- Rail-to-rail inputs and outputs
• Built-in power sequencing
• Internal soft-start
• Multiple overload protection
• Thermal shutdown
• 32 Ld 5x5 thin QFN package
• Pb-free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER
(Note)
FN6270.0
PART
TAPE & PACKAGE
MARKING REEL
(Pb-Free)
PKG.
DWG. #
Applications
• TFT-LCD panels
EL7640AILTZ
7640AILTZ
-
32 Ld 5x5
Thin QFN
MDP0051
EL7640AILTZ-T7
7640AILTZ
7”
32 Ld 5x5
Thin QFN
MDP0051
EL7640AILTZ-T13 7640AILTZ
13”
32 Ld 5x5
Thin QFN
MDP0051
• LCD monitors
EL7641AILTZ
7641AILTZ
-
32 Ld 5x5
Thin QFN
MDP0051
EL7641AILTZ-T7
7641AILTZ
7”
32 Ld 5x5
Thin QFN
MDP0051
EL7641AILTZ-T13 7641AILTZ
13”
32 Ld 5x5
Thin QFN
MDP0051
EL7642AILTZ
7642AILTZ
-
32 Ld 5x5
Thin QFN
MDP0051
EL7642AILTZ-T7
7642AILTZ
7”
32 Ld 5x5
Thin QFN
MDP0051
EL7642AILTZ-T13 7642AILTZ
13”
32 Ld 5x5
Thin QFN
MDP0051
• Notebooks
• LCD-TVs
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements
of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL7640A, EL7641A, EL7642A
Pinouts
25 FBP
26 DRVP
27 FBN
28 DRVN
30 CTL
31 DRN
32 COM
25 FBP
26 DRVP
27 FBN
28 DRVN
29 DEL
30 CTL
31 DRN
32 COM
29 DEL
EL7641A
(32 LD QFN)
TOP VIEW
EL7640A
(32 LD QFN)
TOP VIEW
SRC 1
24 COMP
SRC 1
24 COMP
REF 2
23 FB
REF 2
23 FB
22 IN
AGND 3
21 LX
PGND 4
20 NC
OUT1 5
NEG1 6
19 NC
NEG1 6
19 NC
POS1 7
18 IC
POS1 7
18 IC
17 NC
OUT2 8
17 OUT3
NC = NOT INTERNALLY CONNECTED
IC = INTERNALLY CONNECTED
NEG3 16
POS3 15
20 NC
SUP 14
NC 13
NC 16
NC 15
SUP 14
NC 13
NC 12
BGND 11
IC 10
NC 9
NC 8
NC 12
OUT1 5
21 LX
THERMAL
PAD
BGND 11
THERMAL
PAD
NEG2 9
PGND 4
22 IN
POS2 10
AGND 3
NC = NOT INTERNALLY CONNECTED
IC = INTERNALLY CONNECTED
25 FBP
26 DRVP
27 FBN
28 DRVN
29 DEL
30 CTL
31 DRN
32 COM
EL7642A
(32 LD QFN)
TOP VIEW
SRC 1
24 COMP
REF 2
23 FB
AGND 3
22 IN
PGND 4
21 LX
THERMAL
PAD
OUT1 5
20 OUT5
2
NEG4 16
POS4 15
SUP 14
17 OUT4
OUT3 13
OUT2 8
POS3 12
18 POS5
BGND 11
POS1 7
POS2 10
19 NEG5
NEG2 9
NEG1 6
FN6270.0
May 15, 2006
EL7640A, EL7641A, EL7642A
Absolute Maximum Ratings (TA = 25°C)
COM, DRN to AGND . . . . . . . . . . . . . . . . . . . . -0.3V to VSRC +0.3V
LX Maximum Continuous RMS Output Current. . . . . . . . . . . . . 1.6A
OUT1, OUT2, OUT3, OUT4, OUT5
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . ±75mA
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Continuous Junction Temperature . . . . . . . . . . . . +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
IN, CTL to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
COMP, FB, FBP, FBN, DEL, REF to AGND. . . . . -0.3V to VIN+0.3V
PGND, BGND to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
SUP to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +18V
DRVP, SRC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V
POS1, NEG1, OUT1, POS2, NEG2, OUT2, POS3, OUT3,
POS4, NEG4, OUT4, POS5, OUT5 to AGND . . -0.3V to VSUP+0.3V
DRVN to AGND . . . . . . . . . . . . . . . . . . . . . . . VIN -20V to VIN +0.3V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
VIN = 3V, VBOOST = VSUP = 12V, VSRC = 20V, Over temperature from -40°C to 85°C.
Unless Otherwise Specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
5.5
V
SUPPLY
VIN
Input Supply Range
VLOR
Undervoltage Lockout Threshold
VIN rising
2.4
2.5
2.6
V
VLOF
Undervoltage Lockout Threshold
VIN falling
2.2
2.3
2.4
V
IS
Quiescent Current
LX not switching
2.5
mA
ISS
Quiescent Current - Switching
LX switching
5
10
mA
TFD
Fault Delay Time
CDEL = 100nF
23
VREF
Reference Voltage
TA = 25°C
SHUTDN
2.6
ms
1.19
1.215
1.235
V
1.187
1.215
1.238
V
Thermal Shutdown Temperature
140
°C
MAIN BOOST REGULATOR
VBOOST
Output Voltage Range
FOSC
Oscillator Frequency
1050
1200
DCM
Maximum Duty Cycle
82
85
VFBB
Boost Feedback Voltage
1.192
1.205
1.218
V
1.188
1.205
1.222
V
0.85
0.925
1.020
V
(Note 1)
TA = 25°C
VIN+
15%
18
V
1350
kHz
%
VFTB
FB Fault Trip Level
Falling edge
VBOOST/
IBOOST
Load Regulation
50mA < ILOAD < 250mA
0.1
%
VBOOST/
VIN
Line Regulation
VIN = 2.6V to 5.5V
0.08
%/V
IFB
Input Bias Current
VFB = 1.35V
gmV
FB Transconductance
dI = ±2.5µA at COMP, FB = COMP
RONLX
LX On Resistance
ILEAKLX
LX Leakage Current
VFB = 1.35V, VLX = 13V
0.02
ILIMLX
LX Current Limit
Duty cycle = 65% (Note 1)
3.0
A
tSSB
Soft-Start Period
CDEL = 100nF
7
ms
3
500
nA
160
µA/V
160
m
40
µA
FN6270.0
May 15, 2006
EL7640A, EL7641A, EL7642A
Electrical Specifications
VIN = 3V, VBOOST = VSUP = 12V, VSRC = 20V, Over temperature from -40°C to 85°C.
Unless Otherwise Specified. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
18
V
600
800
µA
3
12
mV
-50
+50
nA
VSUP
V
OPERATIONAL AMPLIFIERS
VSUP
Supply Operating Range
ISUP
Supply Current per Amplifier
VOS
Offset Voltage
IB
Input Bias Current
CMIR
Common Mode Input Range
0
CMRR
Common Mode Rejection Ratio
60
AOL
Open Loop Gain
VOH
Output Voltage High
VOL
Output Voltage Low
4.5
90
dB
110
dB
IOUT = 100µA
VSUP
-15
VSUP
-2
mV
IOUT = 5mA
VSUP
-250
VSUP
-150
mV
IOUT = -100µA
IOUT = -5mA
ISC
Short-Circuit Current
100
ICONT
Continuous Output Current
±50
PSRR
Power Supply Rejection Ratio
60
BW-3dB
2
30
mV
100
150
mV
150
mA
mA
100
dB
-3dB Bandwidth
12
MHz
GBWP
Gain Bandwidth Product
8
MHz
SR
Slew Rate
12
V/µs
POSITIVE LDO
VFBP
Positive Feedback Voltage
IDRVP = 100µA, TA = 25°C
1.176
1.2
1.224
V
IDRVP = 100µA
1.176
1.2
1.229
V
0.9
0.98
V
50
nA
VFTP
VFBP Fault Trip Level
VFBP falling
0.82
IBP
Positive LDO Input Bias Current
VFBP = 1.4V
-50
VPOS/
IPOS
FBP Load Regulation
VDRVP = 25V, IDRVP = 0 to 20µA
IDRVP
Sink Current
VFBP = 1.1V, VDRVP = 10V
ILEAKP
DRVP Off Leakage Current
VFBP = 1.4V, VDRVP = 30V
tSSP
Soft-Start Period
CDEL = 100nF
FBN Regulation Voltage
IDRVN = 0.2mA, TA = 25°C
0.173
0.203
0.233
V
IDRVN = 0.2mA
0.171
0.203
0.235
V
430
480
mV
50
nA
2
0.5
%
4
mA
0.1
10
7
µA
ms
NEGATIVE LDO
VFBN
VFTN
VFBN Fault Trip Level
VFBN rising
380
IBN
Negative LDO Input Bias Current
VFBN = 250mV
-50
FBN Load Regulation
VDRVN = -6V, IDRVN = 2µA to 20µA
IDRVN
Source Current
VFBN = 500mV, VDRVN = -6V
ILEAKN
DRVN Off Leakage Current
VFBP = 1.35V, VDRVP = 30V
tSSN
Soft-start Period
CDEL = 100nF
4
2
0.5
%
4
mA
0.1
7
10
µA
ms
FN6270.0
May 15, 2006
EL7640A, EL7641A, EL7642A
Electrical Specifications
VIN = 3V, VBOOST = VSUP = 12V, VSRC = 20V, Over temperature from -40°C to 85°C.
Unless Otherwise Specified. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
0.4VIN
V
VON -SLICE CIRCUIT
VLO
CTL Input Low Voltage
VIN = 2.6V to 5.5V
VHI
CTL Input High Voltage
VIN = 2.6V to 5.5V
0.6VIN
ILEAKCTL
CTL Input Leakage Current
CTL = AGND or IN
-1
tDrise
CTL to OUT Rising Prop Delay
1k from DRN to 8V, VCTL = 0V to 3V step,
no load on OUT, measured from VCTL = 1.5V
to OUT = 20%
100
ns
tDfall
CTL to OUT Falling Prop Delay
1k from DRN to 8V, VCTL = 3V to 0V step,
no load on OUT, measured from VCTL = 1.5V
to OUT = 80%
100
ns
VSRC
SRC Input Voltage Range
ISRC
SRC Input Current
V
1
µA
30
V
Start-up sequence not completed
150
250
µA
Start-up sequence completed
150
250
µA
RONSRC
SRC On Resistance
Start-up sequence completed
5
10

RONDRN
DRN On Resistance
Start-up sequence completed
30
60

RONCOM
COM to GND On Resistance
Start-up sequence not completed
1000
1800

tON
Turn On Delay
CDEL = 100nF (See Figure 23)
10
ms
tDEL1
Delay Between VBOOST and VOFF
CDEL = 100nF (See Figure 23)
10
ms
tDEL2
Delay Between VON and VOFF
CDEL = 100nF (See Figure 23)
10
ms
tDEL3
Delay From VON to VON-slice Enabled
CDEL = 100nF (See Figure 23)
10
ms
CDEL
Delay Capacitor
100
nF
350
SEQUENCING
22
NOTE:
1. Guaranteed by design.
5
FN6270.0
May 15, 2006
EL7640A, EL7641A, EL7642A
Pin Descriptions
PIN NAME
EL7642A
EL7641A
EL7640A
SRC
1
1
1
Upper reference voltage for switch output
REF
2
2
2
Internal reference bypass terminal
AGND
3
3
3
Analog ground for boost converter and control circuitry
PGND
4
4
4
Power ground for boost switch
OUT1
5
5
5
Operational amplifier 1 output
NEG1
6
6
6
Operational amplifier 1 inverting input
POS1
7
7
7
Operational amplifier 1 non-inverting input
OUT2
8
8
-
Operational amplifier 2 output
NEG2
9
9
-
Operational amplifier 2 inverting input
POS2
10
10
-
Operational amplifier 2 non-inverting input
BGND
11
11
11
POS3
12
15
-
Operational amplifier 3 non-inverting input
NEG3
-
16
-
Operational amplifier 3 inverting input
OUT3
13
17
-
Operational amplifier 3 output
SUP
14
14
14
POS4
15
-
-
Operational amplifier 4 non-inverting input
NEG4
16
-
-
Operational amplifier 4 inverting input
OUT4
17
-
-
Operational amplifier 4 output
POS5
18
-
-
Operational amplifier 5 non-inverting input
NEG5
19
-
-
Operational amplifier 5 inverting input
OUT5
20
-
-
Operational amplifier 5 output
LX
21
21
21
Main boost regulator switch connection
IN
22
22
22
Main supply input; bypass to AGND with 1µF capacitor
FB
23
23
23
Main boost feedback voltage connection
COMP
24
24
24
Error amplifier compensation pin
FBP
25
25
25
Positive LDO feedback connection
DRVP
26
26
26
Positive LDO transistor drive
FBN
27
27
27
Negative LDO feedback connection
DRVN
28
28
28
Negative LDO transistor driver
DEL
29
29
29
Connection for switch delay timing capacitor
CTL
30
30
30
Input control for switch output
DRN
31
31
31
Lower reference voltage for switch output
COM
32
32
32
Switch output; when CTL = 1, COM is connected to SRC through a 15
resistor; when CTL = 0, COM is connected to DRN through a 30 resistor
6
PIN FUNCTION
Operational amplifier ground
Amplifier positive supply rail. Bypass to BGND with 0.1µF capacitor
FN6270.0
May 15, 2006
EL7640A, EL7641A, EL7642A
Typical Performance Curves
100
94
90
92
70
VIN=5V
VIN=3V
60
EFFICIENCY (%)
EFFICIENCY (%)
80
50
40
30
20
88
86
0
82
200
400
600
800
1000
78
1200
0
200
FIGURE 1. BOOST EFFICIENCY AT VOUT = 12V (PI MODE)
800
1000
1200
0
-0.1
LOAD REGULATION (%)
LOAD REGULATION (%)
600
FIGURE 2. BOOST EFFICIENCY AT VOUT = 12V (P MODE)
0
VIN=3V
-0.2
-0.3
-0.4
VIN=5V
-0.5
0
200
400
600
800
1000
-2
-6
-8
VIN=3.3V
-10
-12
-14
1200
VIN=5.0V
-4
0
200
LOAD CURRENT (mA)
0.1
3
LINE REGULATION (%)
3.5
0.08
0.06
0.04
0.02
3
3.5
4
4.5
5
5.5
6
INPUT VOLTAGE (V)
FIGURE 5. BOOST LINE REGULATION vs INPUT VOLTAGE
(PI MODE)
7
600
800
1000
1200
FIGURE 4. BOOST LOAD REGULATION vs LOAD CURRENT
(P MODE)
0.12
0
400
LOAD CURRENT (mA)
FIGURE 3. BOOST LOAD REGULATION vs LOAD CURRENT
(PI MODE)
LINE REGULATION (%)
400
LOAD CURRENT (mA)
LOAD CURRENT (mA)
-0.6
VIN=5V
VIN=3V
84
80
10
0
90
2.5
2
1.5
1
0.5
0
3
3.5
4
4.5
5
5.5
6
INPUT VOLTAGE (V)
FIGURE 6. BOOST LINE REGULATION vs INPUT VOLTAGE
(P MODE)
FN6270.0
May 15, 2006
EL7640A, EL7641A, EL7642A
Typical Performance Curves
(Continued)
BOOST OUTPUT
VOLTAGE
(AC COUPLING)
BOOST OUTPUT
CURRENT
VBOOST=12V
COUT=30µF
LOAD REGULATION (%)
0
VON=20V
-0.05
-0.1
-0.15
-0.2
-0.25
5
10
15
20
25
30
VON LOAD CURRENT (mA)
FIGURE 7. BOOST PULSE LOAD TRANSIENT RESPONSE
FIGURE 8. VON LOAD REGULATION
0
-0.02
LOAD REGULATION (%)
LINE REGULATION (%)
0
-0.04
-0.06
-0.08
VON=20V
ILOAD=20mA
-0.1
-0.12
20
21
22
23
24
INPUT VOLTAGE (V)
25
26
VOFF=-8V
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
5
10
15
20
FIGURE 9. VON LINE REGULATION
30
FIGURE 10. VOFF LOAD REGULATION
0
LINE REGULATION (%)
25
LOAD CURRENT (mA)
VCDEL
-0.1
VBOOST
-0.2
-0.3
VOFF
-0.4
-0.5
-0.6
-15
VON
VOFF=-8V
ILOAD=50mA
-14
-13
-12
-11
INPUT VOLTAGE (V)
FIGURE 11. VOFF LINE REGULATION
8
-10
TIME (20ms/DIV)
FIGURE 12. START-UP SEQUENCE
FN6270.0
May 15, 2006
EL7640A, EL7641A, EL7642A
Typical Performance Curves
(Continued)
INPUT VOLTAGE
INPUT
VBOOST
VOFF
OUTPUT
VON
TIME (50µs/DIV)
TIME (20ms/DIV)
FIGURE 13. START-UP SEQUENCE
JEDEC JESD51-3 AND SEMI G42-88
(SINGLE LAYER) TEST BOARD
0.7
758mW
3
POWER DISSIPATION (W)
POWER DISSIPATION (W)
0.8
FIGURE 14. OP AMP RAIL-TO-RAIL INPUT/OUTPUT
QFN32
0.6
JA=125°C/W
0.5
0.4
0.3
0.2
0.1
0
0
25
75 85 100
50
125
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD QFN EXPOSED DIEPAD SOLDERED TO
PCB PER JESD51-5
2.5 2.857W
QFN32
2
JA=35°C/W
1.5
1
0.5
0
150
0
FIGURE 15. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
The EL7640A, EL7641A, EL7642A integrate an N-channel
MOSFET in boost converter to minimize the external
component counts and cost. The VON, VOFF linearregulators are independently regulated by using external
resistors. To achieve higher voltage than VBOOST, one or
multiple stage charge pumps may be used.
9
50
75 85 100
125
150
FIGURE 16. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Applications Information
The EL7640A, EL7641A, EL7642A provide a highly
integrated multiple output power solution for TFT-LCD
applications. The system consists of one high efficiency
boost converter and two low cost linear-regulator controllers
(VON and VOFF) with multiple protection functions. The
block diagram of the whole part is shown in Figure 17.
Table 1 lists the recommended components.
25
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
TABLE 1. RECOMMENDED COMPONENTS
DESIGNATION
C1, C2, C3
D1
DESCRIPTION
10µF, 16V X5R ceramic capacitor (1210)
TDK C3216X5R0J106K
1A 20V low leakage schottky rectifier
(CASE 457-04)
ON SEMI MBRM120ET3
D11, D12, D21 200mA 30V schottky barrier diode (SOT-23)
Fairchild BAT54S
L1
6.8µH 1.3A Inductor
TDK SLF6025T-6R8M1R3-PF
Q11
200mA 40V PNP amplifier (SOT-23)
Fairchild MMBT3906
Q21
200mA 40V NPN amplifier (SOT-23)
Fairchild MMBT3904
FN6270.0
May 15, 2006
EL7640A, EL7641A, EL7642A
VREF
REFERENCE
GENERATOR
OSCILLATOR
COMP
SLOPE
COMPENSATION

OSC
LX
PWM
LOGIC
CONTROLLER
BUFFER
VOLTAGE
AMPLIFIER
FBB
GM
AMPLIFIER
CINT
PGND
CURRENT
AMPLIFIER
UVLO
COMPARATOR
CURRENT REF
CURRENT
LIMIT COMPARATOR
SHUTDOWN
& START-UP
CONTROL
VREF
SS
+
DRVP
BUFFER
THERMAL
SHUTDOWN
FBP
UVLO
COMPARATOR
SS
+
DRVN
-
0.2V
BUFFER
FBN
0.4V
UVLO
COMPARATOR
FIGURE 17. BLOCK DIAGRAM
Boost Converter
The main boost converter is a current mode PWM converter
operating at a fixed frequency. The 1.2MHz switching
frequency enables the use of low profile inductor and
multilayer ceramic capacitors, which results in a compact,
low cost power system for LCD panel design.
The boost converter can operate in continuous or
discontinuous inductor current mode. The EL7640A,
EL7641A, EL7642A are designed for continuous current
mode, but they can also operate in discontinuous current
mode at light load. In continuous current mode, current flows
continuously in the inductor during the entire switching cycle
in steady state operation. The voltage conversion ratio in
continuous current mode is given by:
V BOOST
1
------------------------ = ------------1–D
V IN
Figure 18 shows the block diagram of the boost controller.
It uses a summing amplifier architecture consisting of GM
stages for voltage feedback, current feedback and slope
compensation. A comparator looks at the peak inductor
current cycle by cycle and terminates the PWM cycle if the
current limit is reached.
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60k is recommended.
The boost converter output voltage is determined by the
following equation:
R1 + R2
V BOOST = ---------------------  V REF
R1
Where D is the duty cycle of switching MOSFET.
10
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May 15, 2006
EL7640A, EL7641A, EL7642A
The current through MOSFET is limited to 3A peak. This
restricts the maximum output current based on the following
equation:
I L
V IN
I OMAX =  I LMT – --------  --------
2  VO
Where IL is peak to peak inductor ripple current, and is set
by:
V IN D
I L = ---------  ----L
fS
where fS is the switching frequency.
CLOCK
SHUTDOWN
& START-UP
CONTROL
SLOPE
COMPENSATION
IFB
CURRENT
AMPLIFIER
PWM
IREF
LX
LOGIC
BUFFER
IFB
FBB
GM
AMPLIFIER
IREF
VOLTAGE
AMPLIFIER
REFERENCE
GENERATOR
COMP
PGND
FIGURE 18. THE BLOCK DIAGRAM OF THE BOOST CONTROLLER
11
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May 15, 2006
EL7640A, EL7641A, EL7642A
The following table gives typical values (margins are
considered 10%, 3%, 20%, 10% and 15% on VIN, VO, L, fS
and ILMT:
TABLE 2.
VIN (V)
VO (V)
L (µH)
fS (MHz)
IOMAX (mA)
3.3
9
6.8
1.2
898
3.3
12
6.8
1.2
622
3.3
15
6.8
1.2
458
5
9
6.8
1.2
1360
5
12
6.8
1.2
944
5
15
6.8
1.2
694
Input Capacitor
The input capacitor is used to supply the current to the
converter. It is recommended that CIN be larger than 10F.
The reflected ripple voltage will be smaller with larger CIN.
The voltage rating of input capacitor should be larger than
maximum input voltage.
Boost Inductor
The boost inductor is a critical part which influences the
output voltage ripple, transient response, and efficiency.
Value of 3.3H to 10H inductor is recommended in
applications to fit the internal slope compensation. The
inductor must be able to handle the following average and
peak current:
I L
I LPK = I LAVG + -------2
For low ESR ceramic capacitors, the output ripple is
dominated by the charging and discharging of the output
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
NOTE: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across them increases.
COUT in the equation above assumes the effective value of the
capacitor at a particular voltage and not the manufacturer’s stated
value, measured at zero volts.
Compensation
The EL7640A, EL7641A, EL7642A can operate in either P
mode or PI mode. Connecting COMP pin directly to VIN will
enable P mode; For better load regulation, use PI mode with
a 2.2nF capacitor and a 180 resistor in series between
COMP pin and ground. To improve the transient response,
either the resistor value can be increased or the capacitor
value can be reduced, but too high resistor value or too low
capacitor value will reduce loop stability.
Boost Feedback Resistors
As the boost output voltage, VBOOST, is reduced below 12V
the effective voltage feedback in the IC increases the ratio of
voltage to current feedback at the summing comparator
because R2 decreases relative to R1. To maintain stable
operation over the complete current range of the IC, the
voltage feedback to the FBB pin should be reduced
proportionally, as VBOOST is reduced, by means of a series
resistor-capacitor network (R7 and C7) in parallel with R1,
with a pole frequency (fp) set to approximately 10kHz. for C2
effective = 10µF and 4kHz for C2 (effective) = 30µF.
R7 = ((1/0.1 x R2) – 1/R1)^-1
IO
I LAVG = ------------1–D
C7 = 1/(2 x 3.142 x fp x R7)
Linear-Regulator Controllers (VON and VOFF)
Rectifier Diode
A high-speed diode is desired due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The rectifier
diode must meet the output current and peak inductor
current requirements.
The EL7640A, EL7641A, EL7642A include 2 independent
linear-regulator controllers, in which there is one positive
output voltage (VON), and one negative voltage (VOFF). The
VON and VOFF linear-regulator controller function diagram,
application circuit and waveforms are shown in Figure 19
and Figure 20 respectively.
Output Capacitor
The output capacitor supplies the load directly and reduces
the ripple voltage at the output. Output ripple voltage
consists of two components: the voltage drop due to the
inductor ripple current flowing through the ESR of output
capacitor, and the charging and discharging of the output
capacitor.
V O – V IN
IO
1
V RIPPLE = I LPK  ESR + ------------------------  ----------------  ----VO
C OUT f S
12
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May 15, 2006
EL7640A, EL7641A, EL7642A
VBOOST
LX
0.1µF
LDO_ON
0.9V
PG_LDOP
+
-
CP (TO 36V)
36V
ESD
CLAMP
RBP
700
0.1µF
VON (TO 35V)
DRVP
FBP
RP1
CON
RP2
20k
+
GMP
The VOFF power supply is used to power the negative
supply of the row driver in the LCD panel. The DC/DC
consists of an external diode-capacitor charge pump
powered from the inductor (LX) of the boost converter,
followed by a low dropout linear regulator (LDO_OFF). The
LDO_OFF regulator uses an external NPN transistor as the
pass element. The onboard LDO controller is a wide band
(>10MHz) transconductance amplifier capable of 5mA
output current, which is sufficient for up to 50mA or more
output current under the low dropout condition (forced beta
of 10). Typical VOFF voltage supported by EL7640A,
EL7641A and EL7642A ranges from -5V to -25V. A fault
comparator is also included for monitoring the output
voltage. The under-voltage threshold is set at 200mV above
the 0.2V reference level.
1: Np
Set-up Output Voltage
FIGURE 19. VON FUNCTIONAL BLOCK DIAGRAM
LX
0.1µF
Refer to Typical Application Diagram, the output voltages of
VON, VOFF and VLOGIC are determined by the following
equations:
R 12

V ON = V REF   1 + ----------
R 11

R 22
V OFF = V REFN + ----------   V REFN – V REF 
R
21
CP (TO -26V)
LDO_OFF
PG_LDON
0.4V
VREF
+
FBN
1: Nn
Where VREF = 1.2V, VREFN = 0.2V.
0.1µF
High Charge Pump Output Voltage (>36V)
Applications
RN2
20k
RN1
VOFF (TO -20V)
+
GMN
DRVN
36V
ESD
CLAMP
RBN
700
COFF
In the applications where the charge pump output voltage is
over 36V, an external NPN transistor needs to be inserted in
between the DRVP pin and the base of pass transistor Q3 as
shown in Figure 21, or the linear regulator can control only
one stage charge pump and regulate the final charge pump
output as shown in Figure 22.
VIN
CHARGE PUMP
OR VBOOST OUTPUT
700
FIGURE 20. VOFF FUNCTIONAL BLOCK DIAGRAM
The VON power supply is used to power the positive supply
of the row driver in the LCD panel. The DC/DC consists of an
external diode-capacitor charge pump powered from the
inductor (LX) of the boost converter, followed by a low
dropout linear regulator (LDO_ON). The LDO_ON regulator
uses an external PNP transistor as the pass element. The
onboard LDO controller is a wide band (>10MHz)
transconductance amplifier capable of 5mA output current,
which is sufficient for up to 50mA or more output current
under the low dropout condition (forced beta of 10). Typical
VON voltage supported by EL7640A, EL7641A and
EL7642A ranges from +15V to +36V. A fault comparator is
also included for monitoring the output voltage. The undervoltage threshold is set at 25% below the 1.2V reference.
13
DRVP
NPN
CASCODE
TRANSISTOR
Q11
VON
EL764X
FBP
FIGURE 21. CASCODE NPN TRANSISTOR CONFIGURATION
FOR HIGH CHARGE PUMP OUTPUT VOLTAGE
(>36V)
FN6270.0
May 15, 2006
EL7640A, EL7641A, EL7642A
LX
0.1µF
VBOOST
0.1µF
700
DRVP
Q11
0.47µF
EL7642A
0.1µF
0.1µF
0.1µF
VON
(>36V)
0.22µF
FBP
FIGURE 22. THE LINEAR REGULATOR CONTROLS ONE STAGE OF CHARGE PUMP
Calculation of the Linear Regulator Base-emitter
Resistors (RBP and RBN)
For the pass transistor of the linear regulator, low frequency
gain (Hfe) and unity gain frequency (fT) are usually specified
in the datasheet. The pass transistor adds a pole to the loop
transfer function at fp = fT/Hfe. Therefore, in order to
maintain phase margin at low frequency, the best choice for
a pass device is often a high frequency low gain switching
transistor. Further improvement can be obtained by adding a
base-emitter resistor RBE (RBP, RBL, RBN in the Functional
Block Diagram), which increases the pole frequency to:
fp = fT*(1+ Hfe *re/RBE)/Hfe, where re = KT/qIc. So choose
the lowest value RBE in the design as long as there is still
enough base current (IB) to support the maximum output
current (IC).
We will take as an example the VON linear regulator. If a
Fairchild MMBT3906 PNP transistor is used as the external
pass transistor, Q11 in the application diagram, then for a
maximum VON operating requirement of 50mA the data
sheet indicates Hfe_min = 60. The base-emitter saturation
voltage is: Vbe_max = 0.7V.
For the EL7640A, EL7641A and EL7642A, the minimum
drive current is:
I_DRVP_min = 2mA
The minimum base-emitter resistor, RBP, can now be
calculated as:
RBP_min = VBE_max/(I_DRVP_min - Ic/Hfe_min) =
0.7V/(2mA - 50mA/60) = 600
This is the minimum value that can be used – so, we now
choose a convenient value greater than this minimum value;
say 700. Larger values may be used to reduce quiescent
current, however, regulation may be adversely affected by
supply noise if RBP is made too high in value.
14
Charge Pump
To generate an output voltage higher than VBOOST, single or
multiple stages of charge pumps are needed. The number of
stage is determined by the input and output voltage. For
positive charge pump stages:
V OUT + V CE – V INPUT
N POSITIVE  -------------------------------------------------------------V INPUT – 2  V F
where VCE is the dropout voltage of the pass component of
the linear regulator. It ranges from 0.3V to 1V depending on
the transistor selected. VF is the forward-voltage of the
charge-pump rectifier diode.
The number of negative charge-pump stages is given by:
V OUTPUT + V CE
N NEGATIVE  ------------------------------------------------V INPUT – 2  V F
To achieve high efficiency and low material cost, the lowest
number of charge-pump stages, which can meet the above
requirements, is always preferred.
Charge Pump Output Capacitors
Ceramic capacitor with low ESR is recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by the following equation:
I OUT
C OUT  -----------------------------------------------------2  V RIPPLE  f OSC
where fOSC is the switching frequency.
Discontinuous/Continuous Boost Operation and
its Effect on the Charge Pumps
The EL7640A, EL7641A and EL7642A VON and VOFF
architecture uses LX switching edges to drive diode charge
pumps from which LDO regulators generate the VON and
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EL7640A, EL7641A, EL7642A
VOFF supplies. It can be appreciated that should a regular
supply of LX switching edges be interrupted, for example
during discontinuous operation at light boost load currents,
then this may affect the performance of VON and VOFF
regulation – depending on their exact loading conditions at
the time.
Start-up Sequence
Figure 23 shows a detailed start-up sequence waveform. For
a successful power-up, there should be 6 peaks at VCDEL.
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
To optimize VON/VOFF regulation, the boundary of
discontinuous/continuous operation of the boost converter
can be adjusted, by suitable choice of inductor given VIN,
VOUT, switching frequency and the VBOOST current loading,
to be in continuous operation.
When the input voltage is higher than 2.4V, an internal
current source starts to charge CCDEL. During the initial slow
ramp, the device checks whether there is a fault condition. If
no fault is found during the initial ramp, CCDEL is discharged
after the first peak. VREF turns on at the peak of the first
ramp.
The following equation gives the boundary between
discontinuous and continuous boost operation. For
continuous operation (LX switching every clock cycle) we
require that:
Initially the boost is not enabled so VBOOST rises to VINVDIODE through the output diode. Hence, there is a step at
VBOOST during this part of the start-up sequence.
I(VBOOST_load) > D*(1-D)*VIN/(2*L*FOSC)
where the duty cycle, D = (VBOOST – VIN)/VBOOST
For example, with VIN = 5V, FOSC = 1.2MHz and VBOOST =
12V we find continuous operation of the boost converter can
be guaranteed for:
L = 10µH and I(VBOOST) > 51mA
L = 6.8µH and I(VBOOST) > 74mA
L = 3.3µH and I(VBOOST) > 153mA
15
VBOOST soft-starts at the beginning of the third ramp, and is
checked at the end of this ramp. The soft-start ramp
depends on the value of the CDEL capacitor. For CDEL of
100nF, the soft-start time is ~7ms.
VOFF turns on at the start of the fourth peak.
VON is enabled at the beginning of the sixth ramp. VOFF and
VON are checked at end of this ramp.
FN6270.0
May 15, 2006
CHIP DISABLED
FAULT DETECTED
VON SOFT-START
VOFF ON
VBOOST
SOFT-START
VREF ON
EL7640A, EL7641A, EL7642A
VCDEL
IN
VREF
VBOOST
tON
tDEL1
VOFF
tDEL2
VON
VON SLICE CIRCUIT
tDEL3
START-UP SEQUENCE
TIMED BY CDEL
NOTE: Not to scale
NORMAL
OPERATION
FAULT
PRESENT
FIGURE 23. START-UP SEQUENCE
Component Selection for Start-up Sequencing and
Fault Protection
The CREF capacitor is typically set at 220nF and is required
to stabilize the VREF output. The range of CREF is from
22nF to 1µF and should not be more than five times the
capacitor on CDEL to ensure correct start-up operation.
The CDEL capacitor is typically 100nF and has a usable
range from 22nF minimum to several microfarads – only
limited by the leakage in the capacitor reaching µA levels.
16
CDEL should be at least 1/5 of the value of CREF (see
above). Note that with 100nF on CDEL the fault time-out will
be typically 23ms and the use of a larger/smaller value will
vary this time proportionally (e.g. 1µF will give a fault timeout period of typically 230ms).
Fault Sequencing
The EL7640A, EL7641A and EL7642A have an advanced
fault detection system which protects the IC from both
adjacent pin shorts during operation and shorts on the output
FN6270.0
May 15, 2006
EL7640A, EL7641A, EL7642A
supplies. A high quality layout/design of the PCB, in respect
of grounding quality and decoupling is necessary to avoid
falsely triggering the fault detection scheme – especially
during start-up. The user is directed to the layout guidelines
and component selection sections to avoid problems during
initial evaluation and prototype PCB generation.
VON -Slice Circuit
The VON-slice Circuit functions as a three way multiplexer,
switching the voltage on COM between ground, DRN and
SRC, under control of the start-up sequence and the CTL pin.
During the start-up sequence, COM is held at ground via an
NDMOS FET, with ~1k impedance. Once the start-up
sequence has completed, CTL is enabled and acts as a
multiplexer control such that if CTL is low, COM connects to
DRN through a 5internal MOSFET, and if CTL is high,
COM connects to SRC via a 30MOSFET.
The slew rate of start-up of the switch control circuit is mainly
restricted by the load capacitance at COM pin as in the
following equation:
Vg
V
-------- = ----------------------------------t
 R i  R L   C L
Driving Capacitive Loads
EL7640A, EL7641A and EL7642A can drive a wide range of
capacitive loads. As load capacitance increases, however,
the –3dB bandwidth of the device will decrease and the
peaking will increase. The amplifiers drive 10pF loads in
parallel with 10k with just 1.5dB of peaking, and 100pF
with 6.4dB of peaking. If less peaking is desired in these
applications, a small series resistor (usually between 5 and
50) can be placed in series with the output. However, this
will obviously reduce the gain. Another method of reducing
peaking is to add a “snubber” circuit at the output. A snubber
is a shunt load consisting of a resistor in series with a
capacitor. Values of 150 and 10nF are typical. The
advantage of a snubber is that it does not draw any DC load
current and reduce the gain.
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point, the device will be latched off
until either the input supply voltage or enable is cycled.
Layout Recommendation
Where Vg is the supply voltage applied to the switch control
circuit, Ri is the resistance between COM and DRN or SRC
including the internal MOSFET rDS(ON), the trace resistance
and the resistor inserted, RL is the load resistance of the
switch control circuit, and CL is the load capacitance of the
switch control circuit.
In the Typical Application Circuit, R8, R9 and C8 give the
bias to DRN based on the following equation:
V ON  R 9 + A VDD  R 8
V DRN = ------------------------------------------------------------R8 + R9
and R10 can be adjusted to adjust the slew rate.
Op Amps
The EL7640A, EL7641A and EL7642A have 1, 3 and 5
amplifiers respectively. The op amps are typically used to
drive the TFT-LCD backplane (VCOM) or the gammacorrection divider string. They feature rail-to-rail input and
output capability, they are unity gain stable, and have low
power consumption (typical 600A per amplifier). The
EL7640A, EL7641A and EL7642A have a –3dB bandwidth
of 12MHz while maintaining a 10V/s slew rate.
Short Circuit Current Limit
The EL7640A, EL7641A and EL7642A will limit the short
circuit current to ±180mA if the output is directly shorted to
the positive or the negative supply. If an output is shorted for
a long time, the junction temperature will trigger the Over
Temperature Protection limit and hence the part will shut
down.
17
The device’s performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place VREF and VDD bypass capacitors close to the pins.
3. Reduce the loop with large AC amplitudes and fast slew
rate.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point.
6. The exposed die plate, on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
FN6270.0
May 15, 2006
EL7640A, EL7641A, EL7642A
9. Minimize feedback input track lengths to avoid switching
noise pick-up.
8. A signal ground plane, separate from the power ground
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return
connections for feedback resistor networks (R1, R11,
R41) and the VREF capacitor, C22, the CDELAY capacitor
C7 and the integrator capacitor C23.
A demo board is available to illustrate the proper layout
implementation.
Typical Application Circuit
D11
0.1µF
VCP
D21
VCN
D12
0.1µF
0.1µF
0.1µF
VIN
(2.6V-5.5V)
AVDD
(9V)
D1
L1 6.8µH
10
10µF
C1
LX
IN
FB
470nF
R2
64.9k
R1
10.2k
PGND
BOOST
R7 OPEN
C7 OPEN
180 COMP
0.1µF
VNEG
(-8V)
2.2nF
700
VCN
R22
470nF R21
GND
DRVN
Q21
82k
NEG
REG
DRVP
POS
REG
FBN
FBP
REF
CONTROL
INPUT
REF
Q11
R12
182k
R11
9.76k
0.1µF
VON
(24.5V)
470nF
SRC
CTL
COM
SW
CTL
DEL
VCP
700
10k
0.1µF
10µFx2
C2
100nF
DRN
TO GATE
DRIVER IC
R10
1k
R8
68k
R9
1k
AVDD
C8
0.1µF
+
VMAIN
VCOM FB4
VCOM4
VCOM SET4
VCOM FB2
VCOM2
VCOM SET2
OUT3
OP3
POS3
VGAMMA
VGAMMA SET
AVDD
NEG4
NEG5
OUT4
POS4
OP4
+
+
OUT5
OP5
NEG2
NEG1
OUT2
POS2
POS5
OP2
+
+
OUT1
OP1
POS1
VCOM FB3
VCOM3
VCOM SET3
VCOM FB1
VCOM1
VCOM SET1
AGND
18
FN6270.0
May 15, 2006
EL7640A, EL7641A, EL7642A
QFN Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
19
FN6270.0
May 15, 2006
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