DATASHEET

ISL59910, ISL59913
®
Data Sheet
December 15, 2006
Triple Differential Receiver/Equalizer
Features
The ISL59910 and ISL59913 are triple channel differential
receivers and equalizers. They each contain three high speed
differential receivers with five programmable poles. The
outputs of these pole blocks are then summed into an output
buffer. The equalization length is set with the voltage on a
single pin. The ISL59910 and ISL59913 output can also be
put into a high impedance state, enabling multiple devices to
be connected in parallel and used in multiplexing application.
• 150MHz -3dB bandwidth
The gain can be adjusted up or down on each channel by 6dB
using its VGAIN control signal. In addition, a further 6dB of gain
can be switched in to provide a matched drive into a cable.
The ISL59910 and ISL59913 have a bandwidth of 150MHz
and consume just 108mA on ±5V supply. A single input
voltage is used to set the compensation levels for the
required length of cable.
The ISL59910 is a special version of the ISL59913 that
decodes syncs encoded onto the common modes of three
pairs of CAT-5 cable by the EL4543. (Refer to the EL4543
datasheet for details.)
The ISL59910 and ISL59913 are available in a 28 Ld QFN
package and are specified for operation over the full -40°C to
+85°C temperature range.
FN6406.0
• CAT-5 compensation
- 100MHz @ 600 ft
- 135MHz @ 300 ft
• 108mA supply current
• Differential input range 3.2V
• Common mode input range -4V to +3.5V
• ±5V supply
• Output to within 1.5V of supplies
• Available in 28 Ld QFN package
• Pb-free plus anneal available (RoHS compliant)
Applications
• Twisted-pair receiving/equalizer
• KVM (Keyboard/Video/Mouse)
• VGA over twisted-pair
• Security video
Pinouts
23 VCM_R
24 VCM_G
25 VCM_B
27 ENABLE
28 0V
23 HOUT
24 VOUT
25 SYNCREF
26 X2
27 ENABLE
28 0V
26 X2
ISL59913
(28 LD QFN)
TOP VIEW
ISL59910
(28 LD QFN)
TOP VIEW
VSMO_B 1
22 VSP
VSMO_B 1
22 VSP
VOUT_B 2
21 VINM_B
VOUT_B 2
21 VINM_B
VSPO_B 3
20 VINP_B
VSPO_B 3
20 VINP_B
19 VINM_G
VSPO_G 4
VSPO_G 4
THERMAL
PAD
VOUT_R 8
15 VSM
VOUT_R 8
15 VSM
VGAIN_B 14
16 VINP_R
VREF 11
18 VINP_G
VGAIN_G 13
VSMO_R 7
VGAIN_R 12
16 VINP_R
VREF 11
VSMO_R 7
VCTRL 10
17 VINM_R
VSPO_R 9
VSMO_G 6
VGAIN_B 14
17 VINM_R
VGAIN_G 13
VSMO_G 6
VGAIN_R 12
VOUT_G 5
VCTRL 10
18 VINP_G
VSPO_R 9
VOUT_G 5
19 VINM_G
THERMAL
PAD
EXPOSED DIEPLATE SHOULD BE CONNECTED TO -5V
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL59910, ISL59913
Ordering Information
PART
NUMBER
PART
MARKING
TAPE & REEL
PACKAGE
PKG.
DWG. #
ISL59910IRZ
(Note)
59910 CRZ
-
28 Ld QFN
(Pb-free)
MDP0046
ISL59910IRZ-T7
(Note)
59910 CRZ
7”
28 Ld QFN
(Pb-free)
MDP0046
ISL59913IRZ
(Note)
59913 CRZ
-
28 Ld QFN
(Pb-free)
MDP0046
ISL59913IRZ-T7
(Note)
59913 CRZ
7”
28 Ld QFN
(Pb-free)
MDP0046
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6406.0
December 15, 2006
ISL59910, ISL59913
Absolute Maximum Ratings (TA = +25°C)
Operating Conditions
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . . .12V
Maximum Continuous Output Current per Channel. . . . . . . . . 30mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, exposed die plate = -5V, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
Bandwidth
(See Figure 1)
150
MHz
SR
Slew Rate
VIN = -1V to +1V, VG = 0.39, VC = 0,
RL = 75 + 75Ω
1.5
kV/µs
THD
Total Harmonic Distortion
10MHz 2VP-P out, VG = 1V, X2 gain, VC = 0
-50
dBc
DC PERFORMANCE
V(VOUT)OS
Offset Voltage
X2 = high, no equalization
-110
-15
+110
mV
ΔVOS
Channel-to-Channel Offset Matching X2 = high, no equalization
-140
0
+140
mV
INPUT CHARACTERISTICS
CMIR
Common-Mode Input Range
-4/+3.5
V
ONOISE
Output Noise
VG = 0V, VC = 0V, X2 = HIGH, RLOAD = 150Ω,
Input 50Ω to GND, 10MHz
-110
dBm
CMRR
Common-Mode Rejection Ratio
Measured at 10kHz
-80
dB
CMRR
Common-Mode Rejection Ratio
Measured at 10MHz
-55
dB
CMBW
CM Amplifier Bandwidth
10k || 10pF load
50
MHz
CMSLEW
CM Slew Rate
Measured @ +1V to -1V
100
V/µs
CINDIFF
Differential Input Capacitance
Capacitance VINP to VINM
600
fF
RINDIFF
Differential Input Resistance
Resistance VINP to VINM
CINCM
CM Input Capacitance
Capacitance VINP = VINM to GND
RINCM
CM Input Resistance
Resistance VINP = VINM to GND
+IIN
Positive Input Current
DC bias @ VINP = VINM = 0V
-IIN
Negative Input Current
DC bias @ VINP = VINM = 0V
VINDIFF
Differential Input Range
VINP - VINM when slope gain falls to 0.9
1
MΩ
1.2
pF
1
MΩ
1
µA
1
µA
2.5
V
OUTPUT CHARACTERISTICS
V(VOUT)
Output Voltage Swing
RL = 150Ω
I(VOUT)
Output Drive Current
RL = 10Ω, VINP = 1V, VINM = 0V, X2 = high,
VG = 0.39
R(VCM)
CM Output Resistance of
VCM_R/G/B (ISL59913 only)
at 100kHz
Gain
Gain
VC = 0, VG = 0.39, X2 = 5, RL = 150Ω
ΔGain @ DC
Channel-to-Channel Gain Matching
ΔGain @
15MHz
Channel-to-Channel Gain Matching
V(SYNC)HI
High Level output on V/HOUT
(ISL59910 only)
3
50
0.85
±3.5
V
60
mA
30
Ω
1.0
1.1
VC = 0, VG = 0.39, X2 = 5, RL = 150Ω
3
8
%
VC = 0.6, VG = 0.39, X2 = 5, RL = 150Ω,
Frequency = 15MHz
3
11
%
V(VSP)
- 0.1V
V(VSP)
FN6406.0
December 15, 2006
ISL59910, ISL59913
Electrical Specifications
PARAMETER
V(SYNC)LO
VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, exposed die plate = -5V, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
Low Level output on V/HOUT
(ISL59910 only)
TYP
V(SYNC
REF)
MAX
UNIT
V(SYNC
REF)
+ 0.1V
SUPPLY
ISON
Supply Current per Channel
VENBL = 5, VINM = 0
32
ISOFF
Supply Current per Channel
VENBL = 0, VINM = 0
0.2
PSRR
Power Supply Rejection Ratio
DC to 100kHz, ±5V supply
36
39
mA
0.4
mA
65
dB
LOGIC CONTROL PINS (ENABLE, X2)
VHI
Logic High Level
VIN - VLOGIC ref for guaranteed high level
VLOW
Logic Low Level
VIN - VLOGIC ref for guaranteed low level
0.8
V
ILOGICH
Logic High Input Current
VIN = 5V, VLOGIC = 0V
50
µA
ILOGICL
Logic Low Input Current
VIN = 0V, VLOGIC = 0V
15
µA
1.4
V
Pin Descriptions
ISL59910
ISL59913
PIN
NUMBER
PIN NAME
1
VSMO_B
-5V to blue output buffer
VSMO_B
-5V to blue output buffer
2
VOUT_B
Blue output voltage referenced to 0V pin
VOUT_B
Blue output voltage referenced to 0V pin
3
VSPO_B
+5V to blue output buffer
VSPO_B
+5V to blue output buffer
4
VSPO_G
+5V to green output buffer
VSPO_G
+5V to green output buffer
5
VOUT_G
Green output voltage referenced to 0V pin
VOUT_G
Green output voltage referenced to 0V pin
6
VSMO_G
-5V to green output buffer
VSMO_G
-5V to green output buffer
7
VSMO_R
-5V to red output buffer
VSMO_R
-5V to red output buffer
8
VOUT_R
Red output voltage referenced to 0V pin
VOUT_R
Red output voltage referenced to 0V pin
9
VSPO_R
+5V to red output buffer
VSPO_R
+5V to red output buffer
10
VCTRL
11
VREF
12
VGAIN_R
Red channel gain voltage (0V to 1V)
VGAIN_R
Red channel gain voltage (0V to 1V)
13
VGAIN_G
Green channel gain voltage (0V to 1V)
VGAIN_G
Green channel gain voltage (0V to 1V)
14
VGAIN_B
Blue channel gain voltage (0V to 1V)
VGAIN_B
Blue channel gain voltage (0V to 1V)
15
VSM
16
VINP_R
Red positive differential input
VINP_R
Red positive differential input
17
VINM_R
Red negative differential input
VINM_R
Red negative differential input
18
VINP_G
Green positive differential input
VINP_G
Green positive differential input
19
VINM_G
Green negative differential input
VINM_G
Green negative differential input
20
VINP_B
Blue positive differential input
VINP_B
Blue positive differential input
21
VINM_B
Blue negative differential input
VINM_B
Blue negative differential input
22
VSP
23
HOUT
Decoded Horizontal sync referenced to
SYNCREF
VCM_R
Red common-mode voltage at inputs
24
VOUT
Decoded Vertical sync referenced to SYNCREF
VCM_G
Green common-mode voltage at inputs
25
SYNCREF
Reference level for HOUT and VOUT logic outputs
VCM_B
Blue common-mode voltage at inputs
PIN FUNCTION
Equalization control voltage (0V to 0.95V)
Reference voltage for logic signals, VCTRL and
VGAIN pins
-5V to core of chip
+5V to core of chip
4
PIN NAME
VCTRL
VREF
VSM
VSP
PIN FUNCTION
Equalization control voltage (0V to 0.95V)
Reference voltage for logic signals, VCTRL and
VGAIN pins
-5V to core of chip
+5V to core of chip
FN6406.0
December 15, 2006
ISL59910, ISL59913
Pin Descriptions
(Continued)
ISL59910
PIN
NUMBER
PIN NAME
26
X2
27
ENABLE
28
0V
PIN FUNCTION
Logic signal for x1/x2 output gain setting
Chip enable logic signal
0V reference for output voltage
Thermal Pad
ISL59913
PIN NAME
X2
ENABLE
0V
PIN FUNCTION
Logic signal for x1/x2 output gain setting
Chip enable logic signal
0V reference for output voltage
Must be connected to -5V
Typical Performance Curves
5
X2=HIGH
VGAIN=0.35V
VCTRL=0V
RLOAD=150Ω
GAIN (dB)
X2=LOW
VGAIN=0V
3 VCTRL=0V
RLOAD=150
1
-1
-3
-5
1M
10M
100M 200M
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE OF ALL CHANNELS
X2=LOW
VS=±5V
RL=150Ω
VGAIN=0V
VCTRL=0.1V STEPS
Source=-20dBm
VCTRL=1V
FIGURE 2. GAIN vs FREQUENCY ALL CHANNELS
X2=LOW
VS=±5V
RL=150Ω
Source=-20dBm
VCTRL=0.25V
VGAIN=0.25V
VCTRL=0V
VGAIN=0.25V
VCTRL=0V
VGAIN=0V
VCTRL=0V
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS VCTRL
5
FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS VCTRL AND
VGAIN
FN6406.0
December 15, 2006
ISL59910, ISL59913
Typical Performance Curves (Continued)
VCTRL=1V
CABLE=600FT
X2=LOW
VCTRL=1V
VS=±5V
CABLE=3FT
RL=150Ω
VGAIN=1V
SOURCE=-20dBm
X2=LOW
VGAIN=0.5V
VCTRL=0.5V
RLOAD=150Ω
VCTRL=0V
CABLE=3FT
VCTRL=0V
CABLE=600FT
FIGURE 5. GAIN vs FREQUENCY FOR VARIOUS VCTRL AND
CABLE LENGTHS
VS=±5V, RL=150Ω
INPUT 50Ω TO GROUND
X2=HIGH
VCTRL=0V
RLOAD=150Ω
INPUT=50Ω TO GND
VGAIN=1V
X2=LOW
X2=HiGH
VCTRL=0V
X2=LOW
VCTRL=0V
FIGURE 7. OFFSET vs VCTRL
X2=HIGH
VS=±5V
RL=150Ω
VCTRL=0V
VGAIN=1V
TOTAL
HARMONIC
FIGURE 6. CHANNEL MISMATCH
FIGURE 8. DC GAIN vs VGAIN
X2=HIGH
VS=±5V
RL=150Ω
INPUT=50Ω TO GROUND
VCTRL=0V
VGAIN=0V
3rd
HARMONIC
2nd
HAMONIC
FIGURE 9. HARMONIC DISTORTION vs FREQUENCY
6
VCTRL=0V
VGAIN=1V
VCTRL=1V
VGAIN=1V
VCTRL=1V
VGAIN=0V
FIGURE 10. OUTPUT NOISE
FN6406.0
December 15, 2006
ISL59910, ISL59913
-10
4
VGAIN=0.35V
(ALL CHANNELS)
-20 VCTRL=0V
X2=HIGH
VGAIN=0.35V
(ALL CHANNELS)
2 VCTRL=0V
RLOAD=150Ω
X2=HIGH
GAIN (dB)
CMRR (dB)
Typical Performance Curves (Continued)
-40
-60
-80
0
-2
-4
-100
100k
1M
10M
-6
100k
100M
1M
FREQUENCY (Hz)
FIGURE 12. CM AMPLIFIER BANDWIDTH
0
-20
VCC=5V
VCTRL=0V
-20 VGAIN=0V
(ALL CHANNELS)
INPUTS ON GND
VEE=-5V
VCTRL=0V
-40 VGAIN=0V
(ALL CHANNELS)
INPUTS ON GND
-PSRR (dB)
+PSRR (dB)
100M
FREQUENCY (Hz)
FIGURE 11. COMMON-MODE REJECTION
-40
-60
-60
-80
-100
-80
-100
10
10M
100
1k
10k
100k
1M
10M
100M
-120
10
100
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. (+)PSRR vs FREQUENCY
1k
FIGURE 14. (-)PSRR vs FREQUENCY
BLUE
GREEN
RED
FIGURE 15. BLUE CROSSTALK (CABLE LENGTH = 3ft.)
7
X2=LOW
VS=±5V
RL=150Ω
VCTRL=1V
VGAIN=1V
FIGURE 16. BLUE CROSSTALK (CABLE LENGTH = 600ft.)
FN6406.0
December 15, 2006
ISL59910, ISL59913
Typical Performance Curves (Continued)
GREEN
RED
X2=LOW
VS=±5V
RL=150Ω
VCTRL=1V
VGAIN=1V
BLUE
FIGURE 17. GREEN CROSSTALK (CABLE LENGTH = 3ft.)
FIGURE 18. GREEN CROSSTALK (CABLE LENGTH = 600ft.)
RED
GREEN
BLUE
FIGURE 19. RED CROSSTALK (CABLE LENGTH = 3ft.)
X2=LOW
VS=±5V
RL=150Ω
VCTRL=1V
VGAIN=1V
FIGURE 20. RED CROSSTALK (CABLE LENGTH =600ft.)
VCTRL=0V
CABLE=3FT
VCTRL=0.2V
CABLE=600FT
X2=HIGH
VS=±5V
RL=150Ω
VGAIN=0V
INPUT=10MHz
FIGURE 21. RISE TIME AND FALL TIME
8
FIGURE 22. PULSE RESPONSE FOR VARIOUS CABLE
LENGTHS
FN6406.0
December 15, 2006
ISL59910, ISL59913
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
1.2
4.5
POWER DISSIPATION (W)
POWER DISSIPATION (W)
4
3.5 3.378W
3
θ
JA
2.5
QF
=3
7
2
N2
°C
8
/W
1.5
1
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
893mW
0.8
θ
JA =
0.6
QF
N2
14
8
0°
C/
W
0.4
0.2
0.5
0
0
0
25
50
75 85 100
125
150
0
Applications Information
Logic Control
The ISL59913 has two logical input pins, Chip Enable
(ENABLE) and Switch Gain (X2). The logic circuits all have a
nominal threshold of 1.1V above the potential of the logic
reference pin (VREF). In most applications it is expected that
this chip will run from a +5V, 0V, -5V supply system with logic
being run between 0V and +5V. In this case the logic
reference voltage should be tied to the 0V supply. If the logic
is referenced to the -5V rail, then the logic reference should
be connected to -5V. The logic reference pin sources about
60µA and this will rise to about 200µA if all inputs are true
(positive).
The logic inputs all source up to 10µA when they are held at
the logic reference level. When taken positive, the inputs
sink a current dependent on the high level, up to 50µA for a
high level 5V above the reference level.
The logic inputs, if not used, should be tied to the
appropriate voltage in order to define their state.
Control Reference and Signal Reference
Analog control voltages are required to set the equalizer and
contrast levels. These signals are voltages in the range
0V to 1V, which are referenced to the control reference pin. It
is expected that the control reference pin will be tied to 0V
and the control voltage will vary from 0V to 1V. It is; however,
acceptable to connect the control reference to any potential
between -5V and 0V to which the control voltages are
referenced.
The control voltage pins themselves are high impedance.
The control reference pin will source between 0µA and
200µA depending on the control voltages being applied.
9
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
25
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
The control reference and logic reference effectively remove
the necessity for the 0V rail and operation from ±5V (or 0V
and 10V) only is possible. However we still need a further
reference to define the 0V level of the single ended output
signal. The reference for the output signal is provided by the
0V pin. The output stage cannot pull fully up or down to either
supply so it is important that the reference is positioned to
allow full output swing. The 0V reference should be tied to a
'quiet ground' as any noise on this pin is transferred directly to
the output. The 0V pin is a high impedance pin and draws DC
bias currents of a few µA and similar levels of AC current.
Equalizing
When transmitting a signal across a twisted pair cable, it is
found that the high frequency (above 1MHz) information is
attenuated more significantly than the information at low
frequencies. The attenuation is predominantly due to resistive
skin effect losses and has a loss curve which depends on the
resistivity of the conductor, surface condition of the wire and the
wire diameter. For the range of high performance twisted pair
cables based on 24awg copper wire (CAT-5 etc). These
parameters vary only a little between cable types and in general
cables exhibit the same frequency dependence of loss. (The
lower loss cables can be compared with somewhat longer
lengths of their more lossy brothers.) This enables a single
equalizing law equation to be built into the ISL59913.
With a control voltage applied between pins VCTRL and
VREF, the frequency dependence of the equalization is
shown in Figure 8. The equalization matches the cable loss
up to about 100MHz. Above this, system gain is rolled off
rapidly to reduce noise bandwidth. The roll-off occurs more
rapidly for higher control voltages, thus the system (cable +
equalizer) bandwidth reduces as the cable length increases.
This is desirable, as noise becomes an increasing issue as
the equalization increases.
FN6406.0
December 15, 2006
ISL59910, ISL59913
2
BLUE CM
OUT (CH A)
VOLTAGE
(0.5V/DIV)
By varying the voltage between pins VGAIN and VREF, the
gain of the signal path can be changed in the ratio 4:1. The
gain change varies almost linearly with control voltage. For
normal operation it is anticipated the X2 mode will be selected
and the output load will be back matched. A unity gain to the
output load will then be achieved with a gain control voltage of
about 0.35V. This allows the gain to be trimmed up or down by
6dB to compensate for any gain/loss errors that affect the
contrast of the video signal. Figure 26 shows an example plot
of the gain to the load with gain control voltage.
an internal logic decoding block to provide Horizontal and
Vertical sync output signals (HOUT and VOUT).
GREEN CM
OUT (CH B)
RED CM
OUT (CH C)
VSYNC
VOLTAGE
(2.5V/DIV)
Contrast
HSYNC
1.8
TIME (0.5ms/DIV)
GAIN (V)
1.6
FIGURE 26. H AND V SYNCS ENCODED
1.4
TABLE 1. H AND V SYNC DECODING
1.2
RED CM
GREEN CM
BLUE CM
HSYNC
VSYNC
0.8
Mid
High
Low
Low
Low
0.6
High
Low
Mid
Low
High
Low
High
Mid
High
Low
Mid
Low
High
High
High
1
0.4
0
0.2
0.4
0.6
0.8
1
VGAIN
FIGURE 25. VARIATION OF GAIN WITH GAIN CONTROL
VOLTAGE
Common Mode Sync Decoding
The ISL59910 features common mode decoding to allow
horizontal and vertical synchronization information, which has
been encoded on the three differential inputs by the EL4543,
to be decoded. The entire RGB video signal can therefore be
transmitted, along with the associated synchronization
information, by using just three twisted pairs.
NOTE: Level ‘Mid’ is halfway between ‘High’ and ‘Low’
Power Dissipation
The ISL59910 and ISL59913 are designed to operate with
±5V supply voltages. The supply currents are tested in
production and guaranteed to be less than 39mA per
channel. Operating at ±5V power supply, the total power
dissipation is:
V OUTMAX
PD MAX = 3 × 2 × V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------R
L
Decoding is based on the EL4543 encoding scheme, as
described in Figure 26 and Table 1. The scheme is a three-level
system, which has been designed such that the sum of the
common mode voltages results in a fixed average DC level with
no AC content. This eliminates the effect of EMI radiation into
the common mode signals along the twisted pairs of the cable
where:
The common mode voltages are initially extracted by the
ISL59910 from the three input pairs. These are then passed to
• IMAX = Maximum quiescent supply current per
channel = 39mA
(EQ. 1)
• PDMAX = Maximum power dissipation
• VS = Supply voltage = 5V
• VOUTMAX = Maximum output voltage swing of the
application = 2V
RL = Load resistance = 150Ω Ω
(EQ. 2)
PD MAX = 1.29W
θJA required for long term reliable operation can be
calculated. This is done using Equation 3:
10
FN6406.0
December 15, 2006
ISL59910, ISL59913
Where
( Tj – Ta )
θ JA = ----------------------- = 50.4CW
PD
(EQ. 3)
Tj is the maximum junction temperature (+150°C)
Ta is the maximum ambient temperature (+85°C)
For a QFN 28 package in a properly layout PCB heatsinking
copper area, +37°C/W θJA thermal resistance can be
achieved. To disperse the heat, the bottom heatspreader
must be soldered to the PCB. Heat flows through the
heatspreader to the circuit board copper then spreads and
converts to air. Thus the PCB copper plane becomes the
heatsink. This has proven to be a very effective technique. A
separate application note details the 28 Ld QFN. PCB
design considerations are available.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN6406.0
December 15, 2006
ISL59910, ISL59913
QFN (Quad Flat No-Lead) Package Family
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
A
SYMBOL QFN44 QFN38
D
N
(N-1)
(N-2)
B
1
2
3
PIN #1
I.D. MARK
E
(N/2)
2X
0.075 C
2X
0.075 C
N LEADS
TOP VIEW
QFN32
TOLERANCE
NOTES
A
0.90
0.90
0.90
0.90
±0.10
-
A1
0.02
0.02
0.02
0.02
+0.03/-0.02
-
b
0.25
0.25
0.23
0.22
±0.02
-
c
0.20
0.20
0.20
0.20
Reference
-
D
7.00
5.00
8.00
5.00
D2
5.10
3.80
5.80 3.60/2.48
E
7.00
7.00
8.00
E2
5.10
5.80
5.80 4.60/3.40
e
0.50
0.50
0.80
L
0.55
0.40
0.53
Basic
-
Reference
8
6.00
Basic
-
Reference
8
0.50
Basic
-
0.50
±0.05
-
N
44
38
32
32
Reference
4
ND
11
7
8
7
Reference
6
NE
11
12
8
9
Reference
5
0.10 M C A B
(N-2)
(N-1)
N
b
L
PIN #1 I.D.
3
1
2
3
(E2)
(N/2)
NE 5
7
(D2)
BOTTOM VIEW
0.10 C
e
C
SYMBOL QFN28 QFN24
QFN20
QFN16
TOLERANCE NOTES
A
0.90
0.90
0.90
0.90
0.90
±0.10
-
A1
0.02
0.02
0.02
0.02
0.02
+0.03/
-0.02
-
b
0.25
0.25
0.30
0.25
0.33
±0.02
-
c
0.20
0.20
0.20
0.20
0.20
Reference
-
D
4.00
4.00
5.00
4.00
4.00
Basic
-
D2
2.65
2.80
3.70
2.70
2.40
Reference
-
E
5.00
5.00
5.00
4.00
4.00
Basic
-
E2
3.65
3.80
3.70
2.70
2.40
Reference
-
e
0.50
0.50
0.65
0.50
0.65
Basic
-
L
0.40
0.40
0.40
0.40
0.60
±0.05
-
N
28
24
20
20
16
Reference
4
ND
6
5
5
5
4
Reference
6
NE
8
7
5
5
4
Reference
5
Rev 10 12/04
SEATING
PLANE
NOTES:
0.08 C
N LEADS
& EXPOSED PAD
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
SEE DETAIL "X"
2. Tiebar view shown is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
SIDE VIEW
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
(c)
C
2
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
A
(L)
A1
N LEADS
DETAIL X
12
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
FN6406.0
December 15, 2006
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