DATASHEET

EL4584
®
Data Sheet
May 9, 2008
Horizontal Genlock, 4FSC
Features
The EL4584 is a PLL (Phase Lock Loop) sub system,
designed for video applications but also suitable for general
purpose use up to 36MHz. In video applications, this device
generates a TTL/CMOS compatible Pixel Clock (CLK OUT)
which is a multiple of the TV horizontal scan rate and phase
locked to it.
• 36MHz, general purpose PLL
FN7174.3
• 4FSC based timing (use the EL4585 for 8FSC)
• Compatible with EL4583 sync separator
• VCXO, Xtal, or LC tank oscillator
• < 2ns jitter (VCXO)
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog
composite video signal with the EL4583 Sync Separator. An
input signal to “coast” is provided for applications where
periodic disturbances are present in the reference video
timing, such as VTR head switching. The Lock detector
output indicates correct lock.
The divider ratio is four ratios for NTSC and four similar
ratios for the PAL video timing standards, by external
selection of three control pins. These four ratios have been
selected for common video applications including 4FSC,
3FSC, 13.5MHz (CCIR 601 format) and square picture
elements used in some workstation graphics. To generate
8FSC, 6FSC, 27MHz (CCIR 601 format) etc. use the
EL4585, which includes an additional divide-by-two stage.
For applications where these frequencies are inappropriate
or for general purpose PLL applications, the internal divider
can be bypassed and an external divider chain used.
• User controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed TV scan rate clock divisors
• Selectable external divide for custom ratios
• Single 5V, low current operation
• Pb-Free available (RoHS compliant)
Applications
• Pixel clock regeneration
• Video compression engine (MPEG) clock generator
• Video capture or digitization
• PIP (Picture-in-Picture) timing generator
• Text or graphics overlay timing
Ordering Information
TABLE 1. FREQUENCIES AND DIVISORS
FUNCTION
Divisor
PAL FOSC (MHz)
Divisor
NTSC FOSC (MHz)
3FSC
(Note 1)
CCIR 601
(Note 2)
SQUARE
(Note 3)
4FSC
851
864
944
1135
13.301
13.5
14.75
17.734
682
858
780
910
10.738
13.5
12.273
14.318
PART NUMBER
NOTES:
1. 3FSC numbers do not yield integer divisors.
2. CCIR 601 Divisors yield 720 pixels in the portion of each line for
NTSC and PAL.
3. Square pixels format gives 640 pixels for NTSC and 768 pixels
for PAL in the active portion.
PART
MARKING
PACKAGE
PKG.
DWG. #
EL4584CN
EL4584CN
16 Ld PDIP MDP0031
EL4584CS*
EL4584CS
16 Ld SOIC MDP0027
EL4584CSZ*
(Note)
EL4584CSZ 16 Ld SOIC MDP0027
(Pb-free)
*Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
**For 6FSC and 8FSC clock frequencies, see EL4585 datasheet.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Demo Board
A demo PCB is available for this product.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003-2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL4584
Pinout
EL4584
(16 LD SOIC, PDIP)
TOP VIEW
PROG B 1
16 PROG A
PROG C 2
15 CLK OUT
OSC/VCO OUT 3
VDD (A) 4
OSC/VCO IN 5
VSS (A) 6
CHARGE PUMP OUT 7
DIV SELECT 8
2
14 VSS (D)
13 EXT DIVIDER
12 LOCK DETECT
11 VDD (D)
10 HSYNC IN
9 COAST
FN7174.3
May 9, 2008
EL4584
Absolute Maximum Ratings (TA = +25°C)
VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW
Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36MHz
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
VDD = 5V, TA = +25°C unless otherwise noted.
PARAMETER
CONDITIONS
IDD
MIN
VDD = 5V (Note 4)
TYP
MAX
UNIT
2
4
mA
1.5
V
VIL Input Low Voltage
VIH Input High Voltage
3.5
V
-100
nA
IIL Input Low Current
All inputs except COAST, VIN = 1.5V
IIH Input High Current
All inputs except COAST, VIN = 3.5V
IIL Input Low Current
COAST pin, VIN = 1.5V
IIH Input High Current
COAST pin, VIN = 3.5V
VOL Output Low Voltage
Lock Det, IOL = 1.6mA
VOH Output High Voltage
Lock Det, IOH = -1.6mA
VOL Output Low Voltage
CLK, IOL = 3.2mA
VOH Output High Voltage
CLK, IOH = -3.2mA
VOL Output Low Voltage
OSC Out, IOL = 200µA
VOH Output High Voltage
OSC Out, IOH = -200µA
2.4
IOL Output Low Current
Filter Out, VOUT = 2.5V
200
IOH Output High Current
Filter Out, VOUT = 2.5V
IOL/IOH Current Ratio
Filter Out, VOUT = 2.5V
ILEAK Filter Out
Coast Mode, VDD > VOUT > 0V
100
-100
-60
60
nA
µA
100
µA
0.4
V
2.4
V
0.4
2.4
V
V
0.4
V
V
300
µA
-300
-200
µA
1.05
1.0
0.95
-100
±1
100
nA
MIN
TYP
MAX
UNIT
NOTE:
4. All inputs to 0V, COAST floating.
AC Electrical Specifications
VDD = 5V, TA = +25°C unless otherwise noted.
PARAMETER
CONDITIONS
VCO Gain @ 20MHz
Test circuit 1
15.5
HSYNC S/N Ratio
VDD = 5V (Note 5)
Jitter
VCXO oscillator
1
ns
Jitter
LC oscillator (Typ)
10
ns
35
dB
dB
NOTE:
5. Noisy video signal input to EL4583, HSYNC input to EL4584. Test for positive signal lock.
3
FN7174.3
May 9, 2008
EL4584
Pin Descriptions
PIN NUMBER
PIN NAME
1, 2, 16
FUNCTION
PROG B,
Digital inputs to select ÷ N value for internal counter. See Table 2 for values.
PROG C, PROG A
3
OSC/VCO OUT
Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit.
4
VDD (A)
5
OSC/VCO IN
6
VSS (A)
7
CHARGE PUMP
OUT
Connect to loop filter. If the HSYNC phase is leading or HSYNC frequency > CLK ÷ N, current is pumped
into the filter capacitor to increase VCO frequency. If HSYNC phase is lagging or frequency < CLK ÷ N,
current is pumped out of the filter capacitor to decrease VCO frequency. During coast mode or when
locked, charge pump goes to a high impedance state.
8
DIV SELECT
Divide select input. When high, the internal divider is enabled and EXT DIV becomes a test pin, outputting
CLK ÷ N. When low, the internal divider is disabled and EXT DIV is an input from an external ÷ N.
9
COAST
10
HSYNC IN
11
VDD (D)
12
LOCK DETECT
13
EXT DIVIDER
14
VSS (D)
15
CLK OUT
Analog positive supply for oscillator, PLL circuits.
Input from external VCO.
Analog ground for oscillator, PLL circuits.
Tri-state logic input. Low (<1/3*VCC) = normal mode, Hi Z (or 1/3 to 2/3*VCC) = fast lock mode,
High (>2/3*VCC) = coast mode.
Horizontal sync pulse (CMOS level) input.
Positive supply for digital, I/O circuits.
Lock Detect output. Low level when PLL is locked. Pulses high when out of lock.
External Divide input when DIV SEL is low, internal ÷N output when DIV SEL is high.
Ground for digital, I/O circuits.
Buffered output of the VCO.
TABLE 2. VCO DIVISORS
PROG A (PIN 16)
PROG B (PIN 1)
PROG C (PIN 2)
DIV VALUE (N)
0
0
0
851
0
0
1
864
0
1
0
944
0
1
1
1135
1
0
0
682
1
0
1
858
1
1
0
780
1
1
1
910
4
FN7174.3
May 9, 2008
EL4584
Timing Diagrams
FALLING EDGE OF HSYNC +
200ns LOCKS TO RISING EDGE
OF EXT DIV SIGNAL.
200
FIGURE 1. PLL LOCKED CONDITION (PHASE ERROR = 0)
200
ΘE = (tΘ/tH) × 360°
tH = HSYNC PERIOD
tΘ = PHASE ERROR PERIOD
FIGURE 2. OUT OF LOCK CONDITION
FIGURE 3. TEST CIRCUIT 1
5
FN7174.3
May 9, 2008
EL4584
Typical Performance Curves
FIGURE 4. IDD vs FOSC
FIGURE 5. EL4584 OSC GAIN @ 20MHz vs TEMPERATURE
FIGURE 6. TYPICAL VARACTOR
FIGURE 7. OSC GAIN vs FOSC
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
POWER DISSIPATION (W)
1.8
1.6
1.4
1.23W
1.2
PDIP16
θJA = +81°C/W
1.0 0.91W
0.8
0.6
SO16 (0.150”)
θJA = +110°C/W
0.4
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 8. CHARGE PUMP DUTY CYCLE vs θE
6
FIGURE 9. PACKAGE POWER DISSIPATION VS AMBIENT
TEMPERATURE
FN7174.3
May 9, 2008
EL4584
Typical Performance Curves
(Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
POWER DISSIPATION (W)
2.0
1.8
1.6
1.43W
1.4 1.25W
1.2
PDIP16
θJA = +70°C/W
1.0
0.8
SO16 (0.150”)
θJA = +80°C/W
0.6
0.4
0.2
0
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 10. PACKAGE POWER DISSIPATION VS AMBIENT TEMPERATURE
Block Diagram
Description Of Operation
The horizontal sync signal (CMOS level, falling leading
edge) is input to HSYNC input (pin 10). This signal is delayed
about 200ns, the falling edge of which becomes the
reference to which the clock output will be locked (see
“Timing Diagrams” on page 5 and page 6). The clock is
generated by the signal on pin 5, OSC IN. There are 2
general types of VCO that can be used with the EL4584; LC
and crystal controlled. Additionally, each type can be either
built-up using discrete components, including a varactor as
the frequency controlling element, or complete, self
contained modules can be purchased with everything inside
a metal can. The modules are very forgiving of PCB layout,
but cost more than discrete solutions. The VCO or VCXO is
used to generate the clock. An LC tank resonator has
greater “pull” than a crystal controlled circuit, but will also be
more likely to drift over time, and thus will generate more
jitter. The “pullability” of the circuit refers to the ability to “pull”
the frequency of oscillation away from its center frequency
by modulating the voltage on the control pin of a VCO
module or varactor, and is a function of the slope and range
7
of the capacitance-voltage curve of the varactor or VCO
module used. The VCO signal is sent to a divide by N
counter, and to the CLK OUT pin. The divisor N is
determined by the state of pins 1, 2 and 16 and is described
in Table 2. The divided signal is sent, along with the delayed
HSYNC input, to the phase/frequency detector, which
compares the two signals for phase and frequency
differences. Any phase difference is converted to a current at
the charge pump output FILTER (pin 7). A VCO with positive
frequency deviation with control voltage must be used.
Varactors have negative capacitance slope with voltage,
resulting in positive frequency deviation with control voltage
for the oscillators in Figures 12 and 13.
VCO
The VCO should be tuned so its frequency of oscillation is
very close to the required clock output frequency when the
voltage on the varactor is 2.5V. VCXO and VCO modules are
already tuned to the desired frequency, so this step is not
necessary if using one of these units. The range of the
charge pump output (pin 7) is 0V to 5V and it can source or
sink a maximum of about 300µA, so all frequency control
FN7174.3
May 9, 2008
EL4584
must be accomplished with variable capacitance from the
varactor within this range. Crystal oscillators are more stable
than LC oscillators, which translates into lower jitter, but LC
oscillators can be pulled from their mid-point values further,
resulting in a greater capture and locking range. If the
incoming horizontal sync signal is known to be very stable,
then a crystal oscillator circuit can be used. If the HSYNC
signal experiences frequency variations of greater than
about 300ppm, an LC oscillator should be considered, as
crystal oscillators are very difficult to pull this far. When
HSYNC input frequency is greater than CLK frequency ÷ N,
charge pump output (pin 7) sources current into the filter
capacitor, increasing the voltage across the varactor, which
lowers its capacitance, thus tending to increase VCO
frequency. Conversely, filter output pulls current from the
filter capacitor when HSYNC frequency is less than CLK ÷ N,
forcing the VCO frequency lower.
VCO frequency. Modulation will continue until the phase and
frequency of CLK ÷ N exactly match the HSYNC input. When
the phase and frequency match (with some offset in phase
that is a function of the VCO characteristics), the error signal
goes to zero, lock detect no longer pulses high, and the
charge pump enters a high impedance state. The clock is now
locked to the HSYNC input. As long as phase and frequency
differences remain small, the PLL can adjust the VCO to
remain locked and lock detect remains low.
Loop Filter
Forcing the clock to be synchronized to the HSYNC input this
way allows a lock in approximately 2 H-cycles, but the clock
spacing will not be regular during this time. Once the near
lock condition is attained, charge pump output should be
very close to its lock-on value and placing the device into
normal mode should result in a normal lock very quickly.
Fast Lock mode is intended to be used where HSYNC
becomes irregular, until a stable signal is again obtained.
The loop filter controls how fast the VCO will respond to a
change in filter output stimulus. Its components should be
chosen so that fast lock can be achieved, yet with a minimum
of VCO “hunting”, preferably in one to two oscillations of
charge pump output, assuming the VCO frequency starts
within capture range. If the filter is under-damped, the VCO
will over and under-shoot the desired operating point many
times before a stable lock takes place. It is possible to
under-damp the filter so much that the loop itself oscillates,
and VCO lock is never achieved. If the filter is over-damped,
the VCO response time will be excessive and many cycles will
be required for a lock condition. Over-damping is also
characterized by an easily unlocked system because the filter
can’t respond fast enough to perturbations in VCO frequency.
A severely over-damped system will seem to endlessly
oscillate, like a very large mass at the end of a long pendulum.
Due to parasitic effects of PCB traces and component
variables, it will take some trial and error experimentation to
determine the best values to use for any given situation. Use
the component tables as a starting point, but be aware that
deviation from these values is not out of the ordinary.
Fast Lock Mode
Fast Lock mode is enabled by either allowing coast to float, or
pulling it to mid supply (between 1/3 and 2/3*VCC). In this
mode, lock is achieved much faster than in normal mode, but
the clock divisor is modified on the fly to achieve this. If the
phase detector detects an error of enough magnitude, the clock
is either inhibited or reset to attempt a “fast” lock of the signals.
Coast Mode
Coast mode is enabled by pulling the COAST (pin 9) high
(above 2/3*VCC). In coast mode, the internal phase detector
is disabled and filter out remains in high impedance mode to
keep filter out voltage and VCO frequency as constant as
possible. VCO frequency will drift as charge leaks from the
filter capacitor, and the voltage changes the VCO operating
point. Coast mode is intended to be used when noise or
signal degradation results in loss of horizontal sync for many
cycles. The phase detector will not attempt to adjust to the
resultant loss of signal so that when horizontal sync returns,
sync lock can be re-established quickly. However, if much
VCO drift has occurred, it may take as long to re-lock as
when restarting.
External Divide
Lock Detect
DIV SELECT (pin 8) controls the use of the internal divider.
When high, the internal divider is enabled and EXT DIVIDER
(pin 13) outputs the CLK out divided by N. This is the signal
to which the horizontal sync input will lock. When divide
select is low, the internal divider output is disabled, and the
external divide becomes an input from an external divider, so
that a divisor other than one of the 8 pre-programmed
internal divisors can be used.
LOCK DETECT (pin 12) will go low when lock is established.
Any DC current path from charge pump out will skew EXT
DIVIDER relative to HSYNC IN, tending to offset or add to
the 200ns internal delay, depending on which way the extra
current is flowing. This offset is called static phase error, and
is always present in any PLL system. If, when the part
stabilizes in a locked mode, lock detect is not low, adding or
subtracting from the loop filter series resistor R2 will change
this static phase error to allow LDET to go low while in lock.
The goal is to put the rising edge of EXT DIVIDER in sync
with the falling edge of HSYNC + 200ns (see “Timing
Diagrams” on page 5 and page 5). Increasing R2 decreases
phase error, while decreasing R2 increases phase error
(phase error is positive when EXT DIVIDER lags HSYNC.)
Normal Mode
Normal mode is enabled by pulling COAST (pin 9) low (below
1/3*VCC). If HSYNC and CLK ÷ N have any phase or
frequency difference, an error signal is generated and sent to
the charge pump. The charge pump will either force current
into or out of the filter capacitor in an attempt to modulate the
8
FN7174.3
May 9, 2008
EL4584
The resistance needed will depend on VCO design or VCXO
module selection.
Applications Information
Choosing External Components
1. To choose LC VCO components, first pick the desired
operating frequency. For our example, we will use
14.31818MHz, with an HSYNC frequency of 15.734kHz.
2. Choose a reasonable inductor value (10µH to 20µH
works well). We choose 15µH.
3. Calculate CT needed to produce FOSC, as shown in
Equations 1 and 2.
1
F OSC = ----------------------2π LC T
(EQ. 1)
FIGURE 12. TYPICAL LC VCO
1
1
C T = --------------------- = --------------------------------------------------------------------- = 8.2pF
2 2
2
2
4π ( 14.318e6 ) ( 15e – 6 )
4π F L
(EQ. 2)
TABLE 3. LC VCO COMPONENT VALUES (APPROXIMATE)
(NOTE)
4. From the varactor data sheet find CV @ 2.5V, the desired
lock voltage. CV = 23pF for our SMV1204-12, for
example.
FREQUENCY
(MHZ)
L1
(µH)
C1
(pF)
C2
(pF)
13.301
15
18
220
5. C2 should be about 10CV, so we choose C2 = 220pF for
our example.
13.5
15
17
220
14.75
12
18
220
6. Calculate C1 using Equations 3 and 4. Since:
17.734
12
10
220
10.738
22
20
220
12.273
18
17
220
14.318
15
14
220
C1 C2 CV
C T = ---------------------------------------------------------------------------( C 1 C 2 ) + ( C 1 C V ) + ( C 2 C V )′
(EQ. 3)
then:
C2 CT CV
C 1 = -------------------------------------------------------------------------( C2 CV ) –( C2 CT ) – ( CT CV ) ′
(EQ. 4)
NOTE: Use shielded inductors for optimum performance.
For our example, C1 = 14pF (a trim capacitor may be used
for fine tuning). Examples for each frequency using the
internal divider follow.
Typical Application
Horizontal genlock provides clock for an analog to digital
converter, digitizing analog video.
FIGURE 13. TYPICAL XTAL VCO
FIGURE 11.
9
TABLE 4. XTAL VCO COMPONENT VALUES
(APPROXIMATE)
FREQUENCY
(MHz)
R1
(kΩ)
C1
(pF)
C2
(µF)
13.301
300
15
0.001
13.5
300
15
0.001
14.75
300
15
0.001
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May 9, 2008
EL4584
Where:
TABLE 4. XTAL VCO COMPONENT VALUES
(APPROXIMATE) (Continued)
Kd = phase detector gain in A/rad
FREQUENCY
(MHz)
R1
(kΩ)
C1
(pF)
C2
(µF)
17.734
300
15
0.001
KVCO = VCO gain in rad/s/V
10.738
300
15
0.001
N = internal or external divisor
12.273
300
15
0.001
14.318
300
15
0.001
The above oscillators are arranged as Colpitts oscillators,
and the structure is redrawn here to emphasize the split
capacitance used in a Colpitts oscillator. It should be noted
that this oscillator configuration is just one of literally
hundreds possible, and the configuration shown here does
not necessarily represent the best solution for all
applications. Crystal manufacturers are very informative
sources on the design and use of oscillators in a wide variety
of applications, and the reader is encouraged to become
familiar with them.
F(s) = loop filter impedance in V/A
It can be shown that for the loop filter shown in Equation 7:
C3
2Nξω n
K d K VCO
C 3 = ------------------------, C 4 = -------, R 3 = -----------------------2
10
K d K VCO
Nω
n
(EQ. 7)
Where ϖn = loop filter bandwidth, and ζ = loop filter damping
factor.
1. Kd = 300µA/2πrad = 4.77e-5A/rad for the EL4584.
2. The loop bandwidth should be about HSYNC
frequency/20, and the damping ratio should be 1 for
optimum performance. For our example,
ϖn = 15.734kHz/20 = 787Hz≈5000rad/S.
3. N = 910 from Table 2.
VCOfrequency
14.31818M
N = ---------------------------------------------------------- = ------------------------------ = 910
H – SYNCfrequency
15.73426k
(EQ. 8)
4. KVCO represents how much the VCO frequency changes
for each volt applied at the control pin. It is assumed (but
probably is not) linear about the lock point (2.5V). Its
value depends on the VCO configuration and the varactor
transfer function CV = F(VC), where VC is the reverse
bias control voltage, and CV is varactor capacitance.
Since F(VC) is nonlinear, it is probably best to build the
VCO and measure KVCO about 2.5V. The results of one
such measurement are shown in the following. The slope
of the curve is determined by linear regression
techniques and equals KVCO. For our example,
KVCO = 6.05 Mrad/S/V.
FIGURE 14. COLPITTS OSCILLATOR
C1 is to adjust the center frequency, C2 DC isolates the
control from the oscillator, and V1 is the primary control
device. C2 should be much larger than CV so that V1 has
maximum modulation capability. The frequency of oscillation
is given by Equations 5 and 6:
1
F = -------------------------12π LC T
(EQ. 5)
C1 C2 CV
C T = -------------------------------------------------------------------------( C1 C2 ) + ( C1 CV ) + ( C2 CV )
(EQ. 6)
Choosing Loop Filter Components
The PLL, VCO, and loop filter can be represented in Figure 15:
FIGURE 16. FOSC vs VC, LC VCO
5. Now we can solve for C3, C4, and R3. We choose
R3 = 30kΩ for convenience.
FIGURE 15.
10
6. Notice R2 has little effect on the loop filter design. R2
should be large, around 100k, and can be adjusted to
compensate for any static phase error tθ at lock, but if
made too large, will slow loop response. If R2 is made
FN7174.3
May 9, 2008
EL4584
smaller, tθ (see “Timing Diagrams” on page 5) increases,
and if R2 increases, tθ decreases. For LDET to be low at
lock, |tθ| < 50 ns. C4 is used mainly to attenuate high
frequency noise from the charge pump.
K d K VCO
( 4.77e – 5 ) ( 6.05e6 )
C 3 = ------------------------ = ------------------------------------------------------ = 0.01µF
2
2
( 910 ) ( 5000 )
Nω
n
C3
C 4 = ------- = 0.0001µF
10
2Nζω n
( 2 ) ( 910 ) ( 1 ) ( 5000 )
R 3 = ------------------------ = ------------------------------------------------------ = 31.5kΩ
( 4.77e – 5 ) ( 6.05e6 )
K d K VCO
(EQ. 9)
(EQ. 10)
(EQ. 11)
Lock Time
Let = R3C3. As t increases, damping increases, but so does
lock time. Decreasing t decreases damping and speeds up
loop response, but increases overshoot and thus increases
the number of hunting oscillations before lock. Critical
damping (ζ = 1) occurs at minimum lock time. Because
decreased damping also decreases loop stability, it is
sometimes desirable to design slightly overdamped (ζ > 1),
trading lock time for increased stability.
FIGURE 17. TYPICAL LOOP FILTER
TABLE 5. LC LOOP FILTER COMPONENTS (APPROXIMATE)
FREQUENCY
(MHz)
R2
(kΩ)
R3
(kΩ)
C3
(µF)
C4
(µF)
13.301
100
30
0.01
0.001
13.5
100
30
0.01
0.001
14.75
100
33
0.01
0.001
17.734
100
39
0.01
0.001
10.738
100
22
0.01
0.001
12.273
100
27
0.01
0.001
14.318
100
30
0.01
0.001
11
TABLE 6. XTAL LOOP FILTER COMPONENTS
(APPROXIMATE)
FREQUENCY
(MHz)
R2
(kΩ)
R3
(MΩ)
C3
(pF)
C4
(pF)
13.301
100
4.3
68
6.8
13.5
100
4.3
68
6.8
14.75
100
4.3
68
6.8
17.734
100
4.3
68
6.8
10.738
100
4.3
68
6.8
12.273
100
4.3
68
6.8
14.318
100
4.3
68
6.8
PCB Layout Considerations
It is highly recommended that power and ground planes be
used in layout. The oscillator and filter sections constitute a
feedback loop and thus care must be taken to avoid any
feedback signal influencing the oscillator except at the
control input. The entire oscillator/filter section should be
surrounded by copper ground to prevent unwanted
influences from nearby signals. Use separate paths for
analog and digital supplies, keeping the analog (oscillator
section) as short and free from spurious signals as possible.
Careful attention must be paid to correct bypassing. Keep
lead lengths short and place bypass capacitors as close to
the supply pins as possible. If laying out a PCB to use
discrete components for the VCO section, care must be
taken to avoid parasitic capacitance at the OSC pins 3 and
5, and FILTER out (pin 7). Remove ground and power plane
copper above and below these traces to avoid making a
capacitive connection to them. It is also recommended to
enclose the oscillator section within a shielded cage to
reduce external influences on the VCO, as they tend to be
very sensitive to “handwaving” influences, the LC variety
being more sensitive than crystal controlled oscillators. In
general, the higher the operating frequency, the more
important these considerations are. Self contained VCXO or
VCO modules are already mounted in a shielding cage and
therefore do not require as much consideration in layout.
Many crystal manufacturers publish informative literature
regarding use and layout of oscillators which should be
helpful.
The VCO and loop filter section of the EL4583, EL4584,
EL4585 demo board can be implemented in Figures 18, 19
and 20.
FN7174.3
May 9, 2008
EL4584
FIGURE 18. VCXO
FIGURE 20. LC TANK
FIGURE 19. XTAL
Demo Board
+5V
+5V
12
FN7174.3
May 9, 2008
EL4584
Component Sources
Inductors
• Dale Electronics
E. Highway 50
PO Box 180
Yankton, SD 57078-0180
(605) 665-9301
• SaRonix
151 Laura Lane
Palo Alto, CA 94043
(415) 856-6900
• Standard Crystal
9940 Baldwin Place
El Monte, CA 91731
(818) 443-2121
Crystals, VCXO, VCO Modules
Varactors
• Connor-Winfield
2111 Comprehensive Drive
Aurora, IL 60606
(708) 851-4722
• Sky Works Solutions Inc.
20 Sylvan Road
Woburn, MA 01801
(781) 376-3000
www.skyworksinc.com
• Piezo Systems
100 K Street
PO Box 619
Carlisle, PA 17013
(717) 249-2151
• Motorola Semiconductor Products
2100 E. Elliot
Tempe, AZ 85284
(602) 244-6900
• Reeves-Hoffman
400 West North Street
Carlisle, PA 17013
(717) 243-5929
Note: These sources are provided for information purposes
only. No endorsement of these companies is implied by this
listing.
13
FN7174.3
May 9, 2008
EL4584
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
14
FN7174.3
May 9, 2008
EL4584
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN7174.3
May 9, 2008
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