DATASHEET

HA457
Data Sheet
August 1999
95MHz, Low Power, AV = 2, 8 x 8 Video
Crosspoint Switch
File Number
4231.2
Features
The HA457 is an 8 x 8 video crosspoint switch suitable for
high performance video systems. Its high level of integration
significantly reduces component count, board space, and
cost. The crosspoint switch contains a digitally controlled
matrix of 64 fully buffered switches that connect eight video
input signals to any, or all, matrix outputs. Each matrix output
connects to an internal, high-speed (275V/µs), gain of two
buffer capable of driving 150Ω to ±2.5V.
The HA457 will directly drive a double terminated video
cable with some degradation of differential gain and phase.
Applications demanding the best composite video
performance should drive the cable with a unity gain video
buffer, such as the HFA1412 quad buffer (see Figure 7).
This crosspoint’s three-state output capability makes it
feasible to parallel multiple HA457s and form larger switch
matrices.
• Pin Compatible, Cable Driving Upgrade for HA456 and
MAX456
• Fully Buffered Inputs and Outputs (AV = +2)
• Routes Any Input Channel to Any Output Channel
• Switches Standard and High Resolution Video Signals
• Serial or Parallel Digital Interface
• Expandable for Larger Switch Matrices
• Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 95MHz
• High Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . 275V/µs
• Low Crosstalk at 10MHz . . . . . . . . . . . . . . . . . . . . -55dB
Applications
• Video Switching and Routing
• Security and Video Editing Systems
Ordering Information
TEMP.
RANGE (oC)
PART NUMBER
PACKAGE
PKG. NO.
HA457CN
0 to 70
44 Ld MQFP
Q44.10x10
HA457CM
0 to 70
44 Ld PLCC
N44.65
Pinouts
28
27
26
7
8
OUT3
AGND
OUT4
NC
AGND
OUT5
AGND
OUT6
V+
A0
IN1
NC
IN2
DGND
NC
IN3
DGND
IN4
EDGE/LEVEL
IN5
5 4
OUT7
CE
CE
LATCH
WR
NC
V-
V+
SER/PAR
IN7
1
3
2 1 44 43 42 41 40
7
8
39
38
9
37
10
11
36
12
35
34
13
33
14
15
32
31
16
30
17
29
OUT2
VOUT3
AGND
OUT4
NC
AGND
OUT5
AGND
OUT6
V+
18 19 20 21 22 23 24 25 26 27 28
V+
IN6
25
9
24
10
11
23
12 13 14 15 16 17 18 19 20 21 22
6
OUT2
V-
SER/PAR
IN7
VNC
WR
LATCH
CE
CE
OUT7
6
IN0
A1
A2
D0/SER IN
D1/SER OUT
NC
V+
OUT0
D2
OUT1
D3
D3
OUT1
D2
OUT0
V+
NC
D1/SER OUT
D0/SER IN
A2
HA457 (PLCC)
TOP VIEW
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
IN6
A0
IN1
NC
IN2
DGND
NC
IN3
DGND
IN4
EDGE/LEVEL
IN5
A1
IN0
HA457 (MQFP)
TOP VIEW
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
HA457
Functional Block Diagram
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
OUTPUT
BUFFERS
(AV = 2)
+
OUT0
EN0
HA457
8x8
SWITCH
MATRIX
+
OUT7
EN7
EN0:7
LATCH
SLAVE REGISTER
SER/PAR
MASTER REGISTER
D0/SER IN
A0
2
A1
A2
D2
D3
EDGE/LEVEL
WR
CE
CE
D1/SER OUT
HA457
Pin Descriptions
PIN
MQFP
PLCC
NAME
3, 6, 17, 28, 39
1, 9, 12, 23, 34
NC
40
2
D1/ SER OUT
Parallel Data Bit input D1 for parallel programming mode. Serial Data Output (MSB of shift
register) for cascading multiple HA457s in serial programming mode. Simply connect
Serial Data Out of one HA457 to Serial Data In of another HA457 to daisy chain multiple
devices.
41
3
D0/SER IN
Parallel Data Bit input D0 for parallel programming mode. Serial Data Input (input to shift
register) for serial programming mode.
42, 43, 1
4, 5, 7
A2, A1, A0
Output Channel Address Bits. These inputs select the output being programmed in parallel
programming mode.
44, 2, 4, 7, 9, 11,
13, 15
6, 8, 10, 13,
15, 17, 19, 21
IN0-IN7
Analog Video Input Lines.
5, 8
11, 14
DGND
Digital Ground. Connect both DGND pins to AGND.
10
16
EDGE/LEVEL
12, 23, 38
18, 29, 44
V+
14
20
SER/PAR
16, 32
22, 38
V-
Negative supply voltage. Connect both V- pins together and decouple each pin to AGND
(Figure 6).
18
24
WR
WRITE Input. In serial mode, data shifts into the shift register (Master Register) LSB from
SER IN on the WR rising edge. In parallel mode, the Master Register loads with D3:0 (iff
D3:0=0000 through 1000), or the appropriate action is taken (iff D3:0=1011 through 1111),
on the WR rising edge (see Table 1).
19
25
LATCH
Synchronous channel switch control input. If EDGE/LEVEL = 1, data is loaded from the
Master Register to the Slave Register on the rising edge of LATCH. If EDGE/LEVEL = 0,
data is loaded from the Master to the Slave Register while LATCH = 0. In parallel mode,
commands 1011 through 1110 execute asynchronously, on the WR rising edge,
regardless of the state of LATCH or EDGE/LEVEL. Parallel mode command 1111
executes a software “Latch” (see Table 1).
20
26
CE
Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.
21
27
CE
Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.
22, 24, 26, 29,
31, 33, 35, 37
28, 30, 32, 35,
37, 39, 41, 43
OUT7-OUT0
25, 27, 30
31, 33, 36
AGND
34
40
D3
Parallel Data Bit Input D3 when SER/PAR = 0. D3 is unused with serial programming.
36
42
D2
Parallel Data Bit Input D2 when SER/PAR = 0. D2 is unused with serial programming.
3
FUNCTION
No connect. Not internally connected.
A user strapped input that defines whether synchronous channel switching is edge or level
controlled. With this pin strapped high, the slave register loads from the master register
(thus changing the switch matrix state) on the rising edge of the LATCH signal. If it is
strapped low (level mode), the slave register is transparent while LATCH is low, passing
data directly from the master register to the switch state decoders. Strapping EDGE/LEVEL
and LATCH low causes the channel switch to execute on the WR rising edge (not
recommended for serial mode operation).
Positive supply voltage. Connect all V+ pins together and decouple each pin to AGND
(Figure 6).
A user strapped input that defines whether the serial (SER/PAR=1) or parallel
(SER/PAR=0) digital programming interface is being utilized.
Analog Video Outputs.
Analog Ground.
HA457
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Positive Supply Voltage (V+) Referred to AGND . . . . . . . . . . . . . 6V
Negative Supply Voltage (V-) Referred to AGND . . . . . . . . . . . . -6V
DGND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND ±1V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY
Digital Input Voltage . . . . . . . . . . . . . . (V+ + 0.3V) to (DGND - 0.3V)
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . 1.6kV
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature, Soldering 10s . . . . . . . . . . . . . 300oC
(Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . ±4.5V to ±5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
VSUPPLY = ±5V, AGND = DGND = 0V, RL = 400Ω (Note 2), Unless Otherwise Specified.
Electrical Specifications
PARAMETER
TEST CONDITIONS
VIN = -0.75V to +0.75V, Worst Case
Switch Configuration,
RL = 150Ω
Voltage Gain
Channel-to-Channel Gain Mismatch
Supply Current
Disabled Supply Current
(NOTE 3)
TEST
LEVEL
TEMP
(oC)
MIN
TYP
MAX
UNITS
A
25
1.93
1.97
2.10
V/V
A
Full
-
-
-
A
25
-
0.04
0.1
A
Full
-
-
-
V/V
All Outputs Enabled, RL = Open,
VIN = 0V,
Total for All V+ (3) or V- (2) Pins
A
25
-
68
80
A
Full
-
71
83
All Outputs Disabled, RL = Open,
Total for All V+ (3) or V- (2) Pins
A
25
-
47
65
A
Full
-
47
67
A
Full
±2
±2.5
-
V
12
µA
Input Voltage Range
mA
mA
Analog Input Current
VIN = 0V
A
Full
-
1.6
Input Noise (RS = 75Ω)
DC to 40MHz
B
25
-
0.15
-
mVRMS
≥10kHz
B
25
-
22
-
nV/√Hz
Analog Input Resistance
DC
C
25
-
4
-
MΩ
Analog Input Capacitance (Input Connected to
One Output or All Outputs, Note 6)
PLCC Package
B
25
-
3.2
-
pF
MQFP Package
B
25
-
2.5
-
pF
Input Offset Voltage
VIN = 0V, Worst Case Switch
Configuration
A
25
-18
-12
5
mV
A
Full
-20
-15
6
Channel-to-Channel Input Offset Voltage
Mismatch
A
25
-
4
11
A
Full
-
8
-
Input Offset Voltage Drift
B
Full
-
20
-
µV/oC
A
25
±2.45
±2.6
-
V
A
Full
-
-
-
V
B
25
-
0.25
-
Ω
mV
Output Voltage Swing
VIN = ±1.33V, RL = 150Ω
Output Resistance
Enabled, DC
Output Disabled
A
25
1.5
2
-
kΩ
Output Capacitance
(Output Disabled)
PLCC Package
B
25
-
3.5
-
pF
MQFP Package
B
25
-
2.9
-
pF
Power Supply Rejection Ratio
DC, VS = ±4.5V to ±5.5V, VIN = 0V
A
Full
45
53
-
dB
Digital Input Current (Note 5)
VIN = 0V or 5V
A
Full
-
-
1
µA
4
HA457
VSUPPLY = ±5V, AGND = DGND = 0V, RL = 400Ω (Note 2), Unless Otherwise Specified. (Continued)
Electrical Specifications
(NOTE 3)
TEST
LEVEL
TEMP
(oC)
Digital Input Low Voltage
A
Digital Input High Voltage
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Full
-
-
0.8
V
25
2.0
-
-
V
A
Full
2.2
-
-
V
SER OUT Logic Low Voltage
Serial Mode, IOL = 1.6mA
A
Full
-
-
0.4
V
SER OUT Logic High Voltage
Serial Mode, IOH = -0.4mA
A
Full
3.0
-
-
V
SER OUT Leakage Current
Output Disabled, VOUT = 2.5V
A
25
-
0.2
5
µA
A
Full
-
1
10
µA
VOUT = 200mVP-P
B
25
-
95
-
MHz
VOUT = 1VP-P
B
25
-
75
-
MHz
VOUT = 2VP-P
B
25
-
60
-
MHz
VOUT = 2VP-P, RL = 150Ω
B
25
-
50
-
MHz
VOUT = 4VP-P, RL = 150Ω
B
25
-
275
-
V/µs
AC CHARACTERISTICS (Note 4)
-3dB Bandwidth (Note 6)
Slew Rate (Note 6)
All Hostile Crosstalk (Note 6)
All Hostile Off Isolation (Note 6)
10MHz, VIN = 1VP-P , RL = 150Ω
B
25
-
-55
-
dB
10MHz, VIN = 1VP-P , RL = 1kΩ
B
25
-
-58
-
dB
10MHz, VIN = 1VP-P , RL = 150Ω
B
25
-
95
-
dB
10MHz, VIN = 1VP-P , RL = 1kΩ
B
25
-
75
-
dB
NTSC or PAL, RL = 150Ω
B
25
-
0.5
-
DEG
NTSC or PAL, RL = 1kΩ
B
25
-
0.05
-
DEG
NTSC or PAL, RL ≥ 10kΩ
B
25
-
0.05
-
DEG
NTSC or PAL, RL = 150Ω
B
25
-
0.05
-
%
NTSC or PAL, RL = 1kΩ
B
25
-
0.05
-
%
NTSC or PAL, RL ≥ 10kΩ
B
25
-
0.02
-
%
Write Pulse Width High (tWH)
A
Full
20
-
-
ns
Write Pulse Width Low (tWL)
A
Full
20
-
-
ns
Chip-Enable Setup Time to Write (tCS)
A
Full
5
-
-
ns
Differential Phase
Differential Gain
TIMING CHARACTERISTICS (See Figure 8 for more information)
Chip-Enable Hold Time From Write (tCH)
Data and Address Setup Time to Write (tDS)
A
Full
5
-
-
ns
Parallel Mode
A
Full
20
-
-
ns
Serial Mode
A
Full
20
-
-
ns
Data and Address Hold Time From Write (tDH)
A
Full
25
-
-
ns
Latch Pulse Width (tL)
A
Full
40
-
-
ns
A
Full
40
-
-
ns
LATCH Edge to Output Disabled (tOFF)
Latch Delay From Write (tD)
Serial Mode
B
Full
-
30
-
ns
LATCH Edge to Output Enabled (tON)
Serial Mode
B
Full
-
185
-
ns
Output Break-Before-Make Delay
(tON - tOFF)
Serial Mode
B
Full
-
155
-
ns
NOTES:
2. For the lowest crosstalk, and the best composite video performance, use RL ≥ 1kΩ.
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
4. See AC Test Circuits (Figure 1 through Figure 4).
5. Excludes D1/SER OUT which is a bidirectional terminal and thus falls under the higher Output Leakage limit.
6. See Typical Performance Curves for more information.
5
HA457
AC Test Circuits
IN0
OUT0
VOUT
IN1
OUT1
VOUT
OUT2
IN2
OUT2
VOUT
IN3
OUT3
IN3
OUT3
VOUT
IN4
OUT4
IN4
OUT4
VOUT
IN5
OUT5
IN5
OUT5
VOUT
IN6
OUT6
IN6
OUT6
VOUT
IN7
OUT7
IN7
OUT7
VOUT
OUT0
IN0
IN1
OUT1
IN2
VOUT
VIN = 1VP-P, AT 10MHz
VIN = 1VP-P, SWEEP FREQUENCY
FIGURE 1. -3dB BANDWIDTH (NOTES 7-10)
7 X 75Ω
IN0
OUT0
VOUT
IN1
OUT1
VOUT
IN2
OUT2
VOUT
IN3
OUT3
IN4
IN5
FIGURE 2. ALL HOSTILE OFF ISOLATION (NOTES 10-12)
IN0
OUT0
IN1
OUT1
IN2
OUT2
VOUT
IN3
OUT3
OUT4
VOUT
IN4
OUT4
OUT5
VOUT
IN5
OUT5
IN6
OUT6
VOUT
IN6
OUT6
IN7
OUT7
IN7
OUT7
75Ω
VOUT
VIN = 1VP-P, AT 10MHz
VIN = 1VP-P, AT 10MHz
FIGURE 3. SINGLE CHANNEL CROSSTALK (NOTES 10, 13-16)
FIGURE 4. ALL HOSTILE CROSSTALK (NOTES 10, 15, 17-19)
NOTES:
7. Program the desired input to output combination (e.g., IN7 to OUT1).
8. Enable the selected output(s).
9. Drive the selected input with VIN, and measure the -3dB frequency at the selected output (VOUT).
10. Load all outputs with the desired RL.
11. Disable all outputs.
12. Drive all inputs with VIN and measure VOUT at any output; Isolation (in dB) = -20log10 (VOUT/VIN).
13. Drive VIN on one input which connects to one output (e.g., IN7 to OUT7).
14. Terminate all other inputs to GND.
15. Enable all outputs.
16. Measure VOUT at any undriven output; Crosstalk (in dB) = 20log10 (VOUT/VIN).
17. Terminate one input to GND, and connect that input to a single output (e.g., IN0 to OUT0).
18. Drive the other seven inputs with VIN, and connect these active inputs to the remaining seven outputs.
19. Measure VOUT at the quiescent output; Crosstalk (in dB) = 20log10 (VOUT/VIN).
6
HA457
HA457
75Ω
75Ω
INPUT
BUFFERS
VIDEO
INPUTS
8X8
SWITCH
MATRIX
WR
LATCH
VIDEO
OUT
AV = 2
A2
A1
A0
OUTPUT
SELECT
INPUT
SELECT AND
COMMAND
CODES OR
SERIAL I/O
D3
D2
D1/SER OUT
D0/SER IN
FIGURE 5. TYPICAL CABLE DRIVING APPLICATION
Application Information
HA457 Architecture
The HA457 video crosspoint switch consists of 64 switches
in an 8 x 8 grid (Figure 5). Each input is fully buffered and
presents a constant input capacitance whether the input
connects to one output or all eight outputs. This yields
consistent input termination impedances regardless of the
switch configuration. The 8 matrix outputs are followed by 8
gain of 2, wideband, three-stateable buffers optimized for
driving 1kΩ loads. Double terminated video cables
(RL = 150Ω) may be driven if degraded differential phase is
acceptable (see “Electrical Specification” Table). The output
disable function is useful for multiplexing two or more
HA457s to create a larger input matrix (e.g., two multiplexed
HA457s yield a 16x8 crosspoint).
The HA457 outputs can be disabled individually or
collectively under software control. When disabled, an output
enters a pseudo high-impedance state (ROUT = 2kΩ). In
multichip parallel applications, the disable function prevents
inactive outputs from loading lines driven by other devices.
Disabling an unused output also reduces power
consumption.
The HA457 outputs connect easily to two HFA1412 quad,
unity gain buffers when 75Ω loads must be driven with
excellent differential phase (see Figures 7 and 21). The
bandwidth improves to 120MHz, while differential gain and
differential phase improve to 0.03% and 0.09 degrees,
respectively.
Power-On RESET
The HA457 has an internal power-on reset (POR) circuit that
disables all outputs at power-up, and presets the switch
matrix so that all outputs connect to IN0. In parallel mode,
7
the desired switch state may be programmed before the
outputs are enabled. In serial mode, all outputs are
connected to GND each time they are enabled, so switch
state programming must occur after the output is enabled.
Digital Interface
The desired switch state can be loaded using a 7-bit parallel
interface mode or 32-bit serial interface mode (see Tables 1
through 3). All actions associated with the WR line occur on
its rising edge. The same is true for the LATCH line if
EDGE/LEVEL=1. Otherwise, the Slave Register updates
asynchronously (while LATCH=0, if EDGE/LEVEL=0). WR
is logically ANDed with CE and CE to allow active high or
active low chip enable.
7-Bit Parallel Mode
In the parallel programming mode (SER/PAR = 0), the 7
control bits (A2:0 and D3:0) typically specify an output
channel (A2:0) and the corresponding action to be taken
(D3:0). Command codes are available to enable or disable
all outputs, or individual outputs, as shown in Table 1. Each
output has 4-bit Master and Slave Registers associated with
it, that hold the output’s currently selected input address
(defined by D3:0). The input address - if applicable - is
loaded into the Master Register on the rising edge of WR. If
the HA457 is in level mode, and if LATCH=0 (asynchronous
switching), then the input address flows through the
transparent Slave Register, and the output immediately
switches to the new input. For synchronous switching on the
rising edge of LATCH, strap the HA457 for edge mode,
program all the desired switch connections, and then drive
an inverted pulse on the LATCH input. Note: Operations
defined by commands 1011 - 1111 occur asynchronously on
the WR rising edge, without regard for the state of LATCH or
EDGE/LEVEL.
HA457
32-Bit Serial Mode
control interface set up in the 7-bit parallel mode. The HA457
uses 7 data lines and 3 control lines (WR, CE and LATCH).
In the serial programming mode, all master registers are
loaded with data, making it unnecessary to specify an output
address (A2:0). The input data format is D3-D0, starting with
OUT0 and ending with OUT7 for 32 total bits (i.e., first bit
shifted in is D3 for OUT0, and 32nd bit shifted in is D0 for
OUT7). Only codes 0000 through 1010 are valid serial mode
commands. Code 1010 disables an individual output, while
code 1001 enables it. After data is shifted into the 32-bit
Master Register, it transfers to the Slave Register on the
rising edge of the LATCH line (Edge mode), or when
LATCH = 0 (Level mode, see Figure 10).
The input/output information is presented to the chip at A2:0
and D3:0 by a parallel printer port. The data is stored in the
master registers on the rising edge of WR. When the LATCH
line goes high, the switch configuration loads into the slave
registers, and all 8 outputs reconfigure at the same time.
Each 7-bit word updates only one output at a time. If several
outputs are to be updated, the data is individually loaded into
the master registers. Then, a single LATCH pulse can
reconfigure all channels simultaneously.
Figure 6 shows a typical application of the HA457 for driving
75Ω loads. This application shows the HA457 digital-switch
An IBM compatible PC loads the programming data into the
HA457 via its parallel port (LPT1) using a simple BASIC
program.
TABLE 1. PARALLEL INTERFACE COMMANDS
A2:0
D3:0
Selects
Output
Being
Programmed
0000 to 0111
Address
Inputs are
Irrelevant for
These
Functions
ACTION
Connect the input defined by D3:0 to the output selected by A2:0. Doesn’t enable a disabled output.
1000
Connect the output selected by A2:0 to GND. Doesn’t enable a disabled output.
1011
Asynchronously disable the single output selected by A2:0, and leave the Master Register unchanged.
1100
Asynchronously enable the single output selected by A2:0, and leave the Master Register unchanged.
1101
Asynchronously disable all outputs, and leave the Master Register unchanged.
1110
Asynchronously enable all outputs, and leave the Master Register unchanged.
1111
Send a Software pulse to the Slave Register to load it from the Master Register, iff, the LATCH input=1. If the
LATCH input=0, then this command is a NOP. The Master Register is unchanged by this command.
1001 or 1010
Do not use these codes in the parallel programming mode. These codes are for serial programming only.
TABLE 2. SERIAL INTERFACE COMMANDS
D3:0
0000 to 0111
ACTION
Connect the output to the input channel defined by D3:0. Doesn’t enable a disabled output.
1000
Connect the output to GND. Doesn’t enable a disabled output.
1001
Enable the output and connect it to GND. The default power-up state is all outputs disabled, so use this code to enable
outputs after power is applied, but before programming the switch configuration.
1010
Disable the output. The output is no longer associated with any input channel; the desired input must be redefined after
reenabling the output.
1011 to 1111
Do not use these codes in the serial programming mode.
TABLE 3. DEFINITION OF DATA AND ADDRESS BIT FUNCTIONS
SER/PAR
D3
D2
D1
D0
A2:0
H
X
X
Serial
Data
Output
Serial
Data
Input
X
L
H
Parallel Data
Input
Parallel Data
Input
Parallel Data
Input
Output
Address
Parallel Mode; D2:0 define the
command to be executed.
L
L
Parallel Data
Input
Parallel Data
Input
Parallel Data
Input
Output
Address
Parallel Mode; D2:0 define the
Input Channel
8
COMMENT
32-Bit Serial Mode
HA457
HA457 (MQFP PINOUT)
44
2
4
7
9
11
13
15
VIDEO
INPUTS
OUT0
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
CE
EDGE/LEVEL
1
2
3
4
5
6
7
8
19
30
33
36
18
WR
V+
41
40
36
34
1
43
42
D0/SER IN
AGND
D1/SER OUT DGND
D2
VD3
A0
A1
SER/PAR
A2
CE
19 LATCH
14
16
18
37 75Ω
35
33
31
29
26
24
22
21
10
75Ω
12, 23, 38
+5V
25, 27, 30
5, 8
16, 32
-5V
14
NOTES:
ALL DECOUPLING CAPACITORS 0.1µF CERAMIC (1 PER SUPPLY PIN)
FOR LOWEST CROSSTALK CONNECT UNUSED PINS TO GND
20
NC
FIGURE 6. TYPICAL CABLE DRIVING, PARALLEL MODE APPLICATION CIRCUIT
HFA1412
(AV = +1)
HA457 (MQFP PINOUT)
44
2
4
7
9
11
13
15
VIDEO
INPUTS
OUT0
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
CE
EDGE/LEVEL
19
30
33
36
1
2
3
4
5
6
7
8
18
V+
41
40
36
34
1
43
42
D0/SER IN
AGND
D1/SER OUT DGND
D2
VD3
A0
A1
SER/PAR
A2
CE
19 LATCH
14
16
18
WR
NC
37
RS
3 IN 1
35
33
31
29
26
24
22
21
10
RS
5
IN 2
10
IN 3
12
IN 4
75Ω
OUT1 1
VOUT
7
OUT2
8
OUT3
14
OUT4
75Ω
RS
12, 23, 38
25, 27, 30
5, 8
16, 32
V+
4
-IN0:3
V-
2, 6 9, 13
11
NC
-5V
+5V
-5V
14
20
NOTES:
ALL DECOUPLING CAPACITORS 0.1µF CERAMIC (1 PER SUPPLY PIN)
FOR LOWEST CROSSTALK CONNECT UNUSED PINS TO GND
USE RS TO TUNE THE OVERALL OUTPUT RESPONSE
FIGURE 7. TYPICAL HIGH PERFORMANCE (IMPROVED DG, DP) APPLICATION CIRCUIT (SEE FIGURE 21)
9
HA457
Waveforms
VALID DATA
VALID DATA
A2:0, D3:0
tDS
tDH
tCS
CE
tCH
tWL
tWH
WR
tD
tL
LATCH
(EDGE MODE)
FIGURE 8. DIGITAL TIMING REQUIREMENTS
DATA (N)
DATA (N + 1)
DATA (N + 2)
WR
LATCH
DATA (N + 1)
DATA (N)
MASTER REGISTER CONTENTS
SLAVE REGISTER CONTENTS
(EDGE/LEVEL = 0)
DATA (N + 1)
DATA (N)
SLAVE REGISTER CONTENTS
(EDGE/LEVEL = 1)
DATA (N + 2)
DATA (N + 2)
DATA (N + 1)
DATA (N)
DATA (N + 2)
FIGURE 9. PARALLEL PROGRAMMING MODE OPERATION (SER/PAR = 0)
NEW DATA FOR
OUT0
SER IN
WR
D3
D2
D1
NEW DATA FOR
OUT1 TO OUT6
D0
D3
D2
NEW DATA FOR
OUT7
D3
D2
D1
1ST
WRITE
D0
32ND
WRITE
LATCH
t=0
SLAVE REGISTER CONTENTS
(EDGE/LEVEL = 0)
OLD DATA
SLAVE REGISTER CONTENTS
(EDGE/LEVEL = 1)
OLD DATA
FIGURE 10. SERIAL PROGRAMMING MODE OPERATION (SER/PAR = 1)
10
NEW DATA
NEW DATA
HA457
VSUPPLY = ±5V, TA = 25oC, RL = 150Ω, Unless Otherwise Specified
1.75
4.0
1.50
3.0
1.25
2.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Typical Performance Curves
1.0
0.75
0.50
0.25
1.0
0
-1.0
-2.0
-3.0
0
-4.0
-0.25
TIME (20ns/DIV.)
TIME (20ns/DIV.)
GAIN (dB)
FIGURE 11. SMALL SIGNAL PULSE RESPONSE
FIGURE 12. LARGE SIGNAL PULSE RESPONSE
3
VOUT = 0.2VP-P
GAIN
0
VOUT = 1VP-P
-3
1.0
PHASE
0
45
VOUT = 2VP-P
90
135
VOUT = 1VP-P
180
PHASE (DEGREES)
VOUT = 2VP-P
GAIN (dB)
-6
0.5
0
-0.5
VOUT = 1VP-P
-1.0
-1.5
VOUT = 0.2VP-P
-2.0
VOUT = 0.2VP-P
1
10
FREQUENCY (MHz)
100
1
200
FIGURE 13. FREQUENCY RESPONSE
10
FREQUENCY (MHz)
100
200
100
200
FIGURE 14. GAIN FLATNESS
VOUT = 0.2VP-P
GAIN
0
VOUT = 1VP-P
-3
VOUT = 2VP-P
1.0
PHASE
0
45
VOUT = 0.2VP-P
90
135
VOUT = 1VP-P
RL = 400Ω
1
180
VOUT = 2VP-P
10
FREQUENCY (MHz)
0.5
0
-0.5
VOUT = 1VP-P
-1.0
-1.5
VOUT = 0.2VP-P
-2.0
RL = 400Ω
100
FIGURE 15. FREQUENCY RESPONSE
11
GAIN (dB)
-6
PHASE (DEGREES)
GAIN (dB)
3
200
1
10
FREQUENCY (MHz)
FIGURE 16. GAIN FLATNESS
HA457
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RL = 150Ω, Unless Otherwise Specified (Continued)
20
-10
VIN = 1VP-P
-20
30
-30
40
OFF ISOLATION (dB)
-40
RL = 150Ω
-50
RL = 1kΩ
-60
-70
RL = 1kΩ
50
60
70
RL = 150Ω
80
-80
90
-90
100
110
-100
1
10
100
1
200
10
FIGURE 17. ALL HOSTILE CROSSTALK
200
FIGURE 18. ALL HOSTILE OFF-ISOLATION
120
350
110
MAGNITUDE (dBΩ)
400
300
250
200
1 INPUT TO ALL OUTPUTS
100
90
1 INPUT TO 1 OUTPUT
80
70
60
150
PHASE
0
100
10
50
0
0.5
20
1.0
1.5
2.0
2.5 3.0 3.5
VOUT (VP-P)
4.0
4.5
5.0
5.5
0.03
0.1
1
10
FIGURE 20. INPUT IMPEDANCE vs FREQUENCY
RS = 0Ω
3
0
-3
VOUT = 1VP-P
-6
1
10
100
200
FREQUENCY (MHz)
FIGURE 21. FREQUENCY RESPONSE OF HA457-HFA1412 (AV = 1) COMBINATION (PER FIGURE 7)
12
30
100
FREQUENCY (MHz)
FIGURE 19. SLEW RATE vs VOUT
GAIN (dB)
SLEW RATE (V/µs)
100
FREQUENCY (MHz)
FREQUENCY (MHz)
PHASE (DEGREES)
CROSSTALK (dB)
VIN = 1VP-P
HA457
Metric Plastic Quad Flatpack Packages (MQFP)
Q44.10x10 (JEDEC MS-022AB ISSUE B)
D
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
D1
-D-
INCHES
-A-
-B-
E E1
e
PIN 1
SEATING
A PLANE
-H-
0.076
0.003
-C-
12o-16o
0.40
0.016 MIN
0.20
M C A-B S
0.008
0o MIN
A2 A1
0o-7o
L
13
MIN
MAX
MIN
MAX
NOTES
A
-
0.096
-
2.45
-
A1
0.004
0.010
0.10
0.25
-
A2
0.077
0.083
1.95
2.10
-
b
0.012
0.018
0.30
0.45
6
b1
0.012
0.016
0.30
0.40
-
D
0.515
0.524
13.08
13.32
3
D1
0.389
0.399
9.88
10.12
4, 5
E
0.516
0.523
13.10
13.30
3
E1
0.390
0.398
9.90
10.10
4, 5
L
0.029
0.040
0.73
1.03
N
44
44
e
0.032 BSC
0.80 BSC
7
Rev. 2 4/99
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
b
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
b1
BASE METAL
WITH PLATING
SYMBOL
D S
0.13/0.17
0.005/0.007
12o-16o
MILLIMETERS
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
7. “N” is the number of terminal positions.
0.13/0.23
0.005/0.009
HA457
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER
N44.65 (JEDEC MS-018AC ISSUE A)
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
0.025 (0.64)
R
0.045 (1.14)
0.050 (1.27) TP
C
L
D2/E2
C
L
E1 E
D2/E2
VIEW “A”
A1
A
D1
D
0.020 (0.51) MAX
3 PLCS
0.020 (0.51)
MIN
44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.165
0.180
4.20
4.57
-
A1
0.090
0.120
2.29
3.04
-
D
0.685
0.695
17.40
17.65
-
D1
0.650
0.656
16.51
16.66
3
D2
0.291
0.319
7.40
8.10
4, 5
E
0.685
0.695
17.40
17.65
-
E1
0.650
0.656
16.51
16.66
3
E2
0.291
0.319
7.40
8.10
4, 5
N
44
44
6
Rev. 2 11/97
SEATING
-C- PLANE
0.026 (0.66)
0.032 (0.81)
0.045 (1.14)
MIN
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
14
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
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