DATASHEET

ISL59452
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TERSIL
1-888-IN
®
September 24, 2007
Triple 4:1 Single Supply Video
Multiplexing Amplifier
Features
• 250MHz Small Signal Bandwidth (GAIN 1)
The ISL59452 is a 4-input, single-supply, triple video
multiplexer suited for component video applications. The
device features single +5V supply operation, high bandwidth
and TTL/CMOS logic compatible gain select (AV2) of x1 or
x2. When HIZ is pulled high, the outputs are put into highimpedance states and the video inputs are disconnected
putting the device in a low power state. This is an essential
feature for power sensitive applications. The ISL59452 also
features fast channel switching at pixel rates to allow for
video overlays.
The ISL59452 will drive 150Ω loads making it suitable for
75Ω cable driving applications. The ISL59452 is ideal for
RGB, YPbPr, as well as S-Video and composite
applications.
The ISL59452 comes in a 32 Ld QFN package and is
specified for operation over -40°C to +85°C temperature
range.
Ordering Information
• +5V Single Supply Operation
• TTL/CMOS Compatible Gain Select of x1 or x2
• High Impedance Output Setting
• Ideal for RGB/YPbPr/S-Video/Composite Video Signals
• 150Ω Output Load Capability for Video Cable Driving
• 0.0013% Differential Gain and 0.035° Differential Phase
Accuracy
• Pb-Free (RoHS Compliant)
Applications
• SDTVs and HDTVs
• Set-Top Boxes
• Video Overlay
• Security Video
L32.5x5
ISL59452IRZ-T7*
ISL594 52IRZ 32 Ld 5x5 QFN
L32.5x5
Pinout
ISL59452
(32 LD QFN)
TOP VIEW
30 B0
31 G0
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
32 GND
*Please refer to TB347 for details on reel specifications.
25 AV2
ISL594 52IRZ 32 Ld 5x5 QFN
26 HIZ
ISL59452IRZ
• Broadcast Video Equipment
27 GND
PKG.
DWG. #
28 V+
PACKAGE
(Pb-Free)
29 R0
PART
MARKING
• Capable of Pixel Rate Channel Switching
2/1
R1 1
24 ROUT
23 GND
B1 2
G1 3
22 GND
2/1
21 BOUT
GND 4
20 V+
V+ 5
2/1
19 V+
GND 6
R2 7
18 GOUT
17 GND
GND 16
S0 15
G3 13
R3 11
GND 10
G2 9
B2 8
S1 14
Gray =
Thermal
Pad
B3 12
PART NUMBER
(Note)
FN6254.0
EXPOSED THERMAL PAD MUST BE CONNECTED TO GND.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL59452
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Input Voltage to GND . . . . . . . . . . . . . . . . . GND - 0.5V to V+ + 0.5V
Voltage between HIZ, AV2 and GND . . . . . . . . . GND -0.5;V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Digital and Analog Input Current (Note 1) . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
2. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested.
Electrical Specifications
PARAMETER
V+ = +5V, GND = 0V, TA = +25°C, RL = 150Ω to GND, AV2 = HIZ = 0.8V,
unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
(Note 2)
TYP
MAX
(Note 2)
UNIT
4.5
5.0
5.5
V
DC CHARACTERISTICS
V+
Supply Voltage
+IS Enabled
Enabled Supply Current
No load, VIN = 0V, HIZ = 0.8V
45
75
mA
+IS Disabled
Disabled Supply Current
No load, VIN = 0V, HIZ = 2.0V
3
5
mA
Output Offset Voltage
AV2 = 0.8V, GAIN = 1, VIN = 0.1V
-35
0
35
mV
AV2 = 2.0V, GAIN = 2, VIN = 0.1V
-35
0
35
mV
VOS
IB
ROUT-DIS
AV
PSRRDC
Input Bias Current
VIN = 2.2V, No Load
-6
-4
-2
µA
Disabled Output Resistance (DC)
HIZ = 2.0V
1.5
2
2.5
kΩ
Voltage Gain
AV2 = 0.8V, GAIN = 1
.98
1
1.02
V/V
AV2 = 2.0V, GAIN = 2
1.95
1.99
2.05
V/V
V+ = 4.5V to 5.5V
50
55
3.5
Power Supply Rejection Ratio
dB
OUTPUT AMPLIFIERS
VOUT+
Output High Swing
RL = 150Ω, VIN = 4V, AV2 = 2.0V, GAIN = 2
VOUT-
Output Low Swing
RL = 150Ω,VIN = 0V, AV2 = 2.0V, GAIN = 2
Short Circuit Current
Sourcing, VIN = 3V, AV2 = 2.0V, RL = 10Ω to
GND, GAIN = 2
125
mA
Sinking, VIN = 0V, RL = 10Ω to +3V
57
mA
ISC
V
30
mV
LOGIC (AV2, HIZ, S1, S0)
VIH
Input High Voltage (HIGH)
VIL
Input Low Voltage (LOW)
IIH
Input High Current (Logic Inputs)
IIL
Input Low Current (Logic Inputs)
2
S1 = S0 = 5V (no pull-up or pull-down)
V
0.8
V
µA
-2
0
2
AV2 = HIZ= 5V (300kΩ internal pull-downs)
8
17
34
µA
S1 = S0 = 0V (no pull-up or pull-down)
-2
0
2
µA
AV2 = HIZ = 5V (300kΩ internal pull-downs)
-2
0
2
µA
AC GENERAL
PSRR
Power Supply Rejection Ratio
VIN = 0V, f = 10kHz to 10MHz, V+ = 5VDC
+100mVP-P sine wave
55
dB
XTALK
Channel to Channel Crosstalk
(ROUT/BOUT to Green Input)
f = 10MHz, VIN = 0.7VP-P; (GAIN = 1)
75
dB
f = 10MHz, VIN = 0.7VP-P; (GAIN = 2)
70
dB
2
FN6254.0
ISL59452
Electrical Specifications
PARAMETER
Off - ISO
V+ = +5V, GND = 0V, TA = +25°C, RL = 150Ω to GND, AV2 = HIZ = 0.8V,
unless otherwise specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
(Note 2)
TYP
MAX
(Note 2)
UNIT
Off-State Isolation (any de-selected output f = 10MHz, Ch-Ch Off Isolation
to driven input)
VIN = 0.7VP-P; (GAIN = 1)
90
dB
f = 10MHz, Ch-Ch Off Isolation
VIN = 0.7VP-P; (GAIN = 2)
90
dB
%
Differential Gain Error
RL = 150
0.0013
dP
Differential Phase Error
RL = 150
0.035
°
BW
Small Signal -3dB Bandwidth
VOUT = 0.1VP-P; RL = 150Ω, CL = 0.6pF
(GAIN = 1)
250
MHz
VOUT = 0.2VP-P; RL = 150Ω, CL = 0.6pF
(GAIN = 2)
210
MHz
VOUT = 0.7VP-P; RL = 150Ω, CL = 0.6pF
(GAIN = 1)
240
MHz
VOUT = 1.4VP-P; RL = 150Ω, CL = 0.6pF
(GAIN = 2)
200
MHz
VOUT = 1.4VP-P; RL = 150Ω, CL = 0.6pF
(GAIN = 1)
40
MHz
VOUT = 1.4VP-P; RL = 150Ω, CL = 0.6pF
(GAIN = 2)
33
MHz
VIN = 0.5V to 2.5V, time = 20% to 80%,
RL = 150Ω, AV2 = 0.8V, CL = 2.1pF, GAIN = 1
480
V/µs
VIN = 0.5V to 1.5V, time = 20% to 80%,
RL = 150Ω, AV2 = 2.0V, CL = 2.1pF, GAIN = 2
980
V/µs
VIN = 2.5V to 0.5V, time = 80% to 20%,
RL = 150Ω, AV2 = 0.8V, CL = 2.1pF, GAIN = 1
300
V/µs
VIN = 1.5V to 0.5V, time = 80% to 20%,
RL = 150Ω, AV2 = 2.0V, CL = 2.1pF, GAIN = 2
568
V/µs
VOUT = 1VP-P; RL = 150Ω, CL = 2.1pF,
AV2 = 0.8V, GAIN = 1
1.72
ns
VOUT = 1VP-P; RL = 150Ω, CL = 2.1pF,
AV2 = 2.0V, GAIN = 2
1
ns
VOUT = 2VP-P; RL = 150Ω, CL = 2.1pF,
AV2 = 2.0V, GAIN = 2
1.88
ns
VOUT = 1VP-P; RL = 150Ω, CL = 2.1pF,
AV2 = 0.8V, GAIN = 1
2.7
ns
VOUT = 1VP-P; RL = 150Ω, CL = 2.1pF,
AV2 = 2.0V, GAIN = 2
2.2
VOUT = 2VP-P; RL = 150Ω, CL = 2.1pF,
AV2 = 2.0V, GAIN = 2
2.7
ns
VOUT = 1VP-P; RL = 150Ω, CL = 2.1pF,
GAIN = 1, time from 90% crossing to 1% of final
value
3
ns
VOUT = 1VP-P; RL = 150Ω, CL = 2.1pF,
GAIN = 2, time from 90% crossing to 1% of final
value
5
ns
VIN = 1V, RL = 150Ω; CL = 2.1pF, AV2 = 0.8V
400
mVP-P
VIN = 1V, RL = 150Ω; CL = 2.1pF, AV2 = 2.0V
300
mVP-P
dG
Large Signal -3dB Bandwidth
BW_0.1
SR+
SR-
0.1dB Bandwidth
Positive Slew Rate
Negative Slew Rate
TRANSIENT RESPONSE
tR
tF
tS 1%
Rise Time
10% to 90%
Fall Time
90% to 10%
Settling Time to 1%
SWITCHING CHARACTERISTICS
VGLITCH
HIZ High to Low Switching Glitch
3
FN6254.0
ISL59452
Electrical Specifications
PARAMETER
V+ = +5V, GND = 0V, TA = +25°C, RL = 150Ω to GND, AV2 = HIZ = 0.8V,
unless otherwise specified. (Continued)
DESCRIPTION
MIN
(Note 2)
CONDITIONS
TYP
MAX
(Note 2)
UNIT
tSW-L-H
Channel Switching Delay Time Low to
High
1.2V logic threshold to 10% movement of
analog output
3
ns
tSW-H-L
Channel Switching Delay Time High to
Low
1.2V logic threshold to 10% movement of
analog output
5
ns
tHIZ-L-H
HIZ Switching Delay Time Low to High
1.2V logic threshold to 10% movement of
analog output
30
ns
tHIZ-H-L
HIZ Switching Delay Time High to Low
1.2V logic threshold to 10% movement of
analog output
220
ns
Propagation Delay
10% input to 10% output, VIN = 100mVP-P
5
ns
10% input to 10% output, VIN = 700mVP-P
2
ns
tpd
Settling Time Diagram
±1%
VALUE BAND
±1%OF
OFFINAL
FINAL
VALUE BAND
FINAL
FINALVALUE
VALUE
90% FINAL
OF FINAL
VALUE
90%
VALUE
10% OF
FINALVALUE
VALUE
10%
FINAL
tR
4
ts
1%
tS 1%
FN6254.0
ISL59452
Typical Application Diagram
+5V
1nF
10nF
1µF
µC
S1
RED/Pr
S0
AV2
V+
R0
75Ω
GREEN/Y
3
G0
75Ω
BLUE/Pb
B0
75Ω
RED/Pr
R1
75Ω
GREEN/Y
RED/Pr
75Ω
X1/
X2
ROUT
VIDEO OUT
3
G1
75Ω
00
BLUE/Pb
B1
01
75Ω
10
RED/Pr
R2
G2
GOUT
GREEN/Y
VIDEO OUT
11
75Ω
GREEN/Y
75Ω
X1/
X2
3
75Ω
S1, S0
75Ω
X1/
X2
BLUE/Pb
B2
BOUT
BLUE/Pb
VIDEO OUT
75Ω
RED/Pr
R3
75Ω
GREEN/Y
G3
75Ω
3
ISL59452
BLUE/Pb
B3
75Ω
HIZ
5
GND
FN6254.0
ISL59452
Typical Performance Curves
V+ = +5V, RL = 150Ω to GND, CL = 0.6pF, TA = +25°C, unless otherwise specified.
CL = 12.6pF
VIN = 100mVP-P
CL = 7.4pF
0
CL = 8.8pF
-5
CL = 0.6pF
-10
CL = 5.3pF
CL = 3.3pF
-15
-20
-25
100k
1M
10M
100M
1G
5
NORMALIZED MAGNITUDE (dB)
NORMALIZED MAGNITUDE (dB)
5
CL = 7.4pF
-5
CL = 8.8pF
-10
-15
CL = 2.1pF
-20
CL = 5.3pF
-25
100k
10G
1M
10M
100M
1G
10G
FREQUENCY (Hz)
FIGURE 2. LARGE SIGNAL GAIN vs FREQUENCY vs CL
INTO 150Ω LOAD, GAIN = 1
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL
INTO 150Ω LOAD, GAIN = 1
VIN = 100mVP-P
CL = 12.6pF
0
CL = 8.8pF
-5
CL = 7.4pF
-10
CL = 5.3pF
CL = 2.1pF
CL = 3.3pF
CL = 0.6pF
-15
-20
-25
100k
1M
10M
100M
1G
10G
NORMALIZED MAGNITUDE (dB)
5
5
NORMALIZED MAGNITUDE (dB)
CL = 3.3pF
CL = 0.6pF
FREQUENCY (Hz)
VIN = 700mVP-P
0
CL = 7.4pF
-5
CL = 8.8pF
CL =0.6pF
-10
-20
CL = 5.3pF
-25
100k
1M
10M
100M
CL = 12.6pF
0
CL = 7.4pF
-1
-2
-3
CL = 0.6pF
CL = 3.3pF
1M
10M
100M
FREQUENCY (Hz)
FIGURE 5. SMALL SIGNAL GAIN FLATNESS, GAIN = 1
6
1G
NORMALIZED MAGNITUDE (dB)
1
-5
100k
10G
FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs CL
INTO 150Ω LOAD, GAIN = 2
1
-4
1G
FREQUENCY (Hz)
FIGURE 3. SMALL SIGNAL GAIN vs FREQUENCY vs CL
INTO 150Ω LOAD, GAIN = 2
VIN = 100mVP-P
CL = 2.1pF
CL = 12.6pF
-15
FREQUENCY (Hz)
NORMALIZED MAGNITUDE (dB)
CL = 12.6pF
VIN = 700mVP-P
0
CL = 12.6pF
VIN = 700mVP-P
0
CL = 7.4pF
-1
-2
-3
CL = 0.6pF
-4
CL = 3.3pF
-5
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 6. LARGE SIGNAL GAIN FLATNESS, GAIN = 1
FN6254.0
ISL59452
V+ = +5V, RL = 150Ω to GND, CL = 0.6pF, TA = +25°C, unless otherwise specified. (Continued)
1
VIN = 100mVP-P
0
-1
CL = 7.4pF
-2
-3
CL = 0.6pF
-4
CL = 3.3pF
-5
100k
1M
10M
100M
NORMALIZED MAGNITUDE (dB)
NORMALIZED MAGNITUDE (dB)
Typical Performance Curves
1G
1
VIN = 700mVP-P
0
CL = 7.4pF
-1
-2
-3
CL = 0.6pF
-4
CL = 3.3pF
-5
100k
1M
10M
FIGURE 7. SMALL SIGNAL GAIN FLATNESS, GAIN = 2
1G
FIGURE 8. LARGE SIGNAL GAIN FLATNESS, GAIN = 2
30.6
2.85
NO INPUT
NO LOAD
30.4
HIZ = HIGH
2.80
DISABLED CURRENT (mA)
SUPPLY CURRENT (mA)
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
30.2
30.0
29.8
29.6
2.75
2.70
2.65
2.60
2.55
2.50
2.45
2.40
2.35
29.4
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
2.30
4.5
5.5
4.6
4.7
4.8
FIGURE 9. SUPPLY CURRENT vs SUPPLY VOLTAGE
5.0
5.1
5.2
1.9
14.0
GAIN = 2
IMPEDANCE (kΩ)
13.0
12.5
12.0
GAIN = 1
1.1
0.9
0.7
0.5
0.3
1M
FREQUENCY (Hz)
10M
FIGURE 11. ZOUT vs FREQUENCY - ENABLED
7
HIZ = HIGH
1.3
10.5
100k
5.5
1.5
11.0
10.0
10k
5.4
1.7
13.5
11.5
5.3
FIGURE 10. DISABLED SUPPLY CURRENT vs SUPPLY
VOLTAGE
14.5
IMPEDANCE (Ω)
4.9
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
100M
0.1
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 12. ZOUT vs FREQUENCY - DISABLED
FN6254.0
ISL59452
Typical Performance Curves
V+ = +5V, RL = 150Ω to GND, CL = 0.6pF, TA = +25°C, unless otherwise specified. (Continued)
0
1000
VAC = 100mVP-P
100
PSRR (dB)
IMPEDANCE (kΩ)
-10
10
-20
-30
-40
1
-50
0.1
10k
100k
1M
10M
-60
100k
100M
1M
FREQUENCY (Hz)
FIGURE 13. ZIN vs FREQUENCY
0
1 INPUT DRIVEN TO 100mVP-P TO
-10 ANY DE-SELECTED OUTPUT
-20
TO
GREEN TO BLUE
GAIN = 2
-20
CROSSTALK (dB)
CROSSTALK (dB)
-10
GREEN TO BLUE
GAIN = 1
-30
-40
GREEN TO RED
GAIN = 2
-50
-60
GREEN TO RED
GAIN = 1
-70
-30
-40
-50
-60
-70
-80
-80
-90
-90
100k
1M
10M
100M
1G
-100
100k
10G
1M
1G
10G
900
0
HIZ = HIGH
1 INPUT DRIVEN TO 100mVP-P
TO ANY OUTPUT
800
700
-30
600
-40
nV/√Hz
CROSSTALK (dB)
100M
FIGURE 16. OFF ISOLATION
FIGURE 15. CROSSTALK
-20
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
-10
100M
FIGURE 14. PSRR vs FREQUENCY
0
GREEN INPUT DRIVEN
100mVP-P TO ROUT/GOUT
10M
FREQUENCY (Hz)
-50
-60
500
400
300
-70
-80
200
-90
100
-100
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 17. DISABLED ISOLATION
8
10G
0
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 18. OUTPUT REFERRED NOISE vs FREQUENCY
FN6254.0
ISL59452
Typical Performance Curves
V+ = +5V, RL = 150Ω to GND, CL = 0.6pF, TA = +25°C, unless otherwise specified. (Continued)
0.02
0.0015
GAIN = 2
0.0010
0.0005
GAIN = 1
0.0000
-0.0005
-0.0010
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.01
0.00
-0.01
GAIN = 2
-0.02
-0.03
-0.04
-0.05
0.3
0.4
FIGURE 19. DIFFERENTIAL GAIN; fO = 3.58MHz, RL = 150Ω
INPUT = CH1
OUTPUT = CH2
CH1 = 50mV/DIV
CH2 = 50mV/DIV
TIMEBASE = 10ns/DIV
OUTPUT
0.5
0.6
0.7
0.8
0.9
1.0
DC INPUT VOLTAGE (V)
DC INPUT VOLTAGE (V)
INPUT
VIN = 100mVP-P
f = 3.58MHz
GAIN = 1
VIN = 100mVP-P
f = 3.58MHz
DIFFERENTIAL PHASE (°)
DIFFERENTIAL GAIN (%)
0.0020
FIGURE 20. DIFFERENTIAL PHASE; fO = 3.58MHz, RL = 150Ω
INPUT
INPUT = CH1
OUTPUT = CH2
CH1 = 50mV/DIV
CH2 = 100mV/DIV
TIMEBASE = 10ns/DIV
OUTPUT
FIGURE 21. SMALL SIGNAL TRANSIENT RESPONSE;
GAIN = 1
INPUT = CH1
OUTPUT = CH2
CH1 = 500mV/DIV
CH2 = 500mV/DIV
TIMEBASE = 10ns/DIV
INPUT
OUTPUT
FIGURE 22. SMALL SIGNAL TRANSIENT RESPONSE;
GAIN = 2
INPUT
INPUT = CH1
OUTPUT = CH2
CH1 = 500mV/DIV
CH2 = 1.0V/DIV
TIMEBASE = 10ns/DIV
OUTPUT
FIGURE 23. LARGE SIGNAL TRANSIENT RESPONSE;
GAIN = 1
9
FIGURE 24. LARGE SIGNAL TRANSIENT RESPONSE;
GAIN = 2
FN6254.0
ISL59452
Typical Performance Curves
V+ = +5V, RL = 150Ω to GND, CL = 0.6pF, TA = +25°C, unless otherwise specified. (Continued)
HIZ
HIZ
HIZ = CH1
OUTPUT = CH2
CH1 = 1V/DIV
CH2 = 100mV/DIV
TIMEBASE = 100ns/DIV
HIZ = CH1
OUTPUT = CH2
CH1 = 1V/DIV
CH2 = 100mV/DIV
TIMEBASE = 100ns/DIV
OUTPUT
FIGURE 25. HIZ SWITCHING GLITCH, VIN = 0, GAIN = 1
OUTPUT
FIGURE 26. HIZ SWITCHING GLITCH, VIN = 0, GAIN = 2
HIZ
HIZ
tHIZ-L-H
HIZ = CH1
OUTPUT = CH2
CH1 = 1V/DIV
CH2 = 500mV/DIV
TIMEBASE = 100ns/DIV
tHIZ-H-L
S1, S0 = CH1
OUTPUT = CH2
CH1 =1V/DIV
CH2 = 500mV/DIV
TIMEBASE = 100ns/DIV
OUTPUT
OUTPUT
FIGURE 28. HIZ TIMING, GAIN = 2
FIGURE 27. HIZ TIMING, GAIN = 1
tSW-L-H
S1, S0 = CH1
OUTPUT = CH2
CH1 =1V/DIV
CH2 = 500mV/DIV
TIMEBASE = 5ns/DIV
tSW-H-L
FIGURE 29. CHANNEL TO CHANNEL SWITCHING TIME
10
FN6254.0
ISL59452
Typical Performance Curves
V+ = +5V, RL = 150Ω to GND, CL = 0.6pF, TA = +25°C, unless otherwise specified. (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
3.0
1.0
2.5
POWER DISSIPATION (W)
POWER DISSIPATION (W)
2.857W
0.8
758mW
0.6
QFN32
θJA = 125°C/W
0.4
0.2
QFN32
θJA = 35°C/W
2.0
1.5
1.0
0.5
0
0
0
25
50
75 85 100
125
0
150
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Functional Block Diagram (Each Output
Channel)
TABLE 1. CHANNEL SELECT LOGIC TABLE
S1
S0
HIZ
S0
0
0
0
R0, G0, B0
S1
0
1
0
R1, G1, B1
1
0
0
R2, G2, B2
1
1
0
R3, G3, B3
X
X
1
High Impedance,
Inputs Disconnected
AV2
V+
R0/G0/B0
R1/G1B/1
x2/1
R2/G2/B2
R3/G3/B3
150
ROUT
GOUT
BOUT
OUTPUT
GND
11
FN6254.0
ISL59452
Pin Descriptions
ISL59452
(32 LD QFN)
PIN NAME
EQUIVALENT
CIRCUIT
1
R1
Circuit 1
Channel 1 Red/Pr/Chroma Input
2
B1
Circuit 1
Channel 1 Blue/Pb/Chroma Input
3
G1
Circuit 1
Channel 1 Green/Luma Input
4, 6, 10, 16, 17, 22,
23, 27, 32
GND
Circuit 4
Ground
5, 19, 20, 28
V+
Circuit 4
Positive Supply. Bypass to GND with 0.01µF and 1nF capacitors.
7
R2
Circuit 1
Channel 2 Red/Pr/Chroma Input
8
B2
Circuit 1
Channel 2 Blue/Pb/Chroma Input
DESCRIPTION
9
G2
Circuit 1
Channel 2 Green/Luma Input
11
R3
Circuit 1
Channel 3 Red/Pr/Chroma Input
12
B3
Circuit 1
Channel 3 Blue/Pb/Chroma Input
13
G3
Circuit 1
Channel 3 Green/Luma Input
14
S1
Circuit 2
Channel selection pin MSB (binary logic code). This pin does not have internal pull-up or
pull-down resistors
15
S0
Circuit 2
Channel selection pin LSB (binary logic code). This pin does not have internal pull-up or
pull-down resistors
18
GOUT
Circuit 3
Green/Luma Output
21
BOUT
Circuit 3
Blue/Pb/Chroma Output
24
ROUT
Circuit 3
Red/Pr/Chroma Output
25
AV2
Circuit 2
Gain Set. Set to logic high for gain of x2 (+6dB), or set to logic low for a gain of x1 (0dB). If
left floating, an internal pull-down resitor pulls this pin low (300k pull-down).
26
HIZ
Circuit 2
Output disable (active high). Internal pull-down resistor ensures the device will be active with
no connection to this pin. A logic high, puts the outputs in a high impedance state. Use this
state to control logic when more than one MUX-amp share the same video output line.
During high impedance state, there is a 2kΩ pull-down present at each output. If left floating,
an internal pull-down resistor pulls this pin low (300k pull-down).
29
R0
Circuit 1
Channel 0 Red/Pr/Chroma Input
30
B0
Circuit 1
Channel 0 Blue/Pb/Chroma Input
31
G0
Circuit 1
Channel 0 Green/Luma Input
PAD
EP
Exposed Pad. Connect to GND
V+
*
V+
V+
LOGIC PIN
OUT
*
IN
GND
GND
CIRCUIT 1
GND
CIRCUIT 2
*NOT ALWAYS PRESENT.
REFER TO PIN DESCRIPTION
CIRCUIT 3
THERMAL HEAT SINK PAD
V+
CAPACITIVELY
COUPLED
ESD CLAMP
~1MΩ
GND
SUBSTRATE
GND
CIRCUIT 4
12
FN6254.0
ISL59452
AC Design Considerations
ISL59452
VIN
VOUT
x2
*CL
2.1pF
50Ω
or
75Ω
RL
150Ω
*CL Includes PCB trace capacitance
FIGURE 32A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
ISL59452
VIN
LCRIT
x2
50Ω
or
75Ω
RS
CL
CS
RL
FIGURE 32B. INTER-STAGE APPLICATION CIRCUIT
ISL59452
VIN
LCRIT
TEST
EQUIPMENT
RS
x2
118Ω
50Ω,or
75Ω
*CL
2.1pF
86.6Ω
50Ω
High speed current-feed amplifiers are sensitive to
capacitance at the inverting input and output terminals.
Capacitance at the output terminal increases gain peaking
and overshoot. The AC response of the ISL59452 is
optimized for a total output capacitance of 2.1pF with a load
of 150Ω (Figure 32A). When PCB trace capacitance and
component capacitance exceed 2pF, overshoot becomes
strongly dependent on the input pulse amplitude and slew
rate. Increasing levels of output capacitance reduce stability,
resulting in increased overshoot and settling time.
PC board trace length (LCRIT) should be kept to a minimum
in order to minimize output capacitance. At 500MHz, trace
lengths approaching 1” begin exhibiting transmission line
behavior and may cause excessive ringing if controlled
impedance traces are not used. Figure 32B shows the
optimum inter-stage circuit when the total output trace length
is less than the critical length of the highest signal frequency.
As a general rule of thumb the trace lengths should be less
than one-tenth of the wavelength of the highest frequency
component in the signal. Equation 1 shows an approximate
way to calculate LCRIT in meters.
c
L CRIT ≤ -------------------------------------------10 × f MAX × ε R
*CL Includes PCB trace capacitance
(EQ. 1)
FIGURE 32C. 150Ω TEST CIRCUIT WITH 50Ω LOAD
c = speed of light (3 x 10^8 m/s)
ISL59452
VIN
LCRIT
x2
TEST
EQUIPMENT
RS
50Ω or 75Ω
*CL
2.1pF
50Ω
or
75Ω
50Ω/75Ω
*CL Includes PCB trace capacitance
FIGURE 32D. BACKLOADED TEST CIRCUIT FOR 150Ω VIDEO
CABLE APPLICATION
FIGURE 32. AC TEST CIRCUITS
AC Test Circuits
Figure 32A and 32B illustrate the optimum output load for
testing AC performance at 150Ω loads. Figure 32C
illustrates how to use the optimal 150Ω load for a 50Ω cable.
Figure 32D illustrates the optimum output load for 50Ω and
75Ω cable-driving.
Application Information
General
The ISL59452 triple 4:1 video MUX features +5V single-supply
operation, high bandwidth and TTL/CMOS logic compatible
gain select (AV2) of x1 (0dB) or x2 (+6dB). The ISL59452 also
features buffered high impedance analog inputs and excellent
AC performance at output loads down to 150Ω for video cabledriving. The current feedback output amplifiers are stable
operating into capacitive loads.
13
fMAX = maximum frequency component
εR = relative dielectric of board material (e.g. FR4 = 4.2)
For applications where inter-stage distances are long but
pulse response is not critical, capacitor CS can be added to
low values of RS to form a low-pass filter to dampen pulse
overshoot. This approach avoids the need for the large gain
correction required by the -6dB attenuation of the
back-loaded controlled impedance interconnect. Load
resistor RL is still required but can be 500Ω or greater,
resulting in a much smaller attenuation factor.
For applications where pulse response is critical and where
inter-stage distances exceed LCRIT, the circuit shown in
Figure 32C is recommended. Resistor RS constrains the
capacitance seen by the amplifier output to the trace
capacitance betweeen the output pin and the resistor.
Therefore, RS should be placed as close to the ISL59452
output pin as possible. For inter-stage distances much greater
than LCRIT, the back-loaded circuit shown in Figure 32D
should be used with controlled impedance PCB lines, with RS
and RL equal to the controlled impedance.
Control Signals
S0, S1, AV2, and HIZ are binary coded, TTL/CMOS
compatible control inputs. The S0, S1 pins select the inputs.
All three output amplifiers are switched simultaneously from
their respective inputs. When HIZ is pulled high, it puts the
outputs in a high-impedance state. For control signal rise and
FN6254.0
ISL59452
fall times less than 10ns, the use of termination resistors on
the control lines close to the part may be necessary to prevent
reflections and to minimize transients coupled to the output.
See Table 1 for the S1, S0 selection states.
HIZ State
An internal pull-down resistor ensures the device will be
active with no connection to the HIZ pin. The HIZ state is
established within approximately 30ns (Figure 26) by placing
a logic high (>2V) on the HIZ pin. If the HIZ state is selected,
the output impedance is ~2000Ω (Figure 12). The supply
current during this state is reduced to ~3mA.
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than
50mA. Adequate thermal heat sinking of the parts is also
required.
PC Board Layout
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
capacitor and the device because vias adds unwanted
inductance. Larger caps can be farther away. When vias
are required in a layout, they should be routed as far away
from the device as possible.
The QFN Package Requires Additional PCB Layout
Rules for the Thermal Pad
The thermal pad is electrically connected to GND through
the high resistance IC substrate. Its primary function is to
provide heat sinking for the IC.
Maximum AC performance is achieved if the thermal pad is
attached to a dedicated decoupled layer in a multi-layered
PC board. In cases where a dedicated layer is not possible,
AC performance may be reduced at upper frequencies.
• The thermal pad requirements are proportional to power
dissipation and ambient temperature. A dedicated layer
(oftern the ground plane) eliminates the need for individual
thermal pad area. When a dedicated layer is not possible,
a 1”x1” pad area is sufficient for an ISL59452 dissipating
0.5W at +50°C ambient. Pad area requirements should be
evaluated according to the maximum ambient
temperature, the maximum supply current (including worst
case signals + loads), and the thermal characteristic of the
PCB.
• Use low inductance components, such as chip resistors
and chip capacitors whenever possible.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners; use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces longer than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. To maintain frequency performance
with longer traces, use striplines.
• Match channel-to-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• All signal I/O lines should be routed over continuous
ground planes (i.e. no split planes or PCB gaps under
these lines).
• Put the proper termination resistors in their optimum
location as close to the device as possible.
• When testing, use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
• Decouple well, using aminimum of 2 power supply
decoupling capacitors (1000pF, 0.01µF), placed as close
to the devices as possible. Avoid vias between the
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6254.0
ISL59452
Package Outline Drawing
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 02/07
4X 3.5
5.00
28X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
32
25
1
5.00
24
3 .10 ± 0 . 15
17
(4X)
8
0.15
9
16
TOP VIEW
0.10 M C A B
+ 0.07
32X 0.40 ± 0.10
4 32X 0.23 - 0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08 C
( 4. 80 TYP )
(
( 28X 0 . 5 )
SIDE VIEW
3. 10 )
(32X 0 . 23 )
C
0 . 2 REF
5
( 32X 0 . 60)
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
15
FN6254.0
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