DATASHEET

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UTSingle Digitally Controlled Potentiometer
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ISL2
SI B L
September 9, 2009
POS Data Sheet
ISL22319
(XDCP™)
FN6310.1
Low Noise, Low Power, I2C™ Bus,
128 Taps, Wiper Only
Features
The ISL22319 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
• I2C serial interface
- Two address pins, up to four devices/bus
• 128 resistor taps
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the content of the
DCP’s IVR to the WR.
The DCP can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.
• Non-volatile storage of wiper position
• Wiper resistance: 70Ω typical @ 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ or 10kΩ total resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T ≤ +55 °C
• 8 Ld MSOP
• Pb-free (RoHS compliant)
Pinout
ISL22319
(8 LD MSOP)
TOP VIEW
SCL
1
8
SDA
2
7
VCC
RW
A1
3
6
SHDN
A0
4
5
GND
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
RESISTANCE OPTION
(kΩ)
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL22319UFU8Z*
319UZ
50
-40 to +125
8 Ld MSOP
M8.118
ISL22319WFU8Z*
319WZ
10
-40 to +125
8 Ld MSOP
M8.118
*Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL22319
Block Diagram
VCC
SCL
SDA
I2C
A0
INTERFACE
A1
POWER-UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
WR
RW
NON-VOLATILE
REGISTERS
SHDN
GND
Pin Descriptions
MSOP PIN
SYMBOL
DESCRIPTION
1
SCL
Open drain I2C interface clock input
2
SDA
Open drain serial data I/O for the I2C interface
3
A1
Device address input for the I2C interface
4
A0
Device address input for the I2C interface
5
GND
6
SHDN
7
RW
“Wiper” terminal of DCP
8
VCC
Power supply pin
2
Device ground pin
Shutdown active low input
FN6310.1
September 9, 2009
ISL22319
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Voltage at any DCP Pin with
Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Latchup (Note 2) . . . . . . . . . . . . . . . . . . Class II, Level B @+125°C
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
8 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
165
Maximum Junction Temperature (Plastic Package). . . .. . . . .+150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature (Extended Industrial) . . . . . .-40°C to +125°C
VCC Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
ΝΟΤΕΣ:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -1V for all pins.
Analog Specifications
SYMBOL
RTOTAL
Over recommended operating conditions unless otherwise stated.
MIN
TYP
MAX
(Note 14) (Note 3) (Note 14)
UNIT
W option
10
kΩ
U option
50
kΩ
PARAMETER
End-to-End Resistance
TEST CONDITIONS
End-to-End Resistance Tolerance
-20
+20
%
End-to-End Temperature Coefficient W option
±50
ppm/°C
(Note 12)
U option
±80
ppm/°C
(Note 12)
VCC = 3.3V @ +25°C,
wiper current = VCC/RTOTAL
70
Ω
25
pF
RW
(Note 12)
Wiper Resistance
CW
(Note 12)
Wiper Capacitance
ILkgRW
Leakage on RW Pin
Voltage at pin from GND to VCC
2
4
µA
-1
1
LSB
(Note 4)
-0.5
0.5
LSB
(Note 4)
LSB
(Note 4)
VOLTAGE DIVIDER MODE (measured at RW, unloaded)
INL
(Note 8)
Integral Non-linearity
DNL
(Note 7)
Differential Non-linearity
Monotonic over all tap positions
ZSerror
(Note 5)
Zero-scale Error
W option
0
1
5
U option
0
0.5
2
FSerror
(Note 6)
Full-scale Error
W option
-5
-1
0
U option
-2
-1
0
TCV
(Notes 9, 12)
Ratiometric Temperature Coefficient DCP register set to 40 hex
3
±4
LSB
(Note 4)
ppm/°C
FN6310.1
September 9, 2009
ISL22319
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
ICC1
ICC2
ISB
ISD
PARAMETER
TEST CONDITIONS
MIN
(Note 14)
TYP
(Note 3)
MAX
(Note 14)
UNIT
VCC Supply Current (volatile
write/read)
10k DCP, fSCL = 400kHz; (for I2C active,
read and write states)
1
mA
VCC Supply Current (volatile
write/read, non-volatile read)
50k DCP, fSCL = 400kHz; (for I2C active,
read and write states)
0.5
mA
VCC Supply Current (non-volatile
write/read)
10k DCP, fSCL = 400kHz; (for I2C active,
read and write states)
3.2
mA
VCC Supply Current (non-volatile
write/read)
50k DCP, fSCL = 400kHz; (for I2C active,
read and write states)
2.7
mA
VCC Current (standby)
VCC = +5.5V, 10k DCP, I2C interface in
standby state
850
µA
VCC = +3.6V, 10k DCP, I2C interface in
standby state
550
µA
VCC = +5.5V, 50k DCP, I2C interface in
standby state
160
µA
VCC = +3.6V, 50k DCP, I2C interface in
standby state
100
µA
VCC = +5.5V @ +85°C, I2C interface in
standby state
3
µA
VCC = +5.5V @ +125°C, I2C interface in
standby state
5
µA
VCC = +3.6V @ +85°C, I2C interface in
standby state
2
µA
VCC = +3.6V @ +125°C, I2C interface in
standby state
4
µA
1
µA
VCC Current (shutdown)
Leakage Current, at Pins A0, A1,
SHDN, SDA, and SCL
Voltage at pin from GND to VCC
tDCP
(Note 12)
DCP Wiper Response Time
SCL falling edge of last bit of DCP data byte
to wiper new position
1.5
µs
tShdnRec
(Note 12)
DCP Recall Time from Shutdown
Mode
From rising edge of SHDN signal to wiper
stored position and RH connection
1.5
µs
SCL falling edge of last bit of ACR data byte
to wiper stored position and RH connection
1.5
µs
ILkgDig
Vpor
Power-on Recall Voltage
VCC Ramp
VCC Ramp Rate
tD
Power-up Delay
Minimum VCC at which memory recall occurs
-1
2.0
2.6
0.2
V
V/ms
3
VCC above Vpor, to DCP Initial Value
Register recall completed, and I2C Interface
in standby state
ms
EEPROM SPECIFICATION
EEPROM Endurance
EEPROM Retention
tWC
(Note 13)
Non-volatile Write Cycle Time
4
Temperature T ≤ +55°C
1,000,000
Cycles
50
Years
12
20
ms
FN6310.1
September 9, 2009
ISL22319
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 14)
TYP
(Note 3)
MAX
(Note 14)
UNIT
SERIAL INTERFACE SPECS
VIL
A1, A0, SHDN, SDA, and SCL Input
Buffer LOW Voltage
-0.3
0.3*VCC
V
VIH
A1, A0, SHDN, SDA, and SCL Input
Buffer HIGH Voltage
0.7*VCC
VCC+0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis
VOL
SDA Output Buffer LOW Voltage,
Sinking 4mA
Cpin
fSCL
0.05*
VCC
0
V
0.4
V
A1, A0, SHDN, SDA, and SCL Pin
Capacitance
10
pF
SCL Frequency
400
kHz
tsp
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is
and SCL Inputs
suppressed
50
ns
tAA
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until
Valid
SDA exits the 30% to 70% of VCC window
900
ns
tBUF
Time the Bus Must be Free before the SDA crossing 70% of VCC during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of VCC
during the following START condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
0
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
600
ns
tHD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
From SDA rising edge to SCL falling edge;
both crossing 70% of VCC
1300
ns
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
0
ns
tR
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1*Cb
250
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1*Cb
250
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
tDH
5
FN6310.1
September 9, 2009
ISL22319
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
MIN
(Note 14)
TEST CONDITIONS
TYP
(Note 3)
MAX
(Note 14)
UNIT
1
kΩ
Before START condition
600
ns
After STOP condition
600
ns
Rpu
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by tR and tF
For Cb = 400pF, max is about 2kΩ~2.5kΩ
For Cb = 40pF, max is about 15kΩ~20kΩ
tSU:A
A1 and A0 Setup Time
tHD:A
A1 and A0 Hold Time
NOTES:
3. Typical values are for TA = +25°C and 3.3V supply voltage.
4. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
5. ZSerror = V(RW)0/LSB.
6. FSerror = [V(RW)127 – VCC]/LSB.
7. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
8. INL = [V(RW)i – (i • LSB) – V(RW)0]/LSB for i = 1 to 127
Max ( V ( RW ) i ) – Min ( V ( RW ) i )
10 6 - for i = 16 to 127 decimal, T = -40°C to +125°C. Max() is the maximum value of the wiper
9. TC = --------------------------------------------------------------------------------------------- × -------------------V
[ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 +165°C voltage and Min () is the minimum value of the wiper voltage over the temperature range.
10. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and
00 hex respectively.
11. Roffset = RW0/MI, when measuring between RW and RL.
Roffset = RW127/MI, when measuring between RW and RH.
12. This parameter is not 100% tested.
13. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile
write cycle.
14. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
SDA vs SCL Timing
tHIGH
tF
SCL
tLOW
tsp
tR
tHD:STO
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
SDA
(INPUT TIMING)
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
6
FN6310.1
September 9, 2009
ISL22319
A0 and A1 Pin Timing
STOP
START
SCL
CLK 1
SDA
tSU:A
tHD:A
A0, A1
Typical Performance Curves
100
1.4
VCC = 3.3V, T = +125ºC
1.2
T = +125°C
80
1.0
70
60
Isb (µA)
WIPER RESISITANCE (W)
90
50
40
30
0.6
0.4
VCC = 3.3V, T = -40ºC
VCC = 3.3V, T = +20ºC
0.8
20
0.2
10
0
0
20
40
60
80
100
T = +25°C
0
2.7
120
3.2
3.7
TAP POSITION (DECIMAL)
0.2
5.2
0.2
VCC = 2.7V
T = +25°C
T = +25°C
0.1
VCC = 2.7V
0.1
INL (LSB)
DNL (LSB)
4.7
FIGURE 2. STANDBY Isb vs VCC
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[I(RW) = VCC/RTOTAL ] FOR 10kΩ (W)
0
-0.1
0
-0.1
VCC = 5.5V
VCC = 5.5V
-0.2
4.2
VCC (V)
0
20
40
60
80
100
TAP POSITION (DECIMAL)
120
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
7
-0.2
0
20
40
60
80
100
TAP POSITION (DECIMAL)
120
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
FN6310.1
September 9, 2009
ISL22319
Typical Performance Curves
(Continued)
1.30
0.00
10k
1.10
-0.30
FSerror (LSB)
ZSerror (LSB)
0.90
0.70
0.50
VCC = 2.7V
VCC = 5.5V
0.30
50k
VCC = 5.5V
VCC = 2.7V
-0.60
-0.90
10k
0.10
50k
-0.10
-0.30
-40
-1.20
-20
0
20
40
60
TEMPERATURE (ºC)
80
100
-1.50
-40
120
20
40
60
TEMPERATURE (ºC)
80
100
120
105
1.0
90
VCC = 2.7V
0.5
10k
75
TCv (ppm/°C)
END-TO-END RTOTAL CHANGE (%)
0
FIGURE 6. FSerror vs TEMPERATURE
FIGURE 5. ZSerror vs TEMPERATURE
50k
0.0
60
45
50k
30
-0.5
VCC = 5.5V
-1.0
-40
-20
-20
0
15
10k
20
40
60
TEMPERATURE (ºC)
80
100
FIGURE 7. END-TO-END RTOTAL% CHANGE vs
TEMPERATURE
120
0
16
36
56
76
TAP POSITION (DECIMAL)
96
FIGURE 8. TC FOR VOLTAGE DIVIDER MODE IN ppm
SIGNAL AT WIPER
(WIPER UNLOADED
SIGNAL AT WIPER
(WIPER UNLOADED MOVEMENT
FROM 7Fh TO 00h)
FIGURE 9. MIDSCALE GLITCH, CODE 3Fh TO 40h
8
FIGURE 10. LARGE SIGNAL SETTLING TIME
FN6310.1
September 9, 2009
ISL22319
Pin Description
Potentiometers Pins
RW
RW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.
SHDN
The active low SHDN pin forces the resistor to end-to-end
open circuit condition and shorts RWi to GND. When SHDN
is returned to logic high, the previous latch settings put RW
at the same resistance setting prior to shutdown. This pin is
logically ANDed with SHDN bit in ACR register. I2C interface
is still available in shutdown mode and all registers are
accessible. This pin must remain HIGH for normal operation
(see Figure 11).
RW
FIGURE 11. DCP CONNECTION IN SHUTDOWN MODE
Bus Interface Pins
host and the potentiometer and memory. The resistor array
is comprised of individual resistors connected in series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the contents of the IVR is recalled and
loaded into the WR to set the wiper to the initial value.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer and internally connected to VCC and GND.
The RW pin of the DCP is connected to intermediate nodes,
and is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the
DCP is controlled by an 7-bit volatile Wiper Register (WR).
When the WR of a DCP contains all zeroes (WR[6:0]= 00h),
its wiper terminal (RW) is closest to GND. When the WR
register of a DCP contains all ones (WR[6:0] = 7Fh), its wiper
terminal (RW) is closest to VCC. As the value of the WR
increases from all zeroes (0) to all ones (127 decimal), the
wiper moves monotonically from the position closest to GND
to the closest to VCC.
interface. It receives device address, operation code, wiper
address and data from an I2C external master device at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.
While the ISL22319 is being powered up, the WR is reset to
40h (64 decimal), which locates RW roughly at the center
between VCC and GND. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WR will be reload with the value stored in a
non-volatile Initial Value Register (IVR).
SDA requires an external pull-up resistor, since it is an open
drain input/output.
The WR and IVR can be read or written to directly using the
I2C serial interface as described in the following sections.
SERIAL CLOCK (SCL)
Memory Description
This is the serial clock input of the I2C serial interface. SCL
requires an external pull-up resistor, since it is an open drain
input.
The ISL22319 contains one non-volatile 8-bit register, known as
the Initial Value Register (IVR), and two volatile 8-bit registers,
Wiper Register (WR) and Access Control Register (ACR). The
memory map of ISL22319 is on Table 1. The non-volatile
register (IVR) at address 0, contains initial wiper position and
volatile register (WR) contains current wiper position.
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for I2C
DEVICE ADDRESS (A1, A0)
The address inputs are used to set the least significant 2 bits
of the 7-bit I2C interface slave address. A match in the slave
address serial data stream must match with the Address
input pins in order to initiate communication with the
ISL22319. A maximum of 4 ISL22319 devices may occupy
the I2C serial bus.
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
2
—
ACR
1
Principles of Operation
The ISL22319 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and an I2C
serial interface providing direct communication between a
9
0
Reserved
IVR
WR
The non-volatile IVR and volatile WR registers are
accessible with the same address.
FN6310.1
September 9, 2009
ISL22319
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
The VOL bit (ACR[7]) determines whether the access is to
wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
VOL
SHDN
0
WIP
0
0
0
0
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shutdown mode.
This bit is logically ANDed with SHDN pin. When this bit is 0,
DCP is in Shutdown mode. Default value of SHDN bit is 1.
The WIP bit (ACR[5]) is read only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the WR or ACR while WIP bit is 1.
Shutdown Mode
The device can be put in Shutdown mode either by pulling the
SHDN pin to GND or setting the SHDN bit in the ACR register
to 0. The truth table for Shutdown mode is in Table 3.
TABLE 3.
SHDN pin
SHDN bit
Mode
High
1
Normal operation
Low
1
Shutdown
High
0
Shutdown
Low
0
Shutdown
I2C Serial Interface
The ISL22319 supports an I2C bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22319
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions
(see Figure 12). On power-up of the ISL22319 the SDA pin
is in the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22319 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met
(see Figure 12). A START condition is ignored during the
power-up of the device.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 12). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 13).
The ISL22319 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22319 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 01010 as the five MSBs, and
the following two bits matching the logic values present at pins
A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a
Read operation, and “0” for a Write operation (see Table 4).
TABLE 4. IDENTIFICATION BYTE FORMAT
Logic values at pins A1 and A0 respectively
0
1
0
1
0
(MSB)
A1
A0
R/W
(LSB)
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS
10
FN6310.1
September 9, 2009
ISL22319
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
S
T
A
R
T
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
IDENTIFICATION
BYTE
ADDRESS
BYTE
0 1 0 1 0 A1 A0 0
SIGNALS FROM
THE SLAVE
S
T
O
P
DATA
BYTE
0 0 0 0
A
C
K
A
C
K
A
C
K
FIGURE 14. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
IDENTIFICATION
BYTE WITH
R/W=0
ADDRESS
BYTE
0 1 0 1 0 A1 A0 0
A
C
K
S
A T
C O
K P
A
C
K
0 1 0 1 0 A1 A0 1
0 0 0 0
A
C
K
SIGNALS FROM
THE SLAVE
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W=1
A
C
K
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 15. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22319 responds with an ACK. At this time, the device
enters its standby state (see Figure 14).
The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next
non-volatile write.
the three bytes, the ISL22319 responds with an ACK. Then
the ISL22319 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a ACK and STOP condition) following the
last bit of the last Data Byte (see Figure15).
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure15). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
11
Applications Information
The typical application diagram is shown on Figure 16. For
proper operation adding 0.1µF decoupling ceramic capacitor
to VCC is recommended. The capacitor value may vary
based on expected noise frequency of the design.
FN6310.1
September 9, 2009
ISL22319
VCC
VCC VCC
0.1µF
Rpu
Rpu
VCC
SHDN
0.1µF
RW
SCL
SDA
A0
A1
VOUT
R2
ISL22319
R1
FIGURE 16. TYPICAL APPLICATION DIAGRAM FOR IMPLEMENTING ADJUSTABLE VOLTAGE REFERANCE
12
FN6310.1
September 9, 2009
ISL22319
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
SYMBOL
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
SEATING
PLANE -CA
4X θ
A2
A1
b
-H-
0.10 (0.004)
L1
SEATING
PLANE
C
-Ae
D
0.20 (0.008)
C
C
a
SIDE VIEW
CL
E1
0.20 (0.008)
C D
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.010
0.014
0.25
0.36
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
e
L
MIN
0.026 BSC
0.65 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
L1
0.037 REF
0.95 REF
-
N
8
8
7
R
0.003
-
0.07
-
-
R1
0.003
-
0.07
-
-
0
5o
15o
5o
15o
-
α
0o
6o
0o
6o
-
-B-
Rev. 2 01/03
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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13
FN6310.1
September 9, 2009
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