DATASHEET

NS
W DESIG
E
N
R
O
NDED F LACEMENT:
C OM ME
P
NOT RE MMENDED RE
Digitally Controlled Potentiometer
O
0
C
1
E
3
R
ISL95
Data Sheet
August 31, 2006
ISL95710
Terminal Voltage ±2.7V to ±5V, 128 Taps,
Up/Down Interface
The Intersil ISL95710 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a Up/Down interface.
The potentiometer is implemented by a resistor array
composed of 127 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile memory
and then be recalled upon a subsequent power-up operation.
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:
• Industrial and automotive control
(XDCP™)
FN8240.3
Features
• Non-Volatile Solid-State Potentiometer
• Up/Down Interface with Chip Select Enable
• DCP Terminal Voltage ±2.7V to ±5.5V
• 128 Wiper Tap Points
- Wiper position stored in nonvolatile memory and
recalled on power-up
• 127 Resistive Elements
- Typical RTOTAL tempco = ±50ppm/°C
- End to end resistance range ±20%
• Low Power CMOS
- Standby current, 1µA
- Active current, 3mA max
- VCC = 2.7V to 5.5V
- V- = -2.7V to -5.5V
• High Reliability
- Endurance, 200,000 data changes per bit
- Register data retention, 50 years
• Parameter and bias adjustments
• Amplifier bias and control
• RTOTAL Values = 10k50k
Pinout
• Package
- 10 Ld MSOP
- Pb-free plus anneal (RoHS compliant)
ISL95710
(10 LD MSOP)
TOP VIEW
U/D
1
10
INC
V-
2
9
VCC
GND
3
8
RL
CS
4
7
RW
NC
5
6
RH
Ordering Information
PART NUMBER
(Notes 1, 2)
PART MARKING
RESISTANCE OPTION
()
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
ISL95710WIU10Z
AKR
10k
-40 to +85
10 Ld MSOP
M10.118
ISL95710UIU10Z
AKP
50k
-40 to +85
10 Ld MSOP
M10.118
NOTES:
1. Add “-T” suffix for tape and reel.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil, Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL95710
Block Diagram
U/D
INC
VCC
V- (ANALOG VOLTAGE)
CS
UP/DOWN
(INC)
DEVICE SELECT
CONTROL
AND
MEMORY
126
125
7-BIT
NONVOLATILE
MEMORY
RW
(CS)
RH
127
RH
(U/D)
INCREMENT
7-BIT
UP/DOWN
COUNTER
124
ONE
OF
128
TRANSFER
GATES
RESISTOR
ARRAY
DECODER
RL
2
GND (GROUND)
VGND
GENERAL
STORE AND
RECALL
CONTROL
CIRCUITRY
1
0
RL
RW
DETAILED
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1
U/D
2
V-
3
GND
4
CS
Chip select. The device is selected when the CS input is LOW. Also used to initiate a nonvolatile store
5
NC
No Connect. Pin is to be left unconnected
6
RH
A fixed terminal for one end of the potentiometer resistor
7
RW
The wiper terminal which is equivalent to the movable terminal of a potentiometer
8
RL
A fixed terminal for one end of the potentiometer resistor
9
VCC
Positive logic supply voltage
10
INC
Increment input; negative edge triggered
Controls the direction of wiper movement and whether the counter is incremented or decremented
Negative bias voltage for the potentiometer wiper control
Ground
2
FN8240.3
August 31, 2006
ISL95710
Absolute Maximum Ratings
Thermal Information
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on CS, INC, U/D and VCC
with respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +6V
Voltage on V- (referenced to GND) . . . . . . . . . . . . . . . . . . . . . . . -6V
V = |V(RH)-V(RL)| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Lead temperature (soldering 10 seconds) . . . . . . . . . . . . . . . . 300°C
IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
ESD (Mil-Std 883, Method 3015) . . . . . . . . . . . . . . . . . . . . . . . .>2kV
ESD Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>150V
Thermal Resistance (Typical, Note 3)
JA (°C/W)
MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+170
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40°C to +85°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to -5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
NOTE:
3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
SYMBOL
RTOTAL
Over recommended operating conditions unless otherwise stated.
PARAMETER
RH to RL resistance
TEST CONDITIONS
VRH,VRL
RW
CH/CL/CW
(Note 13)
ILkgDCP
UNIT
k
U option
50
k
-20
IDCP = 1mA
T = -40°C to +85°C
+20
±50
VV- = -5.5V; VCC = +5.5V,
wiper current = (VCC-V-)/RTOTAL
VCC
V
200

10/10/25
Voltage at pins; V- to VCC
-1
%
ppm/°C
70
Potentiometer Capacitance
Leakage on DCP pins
MAX
10
RH,RL terminal voltage
Wiper resistance
TYP
(Note 1)
W option
RH to RL resistance tolerance
TCR
Resistance Temperature Coefficient
(Note 12, 13)
MIN
0.1
pF
1
µA
-1
1
LSB
(Note 2)
-0.5
0.5
LSB
(Note 2)
LSB
(Note 2)
VOLTAGE DIVIDER MODE (V- @ RL; VCC @ RH; Voltage at RW = VRW unloaded)
INL
(Note 6)
Integral non-linearity
DNL
(Note 5)
Differential non-linearity
W, U options
ZSerror
(Note 3)
Zero-scale error
W option
0
1
4
U option
0
0.5
2
FSerror
(Note 4)
Full-scale error
W option
-4
-1
0
U option
-2
-0.5
0
TCV
Ratiometric Temperature Coefficient
(Notes 7, 13)
DCP Register set at 63d,
T = -40°C to +85°C
±4
LSB
(Note 2)
ppm/°C
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)
RINL
(Note 11)
Integral non-linearity
DCP register set between 20 hex and 5F hex.
Monotonic over all tap positions
RDNL
(Note 10)
Differential non-linearity
W, U options
Roffset
(Note 9)
Offset
DCP Register set to 00 hex, W option
0
DCP Register set to 00 hex, U option
0
3
-1
1
MI
(Note 8)
-0.5
0.5
MI
(Note 8)
2
5
0.5
2
MI
(Note 8)
FN8240.3
August 31, 2006
ISL95710
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNIT
500
µA
ICC1
VCC supply current, volatile write/read CS = VIL, U/D = VIL or VIH and INC = VIL or VIH,
RL, RH, RW not connected
IV-1
V- supply current, volatile write/read
CS = VIL, U/D = VIL or VIH and INC = VIL or VIH,
RL, RH, RW not connected
ICC2
VCC supply current, nonvolatile write
U/D = VIL or VIH and INC = VIH, CS = transitions
from VIL to VIH. RL, RH, RW not connected
IV-2
V- supply current, nonvolatile write
U/D = VIL or VIH and INC = VIH, CS = transitions
from VIL to VIH. RL, RH, RW not connected
VCC current (standby)
VCC = +5.5V, I2C Interface in Standby State
1
µA
VCC = +3.6V, I2C Interface in Standby State
1
µA
ICCSB
IV-SB
V- current (standby)
A
-100
500
µA
-3
mA
V- = -5.5V, CS = VIH
-5
µA
V- = -3.6V, CS = VIH
-2
µA
ILkgDig
Leakage current, at pins INC, CS, and VIL or VIH applied at pin
U/D
-10
IIL_CS
Leakage at CS, input low
VIL = 0V
-300
A
Power-on recall for both V- and VCC
V-
-2.5
V
Vpor
10
VCC
V- Ramp
V- ramp rate
µA
2.5
V
-0.2
V/ms
EEPROM SPECS
EEPROM Endurance
200,000
Cycles
50
Years
Temperature  +75°C
EEPROM Retention
3-WIRE INTERFACE SPECS
VIL
INC, CS, and U/D input buffer LOW
voltage
-0.3
0.3*VCC
V
VIH
INC, CS, and U/D input buffer HIGH
voltage
0.7*VCC
VCC+
0.3
V
Hysteresis
(Note 13)
Cpin
INC, CS, and U/D input buffer
hysteresis
INC, CS, and U/D pin capacitance
AC Electrical Specifications
SYMBOL
0.15*
VCC
V
10
pF
VCC = 5V ±10%, TA = Full Operating Temperature Range unless otherwise stated
PARAMETER
MIN
TYP (Note 1)
MAX
UNIT
tCl
CS to INC setup
100
ns
tlD
INC HIGH to U/D change
100
ns
tDI
U/D to INC setup
1
µs
tlL
INC LOW period
1
µs
tlH
INC HIGH period
1
µs
tlC
INC inactive to CS inactive
1
µs
tCPHS
(Note 14)
CS deselect time (STORE)
20
ms
CS deselect time (NO STORE)
1
µs
tCPHNS
4
FN8240.3
August 31, 2006
ISL95710
AC Electrical Specifications
VCC = 5V ±10%, TA = Full Operating Temperature Range unless otherwise stated (Continued)
SYMBOL
tIW
PARAMETER
MIN
INC to RW change
tCYC
INC cycle time
tR, tF
INC input rise and fall time
TYP (Note 1)
MAX
UNIT
100
500
µs
2
µs
500
µs
NOTES:
1. Typical values are for TA = +25°C and 3.3V supply voltage.
2. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = (V(RW)0– V-)/LSB.
4. FS error = [V(RW)127 – V+]/LSB.
5. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
6. INL = V(RW)i – (i • LSB – V(RW)0)/LSB for i = 1 to 127.
Max  V  RW  i  – Min  V  RW  i 
10 6
7. TC V = ----------------------------------------------------------------------------------------------x ---------------- Max  V  RW  i  + Min  V  RW  i    2 125°C
for i = 16 to 120 decimal. Max ( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the
temperature range.
8. MI = |R127 – R0| /127. R127 and R0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively.
9. Roffset = R0/MI, when measuring between RW and RL.
Roffset = R127/MI, when measuring between RW and RH.
10. RDNL = (Ri – Ri-1)/MI -1, for i = 16 to 127.
11. RINL = [Ri – (MI • i) – R0]/MI, for i = 16 to 127.
6
 Max  Ri  – Min  Ri  
10
12. TC = ----------------------------------------------------------------  ----------------R
 Max  Ri  + Min  Ri    2 125°C
for i = 16 to 127, T = -40°C to +85°C. Max ( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over
the temperature range.
13. This parameter is not 100% tested.
14. tCPHS is the minimum cycle time to be allowed for any non-volatile Write by the user. It is the time from a valid STORE condition to the end of
the self-timed internal non-volatile write cycle. No CS or INC changes should be allowed.
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change from Low to High
Will change from Low to High
May change from High to Low
Will change from High to Low
Don’t Care: Changes Allowed
Changing: State Not Known
N/A
Center Line is High Impedance
5
FN8240.3
August 31, 2006
ISL95710
A.C. Timing
CS
tCYC
tCI
tIL
tIC
tIH
tCPHNS
tCPHS
90%
90%
10%
INC
tID
tDI
tF
tR
U/D
tIW
MI
RW
(1)
NOTE (1): MI IN THE TIMING DIAGRAM REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE WIPER POSITION.
Typical Performance Curves
120
Irw=0.6mA
T=85ºC
80
0.6
60
0.5
Isb (µA)
WIPER RESISTANCE ()
100
T=25ºC
40
20
T = 85ºC
T = 25ºC
T = -40ºC
0.4
T=-40ºC
0.3
2.7
0
0
20
40
60
80
100
120
3.2
3.7
4.2
TAP POSITION (DECIMAL)
5.2
FIGURE 2. STANDBY ICC vs VCC
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[I(RW) = VCC/RTOTAL] for 10k (W)
0.2
0.2
Vrh=5.5V, Vrl=-5.5V
Vrh=5.5V, Vrl=-5.5V
0.1
0.1
INL (LSB)
DNL (LSB)
4.7
Vcc, V
0
0
-0.1
-0.1
Vrh=2.7V, Vrl=-2.7V
Vrh=2.7V, Vrl=-2.7V
-0.2
0
20
40
60
80
-0.2
100
120
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
6
0
20
40
60
80
100
120
TAP POSITION (DECIMAL)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
FN8240.3
August 31, 2006
ISL95710
Typical Performance Curves
(Continued)
1.6
0
Vrh=2.7V, Vrl=-2.7V, 10k
-0.4
FSerror (LSB)
ZSerror (LSB)
1.2
0.8
Vrh=5.5V, Vrl=-5.5V, 10k
0.4
Vrh=5.5V, Vrl=-5.5V, 10k
-0.8
-1.2
-1.6
Vrh=2.7V, Vrl=-2.7V, 10k
0
-40
-20
0
20
40
60
-2
-40
80
-20
TEMPERATURE (C)
0
20
60
80
TEMPERATURE (C)
FIGURE 5. ZSerror vs TEMPERATURE
FIGURE 6. FSerror vs TEMPERATURE
1
0.1
T=25ºC
T=25º
C
Vcc=2.7V, V-=-2.7V
0.8
Vcc=2.7V, V-=2 7V
0.05
RINL (LSB)
0.6
RDNL (LSB)
40
0
0.4
0.2
-0.05
0
Vcc=5.5V, V-=-5.5V
-0.1
Vcc=5.5V, V-=5 5V
-0.2
0
20
40
60
80
100
120
0
50
TAP POSITION (DECIMAL)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR
10k (W)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR
10k (W)
100
1
Idcp= 0.57mA
80
0.5
TCv (ppm/°C)
END TO END RTOTAL CHANGE (%)
100
TAP POSITION (DECIM AL)
0
Idcp= 1.16mA
-0.5
60
40
10k
20
50k
-1
-40
0
-20
0
20
40
60
TEMPERATURE (ºC)
FIGURE 9. END TO END RTOTAL % CHANGE vs
TEMPERATURE
7
80
16
36
56
76
96
116
TAP POSITION (DECIMAL)
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
FN8240.3
August 31, 2006
ISL95710
Typical Performance Curves
(Continued)
200
10k
TCr (ppm/°C)
150
100
50
50k
0
16
36
56
76
96
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (1.8MHz)
FIGURE 13. WIPER MOVEMENT
FIGURE 14. LARGE SIGNAL SETTLING TIME
Power Up and Down Requirements
RW
In order to prevent unwanted tap position changes, or an
inadvertent store, bring the CS and INC high before or
concurrently with the VCC pin on power-up. The
potentiometer voltages must be applied after this sequence
is completed. During power-up, the data sheet parameters
for the DCP do not fully apply until 1ms after VCC reaches its
final value. The VCC ramp spec is always in effect.
Rw is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the wiper counter.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement and
whether the wiper counter is incriminated or decremented.
Increment (INC)
Pin Descriptions
RH and RL
The high (RH) and low (RL) terminals of the ISL95710 are
equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of RL and RH references the
relative position of the terminal in relation to wiper movement
direction selected by the U/D input and not the voltage
potential on the terminal.
8
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the wiper
counter in the direction indicated by the logic level on the
U/D input.
Chip Select (CS)
The device is selected when the CS input is LOW. The
current wiper counter value is stored in nonvolatile memory
when CS is returned HIGH while the INC input is also HIGH.
After the store operation is complete the ISL95710 will be
FN8240.3
August 31, 2006
ISL95710
placed in the low power standby mode until the device is
selected once again.
Principles of Operation
There are three sections of the ISL95710: the input control,
wiper counter and decode section; the nonvolatile memory;
and the resistor array. The input control section operates as
an up/down counter. The output of this wiper counter is
decoded to turn on a electronic switch connecting a point on
the resistor array to the wiper output. The contents of the
wiper counter can be stored in nonvolatile memory and
retained for future use. The resistor array is comprised of
individual resistors connected in series. At either end of the
array and between each resistor is an electronic switch that
transfers the potential at that point to the wiper.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. The wiper counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for tIW (INC to RW change). The
RTOTAL value for the device can temporarily be reduced by
a significant amount if the wiper is moved several positions.
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
During initial power-up CS must go high along with or before
VCC to avoid an accidental store generation.
TABLE 1. MODE SELECTION
CS
INC
U/D
MODE
L
H
Wiper up
L
L
Wiper down
H
X
Store wiper position
X
X
Standby current
L
X
No store, return to standby
H
X
Standby
L
H
Wiper up one position
(not recommended)
L
L
Wiper down one position
(not recommended)
H
H
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.
Instructions and Programming
The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS set LOW the device
is selected and enabled to respond to the U/D and INC
inputs. HIGH to LOW transitions on INC will increment or
decrement (depending on the state of the U/D input) a seven
bit wiper counter. The output of this wiper counter is decoded
to select one of 128 wiper positions along the resistive array.
The value of the wiper counter is stored in nonvolatile
memory whenever CS transitions HIGH while the INC input
is also HIGH.
The system may select the ISL95710, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as described above and once the new position is
reached, the system must keep INC LOW while taking CS
HIGH. The new wiper position will be maintained until
changed by the system or until a power-up/down cycle
recalls the previously stored data.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The
9
FN8240.3
August 31, 2006
ISL95710
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X 
0.25
(0.010)
R1
R
GAUGE
PLANE
SEATING
PLANE -CA
4X 
A2
A1
b
-H-
0.10 (0.004)
L
SEATING
PLANE
C
D
0.20 (0.008)
MAX
MIN
MAX
NOTES
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.007
0.011
0.18
0.27
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.020 BSC
C
a
CL
E1
0.20 (0.008)
C D
0.50 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
C
SIDE VIEW
MIN
A
L1
-A-
e
SYMBOL
e
L1
MILLIMETERS
0.95 REF
10
R
0.003
R1
-
10
-
0.07
0.003
-

5o
15o

0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
-B-
Rev. 0 12/02
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B -
to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN8240.3
August 31, 2006
Similar pages