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1-888-IN
ISL23711
®
Digitally Controlled Potentiometer (XDCP™)
Terminal Voltage ±3V or ±5V, 128 Taps I2C
Serial Interface
The Intersil ISL23711 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, and a control section. The wiper position is
controlled by an I2C interface.
The potentiometer is implemented by a resistor array
composed of 127 resistive elements and a wiper switching
network. The wiper terminal can be connected to either end
of the resistor array or at any one of the Tap Positions in
between, providing 128 steps of resolution between RL and
RH. The “position” of the wiper is determined by the value
assigned to the volatile Wiper Register (WR). The WR can
be directly written to and read from using standard I2C
interface protocol. The device is available in either a 10kor
50k version.
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:
August 16, 2005
FN6127.0
Features
• I2C Serial Interface with Hardwire Slave Address Allows
up to Four Devices
• DCP Terminal Voltage, from V- to VCC
• 127 Resistive Elements
- Typical RTOTAL tempco ±50ppm/°C
- Typical ratiometric tempco ±4ppm/°C
- End to end resistance range ±20%
- Wiper resistance = 70 typ at VCC = 3.3V
• Low Power CMOS
- Standby current, 500nA max
- Active current, 200A max
- VCC = 2.7V to 5.5V
- V- = -2.7V to -5.5V
• RTOTAL Values = 10k50k
• Volatile Wiper Storage
• Industrial and Automotive Control
• Package
- 10 Ld MSOP
• Parameter and Bias Adjustments
• Pb-Free Plus Anneal Available (RoHS Compliant)
• Amplifier Bias and Control
Pinout
ISL23711
(10 LD MSOP)
TOP VIEW
Ordering Information
PART NUMBER
(BRAND)
RESISTANCE
OPTION ()
TEMP
RANGE
(°C)
ISL23711WIU10Z
(AOE) (Notes 1, 2)
10K
-40 to +85
ISL23711UIU10Z
(AOD) (Notes 1, 2)
50K
-40 to +85
PACKAGE
PKG.
DWG. #
10 Ld MSOP
(Pb-Free)
M10.118
10 Ld MSOP
(Pb-Free)
M10.118
NOTES:
SDA
1
10
SCL
V-
2
9
VCC
GND
3
8
RL
A1
4
7
RW
A0
5
6
RH
1. Add “-T” suffix for tape and reel.
2. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil, Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL23711
Block Diagram
SDA
SCL
GND
VCC
7-BIT
WIPER
REGISTER
(VOLATILE)
RH
127
126
SDA
125
RH
SCL
124
INTERFACE
AND
CONTROL
A1
RW
ONE
OF
128
A0
TRANSFER
GATES
RESISTOR
ARRAY
DECODER
RL
2
RECALL
CONTROL
CIRCUITRY
VSIMPLE BLOCK DIAGRAM
A1
A0
1
0
RL
RW
SLAVE
ADDRESS
DECODE
DETAILED BLOCK DIAGRAM
Pin Descriptions
PIN NUMBER
1
SYMBOL
SDA
DESCRIPTION
Data I/O for I2C serial interface. It has an open drain output and may be wire ORed with other open
drain active low outputs.
2
V-
Negative supply voltage for the potentiometer wiper control.
3
GND
4
A1
A1 and A0 are address select pins used to set the slave address for the I2C serial interface.
5
A0
A1 and A0 are address select pins used to set the slave address for the I2C serial interface.
6
RH
A fixed terminal for one end of the potentiometer resistor.
7
RW
The wiper terminal which is equivalent to the movable terminal of a potentiometer.
8
RL
A fixed terminal for one end of the potentiometer resistor.
9
VCC
Positive logic supply voltage.
10
SCL
Clock input for the I2C serial interface.
2
Ground. Should be connected to a digital ground
FN6127.0
August 16, 2005
ISL23711
Absolute Maximum Ratings
Thermal Information
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on SDA, SCL, A0, and A1
with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3 to VCC+0.3V
Voltage on V- (referenced to GND) . . . . . . . . . . . . . . . . . . . . . . . -6V
V = |V(RH)-V(RL)| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Lead Temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . . 300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
RH, RL, RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to VCC
ESD Rating (MIL-STD-883, Method 3015.7 . . . . . . . . . . . . . . .>2kV
Thermal Resistance (Typical, Note 3)
JA (°C/W)
MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40°C to +85°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to -5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
NOTE:
3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
SYMBOL
RTOTAL
VRH,VRL
RW
CH/CL/CW
ILkgDCP
Over recommended operating conditions unless otherwise stated.
PARAMETER
RH to RL Resistance
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNIT
W option
10
k
U option
50
k
RH to RL Resistance Tolerance
-20
+20
%
RH, RL Terminal Voltage
V-
VCC
V
200

Wiper Resistance
V- = -5.5V; VCC = +5.5V
Wiper current = (VCC - V-)/RTOTAL
70
Potentiometer Capacitance (Note 13)
Leakage on RH, RL, RW pins
10/10/25
Voltage at pins; V- to VCC
-1
0.1
pF
1
µA
-1
1
LSB
(Note 2)
-0.5
0.5
LSB
(Note 2)
LSB
(Note 2)
VOLTAGE DIVIDER MODE (V- @ RL; VCC @ RH; Voltage at RW = VRW unloaded)
INL
(Note 6)
Integral Non-linearity
DNL
(Note 5)
Differential Non-linearity
W, U options
ZSerror
(Note 3)
Zero-scale Error
W option
0
1
4
U option
0
0.5
2
FSerror
(Note 4)
Full-scale Error
W option
-4
-1
0
U option
-2
-0.5
0
TCV
(Notes 7, 13)
Ratiometric Temperature Coefficient
DCP register set from 16 to 120d, T = -40°C to
+85°C
±4
LSB
(Note 2)
ppm/°C
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)
RINL
(Note 11)
Integral Non-linearity
RDNL
(Note 10)
Differential Non-linearity
Roffset
(Note 9)
Offset
TCR
Resistance Temperature Coefficient
(Notes 12, 13)
3
DCP register set between 20 hex and 7F hex.
Monotonic over all tap positions
-1
1
MI
(Note 8)
-0.5
0.5
MI
(Note 8)
DCP register set to 00 hex, W option
0
2
5
MI
(Note 8)
DCP register set to 00 hex, U option
0
0.5
2
MI
(Note 8)
DCP register set from 16 to 127d, T = -40°C to
+85°C
±50
ppm/°C
FN6127.0
August 16, 2005
ISL23711
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
ICC1
PARAMETER
VCC Supply Current, Volatile
Write/Read
UNIT
200
A
-1
A
VCC = +5.5V, I2C Interface in Standby State
500
nA
VCC = +3.6V, I2C Interface in Standby State
300
nA
V- Supply Current, Volatile Write/Read fSCL = 400kHz; SDA = Open; (for I2C, Active,
Read and Write states only)
ISB
VCC Current (Standby)
ILkgDig
tDCP
(Note 13)
Vpor
MIN
fSCL = 400kHz; SDA = Open; (for I2C, Active,
Read and Write states only)
IV-
IV-SB
TYP
(Note 1)
MAX
TEST CONDITIONS
-100
V- = -5.5V, I2C Interface in Standby State
-500
V- = -2.7V, I2C Interface in Standby State
-300
-1
nA
Leakage Current, at Pins SDA, SCL,
A0, and A1
Voltage at pin from GND to VCC
-10
10
µA
DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to
wiper change
V- Current (Standby)
Power-on Recall for VCC
nA
1
µs
2.5
V
SERIAL INTERFACE SPECS
VIL
A0, A1, SDA, and SCL Input Buffer
LOW Voltage
-0.3
0.3*VCC
V
VIH
A0, A1, SDA, and SCL Input Buffer
HIGH Voltage
0.7*VCC
VCC+
0.3
V
Hysteresis
VOL
SDA and SCL Input Buffer Hysteresis
V
0.05*
VCC
0.4
V
A0, A1, SDA, and SCL Pin
Capacitance
10
pF
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is
and SCL Inputs
suppressed
50
ns
tAA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of VCC, until SDA
exits the 30% to 70% of VCC window
900
ns
tBUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC during
the following START condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VCC
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to
SCL falling edge crossing 70% of VCC
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to
SDA entering the 30% to 70% of VCC window
0
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VCC
600
ns
tHD:STO
STOP Condition Setup Time
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC
600
ns
Cpin
(Note 14)
fSCL
SDA Output Buffer LOW Voltage,
Sinking 4mA
4
0
FN6127.0
August 16, 2005
ISL23711
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
TYP
(Note 1)
TEST CONDITIONS
MIN
Output Data Hold Time
From SCL falling edge crossing 30% of VCC, until
SDA enters the 30% to 70% of VCC window
0
tR
(Note 14)
SDA, SCL, A0, A1 Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
ns
tF
(Note 14)
SDA, SCL, A0, A1 Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb
(Note 14)
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
(Note 14)
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by tR and tF
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
1
k
tSU:A
A0, A1 Setup Time
Before START condition
600
ns
tHD:A
A0, A1 Hold Time
After STOP condition
600
ns
tDH
PARAMETER
MAX
UNIT
ns
SDA vs SCL Timing
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:STA
tHD:DAT
tHD:STA
SDA
(INPUT TIMING)
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
A0, A1 Pin Timing
STOP
START
SCL
Clk 1
SDA IN
tSU:A
tHD:A
A0, A1
5
FN6127.0
August 16, 2005
ISL23711
NOTES:
1. Typical values are for TA = 25°C and ±5V supply voltage.
2. LSB: [V(RW)127 – V(RW)0] / 127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = (V(RW)0 – V-) / LSB.
4. FS error = [V(RW)127 – VCC] / LSB.
5. DNL = [V(RW)i – V(RW)i-1] / LSB-1, for i = 1 to 127. i is the DCP register setting.
6. INL = V(RW)i – (i • LSB – V(RW)0) for i = 1 to 127.
Max  V  RW  i  – Min  V  RW  i 
10 6
7. TC V = ----------------------------------------------------------------------------------------------  ---------------- Max  V  RW  i  + Min  V  RW  i    2 125°C
for i = 16 to 120 decimal, Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the
temperature range.
8. MI = |R127 – R0| / 127. R127 and R0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively.
9. Roffset = R0 / MI, when measuring between RW and RL.
Roffset = R127 / MI, when measuring between RW and RH.
10. RDNL = (Ri – Ri-1) / MI, for i = 16 to 127.
11. RINL = [Ri – (MI • i) – R0] / MI, for i = 16 to 127.
6
 Max  Ri  – Min  Ri  
10
12. TC R = ----------------------------------------------------------------  ---------------- Max  Ri  + Min  Ri    2 125°C
for i = 16 to 127, Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the temperature range.
13. This parameter is not 100% tested.
14. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
RW
Test Circuit
Rw is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs.
TEST POINT
BUS INTERFACE PINS
RW
FORCE
CURRENT
Serial Data Input/Output (SDA)
The SDA is a bidirectional serial data input/output pin for the
I2C interface. It receives device address, operation code,
wiper register address and data from an I2C external master
device at the rising edge of the serial clock SCL, and it shifts
out data after each falling edge of the serial clock SCL.
Equivalent Circuit
RTOTAL
RL
RH
CW
CH
CL
SDA requires an external pull-up resistor, since it’s an open
drain output.
Serial Clock (SCL)
This input is the serial clock of the I2C serial interface.
RW
Pin Descriptions
Potentiometer Pins
RH AND RL
The high (RH) and low (RL) terminals of the ISL23711 are
equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of RL and RH references the
relative position of the terminal in relation to wiper movement
direction selected by the I2C serial input and not the voltage
potential on the terminal.
6
Device Address (A1-A0)
The Address inputs are used to set the least significant 2 bits
of the 7-bit I2C interface slave address. A match in the slave
address serial data stream must be made with the Address
input pins in order to initiate communication with the
ISL23711. A maximum of 4 ISL23711 devices may occupy
the I2C serial bus.
Principles of Operation
The ISL23711 is an integrated circuit incorporating one DCP
with It’s associated register, and an I2C serial interface
providing direct communication between a host and the
potentiometer and memory. The resistor array is comprised
FN6127.0
August 16, 2005
ISL23711
of 127 individual resistors connected in series. At either end
of the array and between each resistor is an electronic
switch that transfers the potential at that point to the wiper.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin is connected to
intermediate nodes, and is equivalent to the wiper terminal
of a mechanical potentiometer. The position of the wiper
terminal is controlled by a 7-bit volatile Wiper Register (WR).
When the WR contains all zeroes (00h), the wiper terminal
(RW) is closest to its “Low” terminal (RL). When the WR
contains all ones (7Fh), the wiper terminal (RW) is closest to
its “High” terminal (RH). As the value of the WR increases
from all zeroes (0 decimal) to all ones (127 decimal), the
wiper moves monotonically from the position closest to RL to
the position closest to RH. At the same time, the resistance
between RW and RL increases monotonically, while the
resistance between RH and RW decreases monotonically.
While the ISL23711 is being powered up, the WR is reset to
20h (64 decimal), which locates the RW at the center
between RL and RH.
indicating START and STOP conditions (See Figure 1). On
power-up of the ISL23711 the SDA pin is in the input mode.
All I2C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH.
The ISL23711 continuously monitors the SDA and SCL lines for
the START condition and does not respond to any command
until this condition is met (See Figure 1).
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 1). A STOP condition at the end of
a read operation, or at the end of a write operation to volatile
bytes only places the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 2).
The ISL23711 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL23711 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present
at pins A1, and A0. The LSB is in the Read/Write bit. Its
value is “1” for a Read operation, and “0” for a Write
operation. (See Table 1.)
TABLE 1. IDENTIFICATION BYTE FORMAT
Logic values at pins A1, and A0 respectively
The WR can be read or written directly using the I2C serial
interface as described in the following sections.
0
Memory Description
• A read operation to address 0 outputs the value of the
volatile WR.
1
0
(MSB)
1
0
A1
A0
R/W
(LSB)
• A write operation to address 0 only writes to the volatile WR.
Write Operation
I2C Serial Interface
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL23711 responds with an ACK.
The ISL23711 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL23711
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
7
Read Operation
A Read operation is initiated by a master using the following
sequence: a START, the Identification byte (slave address)
with the R/W bit set to “1”. At the moment of the first
acknowledge by the ISL23711 (slave device), the mastertransmitter becomes a master receiver and receives the data
byte from the slave-transmitter.The Master receives the data
byte and issues a non-acknowledge (SDA is HIGH), then a
STOP to terminate the read operation. Since the ISL 23711
has just one WR, it will transmit only one byte (see Figure 4).
FN6127.0
August 16, 2005
ISL23711
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 1. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
0 1 0 1 0 A1 A0 0
0 0 0 0 0 0 0 0
SIGNALS FROM
THE ISL23711
A
C
K
A
C
K
S
T
O
P
DATA
BYTE
A
C
K
FIGURE 3. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W=1
SIGNAL AT SDA
SIGNALS FROM
THE SLAVE
S
T
O
P
0 1 0 1 0 A1 A0 1
A
C
K
DATA BYTE READ
BY MASTER
FIGURE 4. READ SEQUENCE
8
FN6127.0
August 16, 2005
ISL23711
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X 
0.25
(0.010)
R1
R
GAUGE
PLANE
SEATING
PLANE -CA
4X 
A2
A1
b
-H-
0.10 (0.004)
L
SEATING
PLANE
C
D
0.20 (0.008)
MAX
MIN
MAX
NOTES
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.007
0.011
0.18
0.27
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.020 BSC
C
a
CL
E1
0.20 (0.008)
C D
0.50 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
C
SIDE VIEW
MIN
A
L1
-A-
e
SYMBOL
e
L1
MILLIMETERS
0.95 REF
10
R
0.003
R1
-
10
-
0.07
0.003
-

5o
15o

0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
-B-
Rev. 0 12/02
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B -
to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN6127.0
August 16, 2005
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