an9537

Operation of the HC5513, HC5526 Evaluation
Board (HC5513EVAL, HC5526EVAL)
TM
Application Note
September 2000
AN9537.3
Features
AGND and BGND must be connected to a common ground,
with a potential difference not exceeding ±100mV.
• Includes the Ringing Relay
• Toggle Switch Programming for Logic States
HC5513/26EVAL Board SLIC Controls
• Convenient Monitoring of DET via LED or Banana Jack
Output
• Provides Easy Interface of Transhybrid Circuit Using Off
Board CODECs Internal Op Amp
The design of the HC5513/26EVAL board incorporates five
SPDT switches. Four of the switches control the functional state
of the HC5513/26 SLIC and the fifth controls the DET output.
Applications
Mode Control Switches
• Solid State Line Interface for Digital and Analog Telephone
Line Cards
The four switches labeled E0, E1, C1 and C2 are used to set
the operational mode of the SLIC. Each switch is a Single
Pole Double Throw (SPDT) switch.
Functional Description
The two inputs labeled E0 and E1 are enable pins. The two
pins labeled C1 and C2 are used to select 1 of 4 operating
states of the SLIC. Refer to the HC5513/26 Subscriber Line
Interface Circuit electrical data sheet for a full description of
the functionality of each pin.
The HC5513/26EVAL Subscriber Line Interface Circuit (SLIC)
evaluation board has provisions for full evaluation of the voice
and DC feeding characteristics of the HC5513 and the
HC5526 line interface circuit including the ringing function.
DET Select Switch
SLIC functional control is provided using the toggle switches
E0, E1, C1 and C2. Table 2 lists the states of the SLIC,
active detector and DET output. DET is available at both a
banana jack for monitoring with test instrumentation as well
as an LED for visual verification.
A switch is provided on the evaluation board to direct the
DET signal to one of two outputs. With the switch positioned
to the right, DET will illuminate the LED, when positioned to
the left, DET may be monitored at the banana jack using an
oscilloscope.
Applying Power to the HC5513/26EVAL
Power Supply Connections
Verifying the HC5513/26EVAL Operation
The HC5513/26EVAL requires three external power supplies
for operation. The supply voltages are labeled on the
HC5513/26EVAL as VCC +5V, VEE -5V and VBAT. The limits
for all supply voltages are provided in Table 1. The table also
includes the typical current of each supply when the SLIC is
in the Active mode and terminated with a 600Ω load.
The operation of the HC5513/26EVAL and sample part can
be verified by performing five tests. The first four tests
require a 600Ω load, an AC voltmeter and an oscilloscope.
The last test requires a telephone and a battery backed AC
source. All of the tests require three external supplies, one
each for VCC, VEE and VBAT.
Verify that the sample HC5513/26 included with the
evaluation board is oriented in its socket correctly. Correct
orientation is with pin 1 pointing towards tip and ring.
TABLE 1. POWER SUPPLY INFORMATION
SUPPLY
TYP (V)
TYP (mA)
VCC +5V
+5
11
VEE -5V
-5
1
VBAT, RSG is Open Circuit
-28
27
VBAT, RSG is 21.4kΩ
-48
30
Application Tip: When terminating tip and ring on the
HC5513/26EVAL it is handy to assemble terminators using a
Pomona MDP dual banana plug connector as the
terminating resistor receptacle. Refer to Figure 1 for details
GND
Ground Connections
The HC5513/26EVAL has two separate grounds designated as
AGND and BGND. AGND is the analog ground reference for
the SLIC. BGND is the battery ground reference, and is to be
connected to zero potential. All loop current and longitudinal
current flow from this ground. For proper SLIC operation,
4-1
1-888-INTERSIL or 321-724-7143
A
B
FIGURE 1. TERMINATION ADAPTER
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Intersil and Design is a trademark of Intersil Corporation.
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Copyright
© Intersil Corporation 2000
Application Note 9537
Using the termination shown in Figure 1 provides an
unobtrusive technique for terminating tip and ring while still
providing access to both signals using the banana jack
feature of the MDP connector. Posts are also available that
fit into holes A and B, providing a solderable connection for
the terminating resistor.
Power Supply Current Verification
A quick check of evaluation board and the HC5513/26
sample is to measure the currents of each supply voltage.
The readings should be similar to the values listed in Table 1.
The measurements can be made using a series ammeter on
each supply, or power supplies with current displays.
SETUP
1.
2.
3.
4.
5.
6.
Connect the power supplies to the HC5513/26EVAL.
Set VBAT to -48V.
Connect AGND and BNGD to common ground point.
Connect RRX pin to common ground point.
Terminate HC5513/26 SLIC with 600Ω load.
Set the mode switches to E0 = 0, E1 = 1, C1 = 0, C2 = 1.
DISCUSSION
Once setup is complete, apply power to the
HC5513/26EVAL and verify the supply currents listed in
Table 1. Note that special power supply sequencing is not
required for the HC5513/26.
Active Mode Verification
This test will verify that the HC5513/26EVAL can
successfully set the HC5513/26 SLIC to Active Mode and
that Switch Hook Detect causes DET to illuminate the LED.
SETUP
1.
2.
3.
4.
5.
6.
7.
Connect the power supplies to the HC5513/26EVAL.
Set VBAT to -48V.
Connect AGND and BNGD to common ground point.
Connect RRX pin to common ground point.
Terminate HC5513/26 SLIC with 600Ω load.
Set the mode switches to E0 = 0, E1 = 1, C1 = 0, C2 = 1.
Position the DET select switch to the right.
DISCUSSION
When power is applied to the HC5513/26EVAL, loop current
will flow from tip to ring and the LED will illuminate. If the LED
does not illuminate, verify the mode control switch settings.
Once the LED illuminates, remove the 600Ω termination. This
will introduce an open circuit across tip and ring, preventing
the flow of loop current and turning off the LED.
VERIFICATION
1. LED is on when tip and ring are terminated with 600Ω.
2. LED is off when tip and ring are open circuit.
4-2
Standby Mode Verification
This test will verify that the HC5513/26EVAL can
successfully set the HC5513/26 SLIC to Standby Mode and
that DET can be monitored using the banana jack interface.
SETUP
1.
2.
3.
4.
5.
6.
7.
8.
9.
Connect the power supplies to the HC5513/26EVAL.
Set VBAT to -48V.
Connect AGND and BNGD to common ground point.
Connect RRX pin to common ground point.
Terminate HC5513/26 SLIC with 600Ω load.
Set the mode switches to E0 = 0, E1 = 1, C1 = 1, C2 = 1.
Position the DET select switch to the left.
Connect an oscilloscope or DC voltmeter to the DET jack.
Monitor the VBAT supply current.
DISCUSSION
When power is applied to the HC5513/26EVAL loop current
will flow from tip to ring and the DET signal will be near zero
volts. Disconnecting the 600Ω termination will prevent the
flow of loop current, and cause DET to be pulled to VCC rail.
In Standby Mode, the VBAT current should be approximately
16.4mA with the 600Ω termination and 0.8mA without the
600Ω termination.
VERIFICATION
1.
2.
3.
4.
DET is near 0V when terminated with 600Ω.
DET is near VCC rail when not terminated with 600Ω.
VBAT current is near 16.4mA when terminated.
VBAT current is near 0.8mA when not terminated.
SLIC Gain Verification
This test will verify that HC5513/26 SLIC is operating
properly and that the SLIC is exhibiting unity gain. Unity gain
will only exist if the SLIC is properly terminated with 600Ω.
SETUP
1.
2.
3.
4.
5.
6.
7.
8.
Connect the power supplies to the HC5513/26EVAL.
Set VBAT to -48V.
Connect AGND and BNGD to common ground point.
Terminate HC5513/26 SLIC with 600Ω load.
Set the mode switches to E0 = 0, E1 = 1, C1 = 0, C2 = 1.
Connect a sine wave generator to the RRX input.
Set the generator for 0.775VRMS and 1kHz.
Connect an AC voltmeter across tip and ring.
DISCUSSION
When terminated with 600Ω, the SLIC will exhibit unity gain
from the RRX input pin to across tip and ring. The unity gain
results from the matched impedance that the 600Ω
termination represents to the internally synthesized 600Ω of
the SLIC. When an open circuit exists, a mismatch occurs
and the gain of the SLIC will double.
Application Note 9537
Two-Wire Side, Tip and Ring
VERIFICATION
1. Tip to ring AC voltage of 0.775VRMS when terminated.
2. Tip to ring AC voltage of 1.55VRMS when not terminated.
Relay
Allows injection of ringing signal.
PTC
Provides thermal protection for relay to ground path
during extended periods of use. The PTC is not provided
with HC5513/26EVAL board.
RF1,
RF2
Feed resistors that limit the current into the tip and ring
inputs of the HC5513/26 SLIC.
D1, D4
Provide transient protection on the tip and ring inputs.
CTC,
CRC
Provide immunity against high frequency noise on tip
and ring respectively.
Ring Trip Detector Verification
This test will verify the ringing function of the
HC5513/26EVAL. A telephone and an AC signal source are
the only additional hardware required to complete the test.
SETUP
1.
2.
3.
4.
5.
6.
7.
Connect the power supplies to the HC5513/26EVAL.
Set VBAT to -28V.
Connect AGND and BNGD to common ground point.
Connect RRX pin to common ground point.
Set the mode switches to E0 = 0, E1 = 1, C1 = 1, C2 = 0.
Connect the telephone across tip and ring.
Connect battery backed AC source to RINGING (VBAT +
90VRMS) banana jack.
8. Position DET select switch to the right (for LED).
DISCUSSION
The 600Ω termination is not necessary for this test since the
phone provides this nominal impedance when off-hook.
Setting the mode switches as shown above will cause the
RINGRLY pin of the HC5513/26 SLIC to energize the relay
that is on the evaluation board. The DT and DR comparator
inputs will sense the flow of DC loop current, causing the
Ring Trip comparator to sense when the phone is either onhook or off-hook. Refer to the HC5513/26 Subscriber Line
Interface Circuit electrical data sheet for a full description of
the functionality of the Ring Trip Detector.
VERIFICATION
1.
2.
3.
4.
Phone starts ringing when power applied to test setup.
While ringing and on-hook, DET LED is not illuminated.
While ringing, going off-hook will illuminate the LED.
CAUTION: Short time durations of off-hook should be
maintained to protect RRT. In systems, the ring relay is
software controlled to turn off milliseconds after off-hook
is detected hence limiting power dissipated in RRT.
5. When phone is returned to on-hook, LED will turn off.
6. Configure SLIC in Active mode to stop phone from ringing.
Set mode switches to E0 = 0, E1 = 1, C1 = 0, C2 = 1.
Passive Components
The HC5513/26EVAL design incorporates all of the external
components necessary for using the HC5513/26 SLIC in
normal applications. A brief description of each component
is provided below. The components will be grouped by
function to provide further insight to the operation of the
HC5513/26EVAL board.
The Two-Wire Side components are typical telephony values.
Design equations are not used for these components.
Ring Trip Detector
R1, R2
Generate a bias voltage from VBAT to drive the RD pin.
R3, R4,
RRT
Combine to sense off-hook condition and drive the RT pin.
CRT
Provides attenuation of the ring signal for stability of DT pin.
The component values for the Ring Trip detector circuit do not
require design equations. For information concerning the
functionality of this supervisory function refer to the
“Supervisory Function” section of the HC5513/26 data sheet.
Loop Current Detector
RD
Sets the loop current detect threshold for the HC5513/26
internal comparator function.
The value of RD programs the loop current detect threshold
for the HC5513/26 SLIC. Since the internal comparator has
hysteresis, there are two equations that apply to the value of
RD. One equation is for on-hook to off-hook threshold and
the other is for off-hook to on-hook threshold. The equations
for each condition are as follows:
On-Hook to Off-Hook Threshold
465
R D = ---------------------------------------------------------------------I ( ON-HOOK TO OFF-HOOK )
Off-Hook to On-Hook Threshold
375
R D = ------------------------------------------------------------------------I ( OFF-HOOK TO ON-HOOK )
For details concerning the design equations refer to the
“Supervisory Function” section of the HC5513/26 data
sheet. As delivered, the HC5513/26EVAL is configured for a
loop current detect level of 11.9mA for on-hook to off-hook
and 9.6mA for off-hook to on-hook.
Saturation Guard Resistor
RSG
Sets the saturation guard for the HC5513/26
SLIC.
When operating in systems with a -28V battery, RSG needs to
be an open circuit. When operating in systems with a -48V
battery, RSG needs to be 21.4kΩ as per the following equation:
4-3
Application Note 9537
5
5 • 10
R SG = -------------------------------------------------------------------------------------------------------------------------------------------------( R DC1 + R DC2 )

( V BAT – V MARGIN ) ×  1 + ------------------------------------------- – 16.66V
600 • R L


For details concerning the design equations refer to the
“Constant Loop Current (DC) Path” section of the
HC5513/26 data sheet. As delivered, the HC5513/26EVAL is
configured for a saturation guard of 4V on both the tip side
and ring side, resulting in a VMARGIN of 8V for VBAT = -48V
(on hook R2 = ∞.
Four-Wire Side, SLIC Impedance Matching
RT
Sets the synthesized impedance across the tip and ring
terminals.
RRX
Performs a voltage to current conversion of the receive
signal. Selected to maintain unity gain from 4-wire to
2-wire side when SLIC is terminated with 600Ω .
The values of RT and RRX have been selected for a 600Ω
system. These values can be modified for different
impedances. Also, complex impedance matching is possible
using these components. For information on impedance
matching of the SLIC, refer to the “(AC) 2-Wire Impedance”
section of the HC5513/26 data sheet.
Constant Feed Current Programming
RDC1,
RDC2
Set the constant feed current that flows from tip to ring
when a DC path is present during off-hook conditions.
Resistance is split to allow capacitor for filtering (CDC).
CDC
Filter capacitor to attenuate high frequency noise that is
fed back from tip and ring.
The constant feed current is programmed using the sum of
RDC1 and RDC2. The design equation used to set the loop
current is shown below.
2.5V
I L = -------------------------------------- × 1000
R DC1 + R DC2
For details concerning the design equations for loop current
as well as the selection of CDC refer to the “Constant Loop
Current (DC) Path” section of the HC5513/26 data sheet. As
delivered, the constant feed current is set at 30mA.
Transhybrid Balance
RTX, RB Used as part of transhybrid balance circuitry that is
located off board.
Transhybrid balance is fully discussed in the “Transhybrid
Circuit” section of the HC5513/26 data sheet. As delivered,
the HC5513/26EVAL does not include these components.
HC5513/26 SLIC Operating States Logic
Truth Table
The logic truth table for controlling the HC5513/26 SLIC using
the HC5513EVAL is provided in Table 2. The SLIC has four
operating states. The states are Open Circuit, Active, Ringing
and Standby. Each state, except Open Circuit, has options
available selecting the supervisory signal that drives the DET
pin. The supervisory signals are Ground Key Detect.
TABLE 2. LOGIC TRUTH TABLE
E0
E1
C1
C2
0
0
0
0
Open Circuit
SLIC OPERATING STATE
No Active Detector
ACTIVE DETECTOR
Logic Level High
DET OUTPUT
0
0
0
1
Active
Ground Key Detector
Ground Key Status
0
0
1
0
Ringing
No Active Detector
Logic Level High
0
0
1
1
Standby
Ground Key Detector
Ground Key Status
0
1
0
0
Open Circuit
No Active Detector
Logic Level High
0
1
0
1
Active
Loop Current Detector
Loop Current Status
0
1
1
0
Ringing
Ring Trip Detector
Ring Trip Status
0
1
1
1
Standby
Loop Current Detector
Loop Current Status
1
0
0
0
Open Circuit
No Active Detector
1
0
0
1
Active
Ground Key Detector
1
0
1
0
Ringing
No Active Detector
1
0
1
1
Standby
Ground Key Detector
Logic Level High
1
1
0
0
Open Circuit
No Active Detector
1
1
0
1
Active
Loop Current Detector
1
1
1
0
Ringing
Ring Trip Detector
1
1
1
1
Standby
Loop Current Detector
4-4
Application Note 9537
TABLE 3. HC5513/26EVAL EVALUATION BOARD PARTS LIST
COMPONENT
VALUE
TOLERANCE
RATING
U1 - SLIC
HC5513/26
N/A
N/A
RF1, RF2
Short
N/A
1/4W
R1, R3
200kΩ
5%
1/4W
R2
910kΩ
5%
1/4W
CDC
1.5µF
20%
10V
R4
1.2MΩ
5%
1/4W
CHP
10nF
20%
100V
CRT
0.39µF
20%
100V
2200pF
20%
100V
RB
COMPONENT
VALUE
RRT
Not Installed
Reference data sheet for calculation
RSG, VBAT = -48V
RDC1, RDC2
TOLERANCE
RATING
150Ω
5%
2W
21.4kΩ
1%
1/4W
41.2kΩ
5%
1/4W
RD
39kΩ
5%
1/4W
CTC, CRC
RFB
20.0kΩ
1%
1/4W
D 1 - D4
Diode with Given Rating
RRX
300kΩ
1%
1/4W
D5
1N914
RT
600kΩ
1%
1/4W
PTC
Shorted
RTX
20kΩ
1%
1/4W
KR
RLED
500Ω
10%
1/4W
Textool Socket
100V, 3A
N/A
N/A
N/A
N/A
2C Contacts, 12V Coil
N/A
228-5523
N/A
HC5513/26EVAL Evaluation Board Schematic Diagram
VBAT
BGND
CRT
RRT
+5V
-5V
NOTE 2
R1
R3
21 HPR
U1
+
OUT VTX
HPT 20
R2
CODEC
RTX
RF1
TIP
22 RD
VTX 19
23 DT
VEE 18
25 DR
RSN 16
27 TIPX
U2
RTX
CHP
RD
R4
RFB
AGND
RT
RB
(NOTE 3)
RRX
IN
RRX
CDC
RDC1
AGND 15
RF2
RING
RELAY
D2
D1
CTC CRC
D3
D4
NOTE
1
PTC
28 RINGX
RDC2
2 BGND
C1 13
4 VCC
C2 12
5 RINGRLY
RINGING
(VBAT + 90VRMS)
RSG
BGND
VBAT
RDC 14
DET
DET 11
6 VBAT
E0 9
7 RSG
E1 8
SPST
10kΩ
LED
LED ON
DET LOW
-5V
SPST
SPST
SPST
SPST
CENTER CENTER CENTER CENTER
OFF
OFF
OFF
OFF
E0
E1
C1
C2
AGND +5V
NOTES:
1. The anodes of D3 and D4 may be connected directly to the VBAT supply if the application is exposed to only low energy transients. For harsher
environments it is recommended that the anodes of D3 and D4 be shorted to ground through a transzorb or surgector (SGT06U13).
2. To meet the specified 25dB 2-wire return loss at 200Hz, CHP needs to be 20nF, 20%, 100V.
3. RB is required for transhybrid balance when using op amps internal to CODEC. RB = RTX .
FIGURE 2.
4-5
Application Note 9537
HC5513/26EVAL Evaluation Board Layout
FIGURE 3. SILK SCREEN
FIGURE 4. TOP SIDE
4-6
Application Note 9537
HC5513/26EVAL Evaluation Board Layout
(Continued)
FIGURE 5. BOTTOM SIDE
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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4-7
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