DATASHEET

SIGNS
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December 1, 2005
contact Data
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1-88
ISL6565A, ISL6565B
FN9135.4
Multi-Phase PWM Controller with
Precision rDS(ON) or DCR Current Sensing
for VR10.X Application
Features
The ISL6565A, ISL6565B controls microprocessor core
voltage regulation by driving up to 3 synchronous-rectified
buck channels in parallel. Multi-phase buck converter
architecture uses interleaved timing to multiply channel
ripple frequency and reduce input and output ripple currents.
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- 0.5% System Accuracy Over Temperature and Life
- Adjustable Reference-Voltage Offset
• Multi-Phase Power Conversion
- 2 or 3 Phase Operation
• Precision rDS(ON) or DCR Current Sensing
- Integrated Programmable Temperature Compensation
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Low-Cost, Lossless Current Sensing
The difference between the ISL6565A and the ISL6565B is
that the ISL6565A utilizes rDS(ON) current sensing, while the
ISL6565B utilizes DCR current sensing for each phase.
These cost and space saving methods of current sensing
are used for adaptive voltage positioning (droop), channelcurrent balancing, and overcurrent protection. To ensure the
accuracy of droop, a programmable internal temperature
compensation function is implemented to compensate the
effect of rDS(ON) and DCR temperature sensitivity.
• Input Voltage: 12V or 5V Bias
• Microprocessor Voltage Identification Input
- Dynamic VID® Technology
- 6-Bit VID Input
- 0.8375V to 1.600V in 12.5mV Steps
A unity gain, differential amplifier is provided for remote
voltage sensing. Any potential difference between remote
and local grounds is eliminated using the remote-sense
amplifier. The precision threshold-sensitive enable input is
available to accurately coordinate the start up of the
ISL6565A, ISL6565B with Intersil MOSFET driver ICs.
Dynamic-VID™ technology allows seamless on-the-fly VID
changes. The offset pin allows accurate voltage offset
settings that are independent of VID setting.
• Threshold Enable Function for Precision Sequencing
• Overcurrent Protection
• Overvoltage Protection
• Digital Soft-Start
• Operation Frequency up to 1.5MHz per Phase
• QFN Package
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package Footprint, which Improves
PCB Efficiency and Has a Thinner Profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER
ISL6565ACB
PART MARKING
ISL6565ACB
TEMP. RANGE (°C)
0 to 105
PACKAGE
PKG. DWG. #
28 Ld SOIC
M28.3
ISL6565ACBZ (Note)
ISL6565ACBZ
0 to 105
28 Ld SOIC (Pb-free)
M28.3
ISL6565ACR
ISL6565ACR
0 to 105
28 Ld 5x5 QFN
L28.5x5
ISL6565ACRZ (Note)
ISL6565ACRZ
0 to 105
28 Ld 5x5 QFN (Pb-free)
L28.5x5
ISL6565ACV
ISL6565ACV
0 to 105
28 Ld TSSOP
M28.173
ISL6565ACVZ (Note)
ISL6565ACVZ
0 to 105
28 Ld TSSOP (Pb-free)
M28.173
ISL6565BCB
ISL6565BCB
0 to 105
28 Ld SOIC
M28.3
ISL6565BCBZ (Note)
ISL6565BCBZ
0 to 105
28 Ld SOIC (Pb-free)
M28.3
ISL6565BCR
ISL6565BCR
0 to 105
28 Ld 5x5 QFN
L28.5x5
ISL6565BCRZ (Note)
ISL6565BCRZ
0 to 105
28 Ld 5x5 QFN (Pb-free)
L28.5x5
ISL6565BCV
ISL6565BCV
0 to 105
28 Ld TSSOP
M28.173
ISL6565BCVZ (Note)
ISL6565BCVZ
0 to 105
28 Ld TSSOP (Pb-free)
M28.173
*Add "-T" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003-2005. All Rights Reserved. Dynamic VID® is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
ISL6565A, ISL6565B
Pinouts
VID3
4
25 ENLL
VID2
5
24 NC
VID1
6
23 ISEN2
VID0
7
22 PWM2
VID12.5
8
21 PWM1
OFS
9
20 ISEN1
TCOMP 10
REF 11
28
27
26
25
24
23
22
21 NC
VID2
2
20 ISEN2
VID1
3
19 PWM2
VID0
4
18 PWM1
19 ISEN3
VID12.5
5
17 ISEN1
18 PWM3
OFS
6
16 ISEN3
TCOMP
7
15 PWM3
9
11
12
13
14
OVP
1
28 FS
PGOOD
2
27 EN
PGOOD
OVP
FS
EN
VCC
ENLL
ISL6565BCR (QFN)
TOP VIEW
VID4
ISL6565BCB (SOIC), ISL6565BCV (TSSOP)
TOP VIEW
10
GND
8
RGND
15 VSEN
VSEN
VDIFF 14
VDIFF
16 RGND
COMP
COMP 13
FB
1
REF
VID3
17 GND
FB 12
ENLL
26 VCC
VCC
3
EN
27 EN
VID4
FS
28 FS
2
OVP
1
PGOOD
OVP
PGOOD
ISL6565ACR (QFN)
TOP VIEW
VID4
ISL6565ACB (SOIC), ISL6565ACV (TSSOP)
TOP VIEW
VID4
3
26 VCC
28
27
26
25
24
23
22
VID3
4
25 ENLL
VID2
5
24 ICOMMON
VID1
6
23 ISEN2
VID3
1
21
ICOMMON
VID2
2
20
ISEN2
VID0
4
18
PWM1
OFS
9
20 ISEN1
TCOMP 10
19 ISEN3
VID12.5
5
17
ISEN1
REF 11
18 PWM3
OFS
6
16
ISEN3
TCOMP
7
15
PWM3
17 GND
FB 12
COMP 13
16 RGND
VDIFF 14
15 VSEN
2
8
9
10
11
12
13
14
GND
PWM2
RGND
19
VSEN
3
VDIFF
VID1
21 PWM1
COMP
22 PWM2
8
FB
7
REF
VID0
VID12.5
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
ISL6565A Block Diagram
VDIFF
PGOOD
RGND
OVP
OVP R
LATCH
S
x1
VSEN
ENLL
VCC
SHUNT
POWER-ON
REGULATOR
RESET
1.24V
EN
Q
SOFT-START
UVP
AND
FAULT LOGIC
CLOCK AND
SAWTOOTH
GENERATOR
OVP
FS
+200mV
PWM1
PWM

x 0.75
VID4
VID3
VID2
DYNAMIC
VID
VID1
D/A
PWM2
PWM

VID0
VID12.5
PWM3
PWM

REF
CHANNEL
DETECT
E/A
FB
CHANNEL
CURRENT
BALANCE
COMP
I_TRIP
OC
ISEN1

OFS
I_AVG
OFFSET
1
N

CHANNEL
CHANNEL
OCP
CURRENT
ISEN2
SENSE
ISEN3
TCOMP
TEMP
COMP
GND
3
NC
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
ISL6565B Block Diagram
VDIFF
PGOOD
RGND
OVP
OVP R
LATCH
S
x1
VSEN
ENLL
VCC
SHUNT
POWER-ON
REGULATOR
RESET
1.24V
EN
Q
SOFT-START
UVP
AND
FAULT LOGIC
CLOCK AND
SAWTOOTH
GENERATOR
OVP
FS
+200mV
PWM1
PWM

x 0.75
VID4
VID3
VID2
DYNAMIC
VID
VID1
D/A
PWM2
PWM

VID0
VID12.5

REF
PWM3
PWM
CHANNEL
DETECT
E/A
FB
CHANNEL
CURRENT
BALANCE
COMP
I_TRIP
OC
ISEN1

OFS
I_AVG
OFFSET
1
N

CHANNEL
CHANNEL
OCP
CURRENT
ISEN2
SENSE
ISEN3
TCOMP
TEMP
COMP
ICOMMON
GND
4
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
Typical Application - ISL6565A
+5V
VIN
VCC
EN
BOOT
UGATE
PHASE
+5V
ISL6605
PWM
LGATE
GND
COMP VCC
FB
VDIFF
VSEN
TCOMP
+5V
RGND
VIN
PGOOD
REF
OVP
VCC
ISL6565A
VID4
VID3
VID2
VID1
VID0
VID12.5
PWM1
ISEN1
EN
PWM2
ISEN2
PWM
BOOT
UGATE
PHASE
ISL6605
LGATE
GND
PWM3
ISEN3
OFS
µP
LOAD
NC
FS
GND ENLL
+5V
EN
RT
VIN
+12V
VCC
VID_PGOOD
EN
BOOT
UGATE
PHASE
ISL6605
PWM
LGATE
GND
5
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
Typical Application - ISL6565B
+5V
VIN
VCC
EN
BOOT
UGATE
PHASE
ISL6605
+5V
PWM
LGATE
GND
COMP VCC
FB
VDIFF
TCOMP
VSEN
+5V
RGND
VIN
PGOOD
REF
OVP
VCC
ISL6565B
VID4
VID3
EN
PWM2
ISEN2
PWM
PHASE
ISL6605
VID2
VID1
VID0
LGATE
GND
PWM3
ISEN3
VID12.5
OFS
PWM1
ISEN1
BOOT
UGATE
µP
LOAD
ICOMMON
FS
GND ENLL
+5V
EN
RT
VIN
+12V
VCC
VID_PGOOD
EN
BOOT
UGATE
PHASE
ISL6605
PWM
LGATE
GND
6
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V
Input, Output, or I/O Voltage (except OVP) . .GND -0.3V to VCC + 0.3V
OVP Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
ESD (Human body model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4kV
ESD (Machine model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V
ESD (Charged device model) . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV
Thermal Resistance
Operating Conditions
JA (°C/W)
JC (°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
62
N/A
QFN Package (Notes 2, 3). . . . . . . . . .
33
3.5
TSSOP Package (Note 1) . . . . . . . . . .
85
N/A
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Supply Voltage, VCC (5V bias mode) . . . . . . . . . . . . . . . . +5V ±5%
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VCC = 5V or ICC < 25mA (Note 4), TJ = 0°C to 105°C.
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC SUPPLY CURRENT
Nominal Supply
VCC = 5VDC; EN = 5VDC; RT = 100k
ISEN1 = ISEN2 = ISEN3 = -70A
-
14
18
mA
Shutdown Supply
VCC = 5VDC; EN = 0VDC; RT = 100k
-
10
14
mA
SHUNT REGULATOR
VCC Voltage
VCC tied to 12VDC thru 300 resistor, RT = 100k
5.6
5.9
6.2
V
VCC Sink Current
VCC tied to 12VDC thru 300 resistor, RT = 100k
-
-
25
mA
VCC Rising
4.2
4.31
4.50
V
VCC Falling
3.7
3.82
4.00
V
EN Rising
1.29
1.31
1.33
V
Hysteresis
-
150
-
mV
Fault Reset
1.10
1.14
1.18
V
POWER-ON RESET AND ENABLE
POR Threshold
ENABLE Threshold
ENLL Input Logic Low Level
-
-
0.4
V
ENLL input Logic High Level
0.8
-
-
V
-
-
1
A
System Accuracy (VID = 1.2V-1.6V, TJ = 0°C to 85°C)
-0.5
-
0.5
%VID
System Accuracy (VID = 0.8375V-1.1875V TJ = 25°C)
-0.7
-
0.7
%VID
System Accuracy (VID = 0.8375V-1.1875V, TJ = 0°C to 85°C)
-0.8
-
0.8
%VID
VID Pull Up
-65
-50
-35
A
VID Input Low Level
-
-
0.4
V
VID Input High Level
0.8
-
-
V
-200
-
200
A
-50
-
50
A
ENLL Leakage Current
ENLL = 5V
REFERENCE VOLTAGE AND DAC
DAC Source/Sink Current
VID = 010100
REF Source/Sink Current
PIN-ADJUSTABLE OFFSET
Voltage at OFS Pin
7
Offset resistor connected to ground
485
500
515
mV
Voltage below VCC, offset resistor connected to VCC
1.97
2.03
2.09
V
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
Electrical Specifications
Operating Conditions: VCC = 5V or ICC < 25mA (Note 4), TJ = 0°C to 105°C.
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR
Accuracy
RT = 100k
-10
-
10
%
0.08
-
1.5
MHz
Sawtooth Amplitude
-
1.5
-
V
Max Duty Cycle
-
66.7
-
%
-
80
-
dB
Adjustment Range
ERROR AMPLIFIER
Open-Loop Gain (Note 7)
RL = 10k to ground
Open-Loop Bandwidth (Note 7)
CL = 100pF, RL = 10k to ground
Slew Rate
CL = 100pF
-
18
-
MHz
4.5
6.0
7.5
V/s
Maximum Output Voltage
4.0
4.3
-
V
Output High Voltage @ 2mA
3.7
-
-
V
Output Low Voltage @ 2mA
-
-
1.35
V
-
20
-
MHz
REMOTE-SENSE AMPLIFIER
Bandwidth (Note 7)
Output High Current
VSEN - RGND = 2.5V
-500
-
500
A
Output High Current
VSEN - RGND = 0.6
-500
-
500
A
PWM OUTPUT
PWM Output Voltage LOW Threshold
Iload = ±500A
-
-
0.3
V
PWM Output Voltage HIGH Threshold
Iload = ±500A
4.3
-
-
V
10
15
20
A
-
2
-
A/V°C
74
81
91
A
95
110
130
A
-
-
0.4
V
74
76
%VID
TEMPERATURE COMPENSATION
Temperature Compensation Current @ 40°C and
Tcomp = 0.5V
Temperature Compensation Transconductance (Note 7)
SENSE CURRENT
Sensed Current Tolerance
ISEN1 = ISEN2 = ISEN3 = 80A, 0°C to 105°C
Overcurrent Trip Level
POWER GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
IPGOOD = 4mA
Undervoltage Offset From VID
VSEN Falling
72
Overvoltage Threshold
Voltage above VID, After Soft-Start (Note 6)
180
200
220
mV
-
1.63
-
V
1.7
1.8
1.87
V
Before Enable
VCC < POR Threshold
Overvoltage Reset Voltage
OVP Drive Voltage
VCC  POR Threshold, VSEN Falling
-
0.6
-
V
VCC < POR Threshold
-
1.5
-
V
IOVP = -100mA, VCC = 5V
-
1.9
-
V
1.4
-
-
V
Minimum VCC for OVP
NOTES:
4. When using the internal shunt regulator, VCC is clamped to 6.02V (max). Current must be limited to 25mA or less.
5. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
6. During soft-start, VDAC rises from 0 to VID. The overvoltage trip level is the higher of 1.7V and VDAC + 0.2V.
7. Parameter magnitude guaranteed by design. Not 100% tested.
8
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
Functional Pin Description
VCC - Supplies all the power necessary to operate the chip.
The controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the
voltage on this pin drops below the falling POR threshold.
Connect this pin directly to a +5V supply or through a series
300 resistor to a +12V supply.
GND - Bias and reference ground for the IC.
EN - This pin is a threshold-sensitive enable input for the
controller. Connecting the 12V supply to EN through an
appropriate resistor divider provides a means to synchronize
power-up of the controller and the MOSFET driver ICs.
When EN is driven above 1.31V, the ISL6565A, ISL6565B is
active depending on status of ENLL, the internal POR, and
pending fault states. Driving EN below 1.14V will clear all
fault states and prime the ISL6565A, ISL6565B to soft-start
when re-enabled.
ENLL - This pin is a logic-level enable input for the
controller. When asserted to a logic high, the ISL6565 is
active depending on status of EN, the internal POR, VID
inputs and pending fault states. Deasserting ENLL will clear
all fault states and prime the ISL6565A, ISL6565B to softstart when re-enabled.
FS - A resistor, placed from FS to ground, will set the
switching frequency. Refer to Equation 45 for proper resistor
calculation.
VID4, VID3, VID2, VID1, VID0, and VID12.5 - These are the
inputs to the internal DAC that provides the reference
voltage for output regulation. Connect these pins either to
open-drain outputs with or without external pull-up resistors
or to active-pull-up outputs. VID4-VID12.5 have 20A
internal pull-up current sources that diminish to zero as the
voltage rises above the logic-high level.
VDIFF, VSEN, and RGND - VSEN and RGND are inputs to
the precision differential remote-sense amplifier. This
amplifier converts the differential voltage of the remote
output to a single-ended voltage referenced to local ground.
VDIFF is the amplifier’s output and the input to the regulation
and protection circuitry. Connect VSEN and RGND to the
sense pins of the remote load.
FB and COMP - Inverting input and output of the error
amplifier respectively. FB is connected to VDIFF through a
resistor. A negative current, proportional to output current is
present on the FB pin. A properly sized resistor between
VDIFF and FB sets the load line (droop). The droop scale
factor is set by the ratio of the ISEN resistors and the lower
MOSFET rDS(ON) or inductor DCR. COMP is tied back to FB
through an external R-C network to compensate the
regulator.
9
REF - The REF input pin is the positive input of the Error
Amp. It is internally connected to the DAC output through a
1k resistor. A capacitor is used between the REF pin and
ground to smooth the voltage transition during Dynamic
VID™ operations.
TCOMP - Temperature compensation scaling input. A
resistor from this pin to ground sets the gain of the internal
thermal sense circuitry. The temperature sensed by the
controller is utilized to modify the droop current output to the
FB pin, adjusting for MOSFET rDS(ON) and Inductor DCR
variations with temperature.
PWM1, PWM2, PWM3 - Pulse-width modulation outputs.
Connect these pins to the PWM input pins of the Intersil
driver ICs. The number of active channels is determined by
the state of PWM3. Tie PWM3 to VCC to configure for
2-phase operation.
ISEN1, ISEN2, ISEN3, ICOMMON (ISL6565B only) These pins are used for sensing individual phase output
currents. The sensed current is used for channel balancing,
protection, and load line regulation. ISEN3 should be left
open for 2-phase operation.
For rDS(ON) current sensing using the ISL6565A, connect a
resistor between the ISEN1, ISEN2, and ISEN3 pins and
their respective phase node. This resistor sets a current
proportional to the current in the lower MOSFET during it’s
conduction interval.
For DCR sensing using the ISL6565B, connect a resistor
from VCORE to the ICOMMON pin. Then connect ISEN1,
ISEN2, and ISEN3 to the node between the RC sense
elements surrounding the inductor of their respective phase.
PGOOD - PGOOD is used as an indication of the end of
soft-start. It is an open-drain logic output that is low
impedance until the soft-start is completed. It will be pulled
low again once the undervoltage point is reached.
OFS - The OFS pin provides a means to program a DC
current for generating an offset voltage across the droop
resistor between FB and VDIFF. The offset current is
generated via an external resistor and precision internal
voltage references. The polarity of the offset is selected by
connecting the resistor to GND or VCC. For no offset, the
OFS pin should be left unconnected.
OVP - Overvoltage protection pin. This is an open drain
device, which can be externally configured with a resistor to
control an SCR to shut down the regulator.
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine the equation representing an
individual channel’s peak-to-peak inductor current.
Operation
Multi-Phase Power Conversion
Microprocessor load current profiles have changed to the
point that the advantages of multi-phase power conversion
are impossible to ignore. The technical challenges
associated with producing a single-phase converter that is
both cost-effective and thermally viable have forced a
change to the cost-saving approach of multi-phase. The
ISL6565A, ISL6565B controller helps simplify
implementation by integrating vital functions and requiring
minimal output components. The block diagrams on pages 3
and 4 provide top level views of multi-phase power
conversion using the ISL6565A and ISL6565B controllers.
IL1 + IL2 + IL3, 7A/DIV
IL3, 7A/DIV
PWM3, 5V/DIV
IL2, 7A/DIV
PWM2, 5V/DIV
IL1, 7A/DIV
PWM1, 5V/DIV
1s/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
Interleaving
The switching of each channel in a multi-phase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has
a combined ripple frequency three times greater than the
ripple frequency of any one phase. In addition, the peak-topeak amplitude of the combined inductor currents is reduced
in proportion to the number of phases (Equations 1 and 2).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle after the PWM pulse of the
previous phase. The peak-to-peak current for each phase is
about 7A, and the DC components of the inductor currents
combine to feed the load.
10
 V IN – V OUT  V OUT
I PP = ----------------------------------------------------L fS V
(EQ. 1)
IN
In Equation 1, VIN and VOUT are the input and output
voltages respectively, L is the single-channel inductor value,
and fS is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Outputvoltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
 V IN – N V OUT  V OUT
I C, PP = ----------------------------------------------------------L fS V
(EQ. 2)
IN
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9A
RMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
1s/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUTCAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
Figures 19 and 20 in the section entitled Input Capacitor
Selection can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution.
The sampled current, at the end of the tSAMPLE, is
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used for
current balance, load-line regulation, and overcurrent
protection.
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the
ISL6565A, ISL6565B is three. One switching cycle is defined
as the time between PWM1 pulse termination signals. The
pulse termination signal is the internally generated clock
signal that triggers the falling edge of PWM1. The cycle time
of the pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. Each cycle begins when the clock signal commands
PWM1 to go low. The PWM1 transition signals the channel-1
MOSFET driver to turn off the channel-1 upper MOSFET
and turn on the channel-1 synchronous MOSFET. In the
default channel configuration, the PWM2 pulse terminates
1/3 of a cycle after the PWM1 pulse. The PWM3 pulse
terminates 1/3 of a cycle after PWM2.
If PWM3 is connected to VCC, two channel operation is
selected and the PWM2 pulse terminates 1/2 of a cycle after
the PWM1 pulse terminates.
Once a PWM pulse transitions low, it is held low for a
minimum of 1/3 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
VCOMP, minus the current correction signal relative to the
sawtooth ramp as illustrated in Figure 6. When the modified
VCOMP voltage crosses the sawtooth ramp, the PWM output
transitions high. The MOSFET driver detects the change in
state of the PWM signal and turns off the synchronous
MOSFET and turns on the upper MOSFET. The PWM signal
will remain high until the pulse termination signal marks the
beginning of the next cycle by triggering the PWM signal low.
Current Sampling
During the forced off-time, following a PWM transition low,
the current-sense amplifier uses the ISEN inputs to
reproduce a signal proportional to the inductor current, IL.
No matter which current-sense method is employed, the
sense current (ISEN) is simply a scaled version of the
inductor current. The sample window opens exactly 1/6 of
the switching period, tSW, after the PWM transitions low. The
sample window then stays open for a fixed amount of time,
tSAMPLE, and is equal to 1/6 of the switching period, tSW as
illustrated in Figure 3.
t SW
1
t SAMPLE = ---------- = -----------------6
6  f SW
IL
PWM
ISEN
tSAMPLE
OLD SAMPLE
CURRENT
NEW SAMPLE CURRENT
SWITCHING PERIOD
TIME
FIGURE 3. SAMPLE AND HOLD TIMING
Current Sensing
The ISL6565A supports MOSFET rDS(ON) current sensing,
while the ISL6565B supports inductor DCR current sensing.
The internal circuitry, shown in Figures 4 and 5, represent
channel n of an N-channel converter. This circuitry is
repeated for each channel in the converter, but may not be
active depending on the status of the PWM3 pin, as
described in the PWM Operation section.
MOSFET rDS(ON) SENSING (ISL6565A ONLY)
The ISL6565A senses the channel load current by sampling
the voltage across the lower MOSFET rDS(ON), as shown in
Figure 4. A ground-referenced operational amplifier, internal
to the ISL6565A, is connected to the PHASE node through a
resistor, RISEN. The voltage across RISEN is equivalent to
the voltage drop across the rDS(ON) of the lower MOSFET
while it is conducting. The resulting current into the ISEN pin
is proportional to the channel current, IL. The ISEN current is
sampled and held as described in the Current Sampling
section. From Figure 4, the following equation for In is
derived where IL is the channel current.
r DS  ON 
I n = I L ---------------------R ISEN
(EQ. 4)
(EQ. 3)
11
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
In
r
DS  ON 
SEN = I L ------------------------R
ISEN
SAMPLE
&
HOLD
CHANNEL N
UPPER MOSFET
IL
VIN
I
ISEN(n)
-
RISEN
+
L
I
ISL6605
r
L DS  ON 
+
EXTERNAL CIRCUIT
Inductor windings have a characteristic distributed
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 5. The channel current
IL, flowing through the inductor, passes through the DCR.
Equation 5 shows the s-domain equivalent voltage, VL,
across the inductor.
(EQ. 5)
A simple R-C network across the inductor (R1 and C)
extracts the DCR voltage, as shown in Figure 5. The voltage
across the sense capacitor, VC, can be shown to be
proportional to the channel current IL, shown in Equation 6.
(EQ. 6)
In some cases it may be necessary to use a resistor divider
R-C network to sense the current through the inductor. This
can be accomplished by placing a second resistor, R2,
across the sense capacitor. In these cases the voltage
across the sense capacitor, VC, becomes proportional to the
channel current IL, and the resistor divider ratio, K.
sL
 ------------+ 1
 DCR

V C  s  = --------------------------------------------------------  K  DCR  I L
  R1  R2 

 s  ------------------------  C + 1
+
R
R


1
2
R2
K = --------------------R2 + R1
(EQ. 7)
(EQ. 8)
12
R2*
ISL6565B INTERNAL CIRCUIT
In
VC(s)
RISEN
+
INDUCTOR DCR SENSING (ISL6565B ONLY)
C
-
FIGURE 4. ISL6565A INTERNAL AND EXTERNAL CURRENTSENSING CIRCUITRY
VOUT
COUT
VC(s)
R1
PWM(n)
sL
 ------------+ 1
 DCR

V C  s  = --------------------------------------  DCR  I L
 s  R1  C + 1 
VL(s)
+
CHANNEL N
LOWER MOSFET
V L  s  = I L   s  L + DCR 
DCR
INDUCTOR
+
ISL6565A INTERNAL CIRCUIT
L
-
I
If the R-C network components are selected such that the
RC time constant matches the inductor L/DCR time
constant, then VC is equal to the voltage drop across the
DCR multiplied by the ratio of the resistor divider, K. If a
resistor divider is not being used, the value for K is 1.
-
VIN
SAMPLE
&
HOLD
ISEN(n)
+
ICOMMON
ISEN
*R2 is OPTIONAL
FIGURE 5. DCR SENSING CONFIGURATION
The capacitor voltage VC, is then replicated across the
sense resistor RISEN. The regulator should have only one
RISEN resistor connected from the VOUT plane to the
ICOMMON pin. The current through RISEN is proportional to
the inductor current. Equation 9 shows that the proportion
between the channel current and the sensed current (ISEN)
is driven by the value of the sense resistor chosen, the
resistor divider ratio, and the DCR of the inductor.
DCR
I n = K  I L  -----------------R ISEN
(EQ. 9)
Channel-Current Balance
The sampled currents, In, from each active channel are
summed together and divided by the number of active
channels. The resulting cycle average current, IAVG,
provides a measure of the total load-current demand on the
converter during each switching cycle. Channel-current
balance is achieved by comparing the sampled current of
each channel to the cycle average current, and making the
proper adjustment to each channel pulse width based on the
error. Intersil’s patented current-balance method is illustrated
in Figure 6, with error correction for channel 1 represented.
In the figure, the cycle average current combines with the
channel 1 sample, I1, to create an error signal IER.
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
The filtered error signal modifies the pulse width
commanded by VCOMP to correct any unbalance and force
IER toward zero. The same method for error signal
correction is applied to each active channel.
EXTERNAL CIRCUIT
R C CC
COMP
VID DAC
RTCOMP
+
VCOMP
+
-
FILTER
I3 *
IER
IAVG
-
+
FB
SAWTOOTH SIGNAL
f(s)
N
1k
REF
CREF
PWM1
-
ISL6565 INTERNAL CIRCUIT
RFB
+
VDROOP
-
+
-
VCOMP
ERROR AMPLIFIER
IAVG
VDIFF

I2
I1
NOTE: *CHANNEL 3 IS OPTIONAL.
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENTBALANCE ADJUSTMENT
Channel-current balance is essential in realizing the thermal
advantage of multi-phase operation. The heat generated in
conversion is dissipated over multiple devices and a large
area. The designer avoids the complexity of driving multiple
parallel MOSFETs, and the expense of using heat sinks and
non-standard magnetic materials.
Voltage Regulation
The integrating compensation network shown in Figure 7
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6565A, ISL6565B to include
the combined tolerances of each of these elements.
VOUT+
VOUT-
VSEN
+
RGND
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 7. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADUJUSTMENT
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID4
through VID12.5. The DAC decodes the 6-bit logic signal
(VID) into one of the discrete voltages shown in Table 1.
Each VID input offers a 20A pull-up to an internal 2.5V
source for use with open-drain outputs. The pull-up current
diminishes to zero above the logic threshold to protect
voltage-sensitive output devices. External pull-up resistors
can augment the pull-up current sources in case leakage
into the driving device is greater than 20A.
The output of the error amplifier, VCOMP, is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
voltage. The internal and external circuitry that controls
voltage regulation is illustrated in Figure 7.
The ISL6565 incorporates an internal differential remotesense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the controller ground reference point
resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the noninverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, VDIFF, is
connected to the inverting input of the error amplifier through
an external resistor.
13
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES (Continued)
VID4
VID3
VID2
VID1
VID0
VID12.5
VDAC
VID4
VID3
VID2
VID1
VID0
VID12.5
VDAC
0
1
0
1
0
0
0.8375V
1
0
1
1
0
1
1.3000V
0
1
0
0
1
1
0.8500V
1
0
1
1
0
0
1.3125V
0
1
0
0
1
0
0.8625V
1
0
1
0
1
1
1.3250V
0
1
0
0
0
1
0.8750V
1
0
1
0
1
0
1.3375V
0
1
0
0
0
0
0.8875V
1
0
1
0
0
1
1.3500V
0
0
1
1
1
1
0.9000V
1
0
1
0
0
0
1.3625V
0
0
1
1
1
0
0.9125V
1
0
0
1
1
1
1.3750V
0
0
1
1
0
1
0.9250V
1
0
0
1
1
0
1.3875V
0
0
1
1
0
0
0.9375V
1
0
0
1
0
1
1.4000V
0
0
1
0
1
1
0.9500V
1
0
0
1
0
0
1.4125V
0
0
1
0
1
0
0.9625V
1
0
0
0
1
1
1.4250V
0
0
1
0
0
1
0.975V0
1
0
0
0
1
0
1.4375V
0
0
1
0
0
0
0.9875V
1
0
0
0
0
1
1.4500V
0
0
0
1
1
1
1.0000V
1
0
0
0
0
0
1.4625V
0
0
0
1
1
0
1.0125V
0
1
1
1
1
1
1.4750V
0
0
0
1
0
1
1.0250v
0
1
1
1
1
0
1.4875V
0
0
0
1
0
0
1.0375V
0
1
1
1
0
1
1.5000V
0
0
0
0
1
1
1.0500V
0
1
1
1
0
0
1.5125V
0
0
0
0
1
0
1.0625V
0
1
1
0
1
1
1.5250V
0
0
0
0
0
1
1.0750V
0
1
1
0
1
0
1.5375V
0
0
0
0
0
0
1.0875V
0
1
1
0
0
1
1.5500V
1
1
1
1
1
1
OFF
0
1
1
0
0
0
1.5625V
1
1
1
1
1
0
OFF
0
1
0
1
1
1
1.5750V
1
1
1
1
0
1
1.1000V
0
1
0
1
1
0
1.5875V
1
1
1
1
0
0
1.1125V
0
1
0
1
0
1
1.600V
1
1
1
0
1
1
1.1250V
1
1
1
0
1
0
1.1375V
1
1
1
0
0
1
1.1500V
1
1
1
0
0
0
1.1625V
1
1
0
1
1
1
1.1750V
1
1
0
1
1
0
1.1875V
1
1
0
1
0
1
1.2000V
1
1
0
1
0
0
1.2125V
1
1
0
0
1
1
1.2250V
1
1
0
0
1
0
1.2475V
1
1
0
0
0
1
1.2500V
1
1
0
0
0
0
1.2625V
1
0
1
1
1
1
1.2750V
1
0
1
1
1
0
1.2875V
14
Load-Line Regulation
Some microprocessor manufacturers require a preciselycontrolled output impedance. This dependence of output
voltage on load current is often termed “droop” or “load line”
regulation.
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
As shown in Figure 7, a current proportional to the average
current in all active channels, IAVG, flows from FB through a
load-line regulation resistor, RFB. The resulting voltage drop
across RFB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as:
V DROOP = I AVG R FB
VDIFF
+
VOFS
-
RFB
VREF
E/A
FB
IOFS
(EQ. 10)
In most cases, each channel uses the same component
values to sense current. If this is the case you can derive a
more complete equation for VDROOP for each current sense
method being used.
I OUT
V DROOP = -----------N
r DS  ON 
---------------------- R FB
R ISEN
I OUT
DCR
V DROOP = -------------  K  ------------------ R FB
N
R ISEN
rDS(ON) SENSING
(ISL6565A ONLY)
(EQ. 11)
OFS
DCR SENSING
(ISL6565B ONLY)
(EQ. 12)
ISL6565A, ISL6565B
GND
Output-Voltage Offset Programming
The ISL6565A, ISL6565B allows the designer to accurately
adjust the offset voltage by connecting a resistor, ROFS,
from the OFS pin to VCC or GND. When ROFS is connected
between OFS and VCC, the voltage across it is regulated to
2.0V. This causes a proportional current (IOFS) to flow into
the OFS pin and out of the FB pin. If ROFS is connected to
ground, the voltage across it is regulated to 0.5V, and IOFS
flows into the FB pin and out of the OFS pin. The offset
current flowing through the resistor between VDIFF and FB
will generate the desired offset voltage which is equal to the
product (IOFS x RFB). These functions are shown in Figures
8 and 9.
Once the desired output offset voltage has been determined,
use the following formulas to set ROFS:
GND
VCC
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VDIFF
VOFS
+
RFB
VREF
E/A
FB
IOFS
VCC
-
OFS
ISL6565A, ISL6565B
For Negative Offset (connect ROFS to VCC):
2.0V
+
+
(EQ. 13)
2  R FB
R OFS = -------------------------V OFFSET
0.5V
ROFS
For Positive Offset (connect ROFS to GND):
0.5  R FB
R OFS = -------------------------V OFFSET
-
ROFS
2.0V
+
+
0.5V
GND
VCC
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
(EQ. 14)
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the corevoltage regulator to do this by making changes to the VID
inputs. The core-voltage regulator is required to monitor the
DAC inputs and respond to on-the-fly VID changes in a
controlled manner supervising a safe output voltage transition
without discontinuity or disruption.
15
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
The ISL6565A, ISL6565B checks the VID inputs six times
every switching cycle. If the VID code is found to have
changed, the controller waits half of a complete cycle before
executing a 12.5mV change. If during the half-cycle wait
period, the difference between the DAC level and the new
VID code changes sign, no change is made. If the VID code
is more than 1 bit higher or lower than the DAC (not
recommended), the controller will execute 12.5mV changes
six times per cycle until VID and DAC are equal. It is
important to carefully control the rate of VID stepping in 1-bit
increments.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network is
required for an ISL6565A, ISL6565B based voltage
regulator. This network is composed of a 1k internal
resistor between the output of DAC and the capacitor CREF,
between the REF pin and ground. The selection of CREF is
based on the time duration for 1 bit VID change and the
allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every TVID, the relationship between CREF and TVID is
given by Equation 15.
C REF = 0.004X T VID
(EQ. 15)
As an example, for a VID step change rate of 5s per bit, the
value of CREF is 22nF based on Equation 15.
created by pushing the average sense current through a
selectable external resistor, RTCOMP.
VDIFF
VDROOP
+
RFB
FB
IAVG
IDROOP
ITCOMP
KTC
TCOMP
IAVG
RTCOMP
ISL6565A, ISL6565B
FIGURE 10. TEMPERATURE COMPENSATION CIRCUITRY
As shown in Figure 10, the voltage drop developed across
RTCOMP is then sensed and multiplied by a known gain,
KTC, which is determined by the internal IC temperature.
This gain creates the temperature compensation current,
ITCOMP, that is injected into the FB pin.
I TCOMP = K TC   T – 25   I AVG  R TCOMP
Temperature Compensation
MOSFET rDS(ON) and inductor DCR are both susceptible to
changes in value due to temperature. Since output voltage
positioning is derived from the channel current sensed
across these two elements, any variation in resistance
results in a corresponding error in the output voltage.
Select RTCOMP such that ITCOMP equals IERR over the
entire range of operating temperature. The resulting droop
current accurately represents the load current; achieving a
linear, temperature-independant load line.
The temperature coefficient, , of the rDS(ON) or DCR is the
parameter that determines how much the resistance varies
with temperature. As temperature increases above ambient,
the average sensed current, IAVG, changes in proportion to
the temperature coefficient and temperature rise as shown in
Equation 16.
Initialization
I AVG = I AVG  T
   1 +   T – T AMBIENT  
AMBIENT
Enable and Disable
(EQ. 16)
With this resulting error, IAVG can now be described as the
sum of two parts, the average sensed current at ambient
temperature and the resulting error current, IERR, due to the
temperature rise.
I ERR  T  = I AVG  T
AMBIENT
     T – T AMBIENT 
(EQ. 17)
In order to compensate for this error current, the ISL6565A,
ISL6565B includes a temperature compensation circuit that
injects a current, ITCOMP, into the FB pin. This current is
16
(EQ. 18)
Prior to initialization, proper conditions must exist on the
enable inputs and VCC. When the conditions are met, the
controller begins soft-start. Once the output voltage is within
the proper window of operation, the controller asserts
PGOOD.
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6565A,
ISL6565B is released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6565A, ISL6565B is guaranteed. Hysteresis
between the rising and falling thresholds assure that once
enabled, the ISL6565A, ISL6565B will not inadvertently
turn off unless the bias voltage drops substantially (see
Electrical Specifications).
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
ISL6565A, ISL6565B INTERNAL CIRCUIT
EXTERNAL CIRCUIT
+12V
VCC
POR
CIRCUIT
10.7k
ENABLE
COMPARATOR
EN
+
-
1.40k
1.24V
ENLL
SOFT-START
AND
FAULT LOGIC
FIGURE 11. POWER SEQUENCING USING THRESHOLDSENSITIVE ENABLE (EN) FUNCTION
2. The voltage on EN must be above 1.31V. The EN input
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6565A, ISL6565B in shutdown until the
voltage at EN rises above 1.31V. The enable comparator
has about 100mV of hysteresis to prevent bounce. It is
important that the driver ICs reach their POR level before
the ISL6565A, ISL6565B becomes enabled. The
schematic in Figure 11 demonstrates sequencing the
ISL6565A, ISL6565B with the HIP660X family of Intersil
MOSFET drivers, which require 12V bias.
existing charge on the output as the controller attempted to
regulate to 0V at the beginning of the soft-start cycle. The
soft-start time, tSS, begins with a delay period equal to 64
switching cycles followed by a linear ramp with a rate
determined by the switching period, 1/fSW.
64 + 1280  VID
t SS = ----------------------------------------f SW
(EQ. 19)
For example, a regulator with a 250kHz switching frequency,
having VID set to 1.35V, has tSS equal to 6.912ms.
A 100mV offset exists on the remote-sense amplifier at the
beginning of soft-start and ramps to zero during the first 640
cycles of soft-start (704 cycles following enable). This
prevents the large inrush current that would otherwise occur
should the output voltage start out with a slight negative
bias.
During the first 640 cycles of soft-start (704 cycles following
enable) the DAC voltage increments the reference in 25mV
steps. The remainder of soft-start sees the DAC ramping
with 12.5mV steps.
VOUT, 500mV/DIV
2ms/DIV
EN, 5V/DIV
3. The voltage on ENLL must be logic high to enable the
controller. This pin is typically connected to the
VID_PGOOD.
4. The VID code must not be 111111 or 111110. These codes
signal the controller that no load is present. The controller
will enter shut-down mode after receiving either of these
codes and will execute soft-start upon receiving any other
code. These codes can be used to enable or disable the
controller but it is not recommended. After receiving one
of these codes, the controller executes a 2-cycle delay
before changing the overvoltage trip level to the shutdown level and disabling PWM. Overvoltage shutdown
cannot be reset using one of these codes.
When each of these conditions is true, the controller
immediately begins the soft-start sequence.
Soft-Start
During soft-start, the DAC voltage ramps linearly from zero
to the programmed VID level. The PWM signals remain in
the high-impedance state until the controller detects that the
ramping DAC level has reached the output-voltage level.
This protects the system against the large, negative inductor
currents that would otherwise occur when starting with a pre-
17
500ms/DIV
FIGURE 12. SOFT-START WAVEFORMS WITH AN UN-BIASED
OUTPUT. FSW = 500kHz
Fault Monitoring and Protection
The ISL6565A, ISL6565B actively monitors output voltage
and current to detect fault conditions. Fault monitors trigger
protective measures to prevent damage to a microprocessor
load. One common power good indicator is provided for
linking to external system monitors. The schematic in
Figure 13 outlines the interaction between the fault monitors
and the power good signal.
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
PGOOD
OC
-
+
UV
110A
+
I1
REPEAT FOR
EACH CHANNEL
75%
DAC
REFERENCE
-
SOFT-START, FAULT
AND CONTROL LOGIC
+
VDIFF
OC
-
+
110A
IAVG
OVP
OV
VID + 0.2V
FIGURE 13. POWER GOOD AND PROTECTION CIRCUITRY
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that transitions high when the converter is operating after
soft-start. PGOOD pulls low during shutdown and releases
high after a successful soft-start. PGOOD only transitions
low when an undervoltage condition is detected or the
controller is disabled by a reset from EN, ENLL, POR, or one
of the no-CPU VID codes. After an undervoltage event,
PGOOD will return high unless the controller has been
disabled. PGOOD does not automatically transition low upon
detection of an overvoltage condition.
Undervoltage Detection
The undervoltage threshold is set at 75% of the VID code.
When the output voltage at VSEN is below the undervoltage
threshold, PGOOD gets pulled low. No other action is taken
by the controller.
Overvoltage Protection
When VCC is above 1.4V, but otherwise not valid as defined
under Power on Reset in Electrical Specifications, the
overvoltage trip circuit is active using auxiliary circuitry. In
this state, an overvoltage trip occurs if the voltage at VSEN
exceeds 1.8V.
With valid VCC, the overvoltage circuit is sensitive to the
voltage at VDIFF. In this state, the trip level is 1.7V prior to
valid enable conditions being met as described in Enable
and Disable. The only exception to this is when the IC has
been disabled by an overvoltage trip. In that case the
overvoltage trip point is VID plus 200mV. During soft-start,
the overvoltage trip level is the higher of 1.7V or VID plus
200mV. Upon successful soft-start, the overvoltage trip level
is 200mV above VID. Two actions are taken by the
18
ISL6565A, ISL6565B to protect the microprocessor load
when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low until the voltage at VSEN falls below
0.6V with valid VCC or 1.5V otherwise. This causes the
Intersil drivers to turn on the lower MOSFETs and pull the
output voltage below a level that might cause damage to the
load. The PWM outputs remain low until VDIFF falls to the
programmed DAC level at which time they enter a highimpedance state. The Intersil drivers respond to the highimpedance input by turning off both upper and lower
MOSFETs. If the overvoltage condition reoccurs, the
ISL6565A, ISL6565B will again command the lower
MOSFETs to turn on. The ISL6565A, ISL6565B will continue
to protect the load in this fashion as long as the overvoltage
condition recurs.
Simultaneous to the protective action of the PWM outputs, the
OVP pin pulls to VCC delivering up to 100mA to the gate of a
crowbar MOSFET or SCR placed either on the input rail or the
output rail. Turning on the MOSFET or SCR collapses the
power rail and causes a fuse placed further up stream to blow.
The fuse must be sized such that the MOSFET or SCR will
not overheat before the fuse blows. The OVP pin is tolerant to
12V (see Absolute Maximum Ratings), so an external resistor
pull up can be used to augment the driving capability. If using
a pull up resistor in conjunction with the internal overvoltage
protection function, care must be taken to avoid nuisance trips
that could occur when VCC is below 2V. In that case, the
controller is incapable of holding OVP low.
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6565A, ISL6565B is reset.
Cycling the voltage on EN, ENLL, or VCC below the PORfalling threshold will reset the controller. Cycling the VID
codes will not reset the controller.
Overcurrent Protection
ISL6565A, ISL6565B has two levels of overcurrent
protection. Each phase is protected from a sustained
overcurrent condition on a delayed basis, while the
combined phase currents are protected on an instantaneous
basis.
In instantaneous protection mode, the ISL6565A, ISL6565B
takes advantage of the proportionality between the load
current and the average current, IAVG, to detect an
overcurrent condition. See the Channel-Current Balance
section for more detail on how the average current is
measured. The average current is continually compared with
a constant 110A reference current as shown in Figure 6.
Once the average current exceeds the reference current, a
comparator triggers the converter to shutdown.
In individual overcurrent protection mode, the ISL6565A,
ISL6565B continuously compares the current of each channel
with the same 110A reference current. If any channel current
exceeds the reference current continuously for eight
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
consecutive cycles, the comparator triggers the converter to
shutdown.
At the beginning of overcurrent shutdown, the controller
places all PWM signals in a high-impedance state
commanding the Intersil MOSFET driver ICs to turn off both
upper and lower MOSFETs. The system remains in this state
for a period of 4096 switching cycles. If the controller is still
enabled at the end of this wait period, it will attempt a softstart (as shown in Figure 14). If the fault remains, the tripretry cycles will continue indefinitely until either the controller
is disabled or the fault is cleared. Note that the energy
delivered during trip-retry cycling is much less than during
full-load operation, so there is no thermal hazard.
OUTPUT CURRENT, 50A/DIV
If through-hole MOSFETs and inductors can be used, higher
per-phase currents are possible. In cases where board
space is the limiting constraint, current can be pushed as
high as 40A per phase, but these designs require heat sinks
and forced air to cool the MOSFETs, inductors and heatdissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is
simple, since virtually all of the loss in the lower MOSFET is
due to current conducted through the channel resistance
(rDS(ON)). In Equation 20, IM is the maximum continuous
output current, IPP is the peak-to-peak inductor current (see
Equation 1), and d is the duty cycle (VOUT/VIN).
I L, 2PP  1 – d 
 I M 2
P LOW 1 = r DS  ON   -----  1 – d  + -------------------------------12
 N
0A
OUTPUT VOLTAGE,
500mV/DIV
0V
2ms/DIV
FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE
FSW = 500kHz
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and example
board layouts for all common microprocessor applications.
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted, the
total board space available for power-supply circuitry, and
the maximum amount of load current. Generally speaking,
the most economical solutions are those in which each
phase handles between 25A and 30A. All surface-mount
designs will tend toward the lower end of this current range.
19
(EQ. 20)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at IM, VD(ON), the switching
frequency, fS, and the length of dead times, td1 and td2, at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
I

I M I PP
M I PP t
P LOW 2 = V D  ON  f S  ----- t d1 +  ----- – --------- d2
 N- + -------2 
2
N
(EQ. 21)
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of PLOW,1 and PLOW,2.
UPPER MOSFET POWER CALCULATION
In addition to rDS(ON) losses, a large portion of the upperMOSFET losses are due to currents conducted across the
input voltage (VIN) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode reverserecovery charge, Qrr, and the upper MOSFET rDS(ON)
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 22,
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
the required time for this commutation is t1 and the
approximated associated power loss is PUP,1.
I M I PP  t 1 
P UP,1  V IN  -----  ----  f
 N- + -------2  2 S
VIN
CHANNEL N
UPPER MOSFET
(EQ. 22)
IL
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t2. In Equation 23, the
approximate power loss is PUP,2.
ISEN(n)
RISEN
-
 I M I PP  t 2 
P UP, 2  V IN  ----- – ---------  ----  f S
2  2
N
(EQ. 23)
ISL6565A
I
r
L DS  ON 
+
A third component involves the lower MOSFET’s reverserecovery charge, Qrr. Since the inductor current has fully
commutated to the upper MOSFET before the lowerMOSFET’s body diode can recover all of Qrr, it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is PUP,3.
(EQ. 24)
P UP,3 = V IN Q rr f S
Finally, the resistive part of the upper MOSFETs is given in
Equation 25 as PUP,4.
2
I PP2
 I M
P UP,4  r DS  ON   ----- d + ---------12
 N
(EQ. 25)
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 22, 23, 24 and 25. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Current Sensing Component Selection
The ISL6565A supports MOSFET rDS(ON) current sensing,
while the ISL6565B uses inductor DCR current sensing. The
procedures for choosing the components for each method of
current sensing are very different and are described in the
next two sections.
MOSFET rDS(ON) SENSING (ISL6565A ONLY)
The ISL6565A senses the channel load current by sampling
the voltage across the lower MOSFET rDS(ON), as shown in
Figure 15. The ISEN pins are denoted ISEN1, ISEN2, and
ISEN3. The resistors connected between these pins and the
respective phase nodes determine the gains in the load-line
regulation loop and the channel-current balance loop as well
as setting the overcurrent trip point.
20
CHANNEL N
LOWER MOSFET
FIGURE 15. ISL6565A INTERNAL AND EXTERNAL CURRENTSENSING CIRCUITRY
Select values for these resistors based on the room
temperature rDS(ON) of the lower MOSFETs; the full-load
operating current, IFL; and the number of phases, N using
Equation 26.
r DS  ON 
R ISEN = ---------------------70 10 – 6
I FL
------N
(EQ. 26)
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistor. When the components of
one or more channels are inhibited from effectively dissipating
their heat so that the affected channels run hotter than
desired, choose new, smaller values of RISEN for the affected
phases (see the section entitled Voltage Regulation). Choose
RISEN,2 in proportion to the desired decrease in temperature
rise in order to cause proportionally less current to flow in the
hotter phase.
T
R ISEN ,2 = R ISEN ----------2
T 1
(EQ. 27)
In Equation 27, make sure that T2 is the desired temperature
rise above the ambient temperature, and T1 is the measured
temperature rise above the ambient temperature. While a
single adjustment according to Equation 27 is usually
sufficient, it may occasionally be necessary to adjust RISEN
two or more times to achieve optimal thermal balance
between all channels.
INDUCTOR DCR SENSING (ISL6565B ONLY)
The ISL6565B senses the channel load current by sampling
the voltage across the output inductor DCR, as described in
the Current Sensing section. As Figure 16 illustrates, an R-C
network across the inductor is required to sense the channel
current accurately.
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
VIN
I
L
ISL6605
below to choose the component values for the resistor
divider R-C network for each phase.
L
DCR
VOUT
+
VC(s)
R1
PWM(n)
COUT
2. Measure the current flowing through each phase,
labeling the highest phase current, IHIGH, and the other,
lower phase currents ILOW(1) and ILOW(2).
-
VL(s)
-
+
INDUCTOR
C
3. Individually, plug the values for each low phase current,
ILOW(n), the highest phase current, IHIGH, the full load
current, ILOAD, and the number of phases, N, into
Equation 30 to calculate the resistor divider ratio, KLOW,
for each low phase. (NOTE: The phase with the highest
phase current is the reference phase and it will not use a
resistor divider network, keeping its resistor divider ratio
equal to 1.)
R2
ISL6565B
RISEN
ISEN(n)
ISEN
I LOW  n  – I HIGH
K LOW  n  = 1 + --------------------------------------------I LOAD  N
ICOMMON
FIGURE 16. DCR SENSING CONFIGURATION
The time constant of this R-C network must match the time
constant of the inductor L/DCR. Follow the steps below to
choose the component values for this R-C network.
1. Choose an arbitrary value for C. The recommended value
is 0.01F.
2. Plug the Inductor L and DCR component values, and the
values for C chosen in steps 1, into Equation 28 to
calculate your value for R1. Do not populate R2.
L
R 1 = ---------------------DCR  C
(EQ. 28)
Due to errors in the inductance or DCR it may be necessary
to adjust the value of R1 for each phase to match the time
constants correctly.
Once the R-C network components have been chosen, use
Equation 29 to calculate the value of RISEN. In Equation 29,
DCR is the DCR of the output inductor at room temperature,
IFL is the full load operating current, and N is the number of
phases.
DCR  I FL
R ISEN = --------------------------------–6
70  10  N
(EQ. 29)
Adjusting Phase Currents (ISL6565B Only)
Layout issues in the core-power regulator may cause the
currents in each phase to be slightly unbalanced. This
problem can be resolved without any changes to the layout or
any significant cost increase. The solution requires populating
R2 in certain phases (as shown in Figure 16) to create a
resistor divider ratio, K, for each phase. The time constant of
each new resistor divider R-C sense network must match the
time constant of the old sense network. Follow the steps
21
1. Load the regulator to full load and allow the board to heat
until the output voltage stabilizes (usually several
minutes).
(EQ. 30)
4. For each phase, calculate the values for the new R-C
network sense resistors, R1,new and R2,new, by plugging
in each phase’s new resistor divider ratio, KLOW, and
each phase’s present sense resistor R1, into Equations
31 and 32.
R1  n 
R 1 new  n  = ------------------------K LOW  n 
(EQ. 31)
R1  n 
R 2 new  n  = ----------------------------------1 – K LOW  n 
(EQ. 32)
After calculating the new resistor divider sense resistors, the
phases will be balanced. It may be necessary to adjust the
RISEN resistor slightly to correct for any changes in the
desired ISEN current that results from adding the resistor
dividers.
The phase currents might also have to be adjusted if the
components of one or more phases are inhibited from
effectively dissipating their heat so that the affected phases
run hotter than desired. In this case it may be necessary to
adjust the resistor divider ratio of one or more of the R-C
networks. Doing so adjusts the current through affected
phases and can balance the temperatures of each phase.
Choose R1,new and R2,new in relation to the desired change
in temperature, as described in Equations 33 and 34, in order
to cause less current to flow in the hotter phase.
T
R 1 ,new = R 1 ----------2
T 1
R1  R2
R 2 ,new = -------------------------------------------------T 1

--------R1 + R2   1 –

T 2

(EQ. 33)
(EQ. 34)
In Equations 33 and 34, T2 is the desired temperature rise
above the ambient temperature, and T1 is the measured
temperature rise above the ambient temperature. It is
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
important to note that when using Equations 33 and 34 the
resistor divider ratio of the corresponding phase RC network
is being changed. In the phase being adjusted, this new ratio,
Knew (described in Equation 35), can not exceed 1.0.
T 1
K new = K ---------T 2
(EQ. 35)
If this occurs, the current in the hot phase cannot be reduced
any more. Instead of decreasing the current in the hot phase,
the current must be increased in the colder phases. To
accomplish this, use Equations 33 and 34 to get the desired
temperature rise in the cold phases.
While a single adjustment, according to Equations 33 and 34,
is usually sufficient, it may occasionally be necessary to adjust
R1 and R2 in the corresponding channels two or more times
to achieve optimal thermal balance between all phases.
Load-Line Regulation Resistor
The load-line regulation resistor is labeled RFB in Figure 7.
Its value depends on the desired full-load droop voltage
(VDROOP in Figure 7). Once the ISEN resistor has been
chosen, the load-line regulation resistor can be calculated
using Equation 36.
V DROOP
R FB = -----------------------–6
70 10
(EQ. 36)
If one or more of the ISEN resistors is adjusted for thermal
balance, as in Equation 26, the load-line regulation resistor
should be selected according to Equation 37 where IFL is the
full-load operating current and RISEN(n) is the ISEN resistor
connected to the nth ISEN pin.
V DROOP
R FB = -------------------------------I FL r DS  ON 
 RISEN  n 
(EQ. 37)
temperature. Resistance is normalized to the value at 25°C
and the value of  is typically between 0.35%/°C and
0.50%/°C.
According to Equation 38, a voltage regulator with 80%
thermal coupling coefficient between the controller and lower
MOSFET and 0.4%/°C temperature coefficient of MOSFET
rDS(ON) requires a 2.5k TCOMP resistor.
If the exact value for KT and  are not known, Equation 38
can give an incorrect value for RTCOMP. If this is the case,
follow the steps below to obtain an accurate value for
RTCOMP. This procedure works by making two output
voltage measurements. The first is made by using too much
temperature compensation, and the second with too little.
Each of the measurements produces an error and a linear
interpolation is used to find a TCOMP resistor value to
produce zero error. Make all measurements using a digital
multimeter accurate to 100V or better.
1. Install a 5k resistor (R1) for RTCOMP.
2. Start the regulator at room temperature and apply full
load current. Record the output voltage, V1, immediately
after loading the regulator.
3. Allow the board to heat until the output voltage stabilizes
(usually several minutes). Record the output voltage, V2.
4. Install a 1k resistor (R2) for RTCOMP.
5. Start the regulator at room temperature and apply full
load current. Record the output voltage, V3, immediately
after loading the regulator.
6. Allow the board to heat until the output voltage stabilizes
(usually several minutes). Record the output voltage, V4.
7. Calculate the correct value for RTCOMP using
Equation 39.
 V2 – V1 
R TCOMP = R 1 –  R 1 – R 2  -------------------------------------------------------V – V  + V – V 
2
n
1
3
(EQ. 39)
4
Temperature Compensation Resistor
Compensation
By combining Equations 17 and 18 found in the Temperature
Compensation section, the value of the TCOMP resistor can
be determined using Equation 38.
The two opposing goals of compensating the voltage
regulator are stability and speed.

R TCOMP = ---------------------K T K TC
(EQ. 38)
In Equation 38, KT is the temperature coupling coefficient
between the ISL6565A and the closest lower MOSFET, or
the ISL6565B and the output inductor. It represents how
closely the controller temperature tracks the lower MOSFET
or inductor temperature. The value of KT is typically between
75% and 100%. KTC is the temperature dependant
transconductance of the internal compensation circuit. Its
value is designed as 2A/V/°C. The temperature coefficient
of MOSFET rDS(ON) or inductor DCR is given by . This is
the ratio of the change in resistance to the change in
22
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, RC and CC.
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
.
C2 (OPTIONAL)
CC
COMP
FB
+
RFB
VDROOP
0.75V IN  ESR  C
C C = -----------------------------------------------2V PP R FB f 0 L
In Equation 40, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and VPP is the peak-topeak sawtooth signal amplitude as described in Figure 6 and
Electrical Specifications.
VDIFF
FIGURE 17. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6565A, ISL6565B
CIRCUIT
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage-mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f0.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f0
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
Case 1:
1
------------------- > f 0
2 LC
2f 0 V pp LC
R C = R FB ----------------------------------0.75V
IN
0.75V IN
C C = ----------------------------------2V PP R FB f 0
Case 2:
1
1
-------------------  f 0 < ----------------------------2C  ESR 
2 LC
V PP  2  2 f 02 LC
R C = R FB -------------------------------------------0.75 V
IN
0.75V IN
C C = -----------------------------------------------------------2
 2  f 02 V PP R FB LC
23
1
f 0 > -----------------------------2C  ESR 
2 f 0 V pp L
R C = R FB ----------------------------------------0.75 V IN  ESR 
ISL6565A, ISL6565B
RC
Case 3:
(EQ. 40)
Once selected, the compensation values in Equation 40
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to RC. Slowly increase the
value of RC while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the value of CC from
Equation 40 unless some performance issue is noted.
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 17). Keep
a position available for C2, and be prepared to install a highfrequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, I,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, VMAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
have sufficiently low ESL and ESR so that the total outputvoltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
di
V   ESL  ----- +  ESR  I
dt
(EQ. 41)
The filter capacitor must have sufficiently low ESL and ESR
so that V < VMAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see Interleaving and
Equation 2), a voltage develops across the bulk-capacitor
ESR equal to IC,PP (ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage,
VPP(MAX), determines the lower limit on the inductance.
V – N V

OUT V OUT
 IN
L   ESR  -----------------------------------------------------------f S V IN V PP MAX 
Input Supply Voltage Selection
The VCC input of the ISL6565 can be connected either
directly to a +5V supply or through a current limiting resistor to
a +12V supply. An integrated 5.8V shunt regulator maintains
the voltage on the VCC pin when a +12V supply is used. A
300 resistor is suggested for limiting the current into the
VCC pin to a worst-case maximum of approximately 25mA.
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper-MOSFET loss calculation. These effects are
outlined in MOSFETs, and they establish the upper limit for
the switching frequency. The lower limit is established by the
requirement for fast transient response and small outputvoltage ripple as outlined in Output Filter Design. Choose the
lowest switching frequency that allows the regulator to meet
the transient-response requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, RT (see the figures labeled
Typical Application on pages 5 and 6). Figure 18 and
Equation 45 are provided to assist in selecting the correct
value for RT.
R T = 10
(EQ. 45)
10.7 – 1.045 log  f S  
(EQ. 42)
Equation 43 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 44
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
RT (k)
1000
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
VMAX. This places an upper limit on inductance.
100
10
10
1000
100
SWITCHING FREQUENCY (kHz)
10000
FIGURE 18. RT vs SWITCHING FREQUENCY
Input Capacitor Selection
2NCVO
L  -------------------- V MAX – I  ESR 
 I  2
(EQ. 43)
 1.25  NC
L  -------------------------- V MAX – I  ESR   V IN – V O


 I  2
(EQ. 44)
24
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
0.3
INPUT-CAPACITOR CURRENT (IRMS/IO)
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.3
0.2
0.1
IL,PP = 0
IL,PP = 0.5 IO
IL,PP = 0.75 IO
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN/VO)
FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
For a two-phase design, use Figure 19 to determine the
input-capacitor RMS current requirement set by the duty
cycle, maximum sustained output current (IO), and the ratio
of the peak-to-peak inductor current (IL,PP) to IO. Select a
bulk capacitor with a ripple current rating which will minimize
the total number of input capacitors required to support the
RMS current calculated. The voltage rating of the capacitors
should also be at least 1.25 times greater than the maximum
input voltage. Figure 20 provides the same input RMS
current information for three phase designs respectively. Use
the same approach for selecting the bulk capacitor type and
number.
25
IL,PP = 0
IL,PP = 0.5 IO
IL,PP = 0.25 IO
IL,PP = 0.75 IO
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN/VO)
FIGURE 20. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 3-PHASE CONVERTER
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the input bulk capacitors to suppress
leading and falling edge voltage spikes. The spikes result
from the high current slew rate produced by the upper
MOSFET turn on and off. Select low ESL ceramic capacitors
and place one as close as possible to each upper MOSFET
drain to minimize board parasitics and maximize
suppression.
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
0.15 C A
D
A
MILLIMETERS
9
D/2
D1
D1/2
2X
N
6
INDEX
AREA
0.15 C B
1
2
3
E1/2
E/2
E
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
9
D2
B
TOP VIEW
A2
0
A
4X P
9
0.30
5,8
5.00 BSC
-
4.75 BSC
2.95
3.10
9
3.25
7,8
E
5.00 BSC
-
4.75 BSC
9
2.95
3.10
3.25
7,8
0.50 BSC
-
k
0.25
-
-
-
L
0.50
0.60
0.75
8
L1
-
-
0.15
10
0.10 M C A B
8
Nd
7
3
NX k
Ne
8
7
3
P
-
-
0.60
9

-
-
12
9
7
D2
2 N
4X P
1
(DATUM A)
2
3
6
INDEX
AREA
E2/2
NX L
N e
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
8
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
BOTTOM VIEW
A1
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
SECTION "C-C"
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
C
L
10
L
L1
e
10
L
e
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
2
NOTES:
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
28
Rev. 0 02/03
(Ne-1)Xe
REF.
E2
7
L1
0.23
9
N
D2
C
L
0.18
e
5
NX b
(DATUM B)
A1
A3
SIDE VIEW
0.20 REF
E1
E2
/ / 0.10 C
0.08 C
8
MAX
D1
C
SEATING PLANE
NOMINAL
D
0.15 C B
4X
MIN
b
E1
2X
0.15 C A
SYMBOL
A3
9
2X
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE C)
2X
9. Features and dimensions A2, A3, D1, E1, P &  are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
FOR EVEN TERMINAL/SIDE
26
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
INDEX
AREA
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
10.00
-
0.394
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
0.419
1.27 BSC
H

NOTES:
MAX
A1
e

MIN
28
0o
10.65
28
-
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
27
FN9135.4
December 1, 2005
ISL6565A, ISL6565B
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
INDEX
AREA
E
0.25(0.010) M
E1
2
INCHES
3
0.05(0.002)
-A-
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
GAUGE
PLANE
-B1
M28.173
B M
0.25
0.010
SEATING PLANE
L
A
D
-C-

e
A1
b
A2
c
0.10(0.004)
0.10(0.004) M
C A M
B S
NOTES:
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.378
0.386
9.60
9.80
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
E
0.246
L
0.0177
N
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
MILLIMETERS

0.65 BSC
0.256
6.25
0.0295
0.45
28
0o
-
6.50
-
0.75
6
28
8o
0o
7
8o
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Rev. 0 6/98
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
28
FN9135.4
December 1, 2005
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