DATASHEET

ICL7149
®
NO RE
UCT
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PROD
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PLACSheet
EData
OBSO
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EN D
C O MM
May 2001
File Number
3-3/4 Digit, Autoranging Multimeter
Features
The Intersil ICL7149 is a high performance, low power,
autoranging digital multimeter lC. Unlike other autoranging
multimeter ICs, the ICL7149 always displays the result of a
conversion on the correct range. There is no “range hunting”
noticeable in the display. The unit will autorange between
the four different ranges. A manual switch is used to select
the 2 high group ranges. DC current ranges are 4mA and
40mA in the low current group, and 400mA and 4A in the
high current group. Resistance measurements are made on
4 ranges, which are divided into two groups. The low
resistance ranges are 4/40kΩ. The high resistance ranges
are 0.4/4MΩ. Resolution on the lowest range is 1Ω.
• 18 Ranges
- 4 DC Voltage 400mV, 4V, 40V, 400V
- 2 AC Voltage with Optional AC Circuit
- 4 DC Current 4mA, 40mA, 400mA, 4A
- 4 AC Current with Optional AC Circuit
- 4 Resistance 4kΩ, 40kΩ, 400kΩ, 4MΩ
0 to 70
PACKAGE
44 Ld MQFP
PKG. NO.
Q44.10x10
LO BAT/V
44 43 42 41 40 39 38 37 36 35 34
33
2
32
1
Functional Block Diagram
SWITCHES
MΩ/µA
Ω/A
3
31
k/m
B3 /C3
4
30
OSC IN
ADG3 /E3
5
29
OSC OUT
POL/AC
6
28
HOLD
NC
7
27
HIΩ-DC/LOΩ-AC
BP2
8
26
Ω/V/A
BP1
9
25
mA/µA
CINT
CAZ
TRIPLE POINT
INT V/Ω
INT I
COMMON
DEINT
HIΩ
LOΩ
V-
24
10
11
23
12 13 14 15 16 17 18 19 20 21 22
VREF
NC
• Low Battery Annunciator with On-Chip Detection
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
F2 /DP3
V+
• Continuity Output Drives Piezoelectric Beeper
Related Literature
NC
B0 /C0
A0 /D0
G0 /E0
F0 /DP1
B1 /C1
A1 /D1
G1 /E1
F1/ DP2
B2 /C2
ICL7149 (MQFP)
TOP VIEW
G2 /E2
• No Additional Active Components Required
• Guaranteed Zero Reading for 0V Input on All Ranges
Pinout
A2 /D2
• On-Chip Duplex LCD Display Drive Including Three
Decimal Points and 11 Annunciators
• Display Hold Input
TEMP.
RANGE ( oC)
ICL7149CM44
• Autoranging - First Reading is Always on Correct Range
• Low Power Dissipation - Less than 20mW - 1000 Hour
Typical Battery Life
Part Number Information
PART NUMBER
3088.3
OSC
CRYSTAL
BEEPER OUT
NC
COUNTERS
DIGITAL
COMMON
POWER
SUPPLY
SECTION
V+ V- COM
1
CONTROL LOGIC
INCLUDING
AUTORANGING
LOGIC
BEEPER
DRIVER
PIEZO
ELECTRIC
BEEPER
DISPLAY
DRIVER
AND
LATCHES
DISPLAY
ANALOG SECTION
ANALOG SWITCHES,
INTEGRATION
AND COMPARATOR
EXTERNAL
RESISTORS
AND CAPACITORS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
ICL7149
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Reference Input Voltage (V REF to COM) . . . . . . . . . . . . . . . . . . .3V
Analog Input Current (IN + Current or IN + Voltage) . . . . . . . .100µA
Clock Input Swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+ to V+ -3
Thermal Resistance (Typical, Note 1)
Operating Conditions
θJA ( oC/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(Lead Tips Only)
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
V+ = 9V, TA = 25oC, VREF adjusted for -3.700 reading on DC volts, test circuit as shown in Figure 3. Crystal =
120kHz. (See Figure 13)
Electrical Specifications
PARAMETER
TEST CONDITIONS
Zero Input Reading
VIN or IIN or RIN = 0.00
Linearity (Best Straight Line) (Note 6)
(Note 1)
MIN
TYP
MAX
UNITS
-00.0
-
+00.0
V, I, Ω
-1
-
+1
Counts
Accuracy DC V, 400V Range Only
(Notes 1 and 7)
-
-
±1
% of RDG ±1
Accuracy DC V, 400V Range Excluded
(Notes 1 and 7)
-
-
±0.30
% of RDG ±1
Accuracy Ω, 4K and 400K Range
(Notes 1 and 7)
-
-
±0.75
% of RDG ±8
Accuracy Ω, 4K and 4M Range
(Notes 1 and 7)
-
-
±1
% of RDG ±9
Accuracy DC I, Unadjusted for Full Scale
(Notes 1 and 7)
-
-
±0.75
% of RDG ±1
Accuracy DC I, Adjusted for Full Scale
(Notes 1 and 7)
-
±0.2
-
% of RDG ±1
Accuracy AC V
At 60Hz (Notes 5 and 7)
-
±2
-
% of RDG
Open Circuit Voltage for Ω Measurements
RUNKNOWN = Infinity
-
VREF
-
V
Noise
VIN = 0, DC V (Note 2, 95% of Time)
-
0.1
-
LSB
Noise
VIN = 0, AC V (Note 2, 95% of Time)
-
4
-
LSB
Supply Current
VIN = 0, DC Voltage Range
Analog Common (with Respect to V+)
ICOMMON < 10µA
< 10µA, Temp. = 0oC To 70oC
Temperature Coefficient of Analog Common
ICOMMON
Output Impedance of Analog Common
ICOMMON < 10µA
Backplane/Segment Drive Voltage
Average DC < 50mV
Backplane/Segment Display Frequency
-
1.5
2.4
mA
2.7
2.9
3.1
V
-
-100
-
ppm/ oC
-
1
10
Ω
2.8
3.0
3.2
V
-
75
-
Hz
-50
-
+50
µA
Switch Input Levels (High Trip Point)
V+ - 0.5
-
V+
V
Switch Input Levels (Mid Trip Point)
V- + 3
-
V+ - 2.5
V
Switch Input Levels (Low Trip Point)
V-
-
V- + 0.5
V
VIN = V+ to V- (Note 3)
Switch Input Current
Beeper Output Drive (Rise or Fall Time)
CLOAD = 10nF
Beeper Output Frequency
-
25
100
µs
-
2
-
kHz
Continuity Detect
Range = Low Ω, VREF = 1.00V
-
1.5
-
kΩ
Power Supply Functional Operation
V+ to V-
7
9
11
V
Low Battery Detect
V+ to V- (Note 4)
6.5
7
7.5
V
NOTES:
1. Accuracy is defined as the worst case deviation from ideal input value including: offset, linearity, and rollover error.
2. Noise is defined as the width of the uncertainty window (where the display will flicker) between two adjacent codes.
3. Applies to pins 25-28.
4. Analog Common falls out of regulation when the Low Battery Detect is asserted, however the ICL7149 will continue to
operate correctly with a supply voltage above 7V and below 11V.
5. For 50Hz use a 100kHz crystal.
6. Guaranteed by design, not tested.
7. RDG = Reading.
2
ICL7149
Timing Waveform
FIRST AUTO ZERO
FIRST INTEGRATE
FIRST DEINTEGRATE
UNDERRANGE
AUTO ZERO
SECOND AUTO ZERO
SECOND INTEGRATE
SECOND DEINTEGRATE
UNDERRANGE
AUTO ZERO
THIRD AUTO ZERO
THIRD INTEGRATE
THIRD DEINTEGRATE
UNDERRANGE
AUTO ZERO
FOURTH AUTO ZERO
FOURTH INTEGRATE
FOURTH DEINTEGRATE
AUTO ZERO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
FIGURE 1. LINE FREQUENCY CYCLES (1 CYCLE = 1000 INTERNAL CLOCK PULSES = 2000 OSCILLATION CYCLES)
Pin Descriptions
I/O
PIN NUMBER
I/O
PIN NUMBER
O
1
Segment Driver A2/D2
DESCRIPTION
O
24
Beeper Output
O
2
Segment Driver G2/E2
I
25
mA/µA
O
3
Segment Driver F2/DP3
I
26
Ω/V/A
O
4
Segment Driver B3 /C3
I
27
Hi Ω DC/Lo Ω AC
O
5
Segment Driver ADG3 /E3
I
28
Hold
O
6
Segment Driver POL/AC
O
29
Oscillator Out
N/A
7
No Connect (NC)
I
30
Oscillator In
O
8
Backplane 2
O
31
Segment DRIVER k/ m
O
9
Backplane 1
O
32
Segment Driver Ω /A
Segment Driver M Ω /µA
DESCRIPTION
I
10
V+
O
33
N/A
11
NC
O
34
Segment Driver Lo Bat/V
I
12
V-
N/A
35
NC
I
13
Reference Input
O
36
Segment Driver B0 /C
O
14
Lo Ω
O
37
Segment Driver A0 /D0
O
15
Hi Ω
O
38
Segment Driver G0 /E0
I/O
16
Deintegrate
O
39
Segment Driver F0/DP1
I/O
17
Analog Common
O
40
Segment Driver B1/C1
I
18
Int I
O
41
Segment Driver A1 /D1
I
19
Int V/Ω
O
42
Segment Driver G1 /E1
I
20
Triple Point
O
43
Segment Driver F1 /DP2
I
21
Auto Zero Capacitor (CAZ)
O
44
Segment Driver B2 /C2
I
22
Integrate Capacitor (CINT)
N/A
23
NC
3
NOTE: For segment drivers, segments are listed as (segment for
backplane 1)/(segment for backplane 2). Example: pin 36; segment
B0 is on backplane 1, segment C0 is on backplane 2.
ICL7149
Detailed Description
inverting inputs are connected to Common. The output of the
integrator, which is equal to its offset, is stored on CAZ - the
autozero capacitor. Similarly, the offset of the comparator is
stored in ClNT . The autozero cycle equals 1000 clock cycles
which is one 60Hz line cycle with a 120kHz oscillator, or one
50Hz line cycle with a 100kHz oscillator.
General
The Functional Block Diagram shows the digital section
which includes all control logic, counters, and display
drivers. The digital section is powered by V+ and Digital
Common, which is about 3V below V+. The oscillator is also
in the digital section. Normally 120kHz for rejection of 60Hz
AC interference and 100kHz for rejection of 50Hz AC should
be used. The oscillator output is divided by two to generate
the internal master clock. The analog section contains the
integrator, comparator, reference section, analog buffers,
and several analog switches which are controlled by the
digital logic. The analog section is powered from V+ and V-.
DIGIT 3
2
1
Range 1 Integrate
The ICL7149 performs a full autorange search for each
reading, beginning with range 1. During the range 1 integrate
period, internal switches connect the INT V/Ω terminal to the
Triple Point (Pin 20). The input signal is integrated for 10 clock
cycles, which are gated out over a period of 1000 clock cycles
to ensure good normal mode rejection of AC line interference.
Range 1 Deintegrate
0
LOW
BATT
f
e
a
g
d
At the beginning of the deintegrate cycle, the polarity of the
voltage on the integrator capacitor (CINT) is checked, and
either the DElNT+ or DElNT- is asserted. The integrator
capacitor CINT is then discharged with a current equal to
VREF/RDElNT . The comparator monitors the voltage on CINT .
When the voltage on CINT is reduced to zero (actually to the
VOS of the comparator), the comparator output switches, and
the current count is latched. If the CINT voltage zero-crossing
does not occur before 4000 counts have elapsed, the
overload flag is set. “OL” (overload) is then displayed on the
LCD. If the latched result is between 360 and 3999, the count
is transferred to the output latches and is displayed. When the
count is less than 360, an underrange has occurred, and the
ICL7149 then switches to range 2 - the 40V scale.
b kΩ MΩ
c mAV µA
AC
DP3
DP2
DP1
FIGURE 2. DISPLAY SEGMENT NOMENCLATURE
DC Voltage Measurement
Autozero
Only those portions of the analog section which are used during
DC voltage measurements are shown in Figure 3. As shown in
the timing diagram (Figure 1), each measurement starts with an
autozero (AZ) phase. During this phase, the integrator and
comparator are configured as unity gain buffers and their nonTRIPLE
POINT
VIN
CAZ
CAZ
RDEINT
CINT
AZ
AZ
T
INT V/ Ω
RDEINT
CINT
DEINTAZ
DEINTVREF
RINTV
T
AZ
-
+
INTEGRATOR
VREF
DEINT+
-
+
COMPARATOR
DEINT+
TO LOGIC SECTION
V+
ANALOG
COMMON
COMMON
6.7V
-
+
80µA
T = (INT)(AR)(AZ)
AR = AUTORANGE CHOPPER
AZ = AUTOZERO
INT = INTEGRATE
V-
FIGURE 3. DETAILED CIRCUIT DIAGRAM FOR DC VOLTAGE MEASUREMENT
4
ICL7149
Range 2
results in a fixed measurement period of 24,000 clock cycles
(24 line cycles).
The range 2 measurement begins with an autozero cycle
similar to the one that preceded range 1 integration. Range 2
cycle length however, is one AC line cycle, minus 360 clock
cycles. When performing the range 2 cycle, the signal is
integrated for 100 clock cycles, distributed throughout one line
cycle. This is done to maintain good normal mode rejection.
Range 2 sensitivity is ten times greater than range 1 (100 vs
10 clock cycle integration) and the full scale voltage of range 2
is 40V. The range 2 deintegrate cycle is identical to the range
1 deintegrate cycle, with the result being displayed only for
readings greater than 360 counts. If the reading is below 360
counts, the ICL7149 again asserts the internal underrange
signal and proceeds to range 3.
DC Current
Figure 4 shows a simplified block diagram of the analog
section of the ICL7149 during DC current measurement. The
DC current measurements are very similar to DC voltage
measurements except: 1) The input voltage is developed by
passing the input current through a 0.1Ω (HI current ranges),
or 9.9Ω (LOW current ranges) current sensing resistor; 2)
Only those ranges with 1000 and 10,000 clock cycles of
integration are used; 3) The RlNT l resistor is 1MΩ, rather
than the 10MΩ value used for the RlNT V resistor.
By using the lower value integration resistor, and only the 2
most sensitive ranges, the voltage drop across the current
sensing resistor is 40mV maximum on the 4mA and 400mA
ranges; 400mV maximum on the 40mA and 4A scales. With
some increase in noise, these “burden” voltages can be
reduced by lowering the value of both the current sense
resistors and the RlNT l resistor proportionally. The DC
current measurement timing diagram is similar to the DC
voltage measurement timing diagram, except in the DC
current timing diagram, the first and second integrate and
deintegrate phases are skipped.
Range 3
The range 3V or 4V full scale measurement is identical to the
range 2 measurement, except that the input signal is integrated
during the full 1000 clock cycles (one line frequency cycle). The
result is displayed if the reading is greater than 360 counts.
Underrange is asserted, and a range 4 measurement is
performed if the result is below 360 counts.
Range 4
This measurement is similar to the range 1, 2 and 3
measurements, except that the integration period is 10,000
clock cycles (10 line cycles) long. The result of this
measurement is transferred to the output latches and
displayed even if the reading is less than 360.
AC Voltage Measurement
The ICL7149 is designed to be used with an optional AC to
DC voltage converter circuit. It will autorange through two
voltage ranges (400V and 40V), and the AC annunciator is
enabled. A typical averaging AC to DC converter is shown in
Figure 5, while an RMS to DC converter is shown in Figure
6. AC current can also be measured with some simple
modifications to either of the two circuits in Figures 5 and 6.
Autozero
After finding the first range for which the reading is above
360 counts, the display is updated and an autozero cycle is
entered. The length of the autozero cycle is variable which
TRIPLE
POINT
INT I
LOW I
I
RDEINT
CINT
AZ
AZ
-
AZ
DEINT-
DEINT-
AZ
+
INTEGRATOR
VREF
DEINT+
0.1Ω
CAZ
VREF
T
HIGH I
RDEINT
CINT
T
RINTI
9.9Ω
CAZ
DEINT+
-
+
COMPARATOR
TO LOGIC SECTION
V+
6.7V
COMMON
ANALOG
COMMON
-
+
80µA
T = (INT)(AR)(AZ)
AR = AUTORANGE CHOPPER
AZ = AUTOZERO
INT = INTEGRATE
V-
FIGURE 4. DETAILED CIRCUIT DIAGRAM FOR DC CURRENT MEASUREMENT
5
ICL7149
1.0µF
100kΩ
V-
V+
11
20MΩ
4
VIN
0VAC - 400VAC
0Hz - 1000Hz
7
-
10
ICL7652
5 +
50kΩ
100kΩ
19
2
8
1
5kΩ
43.2kΩ
FULL
SCALE
ADJUST
0.1µF
0.1µF
V-
V+
ICL7149
11
20MΩ
4
7
ICL7652
5 +
1
0.1µF
8
10
2
0.1µF
17
COM
FIGURE 5. AC VOLTAGE MEASUREMENT USING OPTIONAL AVERAGING CIRCUIT
V+
2.2µF
+
2.2µF
1
10MΩ
VIN
0VAC - 400VAC
50Hz - 1000Hz
2
+
7
3
AD736
5kΩ
6
5
8
4
+
19
INT V/Ω
FULL
SCALE
ADJUST
10µF
4.99kΩ
V-
V+
ICL7149
30kΩ
17
COM
COMMON
FIGURE 6. AC VOLTAGE MEASUREMENT USING OPTIONAL RMS CONVERTER CIRCUIT
6
INT V/Ω
COMMON
ICL7149
R DEINT
TRIPLE
POINT
CAZ
CINT
CAZ
AZ
AZ
T
INT V/Ω
RINTV
T
AZ
RDEINT
CINT
AZ
-
+
LOΩ
RX
INTEGRATOR
-
-
+
+
RKNOWN 1
LOW Ω
HIΩ
DEINT+
COMPARATOR
DEINT+
VREF
-
T = INT + DEINT
AZ = AUTOZERO
INT = INTEGRATE
+
RKNOWN 2
TO LOGIC SECTION
LOW Ω
COMMON
FIGURE 7. DETAILED CIRCUIT DIAGRAM FOR RATIOMETRIC Ω MEASUREMENT
Ratiometric Ω Measurement
Common Voltage
The ratiometric Ω measurement is performed by first integrating
the voltage across an unknown resistor, RX , then effectively
deintegrating the voltage across a known resistor (RKNOWN1
or RKNOWN2 of Figure 7). The shunting effect of RINTV does
not affect the reading because it cancels exactly between
integration and deintegration. Like the current measurements,
the Ω measurements are split into two sets of ranges. LO Ω
measurements use a 10kΩ reference resistor, and the full scale
ranges are 4kΩ and 40kΩ. HI Ω measurements use a 1MΩ
reference resistor, and the full scale ranges are 0.4MΩ and
4MΩ. The measurement phases and timing are the same as
the measurement phases and timing for DC current except: 1)
During the integrate phases the input voltage is the voltage
across the unknown resistor RX , and; 2) During the deintegrate
phases, the input voltage is the voltage across the reference
resistor RKNOWN1 or RKNOWN2 .
The analog and digital common voltages of the ICL7149 are
generated by an on-chip resistor/zener/diode combination,
shown in Figure 9. The resistor values are chosen so the
coefficient of the diode voltage cancels the positive
temperature coefficient of the zener voltage. This voltage is
then buffered to provide the analog common and the digital
common voltages. The nominal voltage between V+ and
analog common is 3V. The analog common buffer can sink
about 20mA, or source 0.01mA, with an output impedance of
10Ω. A pullup resistor to V+ may be used if more sourcing
capability is desired. Analog common may be used to
generate the reference voltage, if desired.
Continuity Indication
When the ICL7149 is in the LO Ω measurement mode, the
continuity circuit of Figure 8 will be active. When the voltage
across RX is less than approximately 100mV, the beeper
output will be on. When RKNOWN is 10kΩ, the beeper output
will be on when RX is less than 1kΩ.
V+
80µA
6.7V
-
125K
-
5K
+
3V
+
ANALOG
COMMON
P (PIN 17)
+
3.1V
-
+
LOGIC
SECTION
DIGITAL
COMMON
P (INTERNAL)
180K
LO BAT
-+
0.3V
+
V-
LOΩ
RKNOWN
+
HIΩ
-
LOΩ
VREF
V+
2kHz
V+
BEEPER
OUTPUT
+
RUNKNOWN
RX
+
-
VX
FIGURE 9. ANALOG AND DIGITAL COMMON VOLTAGE
GENERATOR CIRCUIT
VX = 100mV
COM
FIGURE 8. CONTINUITY BEEPER DRIVE CIRCUIT
7
Oscillator
The ICL7149 uses a parallel resonant-type crystal in a
Pierce oscillator configuration, as shown in Figure 10, and
requires no other external components. The crystal
eliminates the need to trim the oscillator frequency. An
external signal may be capacitively coupled in OSC IN, with
a signal level between 0.5V and 3VP-P . Because the OSC
ICL7149
OUT pin is not designed to drive large external loads,
loading on this pin should not exceed a single CMOS input.
The oscillator frequency is internally divided by two to
generate the ICL7149 clock. The frequency should be
120kHz to reject 60Hz AC signals, and 100kHz to reject
50Hz signals.
OSC IN
string. The DC component of the drive waveforms is
guaranteed to be less than 50mV.
Ternary Input
The Ω/ Volts/Amps logic input is a ternary, or 3-level input.
This input is internally tied to the common voltage through a
high-value resistor, and will go to the middle, or “Volts” state,
when not externally connected. When connected to V-,
approximately 5µA of current flows out of the input. In this
case, the logic level is the “Amps”, or low state. When
connected to V+, about 5µA of current flows into the input.
Here, the logic level is the “Ω”, or high state. For other pins,
see Table 2.
OSC OUT
5M
330K
5pF
10pF
TABLE 2. TERNARY INPUTS CONNECTIONS
FIGURE 10. INTERNAL OSCILLATOR CIRCUIT DIAGRAM
PIN NUMBER
V+
OPEN OR
COM
V-
25
mA
µA
Test
26
Ω
V
Amps
27
HiΩ/DC
LoΩ/AC
Test
28
Hold
Auto
Test
Display Drivers
Figure 11 shows typical LCD Drive waveforms, RMS ON, and
RMS OFF voltage calculations. Duplex multiplexing is used to
minimize the number of connections between the ICL7149
and the LCD. The LCD has two separate back-planes. Each
drive line can drive two individual segments, one referenced
to each backplane. The ICL7149 drives 33/4 7-segment digits,
3 decimal points, and 11 annunciators. Annunciators are used
to indicate polarity, low battery condition, and the range in
use. Peak drive voltage across the display is approximately
3V. An LCD with approximately 1.4VRMS threshold voltage
should be used. The third voltage level needed for duplex
drive waveforms is generated through an on-chip resistor
Component Selection
For optimum performance while maintaining the low-cost
advantages of the ICL7149, care must be taken when
selecting external components. This section reviews
specifications and performance effects of various external
components.
VPEAK
V+
VPEAK / 2
BACKPLANE
V R MS =
5
--- V PEAK ON
8
VPEAK
V R MS =
5
--- V PEAK OFF
8
O
VPEAK = 3V ±10%
VPEAK
RMS ON → 2.37V
RMS OFF → 1.06V
O
SEGMENT ON
DCOM
O
SEGMENT OFF
2VPEAK
(VOLTAGE ACROSS ON SEGMENT)
O
VSEGMENT ON
-2VPEAK
VPEAK
VSEGMENT OFF
(VOLTAGE ACROSS OFF SEGMENT)
O
-VPEAK
FIGURE 11. DUPLEXED LCD DRIVE WAVEFORMS
8
ICL7149
Integrator Capacitor, ClNT
As with all dual-slope integrating convertors, the integration
capacitor must have low dielectric absorption to reduce linearity
errors. Polypropylene capacitors add undetectable errors at a
reasonable cost, while polystyrene and polycarbonate may be
used in less critical applications. The ICL7149 is designed to
use a 3.3nF (0.0033µF) ClNT with an oscillator frequency of
120kHz and an RlNTV of 10MΩ. With a 100kHz oscillator
frequency (for 50Hz line frequency rejection), ClNT and RINTV
affects the voltage swing of the integrator. Voltage swing should
be as high as possible without saturating the integrator.
Saturation occurs when the integrator output is within 1V of
either V+ or V-. Integrator voltage swing should be about ±2V
when using standard component values. For different RlNTV
and oscillator frequencies the value of ClNT can be calculated
from:
( Integrate Time ) × ( Integrate Current )
C I NT = ---------------------------------------------------------------------------------------------------( Desired Integrator Swing )
( 10,000 x 2 x Oscillator Period ) × 0.4V/R INTV
= ------------------------------------------------------------------------------------------------------------------------( 2V )
Integrator Resistors
The normal values of the RlNT V and RlNT l resistors are 10MΩ
and 1MΩ respectively. Though their absolute values are not
critical, unless the value of the current sensing resistors are
trimmed, their ratio should be 10:1, within 0.05%. Some carbon
composition resistors have a large voltage coefficient which will
cause linearity errors on the 400V scale. Also, some carbon
composition resistors are very noisy. The class “A” output of the
integrator begins to have nonlinearities if required to sink more
than 70µA (the sourcing limit is much higher). Because RlNT V
drives a virtual ground point, the input impedance of the meter
is equal to RlNT V .
Deintegration Resistor, RDElNT
Unlike most dual-slope A/D converters, the ICL7149 uses
different resistors for integration and deintegration. RDElNT
should normally be the same value as RlNT V , and have the
same temperature coefficient. Slight errors in matching may
be corrected by trimming the reference voltage.
Autozero Capacitor, CAZ
The CAZ is charged to the integrator’s offset voltage during the
autozero phases, and subtracts that voltage from the input
signal during the integrate phases. The integrator thus appears
to have zero offset voltage. Minimum CAZ value is determined
by: 1) Circuit leakages; 2) CAZ self-discharge; 3) Charge
injection from the internal autozero switches. To avoid errors,
the CAZ voltage change should be less than 1/10 of a count
during the 10,000 count clock cycle integration period for the
400mV range. These requirements set a lower limit of 0.047µF
for CAZ but 0.1µF is the preferred value. The upper limit on the
value of CAZ is set by the time constant of the autozero loop,
and the 1 line cycle time period allotted to autozero. CAZ may
be several 10s of µF before approaching this limit.
9
The ideal CAZ is a low leakage polypropylene or Teflon
capacitor. Other film capacitors such as polyester, polystyrene,
and polycarbonate introduce negligible errors. If a few seconds
of settling time upon power-up is acceptable, the CAZ may be a
ceramic capacitor, provided it does not have excessive
leakage.
Ohm Measurement Resistors
Because the ICL7149 uses a ratiometric ohm measurement
technique, the accuracy of ohm reading is primarily
determined by the absolute accuracy of the R KNOWN1 and
RKNOWN2 . These should normally be 10kΩ and 1MΩ, with
an absolute accuracy of at least 0.5%.
Current Sensing Resistors
The 0.1Ω and 9.9Ω current sensing resistors convert the
measured current to a voltage, which is then measured using
RlNT l. The two resistors must be closely matched, and the ratio
between RlNT l and these two resistors must be accurate normally 0.5%. The 0.1Ω resistor must be capable of handling
the full scale current of 4A, which requires it to dissipate 1.6W.
Continuity Beeper
The Continuity Beeper output is designed to drive a
piezoelectric transducer at 2kHz (using a 120kHz crystal), with
a voltage output swing of V+ to V-. The beeper output off state
is at the V+ rail. When crystals with different frequencies are
used, the frequency needed to drive the transducer can be
calculated by dividing the crystal frequency by 60.
Display
The ICL7149 uses a custom, duplexed drive display with
range, polarity, and low battery annunciators. With a 3V
peak display voltage, the RMS ON voltage will be 2.37V
minimum; RMS OFF voltage will be 1.06V maximum.
Because the display voltage is not adjustable, the display
should have a 10% ON threshold of about 1.4V. Most
display manufacturers supply a graph that shows contrast
versus RMS drive voltage. This graph can be used to
determine what the contrast ratio will be when driven by the
ICL7149. Most display thresholds decrease with increasing
temperature. The threshold at the maximum operating
temperature should be checked to ensure that the “off”
segments will not be turned “on” at high temperatures.
Crystal
The ICL7149 is designed to use a parallel resonant 120kHz
or 100kHz crystal with no additional external components.
The RS parameter should be less than 25kΩ to ensure
oscillation. Initial frequency tolerance of the crystal can be a
relatively loose 0.05%.
Switches
Because the logic input draws only about 5µA, switches
driving these inputs should be rated for low current, or “dry”
operations. The switches on the external inputs must be able
ICL7149
to reliably switch low currents, and be able to handle
voltages in excess of 400VAC .
Reference Voltage Source
A voltage divider connected to V+ and Common is the
simplest source of reference voltage. While minimizing
external component count, this approach will provide the
same voltage tempco as the ICL7149 Common - about
100PPM/oC. To improve the tempco, an ICL8069 bandgap
reference may be used (see Figure 12). The reference
voltage source output impedance must be ≤ R DElNT/4000.
V+
10M
TRIPLE POINT
10K
10M
DEINTEGRATE
EXTERNAL
REFERENCE
INTEGRATE VOLT /Ω
ICL8069
10K
1M
INTEGRATE CURRENT
REFERENCE INPUT
ANALOG COMMON
FIGURE 12. EXTERNAL VOLTAGE REFERENCE CONNECTION
Applications, Examples, and Hints
A complete autoranging 33/4 digit multimeter is shown in
Figure 13. The following sections discuss the functions of
specific components and various options.
Meter Protection
The ICL7149 and its external circuitry should be protected
against accidental application of 110/220V AC line voltages
on the Ω and current ranges. Without the necessary
precautions, the ICL7149 and its external components could
be damaged under such fault conditions. For the current
ranges, fast-blow fuses should be used between S5A in
Figure 13 and the 0.1Ω and 9.9Ω shunt resistors. For the Ω
ranges, no additional protection circuitry is required.
However, the 10kΩ resistor connected to pin 14 must be
able to dissipate 1.2W or 4.8W for short periods of time
during accidental application of 110V or 220V AC line
voltages respectively.
10
ICL7149
10MΩ
3.3nF
120kHz
CRYSTAL
0.1µF
20
INPUTS
V/Ω
V
S4A
Ω
A
µA
A
S5A
mA
30K50K
COMMON
V+ µA V+
V-
Ω
9.9Ω
22
29
30
ICL7149
LO BAT
AC
26
S4B
25
V-
COMMON
kΩMΩ
24
BEEPER
10
V+
+
ON/OFF
17
mAVµA
6, 8-9
31-44
+
1µF
0.1Ω
2W
V
A
21
TRIPLE CAZ CINT OSC OSC
OUT IN
POINT
16
DEINT
DISPLAY
10MΩ 19
DRIVE
INT V/Ω
OUTPUTS
10kΩ
14
LOΩ
1MΩ 15
HIΩ
BEEPER
1MΩ 18
INT I
V+
9V
BATTERY
S1
12
13
VREF
Ω/V/A
HIΩ-DC/LOΩ-AC
mA/µA
mA
HOLD
27
S3
V+
28
S3
V+
4.7µF +
10kΩ
TANT
10kΩ
ICL8069
PIN 17
S2 CLOSED: HIΩ-DC
S3 CLOSED: HOLD READING
NOTES:
1. Crystal is a Statek or SaRonix CX-IV type.
2. Multimeter protection components have not been shown.
3. Display is from LXD, part number 38D8R02H (or Equivalent).
4. Beeper is from muRata, part number PKM24-4A0 (or Equivalent).
FIGURE 13. BASIC MULTIMETER APPLICATION CIRCUIT
Printed Circuit Board Layout Considerations
Particular attention must be paid to rollover performance,
leakages, and guarding when designing the PCB for an
ICL7149-based multimeter.
16
17
18
19
20
21 22
FIGURE 14. PC BOARD LAYOUT
Rollover Performance, Leakages, and Guarding
Because the ICL7149 system measures very low currents, it
is essential that the PCB have low leakage. Boards should
be properly cleaned after soldering. Areas of particular
importance are: 1) The INT V/Ω and INT l Pins; 2) The Triple
Point; 3) The RDElNT and the CAZ pins.
11
The conversion scheme used by the ICL7149 changes the
common mode voltage on the integrator and the capacitors
CAZ and ClNT during a positive deintegrate cycle. Stray
capacitance to ground is charged when this occurs,
removing some of the charge on ClNT and causing rollover
error. Rollover error increases about 1 count for each
picofarad of capacitance between CAZ or the Triple Point
and ground, and is seen as a zero offset for positive
voltages. Rollover error is not seen as gain error.
The rollover error causes the width of the +0 count to be
larger than normal. The ICL7149 will thus read zero until
several hundred microvolts are applied in the positive
direction. The ICL7149 will read -1 when approximately
-100µV is applied.
The rollover error can be minimized by guarding the Triple
Point and CAZ nodes with a trace connected to the ClNT pin,
(see Figure 14) which is driven by the output of the
integrator. Guarding these nodes with the output of the
integrator reduces the stray capacitance to ground, which
ICL7149
minimizes the charge error on ClNT and C AZ . If possible, the
guarding should be used on both sides of the PC board.
Stray Pickup
While the ICL7149 has excellent rejection of line frequency
noise and pickup in the DC ranges, any stray coupling will
affect the AC reading. Generally, the analog circuitry should
be as close as possible to the ICL7149. The analog circuitry
should be removed or shielded from any 120V AC power
inputs, and any AC sources such as LCD drive waveforms.
Keeping the analog circuit section close to the ICL7149 will
also help keep the area free of any loops, thus reducing
magnetically coupled interference coming from power
transformers, or other sources.
12
ICL7149
Metric Plastic Quad Flatpack Packages (MQFP)
Q44.10x10 (JEDEC MS-022AB ISSUE B)
D
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
D1
-D-
INCHES
-A-
-B-
E E1
e
PIN 1
SEATING
A PLANE
-H-
0.40
0.016 MIN
-C-
12 o-16o
0.20 M C A-B S
0.008
0 o MIN
A2 A1
0o-7o
L
0.076
0.003
MAX
MIN
MAX
NOTES
-
0.096
-
2.45
-
A1
0.004
0.010
0.10
0.25
-
A2
0.077
0.083
1.95
2.10
-
b
0.012
0.018
0.30
0.45
6
b1
0.012
0.016
0.30
0.40
-
D
0.515
0.524
13.08
13.32
3
D1
0.389
0.399
9.88
10.12
4, 5
E
0.516
0.523
13.10
13.30
3
E1
0.390
0.398
9.90
10.10
4, 5
L
0.029
0.040
0.73
1.03
N
44
44
e
0.032 BSC
0.80 BSC
7
Rev. 2 4/99
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
b
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
7. “N” is the number of terminal positions.
BASE METAL
13
MIN
A
3. Dimensions D and E to be determined at seating plane -C- .
b1
WITH PLATING
SYMBOL
D S
0.13/0.17
0.005/0.007
12o-16o
MILLIMETERS
0.13/0.23
0.005/0.009
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