DATASHEET

IGNS
EW DES
N
R
O
F
NDED
EM ENT
COMME
R E PL AC
D
t
E
NO T R E
D
N
E
Center a
OMM
S u p p o rt
c
l
NO REC
s
a
/t
ic
m
n
o
h
c
tersil.c
our Te
contact ERSIL or www.in
T
N
88-I Sheet
Data
July 2004
1-8
VRM8.5 Dual PWM and Dual Linear Power
System Controller
The ISL6523 provides the power control and protection for
four output voltages in high-performance microprocessor
and computer applications. The IC integrates two PWM
controllers and two linear controllers, as well as the
monitoring and protection functions into a 28-pin SOIC
package. One PWM controller regulates the microprocessor
core voltage with a synchronous-rectified buck converter.
The second PWM controller supplies the computer system’s
AGTL+ 1.2V bus power with a standard buck converter. The
linear controllers regulate power for the 1.5V AGP bus and
the 1.8V power for the chipset core voltage and/or cache
memory circuits.
The ISL6523 includes an Intel VRM8.5 compatible, TTL 5input digital-to-analog converter (DAC) that adjusts the
microprocessor core-targeted PWM output voltage from
1.050V to 1.825V in 25mV steps. The precision reference
and voltage-mode control provide 1% static regulation. The
second PWM controller’s output provides a voltage level of
1.2V with 3% accuracy. The linear regulators use external
N-channel MOSFETs or bipolar NPN pass transistors to
provide fixed output voltages of 1.5V 3% (VOUT3) and 1.8V
3% (VOUT4).
The ISL6523 monitors all the output voltages. A delayedrising VTT (standard buck output) Power Good signal is
issued before the core PWM starts to ramp up. Another
system Power Good signal is issued when the core is within
10% of the DAC setting and all other outputs are above
their under- voltage levels. Additional built-in overvoltage
protection for the core output uses the lower MOSFET to
prevent output voltages above 115% of the DAC setting. The
PWM controllers’ overcurrent function monitors the output
current by using the voltage drop across the upper
MOSFET’s rDS(ON) , eliminating the need for a current
sensing resistor.
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
DWG. #
• Provides 4 Regulated Voltages
- Microprocessor Core, AGTL+ Bus, AGP Bus Power,
and North/South Bridge Core
• Drives N-Channel MOSFETs
• Linear Regulator Drives Compatible with both MOSFET
and Bipolar Series Pass Transistors
• Simple Single-Loop Control Designs
- Voltage-Mode PWM Control
• Fast PWM Converter Transient Response
- High-Bandwidth Error Amplifiers
- Full 0% to 100% Duty Ratios
• Excellent Output Voltage Regulation
- Core PWM Output . . . . . . . . . . 1% Over Temperature
- All Other Outputs 3% Over Temperature
• VRM8.5 TTL-Compatible 5-Bit DAC Microprocessor Core
Output Voltage Selection
- Wide Range . . . . . . . . . . . . . . . . . . . . 1.050V to 1.825V
• Power-Good Output Voltage Monitors
- Separate delayed VTT Power Good
• Overcurrent Fault Monitors
- Switching Regulators Do Not Require Extra Current
Sensing Elements, Use MOSFET’s rDS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Internal Oscillator
• Pb-free available
Applications
• Motherboard Power Regulation for Computers
Pinout
ISL6523 (SOIC)
TOP VIEW
UGATE2 1
28 VCC
PHASE2 2
27 UGATE1
VID3 3
26 PHASE1
VID2 4
25 LGATE1
VID1 5
24 PGND
VID0 6
23 OCSET1
0 to 70
28 Ld SOIC
M28.3
VID25 7
ISL6523CBZ
(See Note)
0 to 70
28 Ld SOIC
(Pb-free)
M28.3
PGOOD 8
Evaluation Board
*Add “-T” suffix to part number for tape and reel packaging.
1
22 VSEN1
21 FB1
VTTPG 9
20 COMP1
OCSET2 10
19 VSEN3
VSEN2 11
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
FN9024.2
Features
ISL6523CB
ISL6523EVAL1
ISL6523
18 DRIVE3
SS24 12
17 GND
SS13 13
16 VAUX
VSEN4 14
15 DRIVE4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001-2002, 2004. All Rights Reserved
OCSET2
OCSET1
VSEN1
VCC
-
+
VSEN3
VAUX
1.5V
EA3
-
DRIVE3
+
-
UV3
+
UV4
x0.75
POWER-ON
2
+
x 1.10
x0.75
+
DRIVE4
-
-
-
+
+
-
VCC
-
x 0.90
1.8V
PGOOD
200A
DRIVE2
UGATE2
200A
+
EA4
VSEN4
+
+
-
PHASE2
OC2
DRIVE1
SOFTSTART
& FAULT
LOGIC
UGATE1
OC1
-
+
FAULT
VSEN2
-
+
-
x0.90
+
1.2V
SET
VCC
-
PHASE1
GATE
CONTROL
+
EA1
-
PWM
COMP1
VCC
PWM1
SYNCH
DRIVE
28A
Q
CLK
Q
D
CLR
VTTPG
-
UV2
>
-
+
EA2
+
OSCILLATOR
4.5V
SS13
SS24
28A
DACOUT
TTL D/A
CONVERTER
(DAC)
4.5V
FB1
FIGURE 1. BLOCK DIAGRAM
COMP1
VID3 VID2 VID1 VID0 VID25
LGATE1
PGND
GND
ISL6523
VCC
OV
PWM
COMP2
PWM2
-
x 1.15
INHIBIT
GATE
CONTROL
+
VAUX
RESET (POR)
ISL6523
+5VIN
Q1
Q3
PWM2
CONTROLLER
VOUT2
VOUT1
PWM1
CONTROLLER
Q2
ISL6523
+3.3VIN
Q4
VOUT3
LINEAR
CONTROLLER
LINEAR
CONTROLLER
Q5
VOUT4
FIGURE 2. SIMPLIFIED POWER SYSTEM DIAGRAM
+12VIN
+5VIN
LIN
CIN
VCC
OCSET1
OCSET2
Q3
LOUT2
VOUT2
POWERGOOD
PGOOD
UGATE2
PHASE2
UGATE1
1.2V
Q1
LOUT1
PHASE1
COUT2
CR2
LGATE1
VSEN2
Q2
PGND
VSEN1
VTT POWERGOOD
VTTPG
ISL6523
VAUX
+3.3VIN
Q4
FB1
COMP1
DRIVE3
VOUT3
VSEN3
VID3
1.5V
VID2
COUT3
VID1
VID0
DRIVE4
Q5
VOUT4
VID25
VSEN4
SS13
1.8V
SS24
COUT4
CSS13
CSS24
GND
FIGURE 3. TYPICAL APPLICATION
3
COUT1
VOUT1
1.3V to 3.5V
ISL6523
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
PGOOD, RT/FAULT, DRIVE, PHASE, and
GATE Voltage. . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V
Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . GND -0.3V to 7V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, Note 1)
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10%
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for
details.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
9
-
mA
VCC SUPPLY CURRENT
Nominal Supply Current
ICC
UGATE1, LGATE1, UGATE2, DRIVE3, and
DRIVE4 Open
POWER-ON RESET
Rising VCC Threshold
-
-
10.4
V
Falling VCC Threshold
8.2
-
-
V
Rising VAUX Threshold
-
2.5
-
V
VAUX Threshold Hysteresis
-
0.5
-
V
Rising VOCSET1 Threshold
-
1.26
-
V
FOSC
185
200
215
kHz
VOSC
-
1.9
-
VP-P
0.8
V
%
OSCILLATOR
Free Running Frequency
Ramp Amplitude
DAC AND STANDARD BUCK REGULATOR REFERENCE
DAC (VID25-VID3) Input Low Voltage
DAC (VID25-VID3) Input High Voltage
2.0
DACOUT Voltage Accuracy
-1.0
-
+1.0
V
PWM2 Regulation Voltage
-
1.2
-
V
PWM2 Regulation Voltage Tolerance
-
3
-
%
-
3
-
%
1.5V AND 1.8V LINEAR REGULATORS (VOUT3 AND VOUT4)
Regulation Tolerance
VSEN3 Regulation Voltage
VREG3
-
1.5
-
V
VSEN4 Regulation Voltage
VREG4
-
1.8
-
V
-
75
-
VSEN3,4UV VSEN3,4 Rising
VSEN3,4 Under-Voltage Level
VSEN3 Under-Voltage Hysteresis
VSEN3 Falling
Output Drive Current
VAUX-VDRIVE3,4 > 0.6V
7
20
40
%
%
-
mA
SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
GBWP
Slew Rate
SR
Note 2
-
88
-
dB
Note 2
-
15
-
MHz
COMP1 = 10pF, Note 2
-
6
-
V/s
VCC = 12V, VUGATE1 (or VUGATE2) = 6V
-
1
-
A
PWM CONTROLLERS GATE DRIVERS
UGATE1,2 Source
IUGATE
4
ISL6523
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
UGATE1,2 Sink
RUGATE
VGATE-PHASE = 1V
-
1.7
3.5

LGATE Source
ILGATE
VCC = 12V, VLGATE1 = 1V
-
1
-
A
LGATE Sink
RLGATE
VLGATE = 1V
-
1.4
3.0

OCSET1,2 Current Source
IOCSET
VOCSET = 4.5VDC
170
200
230
A
Soft-Start Current
ISS13,24
VSS13,24 = 2.0VDC
-
28
-
A
PROTECTION
POWER GOOD
VSEN1 Upper Threshold
(VSEN1/DACOUT)
VSEN1 Rising
108
-
110
%
VSEN1 Under-Voltage
(VSEN1/DACOUT)
VSEN1 Rising
92
-
94
%
VSEN1 Hysteresis (VSEN1/DACOUT)
VSEN1 Falling
-
2
-
%
IPGOOD = -4mA
-
-
0.8
PGOOD Voltage Low
VPGOOD
VSEN2 Under-Voltage
VSEN2 Rising
VSEN2 Hysteresis
VTTPG Voltage Low
VVTTPG
1.00
V
V
VSEN2 Falling
-
60
-
mV
IVTTPG = -4mA
-
-
0.8
V
NOTE:
2. Guaranteed by design
PGND (Pin 24)
Typical Performance Curve
140
This is the power ground connection. Tie the synchronous
PWM converter’s lower MOSFET source to this pin.
VAUX (Pin 16)
CUGATE1 = CUGATE2 = CLGATE1 = C
120
C = 4800pF
VIN = 5V
Connect this pin to the ATX 3.3V output. The voltage present
at this pin is monitored for sequencing purposes. This pin
provides the necessary base bias for the NPN pass
transistors, as well as the current sunk through the 5k VID
pull-up resistors.
VCC = 12V
ICC (mA)
100
80
C = 3600pF
SS13 (Pin 13)
60
C = 1500pF
40
20
0
100
C = 660pF
200
300
400
500
600
700
800
900
1000
SWITCHING FREQUENCY (kHz)
FIGURE 4. BIAS SUPPLY CURRENT vs FREQUENCY
Functional Pin Descriptions
VCC (Pin 28)
Provide a 12V bias supply for the IC to this pin. This pin also
provides the gate bias charge for all the MOSFETs
controlled by the IC. The voltage at this pin is monitored for
Power-On Reset (POR) purposes.
GND (Pin 17)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
5
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28A current source, sets the soft-start
interval of the synchronous switching converter (VOUT1) and
the AGP regulator (VOUT3). A VTTPG high signal is also
delayed by the time interval required by the charging of this
capacitor from 0V to 1.25V (see Soft-Start details).
SS24 (Pin 12)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28A current source, sets the soft-start
interval of the standard buck converter. Pulling this pin below
0.8V induces a chip reset (POR) and shutdown.
VTTPG (Pin 9)
VTTPG is an open collector output used to indicate the
status of the standard buck regulator output voltage. This pin
is pulled low when the output is below the under-voltage
threshold or when the SS13 pin is below 1.25V.
ISL6523
PGOOD (Pin 8)
VSEN1 (Pin 22)
PGOOD is an open collector output used to indicate the
status of the output voltages. This pin is pulled low when the
synchronous regulator output is not within 10%of the
DACOUT reference voltage or when any of the other outputs
is below its under-voltage threshold.
This pin is connected to the synchronous PWM converters’
output voltage. The PGOOD and OVP comparator circuits
use this signal to report output voltage status.
VID3, VID2, VID1, VID0, VID25 (Pins 3-7)
VID3-25 are the TTL-compatible input pins to the 5-bit DAC.
The logic states of these five pins program the internal
voltage reference (DACOUT). The level of DACOUT sets the
microprocessor core converter output voltage (VOUT1), as
well as the corresponding PGOOD and OVP thresholds.
Each VID pin is connected to the VAUX pin through a 5k
pull-up resistor.
OCSET1, OCSET2 (Pins 23, 10)
Connect a resistor (ROCSET) from one of these pins to the
drain of the corresponding upper MOSFET. ROCSET, an
internal 200A current source (IOCSET), and the upper
MOSFET’s on-resistance (rDS(ON)) set the converter overcurrent (OC) trip point according to the following equation:
I OCSET  R OCSET
I PEAK = ---------------------------------------------------r DS  ON 
VSEN2 (Pin 11)
Connect this pin to the output of the standard buck PWM
regulator. The voltage at this pin is regulated to a 1.5V level.
This pin is also monitored for under-voltage events.
DRIVE3 (Pin 18)
Connect this pin to the gate/base of a N-type external pass
transistor (MOSFET or bipolar). This pin provides the drive
for the 1.5V regulator’s pass transistor.
VSEN3 (Pin 19)
Connect this pin to the output of the 1.5V linear regulator.
This pin is monitored for undervoltage events.
DRIVE4 (Pin 15)
Connect this pin to the base of an external bipolar transistor.
This pin provides the drive for the 1.8V regulator’s pass
transistor.
VSEN4 (Pin 14)
Connect this pin to the output of the linear 1.8V regulator.
This pin is monitored for undervoltage events.
An overcurrent trip cycles the soft-start function.
The voltage at OCSET1 pin is monitored for power-on reset
(POR) purposes.
PHASE1, PHASE2 (Pins 26, 2)
Connect the PHASE pins to the respective PWM converter’s
upper MOSFET sources. These pins represent the gate
drive return current path and are used to monitor the voltage
drop across the upper MOSFETs for overcurrent protection.
UGATE1, UGATE2 (Pins 27, 1)
Connect UGATE pins to the respective PWM converters’
upper MOSFET gate. These pins provide the gate drive for
the upper MOSFETs.
LGATE1 (Pin 25)
Connect LGATE1 to the synchronous PWM converter’s
lower MOSFET gate. This pin provides the gate drive for the
lower MOSFET.
COMP1 and FB1 (Pins 20, 21)
COMP1 and FB1 are the available external pins of the
synchronous PWM regulator error amplifier. The FB1 pin is
the inverting input of the error amplifier. Similarly, the
COMP1 pin is the error amplifier output. These pins are used
to compensate the voltage-mode control feedback loop of
the synchronous PWM converter.
6
Description
Operation
The ISL6523 monitors and precisely controls 4 output voltage
levels (Refer to Figures 1, 2, 3). It is designed for
microprocessor computer applications with 3.3V, 5V, and 12V
bias input from an ATX power supply. The IC has 2 PWM and
two linear controllers. The first PWM controller (PWM1) is
designed to regulate the microprocessor core voltage (VOUT1).
PWM1 controller drives 2 MOSFETs (Q1 and Q2) in a
synchronous-rectified buck converter and regulates the core
voltage to a level programmed by the 5-bit digital-to-analog
converter (DAC). The second PWM controller (PWM2) is
designed to regulate the AGTL+ bus voltage (VOUT2). PWM2
controller drives a MOSFET (Q3) in a standard buck converter
and regulates the output voltage to a level of 1.2V. The two
linear controllers supply the 1.5V advanced graphics port
(AGP) bus power (VOUT3) and the 1.8V chipset core power
(VOUT4).
Initialization
The ISL6523 automatically initializes in ATX-based systems
upon receipt of input power. The Power-On Reset (POR)
function continually monitors the input supply voltages. The
POR monitors the bias voltage (+12VIN) at the VCC pin, the
5V input voltage (+5VIN) at the OCSET1 pin, and the 3.3V
input voltage (+3.3VIN) at the VAUX pin. The normal level on
OCSET1 is equal to +5VIN less a fixed voltage drop (see
ISL6523
overcurrent protection). The POR function initiates soft-start
operation after all supply voltages exceed their POR
thresholds.
Soft-Start
The 1.8V supply designed to power the chipset (OUT4), cannot
lag the ATX 3.3V by more than 2V, at any time. To meet this
special requirement, the linear block controlling this output
operates independently of the chip’s power-on reset. Thus,
DRIVE4 is driven to raise the OUT4 voltage before the input
supplies reach their POR levels. As seen in Figure 5, at time T0
the power is turned on and the input supplies ramp up.
Immediately following, OUT4 is also ramped up, lagging the
ATX 3.3V by about 1.8V. At time T1, the POR function initiates
the SS24 soft-start sequence. Initially, the voltage on the SS24
pin rapidly increases to approximately 1V (this minimizes the
soft-start interval). Then, an internal 28A current source
charges an external capacitor (CSS24) on the SS24 pin to
about 4.5V. As the SS24 voltage increases, the PWM2 error
amplifier allows generation of PHASE pulses of increasing
width that charge the output capacitor(s), providing a smooth
transition to the final set voltage. The OUT4 reference (clamped
to SS24) increasing past the intermediary level, established
based on the ATX 3.3V presence at the VAUX pin, brings the
output in regulation soon after T2.
ATX 12V
10V
VTTPG
SS13
ATX 5V
SS24
PGOOD
0V
3.0V
ATX 3.3V
VOUT1 (1.65V)
VOUT4 (1.8V)
VOUT2 (1.2V)
VOUT3 (1.5V)
0V
T0
T1
T2
T3
T4 T5
TIME
FIGURE 5. SOFT-START INTERVAL
As OUT2 increases past the 90% power-good level, the second
soft-start (SS13) is released. Between T2 and T3, the SS13
pin voltage ramps from 0V to the valley of the oscillator’s
triangle wave (at 1.25V). Contingent upon OUT2 remaining
7
above 1.08V, the first PWM pulse on PHASE1 triggers the
VTTPG pin to go high. The oscillator’s triangular wave form
is compared to the clamped error amplifier output voltage.
As the SS13 pin voltage increases, the pulse-width on the
PHASE1 pin increases, bringing the OUT1 output within
regulation limits. Similarly, the SS13 voltage clamps the
reference voltage for OUT3, enabling a controlled output
voltage ramp-up. At time T4, all output voltages are within
power-good limits, situation reported by the PGOOD pin
going high.
The T2 to T3 time interval is dependent upon the value of
CSS13. The same capacitor is also responsible for the rampup time of the OUT1 and OUT3 voltages. If selecting a
different capacitor then recommended in the circuit application
literature, consider the effects the different value will have on
the ramp-up time and inrush currents of the OUT1 and OUT3
outputs.
Fault Protection
All four outputs are monitored and protected against extreme
overload. The chip’s response to an output overload is
selective, depending on the faulting output.
An overvoltage on VOUT1 output (VSEN1) disables outputs
1, 2, and 3, and latches the IC off. An under-voltage on
VOUT4 output latches the IC off. A single overcurrent event
on outputs 1 or 2, or an under-voltage event on output 3,
increments the respective fault counter and triggers a
shutdown of outputs 1, 2, and 3, followed by a soft-start restart. After three consecutive fault events on either counter,
the chip is latched off. Removal of bias power resets both the
fault latch and the counters. Both counters are also reset by
a successful start-up of all the outputs.
Figure 6 shows a simplified schematic of the fault logic. The
overcurrent latches are set dependent upon the states of the
overcurrent (OC1 and OC2), output 3 under-voltage (UV3)
and the soft-start signals (SS13, SS24). Window
comparators monitor the SS pins and indicate when the
respective CSS pins are fully charged to above 4.0V (UP
signals). An under-voltage on either linear output (VSEN3 or
VSEN4) is ignored until the respective UP signal goes high.
This allows VOUT3 and VOUT4 to increase without fault at
start-up. Following an overcurrent event (OC1, OC2, or UV3
event), bringing the SS24 pin below 0.8V resets the
ISL6523
overcurrent latch and generates a soft-started ramp-up of
the outputs 1, 2, and 3.
FAULT
LATCH
SS13UP
OC
LATCH
INHIBIT1,2,3
S Q
0.8V
COUNT
=3
S Q
SS24UP
POR
R Q
OV
R
UV4
2V
0V
FAULT
LATCH
SS24
4V
COUNT
=2
4V
R
SS13
0
COUNT
=1
COUNTER
4V
CHIP
DISABLED
1
SSDOWN
>
R
SS24
SS13
OC1
FAULT
>
COUNTER
R
INDUCTOR CURRENT
UV3
OC2
above 4.0V at T4 and the counter increments to 3. This sets
the fault latch to disable the converter.
OVERLOAD
APPLIED
0A
T0 T1
S Q
OC
LATCH
FIGURE 6. FAULT LOGIC - SIMPLIFIED SCHEMATIC
OUT1 Overvoltage Protection
The overvoltage circuit provides protection during the initial
application of power. For voltages on the VCC pin below the
power-on reset (and above ~4V), the output level is
monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2, is driven on.
Overcurrent Protection
All outputs are protected against excessive overcurrents.
Both PWM controllers use the upper MOSFET’s onresistance, rDS(ON) to monitor the current for protection
against shorted outputs. Both linear regulators monitor their
respective VSEN pins for under-voltage to protect against
excessive currents.
Figure 7 illustrates the overcurrent protection with an overload
on OUT2. The overload is applied at T0 and the current
increases through the inductor (LOUT2). At time T1, the OC2
comparator trips when the voltage across Q3 (iD • rDS(ON))
exceeds the level programmed by ROCSET. This inhibits
outputs 1, 2, and 3, discharges soft-start capacitor CSS24 with
28A current sink, and increments the counter. Soft-start
capacitor CSS13 is quickly discharged. CSS24 recharges at T2
and initiates a soft-start cycle with the error amplifiers clamped
by soft-start. With OUT2 still overloaded, the inductor current
increases to trip the overcurrent comparator. Again, this
inhibits the outputs, but the soft-start voltage continues
increasing to above 4.0V before discharging. The counter
increments to 2. The soft-start cycle repeats at T3 and trips
the overcurrent comparator. The SS pin voltage increases to
T2
TIME
T3
T4
FIGURE 7. OVERCURRENT OPERATION
The PWM1 controller operates in the same way as PWM2 to
overcurrent faults. Additionally, the two linear controllers
monitor the VSEN pins for under-voltage. Should excessive
currents cause VSEN3 or VSEN4 to fall below the linear
under-voltage threshold, the respective UV signals set the
OC latch or the FAULT latch, providing respective CSS
capacitors are fully charged. Blanking the UV signals during the
CSS charge interval allows the linear outputs to build above
the under-voltage threshold during normal operation. Cycling
the bias input power off then on resets the counter and the
fault latch.
Resistors (ROCSET1 and ROCSET2) program the overcurrent
trip levels for each PWM converter. As shown in Figure 8, the
internal 200A current sink (IOCSET) develops a voltage across
ROCSET (VSET) that is referenced to VIN . The DRIVE signal
enables the overcurrent comparator (OVERCURRENT1 or
OVERCURRENT2). When the voltage across the upper
MOSFET (VDS(ON)) exceeds VSET, the overcurrent
comparator trips to set the overcurrent latch. Both VSET and
VDS are referenced to VIN and a small capacitor across
ROCSET helps VOCSET track the variations of VIN due to
MOSFET switching. The overcurrent function will trip at a peak
inductor current (IPEAK) determined by:
I OCSET  R OCSET
I PEAK = ---------------------------------------------------r DS  ON 
The OC trip point varies with MOSFET’s rDS(ON)
temperature variations. To avoid overcurrent tripping in the
normal operating load range, determine the ROCSET
resistor value from the equation above with:
1. The maximum rDS(ON) at the highest junction temperature
2. The minimum IOCSET from the specification table
8
ISL6523
3. Determine IPEAK for IPEAK > IOUT(MAX) + (I) / 2,
where I is the output inductor ripple current.
TABLE 1. OUT1 OUTPUT VOLTAGE PROGRAM (Continued)
VID3
VID2
VID1
VID0
VID25
NOMINAL
DACOUT
VOLTAGE
1
1
1
0
0
1.350
1
1
1
0
1
1.375
1
1
0
1
0
1.400
1
1
0
1
1
1.425
1
1
0
0
0
1.450
1
1
0
0
1
1.475
1
0
1
1
0
1.500
1
0
1
1
1
1.525
1
0
1
0
0
1.550
1
0
1
0
1
1.575
1
0
0
1
0
1.600
1
0
0
1
1
1.625
1
0
0
0
0
1.650
1
0
0
0
1
1.675
0
1
1
1
0
1.700
0
1
1
1
1
1.725
0
1
1
0
0
1.750
OUT1 Voltage Program
0
1
1
0
1
1.775
The output voltage of the PWM1 converter is programmed to
discrete levels between 1.050V and 1.825V. This output
(OUT1) is designed to supply the core voltage of Intel’s
advanced microprocessors. The voltage identification (VID)
pins program an internal voltage reference (DACOUT) with a
TTL-compatible 5-bit digital-to-analog converter (DAC). The
level of DACOUT also sets the PGOOD and OVP thresholds.
Table 1 specifies the DACOUT voltage for the different
combinations of connections on the VID pins. The VID pins
can be left open for a logic 1 input, since they are internally
pulled to the VAUX pin through 5k resistors. Changing the
VID inputs during operation is not recommended and could
toggle the PGOOD signal and exercise the overvoltage
protection. The output voltage program is Intel VRM8.5
compatible.
0
1
0
1
0
1.800
0
1
0
1
1
1.825
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
OVERCURRENT TRIP:
V
>V
DS
SET
i r
>I
 R OCSET
D
DS  ON  OCSET
OCSET
IOCSET
200A
OVERCURRENT
OC
VIN = +5V
ROCSET
VSET +
VCC
UGATE
DRIVE
iD
+
VDS
+
-
PHASE
GATE
CONTROL
PWM
V
= V –V
PHASE
IN
DS
V OCSET = V IN – V SET
FIGURE 8. OVERCURRENT DETECTION
TABLE 1. OUT1 OUTPUT VOLTAGE PROGRAM
PIN NAME
VID3
VID2
VID1
VID0
VID25
NOMINAL
DACOUT
VOLTAGE
0
1
0
0
0
1.050
0
1
0
0
0
1.050
0
1
0
0
1
1.075
0
0
1
1
0
1.100
0
0
1
1
1
1.125
0
0
1
0
0
1.150
0
0
1
0
1
1.175
0
0
0
1
0
1.200
0
0
0
1
1
1.225
0
0
0
0
0
1.250
0
0
0
0
1
1.275
1
1
1
1
0
1.300
1
1
1
1
1
1.325
9
PIN NAME
NOTE: 0 = connected to GND, 1 = open or connected to 3.3V
through pull-up resistors
Application Guidelines
Soft-Start Interval
Initially, the soft-start function clamps the error amplifier’s output
of the PWM converters. This generates PHASE pulses of
increasing width that charge the output capacitor(s). The
resulting output voltages start-up as shown in Figure 5.
The soft-start function controls the output voltage rate of rise
to limit the current surge at start-up. The soft-start interval
and the surge current are programmed by the soft-start
capacitor, CSS. Programming a faster soft-start interval
increases the peak surge current. Using the recommended
0.1F soft start capacitors ensure all output voltages ramp
up to their set values in a quick and controlled fashion, while
meeting the system timing requirements.
Shutdown
Neither PWM output switches until the soft-start voltage
(VSS) exceeds the oscillator’s valley voltage. Additionally,
the reference on each linear’s amplifier is clamped to the
soft-start voltage. Holding the SS24 pin low (with an open
drain or open collector signal) turns off regulators 1, 2 and 3.
Regulator 4 (MCH) will simply drop its output to the
intermediate soft-start level. This output is not allowed to
violate the 2V maximum potential gap to the ATX 3.3V
output.
ISL6523
The power components and the controller IC should be
placed first. Locate the input capacitors, especially the highfrequency ceramic de-coupling capacitors, close to the
power switches. Locate the output inductor and output
capacitors between the MOSFETs and the load. Locate the
PWM controller close to the MOSFETs.
The critical small signal components include the bypass
capacitor for VCC and the soft-start capacitor, CSS. Locate
these components close to their connecting pins on the
control IC. Minimize any leakage current paths from any SS
node, since the internal current source is only 28A.
A multi-layer printed circuit board is recommended. Figure 9
shows the connections of the critical components in the
converter. Note that the capacitors CIN and COUT each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. The
power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the PHASE nodes, but do not
unnecessarily oversize these particular islands. Since the
PHASE nodes are subjected to very high dV/dt voltages, the
stray capacitor formed between these islands and the
surrounding circuitry will tend to couple switching noise. Use
the remaining printed circuit layers for small signal wiring.
10
CIN
+12V
COCSET2
ROCSET2
Q3
VOUT2
COCSET1
ROCSET1
UGATE2
Q1
UGATE1
PHASE2
LOUT2
COUT2
CVCC
VCC GND
OCSET2
OCSET1
LOUT1
VOUT1
PHASE1
CR2
VOUT3
CSS24,13
LGATE1
CR1
Q2
ISL6523
COUT3
VOUT4
DRIVE3 DRIVE4
Q4
PGND
LOAD
COUT1
SS24
SS13
COUT4
Q5
LOAD
There are two sets of critical components in a DC-DC
converter using an ISL6523 controller. The switching power
components are the most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
LIN
+5VIN
LOAD
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turn-off
transition of the upper MOSFET. Prior to turn-off, the upper
MOSFET was carrying the full load current. During the turnoff, current stops flowing in the upper MOSFET and is picked
up by the lower MOSFET or Schottky diode. Any inductance
in the switched current path generates a large voltage spike
during the switching interval. Careful component selection,
tight layout of the critical components, and short, wide circuit
traces minimize the magnitude of voltage spikes.
The wiring traces from the control IC to the MOSFET gate
and source should be sized to carry 2A peak currents.
LOAD
Layout Considerations
+3.3VIN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA/THROUGH-HOLE CONNECTION TO GROUND PLANE
FIGURE 9. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
PWM1 Controller Feedback Compensation
Both PWM controllers use voltage-mode control for output
regulation. This section highlights the design consideration
for a voltage-mode controller requiring external
compensation. Apply these methods and considerations
only to the synchronous PWM controller. The considerations
for the standard PWM controller are presented separately.
ISL6523
Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The
reference voltage level is the DAC output voltage (DACOUT)
for PWM1. The error amplifier output (VE/A) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of VIN at the PHASE node.
The PWM wave is smoothed by the output filter (LO and CO)..
VIN
OSC
LO
+
PHASE
CO
ZIN
+
ERROR
AMP
VOUT
ESR
(PARASITIC)
ZFB
REFERENCE
DETAILED COMPENSATION COMPONENTS
ZFB
C2
C1
C3
R3
R1
COMP
FB
+
ISL6523
VOUT
ZIN
R2
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
1
F Z1 = ----------------------------------2  R 2  C1
1
F P1 = ------------------------------------------------------C1  C2
2  R 2   ----------------------
 C1 + C2
1
F Z2 = ------------------------------------------------------2   R1 + R3   C3
1
F P2 = ----------------------------------2  R 3  C3
Figure 11 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 11. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at FP2 with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 11 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of VOUT /VE/A. This function is dominated by a DC
Gain, given by VIN /VOSC , and shaped by the output filter, with
a double pole break frequency at FLC and a zero at FESR .
Modulator Break Frequency Equations
1
F ESR = ----------------------------------------2  ESR  C O
The compensation network consists of the error amplifier
(internal to the ISL6523) and the impedance networks ZIN and
ZFB . The goal of the compensation network is to provide a
closed loop transfer function with high 0dB crossing frequency
(f0dB) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f0dB and 180o
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 10. Use these guidelines for locating the poles
and zeros of the compensation network:
11
FZ2
FP1
FP2
OPEN LOOP
ERROR AMP GAIN
 V IN 
20 log  ------------------
 V P – P
80
DACOUT
1
F LC = ---------------------------------------2  L O  C O
FZ1
100
60
GAIN (dB)
VE/A
DRIVER
2. Place 1STZero Below Filter’s Double Pole (~75% FLC)
Compensation Break Frequency Equations
DRIVER
PWM
COMP
VOSC
1. Pick Gain (R2/R1) for desired converter bandwidth
COMPENSATION
GAIN
40
20
0
-20
-40
-60
R2
20 log  --------
 R1
MODULATOR
GAIN
10
100
FLC
1K
CLOSED LOOP
GAIN
FESR
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45 degrees. Include worst case component variations when
determining phase margin.
PWM2 Controller Feedback Compensation
To reduce the number of external small-signal components
required by a typical application, the standard PWM
controller is internally stabilized. The only stability criteria
that needs to be met relates the minimum value of the output
ISL6523
inductor to the equivalent ESR of the output capacitor bank,
as shown in the following equation:
1.75
ESR OUT  10
L OUT  MIN  = -----------------------------------------------2    BW
where
LOUT(MIN) - minimum output inductor value at full output
current
ESROUT - equivalent ESR of the output capacitor bank
BW - desired converter bandwidth (not to exceed 0.25 to
0.30 of the switching frequency)
The design procedure for this output should follow the
following steps:
1. Choose number and type of output capacitors to meet the
output transient requirements based on the dynamic
loading characteristics of the output.
2. Determine the equivalent ESR of the output capacitor
bank and calculate minimum output inductor value.
3. Verify that chosen inductor meets this minimum value
criteria (at full output load). It is recommended the
chosen output inductor be no more than 30% saturated
at full output load.
Oscillator Synchronization
The PWM controllers use a triangle wave for comparison
with the error amplifier output to provide a pulse-width
modulated signal. Should the output voltage of the two
converters be programmed close to each other, then crosstalk between the converters could cause non-uniform
PHASE pulse-widths and increased output voltage ripple.
The ISL6523 avoids this problem by synchronizing the two
converters 180o out of phase.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output capacitor
to filter the current ripple. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
PWM Output Capacitors
Modern microprocessors produce transient load rates
above 1A/ns. High frequency capacitors initially supply the
transient current and slow the load rate-of-change seen by
the bulk capacitors. The bulk filter capacitor values are
generally determined by the ESR (effective series
resistance) and voltage rating requirements rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
12
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage and
the initial voltage drop following a high slew-rate transient’s
edge. An aluminum electrolytic capacitor’s ESR value is
related to the case size with lower ESR available in larger
case sizes. However, the equivalent series inductance (ESL)
of these capacitors increases with case size and can reduce
the usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter. Work
with your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Linear Output Capacitors
The output capacitors for the linear regulators provide
dynamic load current. Thus capacitors COUT3 and COUT4
should be selected for transient load regulation.
PWM Output Inductor Selection
Each PWM converter requires an output inductor. The output
inductor is selected to meet the output voltage ripple
requirements and sets the converter’s response time to a
load transient. Additionally, PWM2 output inductor has to
meet the minimum value criteria for loop stability as
described in paragraph ‘PWM2 Controller Feedback
Compensation’. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
V IN – V OUT V OUT
I = --------------------------------  ---------------FS  L
V IN
V OUT = I  ESR
Increasing the value of inductance reduces the ripple current
and voltage. However, large inductance values increase the
converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6523 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
current value to the post-transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor(s). Minimizing the response time can minimize the
output capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
ISL6523
equations give the approximate response time interval for
application and removal of a transient load:
L O  I TRAN
t RISE = -------------------------------V IN – V OUT
L O  I TRAN
t FALL = ------------------------------V OUT
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. Be sure to check both
of these equations at the minimum and maximum output
levels for the worst case response time.
Input Capacitor Selection
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage. The maximum RMS current rating
requirement for the input capacitors of a buck regulator is
approximately 1/2 of the DC output load current. Worst-case
RMS current draw in a circuit employing the ISL6523
amounts to the largest RMS current draw of either switching
regulator (likely the RMS of VOUT1). Operating at 180o outof-phase, the input-side RMS current of both switchers is
less than the arithmetical sum of individual RMS input
currents.
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors can be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.
For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MV-GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
design factors. The power dissipation includes two main loss
components: conduction losses and switching losses. These
losses are distributed between the upper and lower MOSFETs
according to the duty factor. The conduction losses are the
main component of power dissipation for the lower MOSFETs.
Only the upper MOSFET has significant switching losses, since
the lower device turns on and off into near zero voltage.
The equations presented assume linear voltage-current
transitions and do not model power losses due to the lower
MOSFET’s body diode or the output capacitances
associated with either MOSFET. The gate charge losses are
dissipated by the controller IC (ISL6523) and do not
contribute to the MOSFETs’ heat rise. Ensure that both
MOSFETs are within their maximum junction temperature at
high ambient temperature by calculating the temperature
rise according to package thermal resistance specifications.
A separate heatsink may be necessary depending upon
MOSFET power, package type, ambient temperature and air
flow.
2
I O  r DS  ON   V OUT I O  V IN  t SW  F S
P UPPER = ------------------------------------------------------------ + ---------------------------------------------------V IN
2
2
I O  r DS  ON    V IN – V OUT 
P LOWER = --------------------------------------------------------------------------------V IN
The rDS(ON) is different for the two equations above even if
the same device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 12 shows the gate drive where the
upper MOSFET’s gate-to-source voltage is approximately
VCC less the input supply. For +5V main power and +12VDC
for the bias, the approximate gate-to-source voltage of Q1 is
7V. The lower gate drive voltage is 12V. A logic-level
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if its absolute gate-to-source voltage rating
exceeds the maximum voltage applied to VCC .
VCC
ISL6523
UGATE
PWM1 MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the dominant
13
Q1
PHASE
MOSFET Selection/Considerations
The ISL6523 requires 5 external transistors. Three
N-channel MOSFETs are employed by the PWM converters.
The AGP and memory linear controllers can each drive a
MOSFET or a NPN bipolar as a pass transistor. All these
transistors should be selected based upon rDS(ON) , current
gain, saturation voltages, gate supply requirements, and
thermal management considerations.
+5V OR LESS
+12V
-
+
LGATE
PGND
NOTE:
VGS VCC -5V
Q2
CR1
NOTE:
VGS VCC
GND
FIGURE 12. UPPER GATE DRIVE - DIRECT VCC DRIVE
Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the lower
ISL6523
MOSFET and the turn on of the upper MOSFET. For best
results, the diode must be a surface-mount Schottky type to
prevent the parasitic MOSFET body diode from conducting. It
is acceptable to omit the diode and let the body diode of the
lower MOSFET clamp the negative inductor swing, but one
must ensure the PHASE node negative voltage swing does
not exceed -3V to -5V peak. The diode's rated reverse
breakdown voltage must be equal or greater to 1.5 times the
maximum input voltage.
PWM2 MOSFET and Schottky Selection
The power dissipation in PWM2 converter is similar to
PWM1 except that the power losses of the lower device are
dissipated in the Schottky. The equations below describe an
approximation of this power loss distribution and assume
linear voltage-current switching transitions.
2
I O  r DS  ON   V OUT I O  V IN  t SW  F S
P MOS = ------------------------------------------------------------ + ---------------------------------------------------V IN
2
I O  V f   V IN – V OUT 
P SCH = ------------------------------------------------------------V IN
Linear Controllers Transistor Selection
The ISL6523 linear controllers are compatible with both NPN
bipolar as well as N-channel MOSFET transistors. The main
criteria for selection of pass transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is
P LINEAR = I O   V IN – V OUT 
Select a package and heatsink that maintains the junction
temperature below the maximum desired temperature with
the maximum expected ambient temperature.
When selecting bipolar NPN transistors for use with the
linear controllers, insure the current gain at the given
operating VCE is sufficiently large to provide the desired
output load current when the base is fed with the minimum
driver output current.
In order to ensure the strict timing/level requirement of
OUT4, an NPN transistor is recommended for use as a pass
element on this output (Q5). An low gate threshold NMOS
could be used, but meeting the requirements would then
depend on the VCC bias being sufficiently high to allow
control of the MOSFET.
14
ISL6523
memory controller hub voltage (VOUT4) from +3.3V, +5VDC,
and +12VDC. For detailed information on the circuit,
including a Bill-of-Materials and circuit board description, see
Application Note AN9925. Also see the Intersil web page
(www.intersil.com) for the latest information.
ISL6523 DC-DC Converter Application
Circuit
Figure 13 shows an application circuit of a power supply for
a microprocessor computer system. The power supply
provides the microprocessor core voltage (VOUT1), the AGP
bus voltage (VOUT2), the GTL bus voltage (VOUT3), and the
+5V
L1
1H
+
+12V
C1
680F
+3.3V
GND
GND
GND
C2
1F
C3
1nF
C5
1F
C4
1nF
VCC
R2
2.2k
UGATE2
2.0H
+1.2V
+
PHASE2
C7
1000F
R3
OCSET1 1.5k
1
2
PHASE1
9
POWER GOOD
VAUX
C15
10F
Q4
HUF76107
+1.5V
VSEN3
+
7
17
C21
560F
GND
43k
VID3
SS24
SS13
13
C22
0.1F
FIGURE 13.
15
2.2nF
VID2
12
14
R11
VID1
3
VSEN4
C16
VID0
6
15
C13
270pF
VID25
4
VOUT4 (MCH)
+
COMP1
5
DRIVE4
C8-10
3x1000F
3.32k
18
19
+
C12
0.30F
R8
FB1
21
20
16
C18
560F
Q5
2SD1802
+1.8V
VSEN1
+
DRIVE3
VOUT3 (AGP)
U1
ISL6523
1.8H
R5
4.99k
PGND
22
VTTPG
Q2
HUF76143
LGATE1
24
R7
10k
VOUT1 (CORE)
+1.050V TO 1.825V
L3
26
11
Q1
HUF76139
UGATE1
27
25
VTT
POWER GOOD
PGOOD
CR1
HSM835
VSEN2
R1
10k
23
8
Q3
HUF76121
L2
VOUT2 (VTT)
OCSET2
10
28
C19
0.1F
C14
R10
22nF
33
R12
267k
R9
12.1k
ISL6523
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
B S
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
10.00
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
28
0o
10.65
-
0.394
N
0.419
1.27 BSC
H

NOTES:
MAX
A1
e
µ
MIN
28
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
-
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
Similar pages